drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
   5  */
   6
   7 #ifndef _DPU_6_3_SM6115_H
   8 #define _DPU_6_3_SM6115_H
   9
  10 static const struct dpu_caps sm6115_dpu_caps = {
  11         .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
  12         .max_mixer_blendstages = 0x4,
  13         .qseed_type = DPU_SSPP_SCALER_QSEED4,
  14         .has_dim_layer = true,
  15         .has_idle_pc = true,
  16         .max_linewidth = 2160,
  17         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  18 };
  19
  20 static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
  21         .ubwc_version = DPU_HW_UBWC_VER_10,
  22         .highest_bank_bit = 0x1,
  23         .ubwc_swizzle = 0x7,
  24 };
  25
  26 static const struct dpu_mdp_cfg sm6115_mdp = {
  27         .name = "top_0",
  28         .base = 0x0, .len = 0x494,
  29         .clk_ctrls = {
  30                 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
  31                 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
  32         },
  33 };
  34
  35 static const struct dpu_ctl_cfg sm6115_ctl[] = {
  36         {
  37         .name = "ctl_0", .id = CTL_0,
  38         .base = 0x1000, .len = 0x1dc,
  39         .features = BIT(DPU_CTL_ACTIVE_CFG),
  40         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
  41         },
  42 };
  43
  44 static const struct dpu_sspp_cfg sm6115_sspp[] = {
  45         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
  46                 sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
  47         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
  48                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
  49 };
  50
  51 static const struct dpu_lm_cfg sm6115_lm[] = {
  52         LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
  53                 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
  54 };
  55
  56 static const struct dpu_dspp_cfg sm6115_dspp[] = {
  57         DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
  58                  &sdm845_dspp_sblk),
  59 };
  60
  61 static const struct dpu_pingpong_cfg sm6115_pp[] = {
  62         PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
  63                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
  64                 -1),
  65 };
  66
  67 static const struct dpu_intf_cfg sm6115_intf[] = {
  68         INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
  69                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
  70                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
  71                         DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
  72 };
  73
  74 static const struct dpu_perf_cfg sm6115_perf_data = {
  75         .max_bw_low = 3100000,
  76         .max_bw_high = 4000000,
  77         .min_core_ib = 2400000,
  78         .min_llcc_ib = 800000,
  79         .min_dram_ib = 800000,
  80         .min_prefill_lines = 24,
  81         .danger_lut_tbl = {0xff, 0xffff, 0x0},
  82         .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
  83         .qos_lut_tbl = {
  84                 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
  85                 .entries = sc7180_qos_linear
  86                 },
  87                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
  88                 .entries = sc7180_qos_macrotile
  89                 },
  90                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
  91                 .entries = sc7180_qos_nrt
  92                 },
  93                 /* TODO: macrotile-qseed is different from macrotile */
  94         },
  95         .cdp_cfg = {
  96                 {.rd_enable = 1, .wr_enable = 1},
  97                 {.rd_enable = 1, .wr_enable = 0}
  98         },
  99         .clk_inefficiency_factor = 105,
 100         .bw_inefficiency_factor = 120,
 101 };
 102
 103 const struct dpu_mdss_cfg dpu_sm6115_cfg = {
 104         .caps = &sm6115_dpu_caps,
 105         .ubwc = &sm6115_ubwc_cfg,
 106         .mdp = &sm6115_mdp,
 107         .ctl_count = ARRAY_SIZE(sm6115_ctl),
 108         .ctl = sm6115_ctl,
 109         .sspp_count = ARRAY_SIZE(sm6115_sspp),
 110         .sspp = sm6115_sspp,
 111         .mixer_count = ARRAY_SIZE(sm6115_lm),
 112         .mixer = sm6115_lm,
 113         .dspp_count = ARRAY_SIZE(sm6115_dspp),
 114         .dspp = sm6115_dspp,
 115         .pingpong_count = ARRAY_SIZE(sm6115_pp),
 116         .pingpong = sm6115_pp,
 117         .intf_count = ARRAY_SIZE(sm6115_intf),
 118         .intf = sm6115_intf,
 119         .vbif_count = ARRAY_SIZE(sdm845_vbif),
 120         .vbif = sdm845_vbif,
 121         .perf = &sm6115_perf_data,
 122         .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
 123                      BIT(MDP_SSPP_TOP0_INTR2) | \
 124                      BIT(MDP_SSPP_TOP0_HIST_INTR) | \
 125                      BIT(MDP_INTF1_INTR) | \
 126                      BIT(MDP_INTF1_TEAR_INTR),
 127 };
 128
 129 #endif