drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
   5  */
   6
   7 #ifndef _DPU_6_0_SM8250_H
   8 #define _DPU_6_0_SM8250_H
   9
  10 static const struct dpu_caps sm8250_dpu_caps = {
  11         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
  12         .max_mixer_blendstages = 0xb,
  13         .qseed_type = DPU_SSPP_SCALER_QSEED4,
  14         .has_src_split = true,
  15         .has_dim_layer = true,
  16         .has_idle_pc = true,
  17         .has_3d_merge = true,
  18         .max_linewidth = 4096,
  19         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  20 };
  21
  22 static const struct dpu_mdp_cfg sm8250_mdp = {
  23         .name = "top_0",
  24         .base = 0x0, .len = 0x494,
  25         .clk_ctrls = {
  26                 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
  27                 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
  28                 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
  29                 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
  30                 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
  31                 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
  32                 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
  33                 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
  34                 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
  35                 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
  36         },
  37 };
  38
  39 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
  40 static const struct dpu_ctl_cfg sm8250_ctl[] = {
  41         {
  42                 .name = "ctl_0", .id = CTL_0,
  43                 .base = 0x1000, .len = 0x1e0,
  44                 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
  45                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
  46         }, {
  47                 .name = "ctl_1", .id = CTL_1,
  48                 .base = 0x1200, .len = 0x1e0,
  49                 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
  50                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
  51         }, {
  52                 .name = "ctl_2", .id = CTL_2,
  53                 .base = 0x1400, .len = 0x1e0,
  54                 .features = BIT(DPU_CTL_ACTIVE_CFG),
  55                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
  56         }, {
  57                 .name = "ctl_3", .id = CTL_3,
  58                 .base = 0x1600, .len = 0x1e0,
  59                 .features = BIT(DPU_CTL_ACTIVE_CFG),
  60                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
  61         }, {
  62                 .name = "ctl_4", .id = CTL_4,
  63                 .base = 0x1800, .len = 0x1e0,
  64                 .features = BIT(DPU_CTL_ACTIVE_CFG),
  65                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
  66         }, {
  67                 .name = "ctl_5", .id = CTL_5,
  68                 .base = 0x1a00, .len = 0x1e0,
  69                 .features = BIT(DPU_CTL_ACTIVE_CFG),
  70                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
  71         },
  72 };
  73
  74 static const struct dpu_sspp_cfg sm8250_sspp[] = {
  75         {
  76                 .name = "sspp_0", .id = SSPP_VIG0,
  77                 .base = 0x4000, .len = 0x1f8,
  78                 .features = VIG_SC7180_MASK_SDMA,
  79                 .sblk = &sm8250_vig_sblk_0,
  80                 .xin_id = 0,
  81                 .type = SSPP_TYPE_VIG,
  82                 .clk_ctrl = DPU_CLK_CTRL_VIG0,
  83         }, {
  84                 .name = "sspp_1", .id = SSPP_VIG1,
  85                 .base = 0x6000, .len = 0x1f8,
  86                 .features = VIG_SC7180_MASK_SDMA,
  87                 .sblk = &sm8250_vig_sblk_1,
  88                 .xin_id = 4,
  89                 .type = SSPP_TYPE_VIG,
  90                 .clk_ctrl = DPU_CLK_CTRL_VIG1,
  91         }, {
  92                 .name = "sspp_2", .id = SSPP_VIG2,
  93                 .base = 0x8000, .len = 0x1f8,
  94                 .features = VIG_SC7180_MASK_SDMA,
  95                 .sblk = &sm8250_vig_sblk_2,
  96                 .xin_id = 8,
  97                 .type = SSPP_TYPE_VIG,
  98                 .clk_ctrl = DPU_CLK_CTRL_VIG2,
  99         }, {
 100                 .name = "sspp_3", .id = SSPP_VIG3,
 101                 .base = 0xa000, .len = 0x1f8,
 102                 .features = VIG_SC7180_MASK_SDMA,
 103                 .sblk = &sm8250_vig_sblk_3,
 104                 .xin_id = 12,
 105                 .type = SSPP_TYPE_VIG,
 106                 .clk_ctrl = DPU_CLK_CTRL_VIG3,
 107         }, {
 108                 .name = "sspp_8", .id = SSPP_DMA0,
 109                 .base = 0x24000, .len = 0x1f8,
 110                 .features = DMA_SDM845_MASK_SDMA,
 111                 .sblk = &sdm845_dma_sblk_0,
 112                 .xin_id = 1,
 113                 .type = SSPP_TYPE_DMA,
 114                 .clk_ctrl = DPU_CLK_CTRL_DMA0,
 115         }, {
 116                 .name = "sspp_9", .id = SSPP_DMA1,
 117                 .base = 0x26000, .len = 0x1f8,
 118                 .features = DMA_SDM845_MASK_SDMA,
 119                 .sblk = &sdm845_dma_sblk_1,
 120                 .xin_id = 5,
 121                 .type = SSPP_TYPE_DMA,
 122                 .clk_ctrl = DPU_CLK_CTRL_DMA1,
 123         }, {
 124                 .name = "sspp_10", .id = SSPP_DMA2,
 125                 .base = 0x28000, .len = 0x1f8,
 126                 .features = DMA_CURSOR_SDM845_MASK_SDMA,
 127                 .sblk = &sdm845_dma_sblk_2,
 128                 .xin_id = 9,
 129                 .type = SSPP_TYPE_DMA,
 130                 .clk_ctrl = DPU_CLK_CTRL_DMA2,
 131         }, {
 132                 .name = "sspp_11", .id = SSPP_DMA3,
 133                 .base = 0x2a000, .len = 0x1f8,
 134                 .features = DMA_CURSOR_SDM845_MASK_SDMA,
 135                 .sblk = &sdm845_dma_sblk_3,
 136                 .xin_id = 13,
 137                 .type = SSPP_TYPE_DMA,
 138                 .clk_ctrl = DPU_CLK_CTRL_DMA3,
 139         },
 140 };
 141
 142 static const struct dpu_lm_cfg sm8250_lm[] = {
 143         {
 144                 .name = "lm_0", .id = LM_0,
 145                 .base = 0x44000, .len = 0x320,
 146                 .features = MIXER_SDM845_MASK,
 147                 .sblk = &sdm845_lm_sblk,
 148                 .lm_pair = LM_1,
 149                 .pingpong = PINGPONG_0,
 150                 .dspp = DSPP_0,
 151         }, {
 152                 .name = "lm_1", .id = LM_1,
 153                 .base = 0x45000, .len = 0x320,
 154                 .features = MIXER_SDM845_MASK,
 155                 .sblk = &sdm845_lm_sblk,
 156                 .lm_pair = LM_0,
 157                 .pingpong = PINGPONG_1,
 158                 .dspp = DSPP_1,
 159         }, {
 160                 .name = "lm_2", .id = LM_2,
 161                 .base = 0x46000, .len = 0x320,
 162                 .features = MIXER_SDM845_MASK,
 163                 .sblk = &sdm845_lm_sblk,
 164                 .lm_pair = LM_3,
 165                 .pingpong = PINGPONG_2,
 166         }, {
 167                 .name = "lm_3", .id = LM_3,
 168                 .base = 0x47000, .len = 0x320,
 169                 .features = MIXER_SDM845_MASK,
 170                 .sblk = &sdm845_lm_sblk,
 171                 .lm_pair = LM_2,
 172                 .pingpong = PINGPONG_3,
 173         }, {
 174                 .name = "lm_4", .id = LM_4,
 175                 .base = 0x48000, .len = 0x320,
 176                 .features = MIXER_SDM845_MASK,
 177                 .sblk = &sdm845_lm_sblk,
 178                 .lm_pair = LM_5,
 179                 .pingpong = PINGPONG_4,
 180         }, {
 181                 .name = "lm_5", .id = LM_5,
 182                 .base = 0x49000, .len = 0x320,
 183                 .features = MIXER_SDM845_MASK,
 184                 .sblk = &sdm845_lm_sblk,
 185                 .lm_pair = LM_4,
 186                 .pingpong = PINGPONG_5,
 187         },
 188 };
 189
 190 static const struct dpu_dspp_cfg sm8250_dspp[] = {
 191         {
 192                 .name = "dspp_0", .id = DSPP_0,
 193                 .base = 0x54000, .len = 0x1800,
 194                 .features = DSPP_SC7180_MASK,
 195                 .sblk = &sdm845_dspp_sblk,
 196         }, {
 197                 .name = "dspp_1", .id = DSPP_1,
 198                 .base = 0x56000, .len = 0x1800,
 199                 .features = DSPP_SC7180_MASK,
 200                 .sblk = &sdm845_dspp_sblk,
 201         }, {
 202                 .name = "dspp_2", .id = DSPP_2,
 203                 .base = 0x58000, .len = 0x1800,
 204                 .features = DSPP_SC7180_MASK,
 205                 .sblk = &sdm845_dspp_sblk,
 206         }, {
 207                 .name = "dspp_3", .id = DSPP_3,
 208                 .base = 0x5a000, .len = 0x1800,
 209                 .features = DSPP_SC7180_MASK,
 210                 .sblk = &sdm845_dspp_sblk,
 211         },
 212 };
 213
 214 static const struct dpu_pingpong_cfg sm8250_pp[] = {
 215         {
 216                 .name = "pingpong_0", .id = PINGPONG_0,
 217                 .base = 0x70000, .len = 0xd4,
 218                 .features = PINGPONG_SM8150_MASK,
 219                 .sblk = &sdm845_pp_sblk,
 220                 .merge_3d = MERGE_3D_0,
 221                 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 222                 .intr_rdptr = -1,
 223         }, {
 224                 .name = "pingpong_1", .id = PINGPONG_1,
 225                 .base = 0x70800, .len = 0xd4,
 226                 .features = PINGPONG_SM8150_MASK,
 227                 .sblk = &sdm845_pp_sblk,
 228                 .merge_3d = MERGE_3D_0,
 229                 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
 230                 .intr_rdptr = -1,
 231         }, {
 232                 .name = "pingpong_2", .id = PINGPONG_2,
 233                 .base = 0x71000, .len = 0xd4,
 234                 .features = PINGPONG_SM8150_MASK,
 235                 .sblk = &sdm845_pp_sblk,
 236                 .merge_3d = MERGE_3D_1,
 237                 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
 238                 .intr_rdptr = -1,
 239         }, {
 240                 .name = "pingpong_3", .id = PINGPONG_3,
 241                 .base = 0x71800, .len = 0xd4,
 242                 .features = PINGPONG_SM8150_MASK,
 243                 .sblk = &sdm845_pp_sblk,
 244                 .merge_3d = MERGE_3D_1,
 245                 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
 246                 .intr_rdptr = -1,
 247         }, {
 248                 .name = "pingpong_4", .id = PINGPONG_4,
 249                 .base = 0x72000, .len = 0xd4,
 250                 .features = PINGPONG_SM8150_MASK,
 251                 .sblk = &sdm845_pp_sblk,
 252                 .merge_3d = MERGE_3D_2,
 253                 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
 254                 .intr_rdptr = -1,
 255         }, {
 256                 .name = "pingpong_5", .id = PINGPONG_5,
 257                 .base = 0x72800, .len = 0xd4,
 258                 .features = PINGPONG_SM8150_MASK,
 259                 .sblk = &sdm845_pp_sblk,
 260                 .merge_3d = MERGE_3D_2,
 261                 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
 262                 .intr_rdptr = -1,
 263         },
 264 };
 265
 266 static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
 267         {
 268                 .name = "merge_3d_0", .id = MERGE_3D_0,
 269                 .base = 0x83000, .len = 0x8,
 270         }, {
 271                 .name = "merge_3d_1", .id = MERGE_3D_1,
 272                 .base = 0x83100, .len = 0x8,
 273         }, {
 274                 .name = "merge_3d_2", .id = MERGE_3D_2,
 275                 .base = 0x83200, .len = 0x8,
 276         },
 277 };
 278
 279 static const struct dpu_dsc_cfg sm8250_dsc[] = {
 280         {
 281                 .name = "dsc_0", .id = DSC_0,
 282                 .base = 0x80000, .len = 0x140,
 283                 .features = BIT(DPU_DSC_OUTPUT_CTRL),
 284         }, {
 285                 .name = "dsc_1", .id = DSC_1,
 286                 .base = 0x80400, .len = 0x140,
 287                 .features = BIT(DPU_DSC_OUTPUT_CTRL),
 288         }, {
 289                 .name = "dsc_2", .id = DSC_2,
 290                 .base = 0x80800, .len = 0x140,
 291                 .features = BIT(DPU_DSC_OUTPUT_CTRL),
 292         }, {
 293                 .name = "dsc_3", .id = DSC_3,
 294                 .base = 0x80c00, .len = 0x140,
 295                 .features = BIT(DPU_DSC_OUTPUT_CTRL),
 296         },
 297 };
 298
 299 static const struct dpu_intf_cfg sm8250_intf[] = {
 300         {
 301                 .name = "intf_0", .id = INTF_0,
 302                 .base = 0x6a000, .len = 0x280,
 303                 .features = INTF_SC7180_MASK,
 304                 .type = INTF_DP,
 305                 .controller_id = MSM_DP_CONTROLLER_0,
 306                 .prog_fetch_lines_worst_case = 24,
 307                 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
 308                 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
 309                 .intr_tear_rd_ptr = -1,
 310         }, {
 311                 .name = "intf_1", .id = INTF_1,
 312                 .base = 0x6a800, .len = 0x2c0,
 313                 .features = INTF_SC7180_MASK,
 314                 .type = INTF_DSI,
 315                 .controller_id = MSM_DSI_CONTROLLER_0,
 316                 .prog_fetch_lines_worst_case = 24,
 317                 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
 318                 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
 319                 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
 320         }, {
 321                 .name = "intf_2", .id = INTF_2,
 322                 .base = 0x6b000, .len = 0x2c0,
 323                 .features = INTF_SC7180_MASK,
 324                 .type = INTF_DSI,
 325                 .controller_id = MSM_DSI_CONTROLLER_1,
 326                 .prog_fetch_lines_worst_case = 24,
 327                 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
 328                 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
 329                 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
 330         }, {
 331                 .name = "intf_3", .id = INTF_3,
 332                 .base = 0x6b800, .len = 0x280,
 333                 .features = INTF_SC7180_MASK,
 334                 .type = INTF_DP,
 335                 .controller_id = MSM_DP_CONTROLLER_1,
 336                 .prog_fetch_lines_worst_case = 24,
 337                 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
 338                 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
 339                 .intr_tear_rd_ptr = -1,
 340         },
 341 };
 342
 343 static const struct dpu_wb_cfg sm8250_wb[] = {
 344         {
 345                 .name = "wb_2", .id = WB_2,
 346                 .base = 0x65000, .len = 0x2c8,
 347                 .features = WB_SM8250_MASK,
 348                 .format_list = wb2_formats,
 349                 .num_formats = ARRAY_SIZE(wb2_formats),
 350                 .clk_ctrl = DPU_CLK_CTRL_WB2,
 351                 .xin_id = 6,
 352                 .vbif_idx = VBIF_RT,
 353                 .maxlinewidth = 4096,
 354                 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
 355         },
 356 };
 357
 358 static const struct dpu_perf_cfg sm8250_perf_data = {
 359         .max_bw_low = 13700000,
 360         .max_bw_high = 16600000,
 361         .min_core_ib = 4800000,
 362         .min_llcc_ib = 0,
 363         .min_dram_ib = 800000,
 364         .min_prefill_lines = 35,
 365         .danger_lut_tbl = {0xf, 0xffff, 0x0},
 366         .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
 367         .qos_lut_tbl = {
 368                 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
 369                 .entries = sc7180_qos_linear
 370                 },
 371                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
 372                 .entries = sc7180_qos_macrotile
 373                 },
 374                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
 375                 .entries = sc7180_qos_nrt
 376                 },
 377                 /* TODO: macrotile-qseed is different from macrotile */
 378         },
 379         .cdp_cfg = {
 380                 {.rd_enable = 1, .wr_enable = 1},
 381                 {.rd_enable = 1, .wr_enable = 0}
 382         },
 383         .clk_inefficiency_factor = 105,
 384         .bw_inefficiency_factor = 120,
 385 };
 386
 387 static const struct dpu_mdss_version sm8250_mdss_ver = {
 388         .core_major_ver = 6,
 389         .core_minor_ver = 0,
 390 };
 391
 392 const struct dpu_mdss_cfg dpu_sm8250_cfg = {
 393         .mdss_ver = &sm8250_mdss_ver,
 394         .caps = &sm8250_dpu_caps,
 395         .mdp = &sm8250_mdp,
 396         .ctl_count = ARRAY_SIZE(sm8250_ctl),
 397         .ctl = sm8250_ctl,
 398         .sspp_count = ARRAY_SIZE(sm8250_sspp),
 399         .sspp = sm8250_sspp,
 400         .mixer_count = ARRAY_SIZE(sm8250_lm),
 401         .mixer = sm8250_lm,
 402         .dspp_count = ARRAY_SIZE(sm8250_dspp),
 403         .dspp = sm8250_dspp,
 404         .dsc_count = ARRAY_SIZE(sm8250_dsc),
 405         .dsc = sm8250_dsc,
 406         .pingpong_count = ARRAY_SIZE(sm8250_pp),
 407         .pingpong = sm8250_pp,
 408         .merge_3d_count = ARRAY_SIZE(sm8250_merge_3d),
 409         .merge_3d = sm8250_merge_3d,
 410         .intf_count = ARRAY_SIZE(sm8250_intf),
 411         .intf = sm8250_intf,
 412         .vbif_count = ARRAY_SIZE(sdm845_vbif),
 413         .vbif = sdm845_vbif,
 414         .wb_count = ARRAY_SIZE(sm8250_wb),
 415         .wb = sm8250_wb,
 416         .perf = &sm8250_perf_data,
 417 };
 418
 419 #endif