drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
   5  */
   6
   7 #ifndef _DPU_4_0_SDM845_H
   8 #define _DPU_4_0_SDM845_H
   9
  10 static const struct dpu_caps sdm845_dpu_caps = {
  11         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
  12         .max_mixer_blendstages = 0xb,
  13         .qseed_type = DPU_SSPP_SCALER_QSEED3,
  14         .has_src_split = true,
  15         .has_dim_layer = true,
  16         .has_idle_pc = true,
  17         .has_3d_merge = true,
  18         .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
  19         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  20         .max_hdeci_exp = MAX_HORZ_DECIMATION,
  21         .max_vdeci_exp = MAX_VERT_DECIMATION,
  22 };
  23
  24 static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
  25         .ubwc_version = DPU_HW_UBWC_VER_20,
  26         .highest_bank_bit = 0x2,
  27 };
  28
  29 static const struct dpu_mdp_cfg sdm845_mdp = {
  30         .name = "top_0",
  31         .base = 0x0, .len = 0x45c,
  32         .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
  33         .clk_ctrls = {
  34                 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
  35                 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
  36                 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
  37                 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
  38                 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
  39                 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
  40                 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
  41                 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
  42         },
  43 };
  44
  45 static const struct dpu_ctl_cfg sdm845_ctl[] = {
  46         {
  47                 .name = "ctl_0", .id = CTL_0,
  48                 .base = 0x1000, .len = 0xe4,
  49                 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
  50                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
  51         }, {
  52                 .name = "ctl_1", .id = CTL_1,
  53                 .base = 0x1200, .len = 0xe4,
  54                 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
  55                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
  56         }, {
  57                 .name = "ctl_2", .id = CTL_2,
  58                 .base = 0x1400, .len = 0xe4,
  59                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
  60         }, {
  61                 .name = "ctl_3", .id = CTL_3,
  62                 .base = 0x1600, .len = 0xe4,
  63                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
  64         }, {
  65                 .name = "ctl_4", .id = CTL_4,
  66                 .base = 0x1800, .len = 0xe4,
  67                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
  68         },
  69 };
  70
  71 static const struct dpu_sspp_cfg sdm845_sspp[] = {
  72         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,
  73                 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
  74         SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,
  75                 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
  76         SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,
  77                 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
  78         SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,
  79                 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
  80         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,
  81                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
  82         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,
  83                 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
  84         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
  85                 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
  86         SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
  87                 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
  88 };
  89
  90 static const struct dpu_lm_cfg sdm845_lm[] = {
  91         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
  92                 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
  93         LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
  94                 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
  95         LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
  96                 &sdm845_lm_sblk, PINGPONG_2, LM_5, DSPP_2),
  97         LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
  98                 &sdm845_lm_sblk, PINGPONG_NONE, 0, DSPP_3),
  99         LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
 100                 &sdm845_lm_sblk, PINGPONG_NONE, 0, 0),
 101         LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
 102                 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
 103 };
 104
 105 static const struct dpu_dspp_cfg sdm845_dspp[] = {
 106         DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
 107                  &sdm845_dspp_sblk),
 108         DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
 109                  &sdm845_dspp_sblk),
 110         DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
 111                  &sdm845_dspp_sblk),
 112         DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
 113                  &sdm845_dspp_sblk),
 114 };
 115
 116 static const struct dpu_pingpong_cfg sdm845_pp[] = {
 117         PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
 118                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 119                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
 120         PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
 121                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
 122                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
 123         PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
 124                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
 125                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
 126         PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
 127                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
 128                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 129 };
 130
 131 static const struct dpu_dsc_cfg sdm845_dsc[] = {
 132         DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
 133         DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
 134         DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
 135         DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
 136 };
 137
 138 static const struct dpu_intf_cfg sdm845_intf[] = {
 139         INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,
 140                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
 141                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
 142         INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,
 143                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
 144                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
 145         INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,
 146                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
 147                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
 148         INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,
 149                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
 150                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
 151 };
 152
 153 static const struct dpu_perf_cfg sdm845_perf_data = {
 154         .max_bw_low = 6800000,
 155         .max_bw_high = 6800000,
 156         .min_core_ib = 2400000,
 157         .min_llcc_ib = 800000,
 158         .min_dram_ib = 800000,
 159         .undersized_prefill_lines = 2,
 160         .xtra_prefill_lines = 2,
 161         .dest_scale_prefill_lines = 3,
 162         .macrotile_prefill_lines = 4,
 163         .yuv_nv12_prefill_lines = 8,
 164         .linear_prefill_lines = 1,
 165         .downscaling_prefill_lines = 1,
 166         .amortizable_threshold = 25,
 167         .min_prefill_lines = 24,
 168         .danger_lut_tbl = {0xf, 0xffff, 0x0},
 169         .safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
 170         .qos_lut_tbl = {
 171                 {.nentry = ARRAY_SIZE(sdm845_qos_linear),
 172                 .entries = sdm845_qos_linear
 173                 },
 174                 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile),
 175                 .entries = sdm845_qos_macrotile
 176                 },
 177                 {.nentry = ARRAY_SIZE(sdm845_qos_nrt),
 178                 .entries = sdm845_qos_nrt
 179                 },
 180         },
 181         .cdp_cfg = {
 182                 {.rd_enable = 1, .wr_enable = 1},
 183                 {.rd_enable = 1, .wr_enable = 0}
 184         },
 185         .clk_inefficiency_factor = 105,
 186         .bw_inefficiency_factor = 120,
 187 };
 188
 189 const struct dpu_mdss_cfg dpu_sdm845_cfg = {
 190         .caps = &sdm845_dpu_caps,
 191         .ubwc = &sdm845_ubwc_cfg,
 192         .mdp = &sdm845_mdp,
 193         .ctl_count = ARRAY_SIZE(sdm845_ctl),
 194         .ctl = sdm845_ctl,
 195         .sspp_count = ARRAY_SIZE(sdm845_sspp),
 196         .sspp = sdm845_sspp,
 197         .mixer_count = ARRAY_SIZE(sdm845_lm),
 198         .mixer = sdm845_lm,
 199         .dspp_count = ARRAY_SIZE(sdm845_dspp),
 200         .dspp = sdm845_dspp,
 201         .pingpong_count = ARRAY_SIZE(sdm845_pp),
 202         .pingpong = sdm845_pp,
 203         .dsc_count = ARRAY_SIZE(sdm845_dsc),
 204         .dsc = sdm845_dsc,
 205         .intf_count = ARRAY_SIZE(sdm845_intf),
 206         .intf = sdm845_intf,
 207         .vbif_count = ARRAY_SIZE(sdm845_vbif),
 208         .vbif = sdm845_vbif,
 209         .perf = &sdm845_perf_data,
 210         .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
 211                      BIT(MDP_SSPP_TOP0_INTR2) | \
 212                      BIT(MDP_SSPP_TOP0_HIST_INTR) | \
 213                      BIT(MDP_INTF0_INTR) | \
 214                      BIT(MDP_INTF1_INTR) | \
 215                      BIT(MDP_INTF2_INTR) | \
 216                      BIT(MDP_INTF3_INTR) | \
 217                      BIT(MDP_AD4_0_INTR) | \
 218                      BIT(MDP_AD4_1_INTR),
 219 };
 220
 221 #endif