drivers/gpu/drm/msm/adreno/adreno_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   7  */
   8
   9 #include <linux/ascii85.h>
  10 #include <linux/interconnect.h>
  11 #include <linux/qcom_scm.h>
  12 #include <linux/kernel.h>
  13 #include <linux/of_address.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/slab.h>
  16 #include <linux/soc/qcom/mdt_loader.h>
  17 #include <linux/nvmem-consumer.h>
  18 #include <soc/qcom/ocmem.h>
  19 #include "adreno_gpu.h"
  20 #include "a6xx_gpu.h"
  21 #include "msm_gem.h"
  22 #include "msm_mmu.h"
  23
  24 static u64 address_space_size = 0;
  25 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
  26 module_param(address_space_size, ullong, 0600);
  27
  28 static bool zap_available = true;
  29
  30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
  31                 u32 pasid)
  32 {
  33         struct device *dev = &gpu->pdev->dev;
  34         const struct firmware *fw;
  35         const char *signed_fwname = NULL;
  36         struct device_node *np, *mem_np;
  37         struct resource r;
  38         phys_addr_t mem_phys;
  39         ssize_t mem_size;
  40         void *mem_region = NULL;
  41         int ret;
  42
  43         if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
  44                 zap_available = false;
  45                 return -EINVAL;
  46         }
  47
  48         np = of_get_child_by_name(dev->of_node, "zap-shader");
  49         if (!np) {
  50                 zap_available = false;
  51                 return -ENODEV;
  52         }
  53
  54         mem_np = of_parse_phandle(np, "memory-region", 0);
  55         of_node_put(np);
  56         if (!mem_np) {
  57                 zap_available = false;
  58                 return -EINVAL;
  59         }
  60
  61         ret = of_address_to_resource(mem_np, 0, &r);
  62         of_node_put(mem_np);
  63         if (ret)
  64                 return ret;
  65
  66         mem_phys = r.start;
  67
  68         /*
  69          * Check for a firmware-name property.  This is the new scheme
  70          * to handle firmware that may be signed with device specific
  71          * keys, allowing us to have a different zap fw path for different
  72          * devices.
  73          *
  74          * If the firmware-name property is found, we bypass the
  75          * adreno_request_fw() mechanism, because we don't need to handle
  76          * the /lib/firmware/qcom/... vs /lib/firmware/... case.
  77          *
  78          * If the firmware-name property is not found, for backwards
  79          * compatibility we fall back to the fwname from the gpulist
  80          * table.
  81          */
  82         of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
  83         if (signed_fwname) {
  84                 fwname = signed_fwname;
  85                 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
  86                 if (ret)
  87                         fw = ERR_PTR(ret);
  88         } else if (fwname) {
  89                 /* Request the MDT file from the default location: */
  90                 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
  91         } else {
  92                 /*
  93                  * For new targets, we require the firmware-name property,
  94                  * if a zap-shader is required, rather than falling back
  95                  * to a firmware name specified in gpulist.
  96                  *
  97                  * Because the firmware is signed with a (potentially)
  98                  * device specific key, having the name come from gpulist
  99                  * was a bad idea, and is only provided for backwards
 100                  * compatibility for older targets.
 101                  */
 102                 return -ENODEV;
 103         }
 104
 105         if (IS_ERR(fw)) {
 106                 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
 107                 return PTR_ERR(fw);
 108         }
 109
 110         /* Figure out how much memory we need */
 111         mem_size = qcom_mdt_get_size(fw);
 112         if (mem_size < 0) {
 113                 ret = mem_size;
 114                 goto out;
 115         }
 116
 117         if (mem_size > resource_size(&r)) {
 118                 DRM_DEV_ERROR(dev,
 119                         "memory region is too small to load the MDT\n");
 120                 ret = -E2BIG;
 121                 goto out;
 122         }
 123
 124         /* Allocate memory for the firmware image */
 125         mem_region = memremap(mem_phys, mem_size,  MEMREMAP_WC);
 126         if (!mem_region) {
 127                 ret = -ENOMEM;
 128                 goto out;
 129         }
 130
 131         /*
 132          * Load the rest of the MDT
 133          *
 134          * Note that we could be dealing with two different paths, since
 135          * with upstream linux-firmware it would be in a qcom/ subdir..
 136          * adreno_request_fw() handles this, but qcom_mdt_load() does
 137          * not.  But since we've already gotten through adreno_request_fw()
 138          * we know which of the two cases it is:
 139          */
 140         if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
 141                 ret = qcom_mdt_load(dev, fw, fwname, pasid,
 142                                 mem_region, mem_phys, mem_size, NULL);
 143         } else {
 144                 char *newname;
 145
 146                 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 147
 148                 ret = qcom_mdt_load(dev, fw, newname, pasid,
 149                                 mem_region, mem_phys, mem_size, NULL);
 150                 kfree(newname);
 151         }
 152         if (ret)
 153                 goto out;
 154
 155         /* Send the image to the secure world */
 156         ret = qcom_scm_pas_auth_and_reset(pasid);
 157
 158         /*
 159          * If the scm call returns -EOPNOTSUPP we assume that this target
 160          * doesn't need/support the zap shader so quietly fail
 161          */
 162         if (ret == -EOPNOTSUPP)
 163                 zap_available = false;
 164         else if (ret)
 165                 DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
 166
 167 out:
 168         if (mem_region)
 169                 memunmap(mem_region);
 170
 171         release_firmware(fw);
 172
 173         return ret;
 174 }
 175
 176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
 177 {
 178         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 179         struct platform_device *pdev = gpu->pdev;
 180
 181         /* Short cut if we determine the zap shader isn't available/needed */
 182         if (!zap_available)
 183                 return -ENODEV;
 184
 185         /* We need SCM to be able to load the firmware */
 186         if (!qcom_scm_is_available()) {
 187                 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
 188                 return -EPROBE_DEFER;
 189         }
 190
 191         return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
 192 }
 193
 194 void adreno_set_llc_attributes(struct iommu_domain *iommu)
 195 {
 196         iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA);
 197 }
 198
 199 struct msm_gem_address_space *
 200 adreno_iommu_create_address_space(struct msm_gpu *gpu,
 201                 struct platform_device *pdev)
 202 {
 203         struct iommu_domain *iommu;
 204         struct msm_mmu *mmu;
 205         struct msm_gem_address_space *aspace;
 206         u64 start, size;
 207
 208         iommu = iommu_domain_alloc(&platform_bus_type);
 209         if (!iommu)
 210                 return NULL;
 211
 212         mmu = msm_iommu_new(&pdev->dev, iommu);
 213         if (IS_ERR(mmu)) {
 214                 iommu_domain_free(iommu);
 215                 return ERR_CAST(mmu);
 216         }
 217
 218         /*
 219          * Use the aperture start or SZ_16M, whichever is greater. This will
 220          * ensure that we align with the allocated pagetable range while still
 221          * allowing room in the lower 32 bits for GMEM and whatnot
 222          */
 223         start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
 224         size = iommu->geometry.aperture_end - start + 1;
 225
 226         aspace = msm_gem_address_space_create(mmu, "gpu",
 227                 start & GENMASK_ULL(48, 0), size);
 228
 229         if (IS_ERR(aspace) && !IS_ERR(mmu))
 230                 mmu->funcs->destroy(mmu);
 231
 232         return aspace;
 233 }
 234
 235 u64 adreno_private_address_space_size(struct msm_gpu *gpu)
 236 {
 237         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 238
 239         if (address_space_size)
 240                 return address_space_size;
 241
 242         if (adreno_gpu->info->address_space_size)
 243                 return adreno_gpu->info->address_space_size;
 244
 245         return SZ_4G;
 246 }
 247
 248 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 249                      uint32_t param, uint64_t *value, uint32_t *len)
 250 {
 251         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 252
 253         /* No pointer params yet */
 254         if (*len != 0)
 255                 return -EINVAL;
 256
 257         switch (param) {
 258         case MSM_PARAM_GPU_ID:
 259                 *value = adreno_gpu->info->revn;
 260                 return 0;
 261         case MSM_PARAM_GMEM_SIZE:
 262                 *value = adreno_gpu->gmem;
 263                 return 0;
 264         case MSM_PARAM_GMEM_BASE:
 265                 *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
 266                 return 0;
 267         case MSM_PARAM_CHIP_ID:
 268                 *value =  (uint64_t)adreno_gpu->rev.patchid |
 269                          ((uint64_t)adreno_gpu->rev.minor << 8) |
 270                          ((uint64_t)adreno_gpu->rev.major << 16) |
 271                          ((uint64_t)adreno_gpu->rev.core  << 24);
 272                 if (!adreno_gpu->info->revn)
 273                         *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
 274                 return 0;
 275         case MSM_PARAM_MAX_FREQ:
 276                 *value = adreno_gpu->base.fast_rate;
 277                 return 0;
 278         case MSM_PARAM_TIMESTAMP:
 279                 if (adreno_gpu->funcs->get_timestamp) {
 280                         int ret;
 281
 282                         pm_runtime_get_sync(&gpu->pdev->dev);
 283                         ret = adreno_gpu->funcs->get_timestamp(gpu, value);
 284                         pm_runtime_put_autosuspend(&gpu->pdev->dev);
 285
 286                         return ret;
 287                 }
 288                 return -EINVAL;
 289         case MSM_PARAM_PRIORITIES:
 290                 *value = gpu->nr_rings * NR_SCHED_PRIORITIES;
 291                 return 0;
 292         case MSM_PARAM_PP_PGTABLE:
 293                 *value = 0;
 294                 return 0;
 295         case MSM_PARAM_FAULTS:
 296                 if (ctx->aspace)
 297                         *value = gpu->global_faults + ctx->aspace->faults;
 298                 else
 299                         *value = gpu->global_faults;
 300                 return 0;
 301         case MSM_PARAM_SUSPENDS:
 302                 *value = gpu->suspend_count;
 303                 return 0;
 304         case MSM_PARAM_VA_START:
 305                 if (ctx->aspace == gpu->aspace)
 306                         return -EINVAL;
 307                 *value = ctx->aspace->va_start;
 308                 return 0;
 309         case MSM_PARAM_VA_SIZE:
 310                 if (ctx->aspace == gpu->aspace)
 311                         return -EINVAL;
 312                 *value = ctx->aspace->va_size;
 313                 return 0;
 314         default:
 315                 DBG("%s: invalid param: %u", gpu->name, param);
 316                 return -EINVAL;
 317         }
 318 }
 319
 320 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 321                      uint32_t param, uint64_t value, uint32_t len)
 322 {
 323         switch (param) {
 324         case MSM_PARAM_COMM:
 325         case MSM_PARAM_CMDLINE:
 326                 /* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so
 327                  * that should be a reasonable upper bound
 328                  */
 329                 if (len > PAGE_SIZE)
 330                         return -EINVAL;
 331                 break;
 332         default:
 333                 if (len != 0)
 334                         return -EINVAL;
 335         }
 336
 337         switch (param) {
 338         case MSM_PARAM_COMM:
 339         case MSM_PARAM_CMDLINE: {
 340                 char *str, **paramp;
 341
 342                 str = kmalloc(len + 1, GFP_KERNEL);
 343                 if (!str)
 344                         return -ENOMEM;
 345
 346                 if (copy_from_user(str, u64_to_user_ptr(value), len)) {
 347                         kfree(str);
 348                         return -EFAULT;
 349                 }
 350
 351                 /* Ensure string is null terminated: */
 352                 str[len] = '\0';
 353
 354                 if (param == MSM_PARAM_COMM) {
 355                         paramp = &ctx->comm;
 356                 } else {
 357                         paramp = &ctx->cmdline;
 358                 }
 359
 360                 kfree(*paramp);
 361                 *paramp = str;
 362
 363                 return 0;
 364         }
 365         case MSM_PARAM_SYSPROF:
 366                 if (!capable(CAP_SYS_ADMIN))
 367                         return -EPERM;
 368                 return msm_file_private_set_sysprof(ctx, gpu, value);
 369         default:
 370                 DBG("%s: invalid param: %u", gpu->name, param);
 371                 return -EINVAL;
 372         }
 373 }
 374
 375 const struct firmware *
 376 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
 377 {
 378         struct drm_device *drm = adreno_gpu->base.dev;
 379         const struct firmware *fw = NULL;
 380         char *newname;
 381         int ret;
 382
 383         newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 384         if (!newname)
 385                 return ERR_PTR(-ENOMEM);
 386
 387         /*
 388          * Try first to load from qcom/$fwfile using a direct load (to avoid
 389          * a potential timeout waiting for usermode helper)
 390          */
 391         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 392             (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
 393
 394                 ret = request_firmware_direct(&fw, newname, drm->dev);
 395                 if (!ret) {
 396                         DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
 397                                 newname);
 398                         adreno_gpu->fwloc = FW_LOCATION_NEW;
 399                         goto out;
 400                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 401                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 402                                 newname, ret);
 403                         fw = ERR_PTR(ret);
 404                         goto out;
 405                 }
 406         }
 407
 408         /*
 409          * Then try the legacy location without qcom/ prefix
 410          */
 411         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 412             (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
 413
 414                 ret = request_firmware_direct(&fw, fwname, drm->dev);
 415                 if (!ret) {
 416                         DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
 417                                 newname);
 418                         adreno_gpu->fwloc = FW_LOCATION_LEGACY;
 419                         goto out;
 420                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 421                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 422                                 fwname, ret);
 423                         fw = ERR_PTR(ret);
 424                         goto out;
 425                 }
 426         }
 427
 428         /*
 429          * Finally fall back to request_firmware() for cases where the
 430          * usermode helper is needed (I think mainly android)
 431          */
 432         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 433             (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
 434
 435                 ret = request_firmware(&fw, newname, drm->dev);
 436                 if (!ret) {
 437                         DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
 438                                 newname);
 439                         adreno_gpu->fwloc = FW_LOCATION_HELPER;
 440                         goto out;
 441                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 442                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 443                                 newname, ret);
 444                         fw = ERR_PTR(ret);
 445                         goto out;
 446                 }
 447         }
 448
 449         DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
 450         fw = ERR_PTR(-ENOENT);
 451 out:
 452         kfree(newname);
 453         return fw;
 454 }
 455
 456 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
 457 {
 458         int i;
 459
 460         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
 461                 const struct firmware *fw;
 462
 463                 if (!adreno_gpu->info->fw[i])
 464                         continue;
 465
 466                 /* Skip if the firmware has already been loaded */
 467                 if (adreno_gpu->fw[i])
 468                         continue;
 469
 470                 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
 471                 if (IS_ERR(fw))
 472                         return PTR_ERR(fw);
 473
 474                 adreno_gpu->fw[i] = fw;
 475         }
 476
 477         return 0;
 478 }
 479
 480 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
 481                 const struct firmware *fw, u64 *iova)
 482 {
 483         struct drm_gem_object *bo;
 484         void *ptr;
 485
 486         ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
 487                 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
 488
 489         if (IS_ERR(ptr))
 490                 return ERR_CAST(ptr);
 491
 492         memcpy(ptr, &fw->data[4], fw->size - 4);
 493
 494         msm_gem_put_vaddr(bo);
 495
 496         return bo;
 497 }
 498
 499 int adreno_hw_init(struct msm_gpu *gpu)
 500 {
 501         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 502         int ret, i;
 503
 504         VERB("%s", gpu->name);
 505
 506         ret = adreno_load_fw(adreno_gpu);
 507         if (ret)
 508                 return ret;
 509
 510         for (i = 0; i < gpu->nr_rings; i++) {
 511                 struct msm_ringbuffer *ring = gpu->rb[i];
 512
 513                 if (!ring)
 514                         continue;
 515
 516                 ring->cur = ring->start;
 517                 ring->next = ring->start;
 518                 ring->memptrs->rptr = 0;
 519
 520                 /* Detect and clean up an impossible fence, ie. if GPU managed
 521                  * to scribble something invalid, we don't want that to confuse
 522                  * us into mistakingly believing that submits have completed.
 523                  */
 524                 if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
 525                         ring->memptrs->fence = ring->fctx->last_fence;
 526                 }
 527         }
 528
 529         return 0;
 530 }
 531
 532 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
 533 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
 534                 struct msm_ringbuffer *ring)
 535 {
 536         struct msm_gpu *gpu = &adreno_gpu->base;
 537
 538         return gpu->funcs->get_rptr(gpu, ring);
 539 }
 540
 541 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
 542 {
 543         return gpu->rb[0];
 544 }
 545
 546 void adreno_recover(struct msm_gpu *gpu)
 547 {
 548         struct drm_device *dev = gpu->dev;
 549         int ret;
 550
 551         // XXX pm-runtime??  we *need* the device to be off after this
 552         // so maybe continuing to call ->pm_suspend/resume() is better?
 553
 554         gpu->funcs->pm_suspend(gpu);
 555         gpu->funcs->pm_resume(gpu);
 556
 557         ret = msm_gpu_hw_init(gpu);
 558         if (ret) {
 559                 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 560                 /* hmm, oh well? */
 561         }
 562 }
 563
 564 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)
 565 {
 566         uint32_t wptr;
 567
 568         /* Copy the shadow to the actual register */
 569         ring->cur = ring->next;
 570
 571         /*
 572          * Mask wptr value that we calculate to fit in the HW range. This is
 573          * to account for the possibility that the last command fit exactly into
 574          * the ringbuffer and rb->next hasn't wrapped to zero yet
 575          */
 576         wptr = get_wptr(ring);
 577
 578         /* ensure writes to ringbuffer have hit system memory: */
 579         mb();
 580
 581         gpu_write(gpu, reg, wptr);
 582 }
 583
 584 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 585 {
 586         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 587         uint32_t wptr = get_wptr(ring);
 588
 589         /* wait for CP to drain ringbuffer: */
 590         if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
 591                 return true;
 592
 593         /* TODO maybe we need to reset GPU here to recover from hang? */
 594         DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
 595                 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
 596
 597         return false;
 598 }
 599
 600 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
 601 {
 602         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 603         int i, count = 0;
 604
 605         WARN_ON(!mutex_is_locked(&gpu->lock));
 606
 607         kref_init(&state->ref);
 608
 609         ktime_get_real_ts64(&state->time);
 610
 611         for (i = 0; i < gpu->nr_rings; i++) {
 612                 int size = 0, j;
 613
 614                 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
 615                 state->ring[i].iova = gpu->rb[i]->iova;
 616                 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence;
 617                 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
 618                 state->ring[i].wptr = get_wptr(gpu->rb[i]);
 619
 620                 /* Copy at least 'wptr' dwords of the data */
 621                 size = state->ring[i].wptr;
 622
 623                 /* After wptr find the last non zero dword to save space */
 624                 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
 625                         if (gpu->rb[i]->start[j])
 626                                 size = j + 1;
 627
 628                 if (size) {
 629                         state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
 630                         if (state->ring[i].data) {
 631                                 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
 632                                 state->ring[i].data_size = size << 2;
 633                         }
 634                 }
 635         }
 636
 637         /* Some targets prefer to collect their own registers */
 638         if (!adreno_gpu->registers)
 639                 return 0;
 640
 641         /* Count the number of registers */
 642         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
 643                 count += adreno_gpu->registers[i + 1] -
 644                         adreno_gpu->registers[i] + 1;
 645
 646         state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
 647         if (state->registers) {
 648                 int pos = 0;
 649
 650                 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 651                         u32 start = adreno_gpu->registers[i];
 652                         u32 end   = adreno_gpu->registers[i + 1];
 653                         u32 addr;
 654
 655                         for (addr = start; addr <= end; addr++) {
 656                                 state->registers[pos++] = addr;
 657                                 state->registers[pos++] = gpu_read(gpu, addr);
 658                         }
 659                 }
 660
 661                 state->nr_registers = count;
 662         }
 663
 664         return 0;
 665 }
 666
 667 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
 668 {
 669         int i;
 670
 671         for (i = 0; i < ARRAY_SIZE(state->ring); i++)
 672                 kvfree(state->ring[i].data);
 673
 674         for (i = 0; state->bos && i < state->nr_bos; i++)
 675                 kvfree(state->bos[i].data);
 676
 677         kfree(state->bos);
 678         kfree(state->comm);
 679         kfree(state->cmd);
 680         kfree(state->registers);
 681 }
 682
 683 static void adreno_gpu_state_kref_destroy(struct kref *kref)
 684 {
 685         struct msm_gpu_state *state = container_of(kref,
 686                 struct msm_gpu_state, ref);
 687
 688         adreno_gpu_state_destroy(state);
 689         kfree(state);
 690 }
 691
 692 int adreno_gpu_state_put(struct msm_gpu_state *state)
 693 {
 694         if (IS_ERR_OR_NULL(state))
 695                 return 1;
 696
 697         return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
 698 }
 699
 700 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
 701
 702 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
 703 {
 704         void *buf;
 705         size_t buf_itr = 0, buffer_size;
 706         char out[ASCII85_BUFSZ];
 707         long l;
 708         int i;
 709
 710         if (!src || !len)
 711                 return NULL;
 712
 713         l = ascii85_encode_len(len);
 714
 715         /*
 716          * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
 717          * account for the worst case of 5 bytes per dword plus the 1 for '\0'
 718          */
 719         buffer_size = (l * 5) + 1;
 720
 721         buf = kvmalloc(buffer_size, GFP_KERNEL);
 722         if (!buf)
 723                 return NULL;
 724
 725         for (i = 0; i < l; i++)
 726                 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
 727                                 ascii85_encode(src[i], out));
 728
 729         return buf;
 730 }
 731
 732 /* len is expected to be in bytes
 733  *
 734  * WARNING: *ptr should be allocated with kvmalloc or friends.  It can be free'd
 735  * with kvfree() and replaced with a newly kvmalloc'd buffer on the first call
 736  * when the unencoded raw data is encoded
 737  */
 738 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
 739                 bool *encoded)
 740 {
 741         if (!*ptr || !len)
 742                 return;
 743
 744         if (!*encoded) {
 745                 long datalen, i;
 746                 u32 *buf = *ptr;
 747
 748                 /*
 749                  * Only dump the non-zero part of the buffer - rarely will
 750                  * any data completely fill the entire allocated size of
 751                  * the buffer.
 752                  */
 753                 for (datalen = 0, i = 0; i < len >> 2; i++)
 754                         if (buf[i])
 755                                 datalen = ((i + 1) << 2);
 756
 757                 /*
 758                  * If we reach here, then the originally captured binary buffer
 759                  * will be replaced with the ascii85 encoded string
 760                  */
 761                 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
 762
 763                 kvfree(buf);
 764
 765                 *encoded = true;
 766         }
 767
 768         if (!*ptr)
 769                 return;
 770
 771         drm_puts(p, "    data: !!ascii85 |\n");
 772         drm_puts(p, "     ");
 773
 774         drm_puts(p, *ptr);
 775
 776         drm_puts(p, "\n");
 777 }
 778
 779 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 780                 struct drm_printer *p)
 781 {
 782         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 783         int i;
 784
 785         if (IS_ERR_OR_NULL(state))
 786                 return;
 787
 788         drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
 789                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 790                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 791                         adreno_gpu->rev.patchid);
 792         /*
 793          * If this is state collected due to iova fault, so fault related info
 794          *
 795          * TTBR0 would not be zero, so this is a good way to distinguish
 796          */
 797         if (state->fault_info.ttbr0) {
 798                 const struct msm_gpu_fault_info *info = &state->fault_info;
 799
 800                 drm_puts(p, "fault-info:\n");
 801                 drm_printf(p, "  - ttbr0=%.16llx\n", info->ttbr0);
 802                 drm_printf(p, "  - iova=%.16lx\n", info->iova);
 803                 drm_printf(p, "  - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
 804                 drm_printf(p, "  - type=%s\n", info->type);
 805                 drm_printf(p, "  - source=%s\n", info->block);
 806         }
 807
 808         drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
 809
 810         drm_puts(p, "ringbuffer:\n");
 811
 812         for (i = 0; i < gpu->nr_rings; i++) {
 813                 drm_printf(p, "  - id: %d\n", i);
 814                 drm_printf(p, "    iova: 0x%016llx\n", state->ring[i].iova);
 815                 drm_printf(p, "    last-fence: %u\n", state->ring[i].seqno);
 816                 drm_printf(p, "    retired-fence: %u\n", state->ring[i].fence);
 817                 drm_printf(p, "    rptr: %u\n", state->ring[i].rptr);
 818                 drm_printf(p, "    wptr: %u\n", state->ring[i].wptr);
 819                 drm_printf(p, "    size: %u\n", MSM_GPU_RINGBUFFER_SZ);
 820
 821                 adreno_show_object(p, &state->ring[i].data,
 822                         state->ring[i].data_size, &state->ring[i].encoded);
 823         }
 824
 825         if (state->bos) {
 826                 drm_puts(p, "bos:\n");
 827
 828                 for (i = 0; i < state->nr_bos; i++) {
 829                         drm_printf(p, "  - iova: 0x%016llx\n",
 830                                 state->bos[i].iova);
 831                         drm_printf(p, "    size: %zd\n", state->bos[i].size);
 832                         drm_printf(p, "    name: %-32s\n", state->bos[i].name);
 833
 834                         adreno_show_object(p, &state->bos[i].data,
 835                                 state->bos[i].size, &state->bos[i].encoded);
 836                 }
 837         }
 838
 839         if (state->nr_registers) {
 840                 drm_puts(p, "registers:\n");
 841
 842                 for (i = 0; i < state->nr_registers; i++) {
 843                         drm_printf(p, "  - { offset: 0x%04x, value: 0x%08x }\n",
 844                                 state->registers[i * 2] << 2,
 845                                 state->registers[(i * 2) + 1]);
 846                 }
 847         }
 848 }
 849 #endif
 850
 851 /* Dump common gpu status and scratch registers on any hang, to make
 852  * the hangcheck logs more useful.  The scratch registers seem always
 853  * safe to read when GPU has hung (unlike some other regs, depending
 854  * on how the GPU hung), and they are useful to match up to cmdstream
 855  * dumps when debugging hangs:
 856  */
 857 void adreno_dump_info(struct msm_gpu *gpu)
 858 {
 859         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 860         int i;
 861
 862         printk("revision: %d (%d.%d.%d.%d)\n",
 863                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 864                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 865                         adreno_gpu->rev.patchid);
 866
 867         for (i = 0; i < gpu->nr_rings; i++) {
 868                 struct msm_ringbuffer *ring = gpu->rb[i];
 869
 870                 printk("rb %d: fence:    %d/%d\n", i,
 871                         ring->memptrs->fence,
 872                         ring->fctx->last_fence);
 873
 874                 printk("rptr:     %d\n", get_rptr(adreno_gpu, ring));
 875                 printk("rb wptr:  %d\n", get_wptr(ring));
 876         }
 877 }
 878
 879 /* would be nice to not have to duplicate the _show() stuff with printk(): */
 880 void adreno_dump(struct msm_gpu *gpu)
 881 {
 882         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 883         int i;
 884
 885         if (!adreno_gpu->registers)
 886                 return;
 887
 888         /* dump these out in a form that can be parsed by demsm: */
 889         printk("IO:region %s 00000000 00020000\n", gpu->name);
 890         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 891                 uint32_t start = adreno_gpu->registers[i];
 892                 uint32_t end   = adreno_gpu->registers[i+1];
 893                 uint32_t addr;
 894
 895                 for (addr = start; addr <= end; addr++) {
 896                         uint32_t val = gpu_read(gpu, addr);
 897                         printk("IO:R %08x %08x\n", addr<<2, val);
 898                 }
 899         }
 900 }
 901
 902 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
 903 {
 904         struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
 905         uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
 906         /* Use ring->next to calculate free size */
 907         uint32_t wptr = ring->next - ring->start;
 908         uint32_t rptr = get_rptr(adreno_gpu, ring);
 909         return (rptr + (size - 1) - wptr) % size;
 910 }
 911
 912 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
 913 {
 914         if (spin_until(ring_freewords(ring) >= ndwords))
 915                 DRM_DEV_ERROR(ring->gpu->dev->dev,
 916                         "timeout waiting for space in ringbuffer %d\n",
 917                         ring->id);
 918 }
 919
 920 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
 921 static int adreno_get_legacy_pwrlevels(struct device *dev)
 922 {
 923         struct device_node *child, *node;
 924         int ret;
 925
 926         node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
 927         if (!node) {
 928                 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
 929                 return -ENXIO;
 930         }
 931
 932         for_each_child_of_node(node, child) {
 933                 unsigned int val;
 934
 935                 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
 936                 if (ret)
 937                         continue;
 938
 939                 /*
 940                  * Skip the intentionally bogus clock value found at the bottom
 941                  * of most legacy frequency tables
 942                  */
 943                 if (val != 27000000)
 944                         dev_pm_opp_add(dev, val, 0);
 945         }
 946
 947         of_node_put(node);
 948
 949         return 0;
 950 }
 951
 952 static void adreno_get_pwrlevels(struct device *dev,
 953                 struct msm_gpu *gpu)
 954 {
 955         unsigned long freq = ULONG_MAX;
 956         struct dev_pm_opp *opp;
 957         int ret;
 958
 959         gpu->fast_rate = 0;
 960
 961         /* You down with OPP? */
 962         if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
 963                 ret = adreno_get_legacy_pwrlevels(dev);
 964         else {
 965                 ret = devm_pm_opp_of_add_table(dev);
 966                 if (ret)
 967                         DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
 968         }
 969
 970         if (!ret) {
 971                 /* Find the fastest defined rate */
 972                 opp = dev_pm_opp_find_freq_floor(dev, &freq);
 973                 if (!IS_ERR(opp)) {
 974                         gpu->fast_rate = freq;
 975                         dev_pm_opp_put(opp);
 976                 }
 977         }
 978
 979         if (!gpu->fast_rate) {
 980                 dev_warn(dev,
 981                         "Could not find a clock rate. Using a reasonable default\n");
 982                 /* Pick a suitably safe clock speed for any target */
 983                 gpu->fast_rate = 200000000;
 984         }
 985
 986         DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
 987 }
 988
 989 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
 990                           struct adreno_ocmem *adreno_ocmem)
 991 {
 992         struct ocmem_buf *ocmem_hdl;
 993         struct ocmem *ocmem;
 994
 995         ocmem = of_get_ocmem(dev);
 996         if (IS_ERR(ocmem)) {
 997                 if (PTR_ERR(ocmem) == -ENODEV) {
 998                         /*
 999                          * Return success since either the ocmem property was
1000                          * not specified in device tree, or ocmem support is
1001                          * not compiled into the kernel.
1002                          */
1003                         return 0;
1004                 }
1005
1006                 return PTR_ERR(ocmem);
1007         }
1008
1009         ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
1010         if (IS_ERR(ocmem_hdl))
1011                 return PTR_ERR(ocmem_hdl);
1012
1013         adreno_ocmem->ocmem = ocmem;
1014         adreno_ocmem->base = ocmem_hdl->addr;
1015         adreno_ocmem->hdl = ocmem_hdl;
1016         adreno_gpu->gmem = ocmem_hdl->len;
1017
1018         return 0;
1019 }
1020
1021 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
1022 {
1023         if (adreno_ocmem && adreno_ocmem->base)
1024                 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
1025                            adreno_ocmem->hdl);
1026 }
1027
1028 int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1029 {
1030         return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
1031 }
1032
1033 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
1034                 struct adreno_gpu *adreno_gpu,
1035                 const struct adreno_gpu_funcs *funcs, int nr_rings)
1036 {
1037         struct device *dev = &pdev->dev;
1038         struct adreno_platform_config *config = dev->platform_data;
1039         struct msm_gpu_config adreno_gpu_config  = { 0 };
1040         struct msm_gpu *gpu = &adreno_gpu->base;
1041         struct adreno_rev *rev = &config->rev;
1042         const char *gpu_name;
1043         u32 speedbin;
1044
1045         adreno_gpu->funcs = funcs;
1046         adreno_gpu->info = adreno_info(config->rev);
1047         adreno_gpu->gmem = adreno_gpu->info->gmem;
1048         adreno_gpu->revn = adreno_gpu->info->revn;
1049         adreno_gpu->rev = *rev;
1050
1051         if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1052                 speedbin = 0xffff;
1053         adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1054
1055         gpu_name = adreno_gpu->info->name;
1056         if (!gpu_name) {
1057                 gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
1058                                 rev->core, rev->major, rev->minor,
1059                                 rev->patchid);
1060                 if (!gpu_name)
1061                         return -ENOMEM;
1062         }
1063
1064         adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1065
1066         adreno_gpu_config.nr_rings = nr_rings;
1067
1068         adreno_get_pwrlevels(dev, gpu);
1069
1070         pm_runtime_set_autosuspend_delay(dev,
1071                 adreno_gpu->info->inactive_period);
1072         pm_runtime_use_autosuspend(dev);
1073
1074         return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1075                         gpu_name, &adreno_gpu_config);
1076 }
1077
1078 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1079 {
1080         struct msm_gpu *gpu = &adreno_gpu->base;
1081         struct msm_drm_private *priv = gpu->dev->dev_private;
1082         unsigned int i;
1083
1084         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1085                 release_firmware(adreno_gpu->fw[i]);
1086
1087         if (pm_runtime_enabled(&priv->gpu_pdev->dev))
1088                 pm_runtime_disable(&priv->gpu_pdev->dev);
1089
1090         msm_gpu_cleanup(&adreno_gpu->base);
1091 }