1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
9 #include <linux/ascii85.h>
10 #include <linux/interconnect.h>
11 #include <linux/qcom_scm.h>
12 #include <linux/kernel.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_opp.h>
15 #include <linux/slab.h>
16 #include <linux/soc/qcom/mdt_loader.h>
17 #include <linux/nvmem-consumer.h>
18 #include <soc/qcom/ocmem.h>
19 #include "adreno_gpu.h"
24 static u64 address_space_size = 0;
25 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
26 module_param(address_space_size, ullong, 0600);
28 static bool zap_available = true;
30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
33 struct device *dev = &gpu->pdev->dev;
34 const struct firmware *fw;
35 const char *signed_fwname = NULL;
36 struct device_node *np, *mem_np;
40 void *mem_region = NULL;
43 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
44 zap_available = false;
48 np = of_get_child_by_name(dev->of_node, "zap-shader");
50 zap_available = false;
54 mem_np = of_parse_phandle(np, "memory-region", 0);
57 zap_available = false;
61 ret = of_address_to_resource(mem_np, 0, &r);
69 * Check for a firmware-name property. This is the new scheme
70 * to handle firmware that may be signed with device specific
71 * keys, allowing us to have a different zap fw path for different
74 * If the firmware-name property is found, we bypass the
75 * adreno_request_fw() mechanism, because we don't need to handle
76 * the /lib/firmware/qcom/... vs /lib/firmware/... case.
78 * If the firmware-name property is not found, for backwards
79 * compatibility we fall back to the fwname from the gpulist
82 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
84 fwname = signed_fwname;
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
89 /* Request the MDT file from the default location: */
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
93 * For new targets, we require the firmware-name property,
94 * if a zap-shader is required, rather than falling back
95 * to a firmware name specified in gpulist.
97 * Because the firmware is signed with a (potentially)
98 * device specific key, having the name come from gpulist
99 * was a bad idea, and is only provided for backwards
100 * compatibility for older targets.
106 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
110 /* Figure out how much memory we need */
111 mem_size = qcom_mdt_get_size(fw);
117 if (mem_size > resource_size(&r)) {
119 "memory region is too small to load the MDT\n");
124 /* Allocate memory for the firmware image */
125 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC);
132 * Load the rest of the MDT
134 * Note that we could be dealing with two different paths, since
135 * with upstream linux-firmware it would be in a qcom/ subdir..
136 * adreno_request_fw() handles this, but qcom_mdt_load() does
137 * not. But since we've already gotten through adreno_request_fw()
138 * we know which of the two cases it is:
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
141 ret = qcom_mdt_load(dev, fw, fwname, pasid,
142 mem_region, mem_phys, mem_size, NULL);
146 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
148 ret = qcom_mdt_load(dev, fw, newname, pasid,
149 mem_region, mem_phys, mem_size, NULL);
155 /* Send the image to the secure world */
156 ret = qcom_scm_pas_auth_and_reset(pasid);
159 * If the scm call returns -EOPNOTSUPP we assume that this target
160 * doesn't need/support the zap shader so quietly fail
162 if (ret == -EOPNOTSUPP)
163 zap_available = false;
165 DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
169 memunmap(mem_region);
171 release_firmware(fw);
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
179 struct platform_device *pdev = gpu->pdev;
181 /* Short cut if we determine the zap shader isn't available/needed */
185 /* We need SCM to be able to load the firmware */
186 if (!qcom_scm_is_available()) {
187 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
188 return -EPROBE_DEFER;
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
194 void adreno_set_llc_attributes(struct iommu_domain *iommu)
196 iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA);
199 struct msm_gem_address_space *
200 adreno_iommu_create_address_space(struct msm_gpu *gpu,
201 struct platform_device *pdev)
203 struct iommu_domain *iommu;
205 struct msm_gem_address_space *aspace;
208 iommu = iommu_domain_alloc(&platform_bus_type);
212 mmu = msm_iommu_new(&pdev->dev, iommu);
214 iommu_domain_free(iommu);
215 return ERR_CAST(mmu);
219 * Use the aperture start or SZ_16M, whichever is greater. This will
220 * ensure that we align with the allocated pagetable range while still
221 * allowing room in the lower 32 bits for GMEM and whatnot
223 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
224 size = iommu->geometry.aperture_end - start + 1;
226 aspace = msm_gem_address_space_create(mmu, "gpu",
227 start & GENMASK_ULL(48, 0), size);
229 if (IS_ERR(aspace) && !IS_ERR(mmu))
230 mmu->funcs->destroy(mmu);
235 u64 adreno_private_address_space_size(struct msm_gpu *gpu)
237 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
239 if (address_space_size)
240 return address_space_size;
242 if (adreno_gpu->info->address_space_size)
243 return adreno_gpu->info->address_space_size;
248 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
249 uint32_t param, uint64_t *value, uint32_t *len)
251 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
253 /* No pointer params yet */
258 case MSM_PARAM_GPU_ID:
259 *value = adreno_gpu->info->revn;
261 case MSM_PARAM_GMEM_SIZE:
262 *value = adreno_gpu->gmem;
264 case MSM_PARAM_GMEM_BASE:
265 *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
267 case MSM_PARAM_CHIP_ID:
268 *value = (uint64_t)adreno_gpu->rev.patchid |
269 ((uint64_t)adreno_gpu->rev.minor << 8) |
270 ((uint64_t)adreno_gpu->rev.major << 16) |
271 ((uint64_t)adreno_gpu->rev.core << 24);
272 if (!adreno_gpu->info->revn)
273 *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
275 case MSM_PARAM_MAX_FREQ:
276 *value = adreno_gpu->base.fast_rate;
278 case MSM_PARAM_TIMESTAMP:
279 if (adreno_gpu->funcs->get_timestamp) {
282 pm_runtime_get_sync(&gpu->pdev->dev);
283 ret = adreno_gpu->funcs->get_timestamp(gpu, value);
284 pm_runtime_put_autosuspend(&gpu->pdev->dev);
289 case MSM_PARAM_PRIORITIES:
290 *value = gpu->nr_rings * NR_SCHED_PRIORITIES;
292 case MSM_PARAM_PP_PGTABLE:
295 case MSM_PARAM_FAULTS:
297 *value = gpu->global_faults + ctx->aspace->faults;
299 *value = gpu->global_faults;
301 case MSM_PARAM_SUSPENDS:
302 *value = gpu->suspend_count;
304 case MSM_PARAM_VA_START:
305 if (ctx->aspace == gpu->aspace)
307 *value = ctx->aspace->va_start;
309 case MSM_PARAM_VA_SIZE:
310 if (ctx->aspace == gpu->aspace)
312 *value = ctx->aspace->va_size;
315 DBG("%s: invalid param: %u", gpu->name, param);
320 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
321 uint32_t param, uint64_t value, uint32_t len)
325 case MSM_PARAM_CMDLINE:
326 /* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so
327 * that should be a reasonable upper bound
339 case MSM_PARAM_CMDLINE: {
342 str = kmalloc(len + 1, GFP_KERNEL);
346 if (copy_from_user(str, u64_to_user_ptr(value), len)) {
351 /* Ensure string is null terminated: */
354 if (param == MSM_PARAM_COMM) {
357 paramp = &ctx->cmdline;
365 case MSM_PARAM_SYSPROF:
366 if (!capable(CAP_SYS_ADMIN))
368 return msm_file_private_set_sysprof(ctx, gpu, value);
370 DBG("%s: invalid param: %u", gpu->name, param);
375 const struct firmware *
376 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
378 struct drm_device *drm = adreno_gpu->base.dev;
379 const struct firmware *fw = NULL;
383 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
385 return ERR_PTR(-ENOMEM);
388 * Try first to load from qcom/$fwfile using a direct load (to avoid
389 * a potential timeout waiting for usermode helper)
391 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
392 (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
394 ret = request_firmware_direct(&fw, newname, drm->dev);
396 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
398 adreno_gpu->fwloc = FW_LOCATION_NEW;
400 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
401 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
409 * Then try the legacy location without qcom/ prefix
411 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
412 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
414 ret = request_firmware_direct(&fw, fwname, drm->dev);
416 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
418 adreno_gpu->fwloc = FW_LOCATION_LEGACY;
420 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
421 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
429 * Finally fall back to request_firmware() for cases where the
430 * usermode helper is needed (I think mainly android)
432 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
433 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
435 ret = request_firmware(&fw, newname, drm->dev);
437 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
439 adreno_gpu->fwloc = FW_LOCATION_HELPER;
441 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
442 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
449 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
450 fw = ERR_PTR(-ENOENT);
456 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
460 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
461 const struct firmware *fw;
463 if (!adreno_gpu->info->fw[i])
466 /* Skip if the firmware has already been loaded */
467 if (adreno_gpu->fw[i])
470 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
474 adreno_gpu->fw[i] = fw;
480 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
481 const struct firmware *fw, u64 *iova)
483 struct drm_gem_object *bo;
486 ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
487 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
490 return ERR_CAST(ptr);
492 memcpy(ptr, &fw->data[4], fw->size - 4);
494 msm_gem_put_vaddr(bo);
499 int adreno_hw_init(struct msm_gpu *gpu)
501 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
504 VERB("%s", gpu->name);
506 ret = adreno_load_fw(adreno_gpu);
510 for (i = 0; i < gpu->nr_rings; i++) {
511 struct msm_ringbuffer *ring = gpu->rb[i];
516 ring->cur = ring->start;
517 ring->next = ring->start;
518 ring->memptrs->rptr = 0;
520 /* Detect and clean up an impossible fence, ie. if GPU managed
521 * to scribble something invalid, we don't want that to confuse
522 * us into mistakingly believing that submits have completed.
524 if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
525 ring->memptrs->fence = ring->fctx->last_fence;
532 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
533 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
534 struct msm_ringbuffer *ring)
536 struct msm_gpu *gpu = &adreno_gpu->base;
538 return gpu->funcs->get_rptr(gpu, ring);
541 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
546 void adreno_recover(struct msm_gpu *gpu)
548 struct drm_device *dev = gpu->dev;
551 // XXX pm-runtime?? we *need* the device to be off after this
552 // so maybe continuing to call ->pm_suspend/resume() is better?
554 gpu->funcs->pm_suspend(gpu);
555 gpu->funcs->pm_resume(gpu);
557 ret = msm_gpu_hw_init(gpu);
559 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
564 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)
568 /* Copy the shadow to the actual register */
569 ring->cur = ring->next;
572 * Mask wptr value that we calculate to fit in the HW range. This is
573 * to account for the possibility that the last command fit exactly into
574 * the ringbuffer and rb->next hasn't wrapped to zero yet
576 wptr = get_wptr(ring);
578 /* ensure writes to ringbuffer have hit system memory: */
581 gpu_write(gpu, reg, wptr);
584 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
586 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
587 uint32_t wptr = get_wptr(ring);
589 /* wait for CP to drain ringbuffer: */
590 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
593 /* TODO maybe we need to reset GPU here to recover from hang? */
594 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
595 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
600 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
602 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
605 WARN_ON(!mutex_is_locked(&gpu->lock));
607 kref_init(&state->ref);
609 ktime_get_real_ts64(&state->time);
611 for (i = 0; i < gpu->nr_rings; i++) {
614 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
615 state->ring[i].iova = gpu->rb[i]->iova;
616 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence;
617 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
618 state->ring[i].wptr = get_wptr(gpu->rb[i]);
620 /* Copy at least 'wptr' dwords of the data */
621 size = state->ring[i].wptr;
623 /* After wptr find the last non zero dword to save space */
624 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
625 if (gpu->rb[i]->start[j])
629 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
630 if (state->ring[i].data) {
631 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
632 state->ring[i].data_size = size << 2;
637 /* Some targets prefer to collect their own registers */
638 if (!adreno_gpu->registers)
641 /* Count the number of registers */
642 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
643 count += adreno_gpu->registers[i + 1] -
644 adreno_gpu->registers[i] + 1;
646 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
647 if (state->registers) {
650 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
651 u32 start = adreno_gpu->registers[i];
652 u32 end = adreno_gpu->registers[i + 1];
655 for (addr = start; addr <= end; addr++) {
656 state->registers[pos++] = addr;
657 state->registers[pos++] = gpu_read(gpu, addr);
661 state->nr_registers = count;
667 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
671 for (i = 0; i < ARRAY_SIZE(state->ring); i++)
672 kvfree(state->ring[i].data);
674 for (i = 0; state->bos && i < state->nr_bos; i++)
675 kvfree(state->bos[i].data);
680 kfree(state->registers);
683 static void adreno_gpu_state_kref_destroy(struct kref *kref)
685 struct msm_gpu_state *state = container_of(kref,
686 struct msm_gpu_state, ref);
688 adreno_gpu_state_destroy(state);
692 int adreno_gpu_state_put(struct msm_gpu_state *state)
694 if (IS_ERR_OR_NULL(state))
697 return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
700 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
702 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
705 size_t buf_itr = 0, buffer_size;
706 char out[ASCII85_BUFSZ];
713 l = ascii85_encode_len(len);
716 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
717 * account for the worst case of 5 bytes per dword plus the 1 for '\0'
719 buffer_size = (l * 5) + 1;
721 buf = kvmalloc(buffer_size, GFP_KERNEL);
725 for (i = 0; i < l; i++)
726 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
727 ascii85_encode(src[i], out));
732 /* len is expected to be in bytes */
733 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
744 * Only dump the non-zero part of the buffer - rarely will
745 * any data completely fill the entire allocated size of
748 for (datalen = 0, i = 0; i < len >> 2; i++)
750 datalen = ((i + 1) << 2);
753 * If we reach here, then the originally captured binary buffer
754 * will be replaced with the ascii85 encoded string
756 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
766 drm_puts(p, " data: !!ascii85 |\n");
774 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
775 struct drm_printer *p)
777 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
780 if (IS_ERR_OR_NULL(state))
783 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
784 adreno_gpu->info->revn, adreno_gpu->rev.core,
785 adreno_gpu->rev.major, adreno_gpu->rev.minor,
786 adreno_gpu->rev.patchid);
788 * If this is state collected due to iova fault, so fault related info
790 * TTBR0 would not be zero, so this is a good way to distinguish
792 if (state->fault_info.ttbr0) {
793 const struct msm_gpu_fault_info *info = &state->fault_info;
795 drm_puts(p, "fault-info:\n");
796 drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0);
797 drm_printf(p, " - iova=%.16lx\n", info->iova);
798 drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
799 drm_printf(p, " - type=%s\n", info->type);
800 drm_printf(p, " - source=%s\n", info->block);
803 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
805 drm_puts(p, "ringbuffer:\n");
807 for (i = 0; i < gpu->nr_rings; i++) {
808 drm_printf(p, " - id: %d\n", i);
809 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova);
810 drm_printf(p, " last-fence: %u\n", state->ring[i].seqno);
811 drm_printf(p, " retired-fence: %u\n", state->ring[i].fence);
812 drm_printf(p, " rptr: %u\n", state->ring[i].rptr);
813 drm_printf(p, " wptr: %u\n", state->ring[i].wptr);
814 drm_printf(p, " size: %u\n", MSM_GPU_RINGBUFFER_SZ);
816 adreno_show_object(p, &state->ring[i].data,
817 state->ring[i].data_size, &state->ring[i].encoded);
821 drm_puts(p, "bos:\n");
823 for (i = 0; i < state->nr_bos; i++) {
824 drm_printf(p, " - iova: 0x%016llx\n",
826 drm_printf(p, " size: %zd\n", state->bos[i].size);
827 drm_printf(p, " name: %-32s\n", state->bos[i].name);
829 adreno_show_object(p, &state->bos[i].data,
830 state->bos[i].size, &state->bos[i].encoded);
834 if (state->nr_registers) {
835 drm_puts(p, "registers:\n");
837 for (i = 0; i < state->nr_registers; i++) {
838 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n",
839 state->registers[i * 2] << 2,
840 state->registers[(i * 2) + 1]);
846 /* Dump common gpu status and scratch registers on any hang, to make
847 * the hangcheck logs more useful. The scratch registers seem always
848 * safe to read when GPU has hung (unlike some other regs, depending
849 * on how the GPU hung), and they are useful to match up to cmdstream
850 * dumps when debugging hangs:
852 void adreno_dump_info(struct msm_gpu *gpu)
854 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
857 printk("revision: %d (%d.%d.%d.%d)\n",
858 adreno_gpu->info->revn, adreno_gpu->rev.core,
859 adreno_gpu->rev.major, adreno_gpu->rev.minor,
860 adreno_gpu->rev.patchid);
862 for (i = 0; i < gpu->nr_rings; i++) {
863 struct msm_ringbuffer *ring = gpu->rb[i];
865 printk("rb %d: fence: %d/%d\n", i,
866 ring->memptrs->fence,
867 ring->fctx->last_fence);
869 printk("rptr: %d\n", get_rptr(adreno_gpu, ring));
870 printk("rb wptr: %d\n", get_wptr(ring));
874 /* would be nice to not have to duplicate the _show() stuff with printk(): */
875 void adreno_dump(struct msm_gpu *gpu)
877 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
880 if (!adreno_gpu->registers)
883 /* dump these out in a form that can be parsed by demsm: */
884 printk("IO:region %s 00000000 00020000\n", gpu->name);
885 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
886 uint32_t start = adreno_gpu->registers[i];
887 uint32_t end = adreno_gpu->registers[i+1];
890 for (addr = start; addr <= end; addr++) {
891 uint32_t val = gpu_read(gpu, addr);
892 printk("IO:R %08x %08x\n", addr<<2, val);
897 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
899 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
900 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
901 /* Use ring->next to calculate free size */
902 uint32_t wptr = ring->next - ring->start;
903 uint32_t rptr = get_rptr(adreno_gpu, ring);
904 return (rptr + (size - 1) - wptr) % size;
907 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
909 if (spin_until(ring_freewords(ring) >= ndwords))
910 DRM_DEV_ERROR(ring->gpu->dev->dev,
911 "timeout waiting for space in ringbuffer %d\n",
915 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
916 static int adreno_get_legacy_pwrlevels(struct device *dev)
918 struct device_node *child, *node;
921 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
923 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
927 for_each_child_of_node(node, child) {
930 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
935 * Skip the intentionally bogus clock value found at the bottom
936 * of most legacy frequency tables
939 dev_pm_opp_add(dev, val, 0);
947 static void adreno_get_pwrlevels(struct device *dev,
950 unsigned long freq = ULONG_MAX;
951 struct dev_pm_opp *opp;
956 /* You down with OPP? */
957 if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
958 ret = adreno_get_legacy_pwrlevels(dev);
960 ret = devm_pm_opp_of_add_table(dev);
962 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
966 /* Find the fastest defined rate */
967 opp = dev_pm_opp_find_freq_floor(dev, &freq);
969 gpu->fast_rate = freq;
974 if (!gpu->fast_rate) {
976 "Could not find a clock rate. Using a reasonable default\n");
977 /* Pick a suitably safe clock speed for any target */
978 gpu->fast_rate = 200000000;
981 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
984 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
985 struct adreno_ocmem *adreno_ocmem)
987 struct ocmem_buf *ocmem_hdl;
990 ocmem = of_get_ocmem(dev);
992 if (PTR_ERR(ocmem) == -ENODEV) {
994 * Return success since either the ocmem property was
995 * not specified in device tree, or ocmem support is
996 * not compiled into the kernel.
1001 return PTR_ERR(ocmem);
1004 ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
1005 if (IS_ERR(ocmem_hdl))
1006 return PTR_ERR(ocmem_hdl);
1008 adreno_ocmem->ocmem = ocmem;
1009 adreno_ocmem->base = ocmem_hdl->addr;
1010 adreno_ocmem->hdl = ocmem_hdl;
1011 adreno_gpu->gmem = ocmem_hdl->len;
1016 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
1018 if (adreno_ocmem && adreno_ocmem->base)
1019 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
1023 int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1025 return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
1028 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
1029 struct adreno_gpu *adreno_gpu,
1030 const struct adreno_gpu_funcs *funcs, int nr_rings)
1032 struct device *dev = &pdev->dev;
1033 struct adreno_platform_config *config = dev->platform_data;
1034 struct msm_gpu_config adreno_gpu_config = { 0 };
1035 struct msm_gpu *gpu = &adreno_gpu->base;
1036 struct adreno_rev *rev = &config->rev;
1037 const char *gpu_name;
1040 adreno_gpu->funcs = funcs;
1041 adreno_gpu->info = adreno_info(config->rev);
1042 adreno_gpu->gmem = adreno_gpu->info->gmem;
1043 adreno_gpu->revn = adreno_gpu->info->revn;
1044 adreno_gpu->rev = *rev;
1046 if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1048 adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1050 gpu_name = adreno_gpu->info->name;
1052 gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
1053 rev->core, rev->major, rev->minor,
1059 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1061 adreno_gpu_config.nr_rings = nr_rings;
1063 adreno_get_pwrlevels(dev, gpu);
1065 pm_runtime_set_autosuspend_delay(dev,
1066 adreno_gpu->info->inactive_period);
1067 pm_runtime_use_autosuspend(dev);
1069 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1070 gpu_name, &adreno_gpu_config);
1073 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1075 struct msm_gpu *gpu = &adreno_gpu->base;
1076 struct msm_drm_private *priv = gpu->dev->dev_private;
1079 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1080 release_firmware(adreno_gpu->fw[i]);
1082 if (pm_runtime_enabled(&priv->gpu_pdev->dev))
1083 pm_runtime_disable(&priv->gpu_pdev->dev);
1085 msm_gpu_cleanup(&adreno_gpu->base);