1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
4 #include <linux/ascii85.h>
8 #include "a6xx_gpu_state.h"
9 #include "a6xx_gmu.xml.h"
11 struct a6xx_gpu_state_obj {
16 struct a6xx_gpu_state {
17 struct msm_gpu_state base;
19 struct a6xx_gpu_state_obj *gmu_registers;
22 struct a6xx_gpu_state_obj *registers;
25 struct a6xx_gpu_state_obj *shaders;
28 struct a6xx_gpu_state_obj *clusters;
31 struct a6xx_gpu_state_obj *dbgahb_clusters;
32 int nr_dbgahb_clusters;
34 struct a6xx_gpu_state_obj *indexed_regs;
37 struct a6xx_gpu_state_obj *debugbus;
40 struct a6xx_gpu_state_obj *vbif_debugbus;
42 struct a6xx_gpu_state_obj *cx_debugbus;
45 struct msm_gpu_state_bo *gmu_log;
46 struct msm_gpu_state_bo *gmu_hfi;
47 struct msm_gpu_state_bo *gmu_debug;
49 s32 hfi_queue_history[2][HFI_HISTORY_SZ];
51 struct list_head objs;
56 static inline int CRASHDUMP_WRITE(u64 *in, u32 reg, u32 val)
59 in[1] = (((u64) reg) << 44 | (1 << 21) | 1);
64 static inline int CRASHDUMP_READ(u64 *in, u32 reg, u32 dwords, u64 target)
67 in[1] = (((u64) reg) << 44 | dwords);
72 static inline int CRASHDUMP_FINI(u64 *in)
80 struct a6xx_crashdumper {
82 struct drm_gem_object *bo;
86 struct a6xx_state_memobj {
87 struct list_head node;
88 unsigned long long data[];
91 static void *state_kcalloc(struct a6xx_gpu_state *a6xx_state, int nr, size_t objsize)
93 struct a6xx_state_memobj *obj =
94 kvzalloc((nr * objsize) + sizeof(*obj), GFP_KERNEL);
99 list_add_tail(&obj->node, &a6xx_state->objs);
103 static void *state_kmemdup(struct a6xx_gpu_state *a6xx_state, void *src,
106 void *dst = state_kcalloc(a6xx_state, 1, size);
109 memcpy(dst, src, size);
114 * Allocate 1MB for the crashdumper scratch region - 8k for the script and
115 * the rest for the data
117 #define A6XX_CD_DATA_OFFSET 8192
118 #define A6XX_CD_DATA_SIZE (SZ_1M - 8192)
120 static int a6xx_crashdumper_init(struct msm_gpu *gpu,
121 struct a6xx_crashdumper *dumper)
123 dumper->ptr = msm_gem_kernel_new(gpu->dev,
124 SZ_1M, MSM_BO_WC, gpu->aspace,
125 &dumper->bo, &dumper->iova);
127 if (!IS_ERR(dumper->ptr))
128 msm_gem_object_set_name(dumper->bo, "crashdump");
130 return PTR_ERR_OR_ZERO(dumper->ptr);
133 static int a6xx_crashdumper_run(struct msm_gpu *gpu,
134 struct a6xx_crashdumper *dumper)
136 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
137 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
141 if (IS_ERR_OR_NULL(dumper->ptr))
144 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu))
147 /* Make sure all pending memory writes are posted */
150 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO,
151 REG_A6XX_CP_CRASH_SCRIPT_BASE_HI, dumper->iova);
153 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1);
155 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val,
156 val & 0x02, 100, 10000);
158 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0);
163 /* read a value from the GX debug bus */
164 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
167 u32 reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) |
168 A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block);
170 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg);
171 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg);
172 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg);
173 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg);
175 /* Wait 1 us to make sure the data is flowing */
178 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2);
179 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1);
184 #define cxdbg_write(ptr, offset, val) \
185 msm_writel((val), (ptr) + ((offset) << 2))
187 #define cxdbg_read(ptr, offset) \
188 msm_readl((ptr) + ((offset) << 2))
190 /* read a value from the CX debug bus */
191 static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,
194 u32 reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) |
195 A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block);
197 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A, reg);
198 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B, reg);
199 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C, reg);
200 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D, reg);
202 /* Wait 1 us to make sure the data is flowing */
205 data[0] = cxdbg_read(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2);
206 data[1] = cxdbg_read(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1);
211 /* Read a chunk of data from the VBIF debug bus */
212 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1,
213 u32 reg, int count, u32 *data)
217 gpu_write(gpu, ctrl0, reg);
219 for (i = 0; i < count; i++) {
220 gpu_write(gpu, ctrl1, i);
221 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT);
227 #define AXI_ARB_BLOCKS 2
228 #define XIN_AXI_BLOCKS 5
229 #define XIN_CORE_BLOCKS 4
231 #define VBIF_DEBUGBUS_BLOCK_SIZE \
232 ((16 * AXI_ARB_BLOCKS) + \
233 (18 * XIN_AXI_BLOCKS) + \
234 (12 * XIN_CORE_BLOCKS))
236 static void a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu,
237 struct a6xx_gpu_state *a6xx_state,
238 struct a6xx_gpu_state_obj *obj)
243 obj->data = state_kcalloc(a6xx_state, VBIF_DEBUGBUS_BLOCK_SIZE,
250 /* Get the current clock setting */
251 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON);
253 /* Force on the bus so we can read it */
254 gpu_write(gpu, REG_A6XX_VBIF_CLKON,
255 clk | A6XX_VBIF_CLKON_FORCE_ON_TESTBUS);
257 /* We will read from BUS2 first, so disable BUS1 */
258 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0);
260 /* Enable the VBIF bus for reading */
261 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS_OUT_CTRL, 1);
265 for (i = 0; i < AXI_ARB_BLOCKS; i++)
266 ptr += vbif_debugbus_read(gpu,
267 REG_A6XX_VBIF_TEST_BUS2_CTRL0,
268 REG_A6XX_VBIF_TEST_BUS2_CTRL1,
269 1 << (i + 16), 16, ptr);
271 for (i = 0; i < XIN_AXI_BLOCKS; i++)
272 ptr += vbif_debugbus_read(gpu,
273 REG_A6XX_VBIF_TEST_BUS2_CTRL0,
274 REG_A6XX_VBIF_TEST_BUS2_CTRL1,
277 /* Stop BUS2 so we can turn on BUS1 */
278 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS2_CTRL0, 0);
280 for (i = 0; i < XIN_CORE_BLOCKS; i++)
281 ptr += vbif_debugbus_read(gpu,
282 REG_A6XX_VBIF_TEST_BUS1_CTRL0,
283 REG_A6XX_VBIF_TEST_BUS1_CTRL1,
286 /* Restore the VBIF clock setting */
287 gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk);
290 static void a6xx_get_debugbus_block(struct msm_gpu *gpu,
291 struct a6xx_gpu_state *a6xx_state,
292 const struct a6xx_debugbus_block *block,
293 struct a6xx_gpu_state_obj *obj)
298 obj->data = state_kcalloc(a6xx_state, block->count, sizeof(u64));
304 for (ptr = obj->data, i = 0; i < block->count; i++)
305 ptr += debugbus_read(gpu, block->id, i, ptr);
308 static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg,
309 struct a6xx_gpu_state *a6xx_state,
310 const struct a6xx_debugbus_block *block,
311 struct a6xx_gpu_state_obj *obj)
316 obj->data = state_kcalloc(a6xx_state, block->count, sizeof(u64));
322 for (ptr = obj->data, i = 0; i < block->count; i++)
323 ptr += cx_debugbus_read(cxdbg, block->id, i, ptr);
326 static void a6xx_get_debugbus(struct msm_gpu *gpu,
327 struct a6xx_gpu_state *a6xx_state)
329 struct resource *res;
330 void __iomem *cxdbg = NULL;
331 int nr_debugbus_blocks;
333 /* Set up the GX debug bus */
335 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT,
336 A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(0xf));
338 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM,
339 A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(0xf));
341 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0);
342 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0);
343 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0);
344 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0);
346 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210);
347 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98);
349 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0);
350 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0);
351 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0);
352 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0);
354 /* Set up the CX debug bus - it lives elsewhere in the system so do a
355 * temporary ioremap for the registers
357 res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM,
361 cxdbg = ioremap(res->start, resource_size(res));
364 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT,
365 A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(0xf));
367 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM,
368 A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(0xf));
370 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0, 0);
371 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1, 0);
372 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2, 0);
373 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3, 0);
375 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0,
377 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1,
380 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0, 0);
381 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1, 0);
382 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2, 0);
383 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0);
386 nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
387 (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
389 a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks,
390 sizeof(*a6xx_state->debugbus));
392 if (a6xx_state->debugbus) {
395 for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++)
396 a6xx_get_debugbus_block(gpu,
398 &a6xx_debugbus_blocks[i],
399 &a6xx_state->debugbus[i]);
401 a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
404 * GBIF has same debugbus as of other GPU blocks, fall back to
405 * default path if GPU uses GBIF, also GBIF uses exactly same
408 if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
409 a6xx_get_debugbus_block(gpu, a6xx_state,
410 &a6xx_gbif_debugbus_block,
411 &a6xx_state->debugbus[i]);
413 a6xx_state->nr_debugbus += 1;
417 /* Dump the VBIF debugbus on applicable targets */
418 if (!a6xx_has_gbif(to_adreno_gpu(gpu))) {
419 a6xx_state->vbif_debugbus =
420 state_kcalloc(a6xx_state, 1,
421 sizeof(*a6xx_state->vbif_debugbus));
423 if (a6xx_state->vbif_debugbus)
424 a6xx_get_vbif_debugbus_block(gpu, a6xx_state,
425 a6xx_state->vbif_debugbus);
429 a6xx_state->cx_debugbus =
430 state_kcalloc(a6xx_state,
431 ARRAY_SIZE(a6xx_cx_debugbus_blocks),
432 sizeof(*a6xx_state->cx_debugbus));
434 if (a6xx_state->cx_debugbus) {
437 for (i = 0; i < ARRAY_SIZE(a6xx_cx_debugbus_blocks); i++)
438 a6xx_get_cx_debugbus_block(cxdbg,
440 &a6xx_cx_debugbus_blocks[i],
441 &a6xx_state->cx_debugbus[i]);
443 a6xx_state->nr_cx_debugbus =
444 ARRAY_SIZE(a6xx_cx_debugbus_blocks);
451 #define RANGE(reg, a) ((reg)[(a) + 1] - (reg)[(a)] + 1)
453 /* Read a data cluster from behind the AHB aperture */
454 static void a6xx_get_dbgahb_cluster(struct msm_gpu *gpu,
455 struct a6xx_gpu_state *a6xx_state,
456 const struct a6xx_dbgahb_cluster *dbgahb,
457 struct a6xx_gpu_state_obj *obj,
458 struct a6xx_crashdumper *dumper)
460 u64 *in = dumper->ptr;
461 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
465 for (i = 0; i < A6XX_NUM_CONTEXTS; i++) {
468 in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL,
469 (dbgahb->statetype + i * 2) << 8);
471 for (j = 0; j < dbgahb->count; j += 2) {
472 int count = RANGE(dbgahb->registers, j);
473 u32 offset = REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE +
474 dbgahb->registers[j] - (dbgahb->base >> 2);
476 in += CRASHDUMP_READ(in, offset, count, out);
478 out += count * sizeof(u32);
487 datasize = regcount * A6XX_NUM_CONTEXTS * sizeof(u32);
489 if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
492 if (a6xx_crashdumper_run(gpu, dumper))
495 obj->handle = dbgahb;
496 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
500 static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu,
501 struct a6xx_gpu_state *a6xx_state,
502 struct a6xx_crashdumper *dumper)
506 a6xx_state->dbgahb_clusters = state_kcalloc(a6xx_state,
507 ARRAY_SIZE(a6xx_dbgahb_clusters),
508 sizeof(*a6xx_state->dbgahb_clusters));
510 if (!a6xx_state->dbgahb_clusters)
513 a6xx_state->nr_dbgahb_clusters = ARRAY_SIZE(a6xx_dbgahb_clusters);
515 for (i = 0; i < ARRAY_SIZE(a6xx_dbgahb_clusters); i++)
516 a6xx_get_dbgahb_cluster(gpu, a6xx_state,
517 &a6xx_dbgahb_clusters[i],
518 &a6xx_state->dbgahb_clusters[i], dumper);
521 /* Read a data cluster from the CP aperture with the crashdumper */
522 static void a6xx_get_cluster(struct msm_gpu *gpu,
523 struct a6xx_gpu_state *a6xx_state,
524 const struct a6xx_cluster *cluster,
525 struct a6xx_gpu_state_obj *obj,
526 struct a6xx_crashdumper *dumper)
528 u64 *in = dumper->ptr;
529 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
533 /* Some clusters need a selector register to be programmed too */
534 if (cluster->sel_reg)
535 in += CRASHDUMP_WRITE(in, cluster->sel_reg, cluster->sel_val);
537 for (i = 0; i < A6XX_NUM_CONTEXTS; i++) {
540 in += CRASHDUMP_WRITE(in, REG_A6XX_CP_APERTURE_CNTL_CD,
541 (cluster->id << 8) | (i << 4) | i);
543 for (j = 0; j < cluster->count; j += 2) {
544 int count = RANGE(cluster->registers, j);
546 in += CRASHDUMP_READ(in, cluster->registers[j],
549 out += count * sizeof(u32);
558 datasize = regcount * A6XX_NUM_CONTEXTS * sizeof(u32);
560 if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
563 if (a6xx_crashdumper_run(gpu, dumper))
566 obj->handle = cluster;
567 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
571 static void a6xx_get_clusters(struct msm_gpu *gpu,
572 struct a6xx_gpu_state *a6xx_state,
573 struct a6xx_crashdumper *dumper)
577 a6xx_state->clusters = state_kcalloc(a6xx_state,
578 ARRAY_SIZE(a6xx_clusters), sizeof(*a6xx_state->clusters));
580 if (!a6xx_state->clusters)
583 a6xx_state->nr_clusters = ARRAY_SIZE(a6xx_clusters);
585 for (i = 0; i < ARRAY_SIZE(a6xx_clusters); i++)
586 a6xx_get_cluster(gpu, a6xx_state, &a6xx_clusters[i],
587 &a6xx_state->clusters[i], dumper);
590 /* Read a shader / debug block from the HLSQ aperture with the crashdumper */
591 static void a6xx_get_shader_block(struct msm_gpu *gpu,
592 struct a6xx_gpu_state *a6xx_state,
593 const struct a6xx_shader_block *block,
594 struct a6xx_gpu_state_obj *obj,
595 struct a6xx_crashdumper *dumper)
597 u64 *in = dumper->ptr;
598 size_t datasize = block->size * A6XX_NUM_SHADER_BANKS * sizeof(u32);
601 if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
604 for (i = 0; i < A6XX_NUM_SHADER_BANKS; i++) {
605 in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL,
606 (block->type << 8) | i);
608 in += CRASHDUMP_READ(in, REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE,
609 block->size, dumper->iova + A6XX_CD_DATA_OFFSET);
614 if (a6xx_crashdumper_run(gpu, dumper))
618 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
622 static void a6xx_get_shaders(struct msm_gpu *gpu,
623 struct a6xx_gpu_state *a6xx_state,
624 struct a6xx_crashdumper *dumper)
628 a6xx_state->shaders = state_kcalloc(a6xx_state,
629 ARRAY_SIZE(a6xx_shader_blocks), sizeof(*a6xx_state->shaders));
631 if (!a6xx_state->shaders)
634 a6xx_state->nr_shaders = ARRAY_SIZE(a6xx_shader_blocks);
636 for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++)
637 a6xx_get_shader_block(gpu, a6xx_state, &a6xx_shader_blocks[i],
638 &a6xx_state->shaders[i], dumper);
641 /* Read registers from behind the HLSQ aperture with the crashdumper */
642 static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu,
643 struct a6xx_gpu_state *a6xx_state,
644 const struct a6xx_registers *regs,
645 struct a6xx_gpu_state_obj *obj,
646 struct a6xx_crashdumper *dumper)
649 u64 *in = dumper->ptr;
650 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
653 in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL, regs->val1);
655 for (i = 0; i < regs->count; i += 2) {
656 u32 count = RANGE(regs->registers, i);
657 u32 offset = REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE +
658 regs->registers[i] - (regs->val0 >> 2);
660 in += CRASHDUMP_READ(in, offset, count, out);
662 out += count * sizeof(u32);
668 if (WARN_ON((regcount * sizeof(u32)) > A6XX_CD_DATA_SIZE))
671 if (a6xx_crashdumper_run(gpu, dumper))
675 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
676 regcount * sizeof(u32));
679 /* Read a block of registers using the crashdumper */
680 static void a6xx_get_crashdumper_registers(struct msm_gpu *gpu,
681 struct a6xx_gpu_state *a6xx_state,
682 const struct a6xx_registers *regs,
683 struct a6xx_gpu_state_obj *obj,
684 struct a6xx_crashdumper *dumper)
687 u64 *in = dumper->ptr;
688 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
691 /* Some blocks might need to program a selector register first */
693 in += CRASHDUMP_WRITE(in, regs->val0, regs->val1);
695 for (i = 0; i < regs->count; i += 2) {
696 u32 count = RANGE(regs->registers, i);
698 in += CRASHDUMP_READ(in, regs->registers[i], count, out);
700 out += count * sizeof(u32);
706 if (WARN_ON((regcount * sizeof(u32)) > A6XX_CD_DATA_SIZE))
709 if (a6xx_crashdumper_run(gpu, dumper))
713 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
714 regcount * sizeof(u32));
717 /* Read a block of registers via AHB */
718 static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
719 struct a6xx_gpu_state *a6xx_state,
720 const struct a6xx_registers *regs,
721 struct a6xx_gpu_state_obj *obj)
723 int i, regcount = 0, index = 0;
725 for (i = 0; i < regs->count; i += 2)
726 regcount += RANGE(regs->registers, i);
728 obj->handle = (const void *) regs;
729 obj->data = state_kcalloc(a6xx_state, regcount, sizeof(u32));
733 for (i = 0; i < regs->count; i += 2) {
734 u32 count = RANGE(regs->registers, i);
737 for (j = 0; j < count; j++)
738 obj->data[index++] = gpu_read(gpu,
739 regs->registers[i] + j);
743 /* Read a block of GMU registers */
744 static void _a6xx_get_gmu_registers(struct msm_gpu *gpu,
745 struct a6xx_gpu_state *a6xx_state,
746 const struct a6xx_registers *regs,
747 struct a6xx_gpu_state_obj *obj,
750 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
751 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
752 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
753 int i, regcount = 0, index = 0;
755 for (i = 0; i < regs->count; i += 2)
756 regcount += RANGE(regs->registers, i);
758 obj->handle = (const void *) regs;
759 obj->data = state_kcalloc(a6xx_state, regcount, sizeof(u32));
763 for (i = 0; i < regs->count; i += 2) {
764 u32 count = RANGE(regs->registers, i);
767 for (j = 0; j < count; j++) {
768 u32 offset = regs->registers[i] + j;
772 val = gmu_read_rscc(gmu, offset);
774 val = gmu_read(gmu, offset);
776 obj->data[index++] = val;
781 static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
782 struct a6xx_gpu_state *a6xx_state)
784 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
785 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
787 a6xx_state->gmu_registers = state_kcalloc(a6xx_state,
788 3, sizeof(*a6xx_state->gmu_registers));
790 if (!a6xx_state->gmu_registers)
793 a6xx_state->nr_gmu_registers = 3;
795 /* Get the CX GMU registers from AHB */
796 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0],
797 &a6xx_state->gmu_registers[0], false);
798 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
799 &a6xx_state->gmu_registers[1], true);
801 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
804 /* Set the fence to ALLOW mode so we can access the registers */
805 gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
807 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],
808 &a6xx_state->gmu_registers[2], false);
811 static struct msm_gpu_state_bo *a6xx_snapshot_gmu_bo(
812 struct a6xx_gpu_state *a6xx_state, struct a6xx_gmu_bo *bo)
814 struct msm_gpu_state_bo *snapshot;
819 snapshot = state_kcalloc(a6xx_state, 1, sizeof(*snapshot));
823 snapshot->iova = bo->iova;
824 snapshot->size = bo->size;
825 snapshot->data = kvzalloc(snapshot->size, GFP_KERNEL);
829 memcpy(snapshot->data, bo->virt, bo->size);
834 static void a6xx_snapshot_gmu_hfi_history(struct msm_gpu *gpu,
835 struct a6xx_gpu_state *a6xx_state)
837 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
838 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
839 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
842 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history));
844 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) {
845 struct a6xx_hfi_queue *queue = &gmu->queues[i];
846 for (j = 0; j < HFI_HISTORY_SZ; j++) {
847 unsigned idx = (j + queue->history_idx) % HFI_HISTORY_SZ;
848 a6xx_state->hfi_queue_history[i][j] = queue->history[idx];
853 #define A6XX_GBIF_REGLIST_SIZE 1
854 static void a6xx_get_registers(struct msm_gpu *gpu,
855 struct a6xx_gpu_state *a6xx_state,
856 struct a6xx_crashdumper *dumper)
858 int i, count = ARRAY_SIZE(a6xx_ahb_reglist) +
859 ARRAY_SIZE(a6xx_reglist) +
860 ARRAY_SIZE(a6xx_hlsq_reglist) + A6XX_GBIF_REGLIST_SIZE;
862 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
864 a6xx_state->registers = state_kcalloc(a6xx_state,
865 count, sizeof(*a6xx_state->registers));
867 if (!a6xx_state->registers)
870 a6xx_state->nr_registers = count;
872 for (i = 0; i < ARRAY_SIZE(a6xx_ahb_reglist); i++)
873 a6xx_get_ahb_gpu_registers(gpu,
874 a6xx_state, &a6xx_ahb_reglist[i],
875 &a6xx_state->registers[index++]);
877 if (a6xx_has_gbif(adreno_gpu))
878 a6xx_get_ahb_gpu_registers(gpu,
879 a6xx_state, &a6xx_gbif_reglist,
880 &a6xx_state->registers[index++]);
882 a6xx_get_ahb_gpu_registers(gpu,
883 a6xx_state, &a6xx_vbif_reglist,
884 &a6xx_state->registers[index++]);
887 * We can't use the crashdumper when the SMMU is stalled,
888 * because the GPU has no memory access until we resume
889 * translation (but we don't want to do that until after
890 * we have captured as much useful GPU state as possible).
891 * So instead collect registers via the CPU:
893 for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
894 a6xx_get_ahb_gpu_registers(gpu,
895 a6xx_state, &a6xx_reglist[i],
896 &a6xx_state->registers[index++]);
900 for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
901 a6xx_get_crashdumper_registers(gpu,
902 a6xx_state, &a6xx_reglist[i],
903 &a6xx_state->registers[index++],
906 for (i = 0; i < ARRAY_SIZE(a6xx_hlsq_reglist); i++)
907 a6xx_get_crashdumper_hlsq_registers(gpu,
908 a6xx_state, &a6xx_hlsq_reglist[i],
909 &a6xx_state->registers[index++],
913 /* Read a block of data from an indexed register pair */
914 static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
915 struct a6xx_gpu_state *a6xx_state,
916 const struct a6xx_indexed_registers *indexed,
917 struct a6xx_gpu_state_obj *obj)
921 obj->handle = (const void *) indexed;
922 obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32));
926 /* All the indexed banks start at address 0 */
927 gpu_write(gpu, indexed->addr, 0);
929 /* Read the data - each read increments the internal address by 1 */
930 for (i = 0; i < indexed->count; i++)
931 obj->data[i] = gpu_read(gpu, indexed->data);
934 static void a6xx_get_indexed_registers(struct msm_gpu *gpu,
935 struct a6xx_gpu_state *a6xx_state)
938 int count = ARRAY_SIZE(a6xx_indexed_reglist) + 1;
941 a6xx_state->indexed_regs = state_kcalloc(a6xx_state, count,
942 sizeof(*a6xx_state->indexed_regs));
943 if (!a6xx_state->indexed_regs)
946 for (i = 0; i < ARRAY_SIZE(a6xx_indexed_reglist); i++)
947 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_indexed_reglist[i],
948 &a6xx_state->indexed_regs[i]);
950 /* Set the CP mempool size to 0 to stabilize it while dumping */
951 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE);
952 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 0);
954 /* Get the contents of the CP mempool */
955 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed,
956 &a6xx_state->indexed_regs[i]);
959 * Offset 0x2000 in the mempool is the size - copy the saved size over
960 * so the data is consistent
962 a6xx_state->indexed_regs[i].data[0x2000] = mempool_size;
964 /* Restore the size in the hardware */
965 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size);
967 a6xx_state->nr_indexed_regs = count;
970 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
972 struct a6xx_crashdumper _dumper = { 0 }, *dumper = NULL;
973 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
974 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
975 struct a6xx_gpu_state *a6xx_state = kzalloc(sizeof(*a6xx_state),
977 bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) &
978 A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT);
981 return ERR_PTR(-ENOMEM);
983 INIT_LIST_HEAD(&a6xx_state->objs);
985 /* Get the generic state from the adreno core */
986 adreno_gpu_state_get(gpu, &a6xx_state->base);
988 a6xx_get_gmu_registers(gpu, a6xx_state);
990 a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log);
991 a6xx_state->gmu_hfi = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.hfi);
992 a6xx_state->gmu_debug = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.debug);
994 a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state);
996 /* If GX isn't on the rest of the data isn't going to be accessible */
997 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
998 return &a6xx_state->base;
1000 /* Get the banks of indexed registers */
1001 a6xx_get_indexed_registers(gpu, a6xx_state);
1004 * Try to initialize the crashdumper, if we are not dumping state
1005 * with the SMMU stalled. The crashdumper needs memory access to
1006 * write out GPU state, so we need to skip this when the SMMU is
1007 * stalled in response to an iova fault
1009 if (!stalled && !gpu->needs_hw_init &&
1010 !a6xx_crashdumper_init(gpu, &_dumper)) {
1014 a6xx_get_registers(gpu, a6xx_state, dumper);
1017 a6xx_get_shaders(gpu, a6xx_state, dumper);
1018 a6xx_get_clusters(gpu, a6xx_state, dumper);
1019 a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
1021 msm_gem_kernel_put(dumper->bo, gpu->aspace);
1024 if (snapshot_debugbus)
1025 a6xx_get_debugbus(gpu, a6xx_state);
1027 a6xx_state->gpu_initialized = !gpu->needs_hw_init;
1029 return &a6xx_state->base;
1032 static void a6xx_gpu_state_destroy(struct kref *kref)
1034 struct a6xx_state_memobj *obj, *tmp;
1035 struct msm_gpu_state *state = container_of(kref,
1036 struct msm_gpu_state, ref);
1037 struct a6xx_gpu_state *a6xx_state = container_of(state,
1038 struct a6xx_gpu_state, base);
1040 if (a6xx_state->gmu_log)
1041 kvfree(a6xx_state->gmu_log->data);
1043 if (a6xx_state->gmu_hfi)
1044 kvfree(a6xx_state->gmu_hfi->data);
1046 if (a6xx_state->gmu_debug)
1047 kvfree(a6xx_state->gmu_debug->data);
1049 list_for_each_entry_safe(obj, tmp, &a6xx_state->objs, node) {
1050 list_del(&obj->node);
1054 adreno_gpu_state_destroy(state);
1058 int a6xx_gpu_state_put(struct msm_gpu_state *state)
1060 if (IS_ERR_OR_NULL(state))
1063 return kref_put(&state->ref, a6xx_gpu_state_destroy);
1066 static void a6xx_show_registers(const u32 *registers, u32 *data, size_t count,
1067 struct drm_printer *p)
1074 for (i = 0; i < count; i += 2) {
1075 u32 count = RANGE(registers, i);
1076 u32 offset = registers[i];
1079 for (j = 0; j < count; index++, offset++, j++) {
1080 if (data[index] == 0xdeafbead)
1083 drm_printf(p, " - { offset: 0x%06x, value: 0x%08x }\n",
1084 offset << 2, data[index]);
1089 static void print_ascii85(struct drm_printer *p, size_t len, u32 *data)
1091 char out[ASCII85_BUFSZ];
1092 long i, l, datalen = 0;
1094 for (i = 0; i < len >> 2; i++) {
1096 datalen = (i + 1) << 2;
1102 drm_puts(p, " data: !!ascii85 |\n");
1106 l = ascii85_encode_len(datalen);
1108 for (i = 0; i < l; i++)
1109 drm_puts(p, ascii85_encode(data[i], out));
1114 static void print_name(struct drm_printer *p, const char *fmt, const char *name)
1121 static void a6xx_show_shader(struct a6xx_gpu_state_obj *obj,
1122 struct drm_printer *p)
1124 const struct a6xx_shader_block *block = obj->handle;
1130 print_name(p, " - type: ", block->name);
1132 for (i = 0; i < A6XX_NUM_SHADER_BANKS; i++) {
1133 drm_printf(p, " - bank: %d\n", i);
1134 drm_printf(p, " size: %d\n", block->size);
1139 print_ascii85(p, block->size << 2,
1140 obj->data + (block->size * i));
1144 static void a6xx_show_cluster_data(const u32 *registers, int size, u32 *data,
1145 struct drm_printer *p)
1149 for (ctx = 0; ctx < A6XX_NUM_CONTEXTS; ctx++) {
1152 drm_printf(p, " - context: %d\n", ctx);
1154 for (j = 0; j < size; j += 2) {
1155 u32 count = RANGE(registers, j);
1156 u32 offset = registers[j];
1159 for (k = 0; k < count; index++, offset++, k++) {
1160 if (data[index] == 0xdeafbead)
1163 drm_printf(p, " - { offset: 0x%06x, value: 0x%08x }\n",
1164 offset << 2, data[index]);
1170 static void a6xx_show_dbgahb_cluster(struct a6xx_gpu_state_obj *obj,
1171 struct drm_printer *p)
1173 const struct a6xx_dbgahb_cluster *dbgahb = obj->handle;
1176 print_name(p, " - cluster-name: ", dbgahb->name);
1177 a6xx_show_cluster_data(dbgahb->registers, dbgahb->count,
1182 static void a6xx_show_cluster(struct a6xx_gpu_state_obj *obj,
1183 struct drm_printer *p)
1185 const struct a6xx_cluster *cluster = obj->handle;
1188 print_name(p, " - cluster-name: ", cluster->name);
1189 a6xx_show_cluster_data(cluster->registers, cluster->count,
1194 static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj,
1195 struct drm_printer *p)
1197 const struct a6xx_indexed_registers *indexed = obj->handle;
1202 print_name(p, " - regs-name: ", indexed->name);
1203 drm_printf(p, " dwords: %d\n", indexed->count);
1205 print_ascii85(p, indexed->count << 2, obj->data);
1208 static void a6xx_show_debugbus_block(const struct a6xx_debugbus_block *block,
1209 u32 *data, struct drm_printer *p)
1212 print_name(p, " - debugbus-block: ", block->name);
1215 * count for regular debugbus data is in quadwords,
1216 * but print the size in dwords for consistency
1218 drm_printf(p, " count: %d\n", block->count << 1);
1220 print_ascii85(p, block->count << 3, data);
1224 static void a6xx_show_debugbus(struct a6xx_gpu_state *a6xx_state,
1225 struct drm_printer *p)
1229 for (i = 0; i < a6xx_state->nr_debugbus; i++) {
1230 struct a6xx_gpu_state_obj *obj = &a6xx_state->debugbus[i];
1232 a6xx_show_debugbus_block(obj->handle, obj->data, p);
1235 if (a6xx_state->vbif_debugbus) {
1236 struct a6xx_gpu_state_obj *obj = a6xx_state->vbif_debugbus;
1238 drm_puts(p, " - debugbus-block: A6XX_DBGBUS_VBIF\n");
1239 drm_printf(p, " count: %d\n", VBIF_DEBUGBUS_BLOCK_SIZE);
1241 /* vbif debugbus data is in dwords. Confusing, huh? */
1242 print_ascii85(p, VBIF_DEBUGBUS_BLOCK_SIZE << 2, obj->data);
1245 for (i = 0; i < a6xx_state->nr_cx_debugbus; i++) {
1246 struct a6xx_gpu_state_obj *obj = &a6xx_state->cx_debugbus[i];
1248 a6xx_show_debugbus_block(obj->handle, obj->data, p);
1252 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
1253 struct drm_printer *p)
1255 struct a6xx_gpu_state *a6xx_state = container_of(state,
1256 struct a6xx_gpu_state, base);
1259 if (IS_ERR_OR_NULL(state))
1262 drm_printf(p, "gpu-initialized: %d\n", a6xx_state->gpu_initialized);
1264 adreno_show(gpu, state, p);
1266 drm_puts(p, "gmu-log:\n");
1267 if (a6xx_state->gmu_log) {
1268 struct msm_gpu_state_bo *gmu_log = a6xx_state->gmu_log;
1270 drm_printf(p, " iova: 0x%016llx\n", gmu_log->iova);
1271 drm_printf(p, " size: %zu\n", gmu_log->size);
1272 adreno_show_object(p, &gmu_log->data, gmu_log->size,
1276 drm_puts(p, "gmu-hfi:\n");
1277 if (a6xx_state->gmu_hfi) {
1278 struct msm_gpu_state_bo *gmu_hfi = a6xx_state->gmu_hfi;
1281 drm_printf(p, " iova: 0x%016llx\n", gmu_hfi->iova);
1282 drm_printf(p, " size: %zu\n", gmu_hfi->size);
1283 for (i = 0; i < ARRAY_SIZE(a6xx_state->hfi_queue_history); i++) {
1284 drm_printf(p, " queue-history[%u]:", i);
1285 for (j = 0; j < HFI_HISTORY_SZ; j++) {
1286 drm_printf(p, " %d", a6xx_state->hfi_queue_history[i][j]);
1288 drm_printf(p, "\n");
1290 adreno_show_object(p, &gmu_hfi->data, gmu_hfi->size,
1294 drm_puts(p, "gmu-debug:\n");
1295 if (a6xx_state->gmu_debug) {
1296 struct msm_gpu_state_bo *gmu_debug = a6xx_state->gmu_debug;
1298 drm_printf(p, " iova: 0x%016llx\n", gmu_debug->iova);
1299 drm_printf(p, " size: %zu\n", gmu_debug->size);
1300 adreno_show_object(p, &gmu_debug->data, gmu_debug->size,
1301 &gmu_debug->encoded);
1304 drm_puts(p, "registers:\n");
1305 for (i = 0; i < a6xx_state->nr_registers; i++) {
1306 struct a6xx_gpu_state_obj *obj = &a6xx_state->registers[i];
1307 const struct a6xx_registers *regs = obj->handle;
1312 a6xx_show_registers(regs->registers, obj->data, regs->count, p);
1315 drm_puts(p, "registers-gmu:\n");
1316 for (i = 0; i < a6xx_state->nr_gmu_registers; i++) {
1317 struct a6xx_gpu_state_obj *obj = &a6xx_state->gmu_registers[i];
1318 const struct a6xx_registers *regs = obj->handle;
1323 a6xx_show_registers(regs->registers, obj->data, regs->count, p);
1326 drm_puts(p, "indexed-registers:\n");
1327 for (i = 0; i < a6xx_state->nr_indexed_regs; i++)
1328 a6xx_show_indexed_regs(&a6xx_state->indexed_regs[i], p);
1330 drm_puts(p, "shader-blocks:\n");
1331 for (i = 0; i < a6xx_state->nr_shaders; i++)
1332 a6xx_show_shader(&a6xx_state->shaders[i], p);
1334 drm_puts(p, "clusters:\n");
1335 for (i = 0; i < a6xx_state->nr_clusters; i++)
1336 a6xx_show_cluster(&a6xx_state->clusters[i], p);
1338 for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++)
1339 a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p);
1341 drm_puts(p, "debugbus:\n");
1342 a6xx_show_debugbus(a6xx_state, p);