1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
5 #include <linux/interconnect.h>
6 #include <linux/pm_domain.h>
7 #include <linux/pm_opp.h>
8 #include <soc/qcom/cmd-db.h>
9 #include <drm/drm_gem.h>
12 #include "a6xx_gmu.xml.h"
14 #include "msm_gpu_trace.h"
17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
20 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
21 struct msm_gpu *gpu = &adreno_gpu->base;
23 /* FIXME: add a banner here */
26 /* Turn off the hangcheck timer while we are resetting */
27 del_timer(&gpu->hangcheck_timer);
29 /* Queue the GPU handler because we need to treat this as a recovery */
30 kthread_queue_work(gpu->worker, &gpu->recover_work);
33 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
35 struct a6xx_gmu *gmu = data;
38 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
39 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
41 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
42 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
47 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
48 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
50 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
51 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
52 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
57 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
59 struct a6xx_gmu *gmu = data;
62 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
63 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
65 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
66 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
78 /* This can be called from gpu state code so make sure GMU is valid */
79 if (!gmu->initialized)
82 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
85 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
86 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
89 /* Check to see if the GX rail is still powered */
90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
94 /* This can be called from gpu state code so make sure GMU is valid */
95 if (!gmu->initialized)
98 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
101 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
102 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
105 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
107 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
108 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
109 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
111 unsigned long gpu_freq;
114 gpu_freq = dev_pm_opp_get_freq(opp);
116 if (gpu_freq == gmu->freq)
119 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
120 if (gpu_freq == gmu->gpu_freqs[perf_index])
123 gmu->current_perf_index = perf_index;
124 gmu->freq = gmu->gpu_freqs[perf_index];
126 trace_msm_gmu_freq_change(gmu->freq, perf_index);
129 * This can get called from devfreq while the hardware is idle. Don't
130 * bring up the power if it isn't already active
132 if (pm_runtime_get_if_in_use(gmu->dev) == 0)
136 a6xx_hfi_set_freq(gmu, perf_index);
137 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
138 pm_runtime_put(gmu->dev);
142 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
144 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
145 ((3 & 0xf) << 28) | perf_index);
148 * Send an invalid index as a vote for the bus bandwidth and let the
149 * firmware decide on the right vote
151 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
153 /* Set and clear the OOB for DCVS to trigger the GMU */
154 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
155 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
157 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
159 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
161 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
162 pm_runtime_put(gmu->dev);
165 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
167 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
168 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
169 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
174 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
177 int local = gmu->idle_level;
179 /* SPTP and IFPC both report as IFPC */
180 if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
181 local = GMU_IDLE_STATE_IFPC;
183 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
186 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
187 !a6xx_gmu_gx_is_on(gmu))
194 /* Wait for the GMU to get to its most idle state */
195 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
197 return spin_until(a6xx_gmu_check_idle_level(gmu));
200 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
206 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
207 if (val <= 0x20010004) {
209 reset_val = 0xbabeface;
215 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
217 /* Set the log wptr index
218 * note: downstream saves the value in poweroff and restores it here
220 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
222 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
224 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
225 (val & mask) == reset_val, 100, 10000);
228 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
233 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
238 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
240 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
241 val & 1, 100, 10000);
243 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
248 struct a6xx_gmu_oob_bits {
249 int set, ack, set_new, ack_new, clear, clear_new;
253 /* These are the interrupt / ack bits for each OOB request that are set
254 * in a6xx_gmu_set_oob and a6xx_clear_oob
256 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
257 [GMU_OOB_GPU_SET] = {
267 [GMU_OOB_PERFCOUNTER_SET] = {
268 .name = "PERFCOUNTER",
277 [GMU_OOB_BOOT_SLUMBER] = {
278 .name = "BOOT_SLUMBER",
284 [GMU_OOB_DCVS_SET] = {
292 /* Trigger a OOB (out of band) request to the GMU */
293 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
299 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
301 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
305 request = a6xx_gmu_oob_bits[state].set;
306 ack = a6xx_gmu_oob_bits[state].ack;
308 request = a6xx_gmu_oob_bits[state].set_new;
309 ack = a6xx_gmu_oob_bits[state].ack_new;
310 if (!request || !ack) {
311 DRM_DEV_ERROR(gmu->dev,
312 "Invalid non-legacy GMU request %s\n",
313 a6xx_gmu_oob_bits[state].name);
318 /* Trigger the equested OOB operation */
319 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
321 /* Wait for the acknowledge interrupt */
322 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
323 val & (1 << ack), 100, 10000);
326 DRM_DEV_ERROR(gmu->dev,
327 "Timeout waiting for GMU OOB set %s: 0x%x\n",
328 a6xx_gmu_oob_bits[state].name,
329 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
331 /* Clear the acknowledge interrupt */
332 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
337 /* Clear a pending OOB state in the GMU */
338 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
342 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
344 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
348 bit = a6xx_gmu_oob_bits[state].clear;
350 bit = a6xx_gmu_oob_bits[state].clear_new;
352 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
355 /* Enable CPU control of SPTP power power collapse */
356 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
364 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
366 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
367 (val & 0x38) == 0x28, 1, 100);
370 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
371 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
377 /* Disable CPU control of SPTP power power collapse */
378 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
386 /* Make sure retention is on */
387 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
389 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
391 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
392 (val & 0x04), 100, 10000);
395 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
396 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
399 /* Let the GMU know we are starting a boot sequence */
400 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
404 /* Let the GMU know we are getting ready for boot */
405 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
407 /* Choose the "default" power level as the highest available */
408 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
410 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
411 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
413 /* Let the GMU know the boot sequence has started */
414 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
417 /* Let the GMU know that we are about to go into slumber */
418 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
422 /* Disable the power counter so the GMU isn't busy */
423 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
425 /* Disable SPTP_PC if the CPU is responsible for it */
426 if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
427 a6xx_sptprac_disable(gmu);
430 ret = a6xx_hfi_send_prep_slumber(gmu);
434 /* Tell the GMU to get ready to slumber */
435 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
437 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
438 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
441 /* Check to see if the GMU really did slumber */
442 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
444 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
450 /* Put fence into allow mode */
451 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
455 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
460 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
461 /* Wait for the register to finish posting */
464 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
465 val & (1 << 1), 100, 10000);
467 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
471 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
475 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
479 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
481 /* Set up CX GMU counter 0 to count busy ticks */
482 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
483 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
485 /* Enable the power counter */
486 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
490 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
495 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
497 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
498 val, val & (1 << 16), 100, 10000);
500 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
502 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
505 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
507 return msm_writel(value, ptr + (offset << 2));
510 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
513 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
515 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
516 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
517 struct platform_device *pdev = to_platform_device(gmu->dev);
518 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
519 void __iomem *seqptr;
520 uint32_t pdc_address_offset;
521 bool pdc_in_aop = false;
526 if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
528 else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
529 pdc_address_offset = 0x30090;
531 pdc_address_offset = 0x30080;
534 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
539 /* Disable SDE clock gating */
540 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
542 /* Setup RSC PDC handshake for sleep and wakeup */
543 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
544 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
545 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
546 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
547 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
548 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
549 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
550 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
551 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
552 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
553 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
555 /* Load RSC sequencer uCode for sleep and wakeup */
556 if (adreno_is_a650_family(adreno_gpu)) {
557 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
558 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
559 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
560 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
561 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
563 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
564 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
565 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
566 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
567 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
573 /* Load PDC sequencer uCode for power up and power down sequence */
574 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
575 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
576 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
577 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
578 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
580 /* Set TCS commands used by PDC sequence for low power modes */
581 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
582 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
583 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
584 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
585 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
586 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
587 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
588 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
589 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
591 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
592 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
593 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
595 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
596 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
597 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
598 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
599 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
600 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
602 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
603 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
604 if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
605 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
607 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
608 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
609 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
610 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
614 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
615 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
617 /* ensure no writes happen before the uCode is fully written */
621 if (!IS_ERR_OR_NULL(pdcptr))
623 if (!IS_ERR_OR_NULL(seqptr))
628 * The lowest 16 bits of this value are the number of XO clock cycles for main
629 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
630 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
633 #define GMU_PWR_COL_HYST 0x000a1680
635 /* Set up the idle state for the GMU */
636 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
638 /* Disable GMU WB/RB buffer */
639 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
640 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
641 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
643 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
645 switch (gmu->idle_level) {
646 case GMU_IDLE_STATE_IFPC:
647 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
649 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
650 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
651 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
653 case GMU_IDLE_STATE_SPTP:
654 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
656 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
657 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
658 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
661 /* Enable RPMh GPU client */
662 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
663 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
664 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
665 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
666 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
667 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
668 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
671 struct block_header {
679 /* this should be a general kernel helper */
680 static int in_range(u32 addr, u32 start, u32 size)
682 return addr >= start && addr < start + size;
685 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
687 if (!in_range(blk->addr, bo->iova, bo->size))
690 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
694 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
696 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
697 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
698 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
699 const struct block_header *blk;
702 u32 itcm_base = 0x00000000;
703 u32 dtcm_base = 0x00040000;
705 if (adreno_is_a650_family(adreno_gpu))
706 dtcm_base = 0x10004000;
709 /* Sanity check the size of the firmware that was loaded */
710 if (fw_image->size > 0x8000) {
711 DRM_DEV_ERROR(gmu->dev,
712 "GMU firmware is bigger than the available region\n");
716 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
717 (u32*) fw_image->data, fw_image->size);
722 for (blk = (const struct block_header *) fw_image->data;
723 (const u8*) blk < fw_image->data + fw_image->size;
724 blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
728 if (in_range(blk->addr, itcm_base, SZ_16K)) {
729 reg_offset = (blk->addr - itcm_base) >> 2;
731 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
732 blk->data, blk->size);
733 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
734 reg_offset = (blk->addr - dtcm_base) >> 2;
736 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
737 blk->data, blk->size);
738 } else if (!fw_block_mem(&gmu->icache, blk) &&
739 !fw_block_mem(&gmu->dcache, blk) &&
740 !fw_block_mem(&gmu->dummy, blk)) {
741 DRM_DEV_ERROR(gmu->dev,
742 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
743 blk->addr, blk->size, blk->data[0]);
750 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
752 static bool rpmh_init;
753 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
754 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
758 if (adreno_is_a650_family(adreno_gpu)) {
759 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
760 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
763 if (state == GMU_WARM_BOOT) {
764 ret = a6xx_rpmh_start(gmu);
768 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
769 "GMU firmware is not loaded\n"))
772 /* Turn on register retention */
773 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
775 /* We only need to load the RPMh microcode once */
777 a6xx_gmu_rpmh_init(gmu);
780 ret = a6xx_rpmh_start(gmu);
785 ret = a6xx_gmu_fw_load(gmu);
790 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
791 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
793 /* Write the iova of the HFI table */
794 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
795 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
797 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
798 (1 << 31) | (0xa << 18) | (0xa0));
800 chipid = adreno_gpu->rev.core << 24;
801 chipid |= adreno_gpu->rev.major << 16;
802 chipid |= adreno_gpu->rev.minor << 12;
803 chipid |= adreno_gpu->rev.patchid << 8;
805 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
807 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
808 gmu->log.iova | (gmu->log.size / SZ_4K - 1));
810 /* Set up the lowest idle level on the GMU */
811 a6xx_gmu_power_config(gmu);
813 ret = a6xx_gmu_start(gmu);
818 ret = a6xx_gmu_gfx_rail_on(gmu);
823 /* Enable SPTP_PC if the CPU is responsible for it */
824 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
825 ret = a6xx_sptprac_enable(gmu);
830 ret = a6xx_gmu_hfi_start(gmu);
834 /* FIXME: Do we need this wmb() here? */
840 #define A6XX_HFI_IRQ_MASK \
841 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
843 #define A6XX_GMU_IRQ_MASK \
844 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
845 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
846 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
848 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
850 disable_irq(gmu->gmu_irq);
851 disable_irq(gmu->hfi_irq);
853 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
854 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
857 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
861 /* Make sure there are no outstanding RPMh votes */
862 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
863 (val & 1), 100, 10000);
864 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
865 (val & 1), 100, 10000);
866 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
867 (val & 1), 100, 10000);
868 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
869 (val & 1), 100, 1000);
872 /* Force the GMU off in case it isn't responsive */
873 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
875 /* Flush all the queues */
878 /* Stop the interrupts */
879 a6xx_gmu_irq_disable(gmu);
881 /* Force off SPTP in case the GMU is managing it */
882 a6xx_sptprac_disable(gmu);
884 /* Make sure there are no outstanding RPMh votes */
885 a6xx_gmu_rpmh_off(gmu);
888 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
890 struct dev_pm_opp *gpu_opp;
891 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
893 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
894 if (IS_ERR_OR_NULL(gpu_opp))
897 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
898 a6xx_gmu_set_freq(gpu, gpu_opp);
899 dev_pm_opp_put(gpu_opp);
902 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
904 struct dev_pm_opp *gpu_opp;
905 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
907 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
908 if (IS_ERR_OR_NULL(gpu_opp))
911 dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
912 dev_pm_opp_put(gpu_opp);
915 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
917 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
918 struct msm_gpu *gpu = &adreno_gpu->base;
919 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
922 if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
927 /* Turn on the resources */
928 pm_runtime_get_sync(gmu->dev);
931 * "enable" the GX power domain which won't actually do anything but it
932 * will make sure that the refcounting is correct in case we need to
933 * bring down the GX after a GMU failure
935 if (!IS_ERR_OR_NULL(gmu->gxpd))
936 pm_runtime_get_sync(gmu->gxpd);
938 /* Use a known rate to bring up the GMU */
939 clk_set_rate(gmu->core_clk, 200000000);
940 clk_set_rate(gmu->hub_clk, 150000000);
941 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
943 pm_runtime_put(gmu->gxpd);
944 pm_runtime_put(gmu->dev);
948 /* Set the bus quota to a reasonable value for boot */
949 a6xx_gmu_set_initial_bw(gpu, gmu);
951 /* Enable the GMU interrupt */
952 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
953 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
954 enable_irq(gmu->gmu_irq);
956 /* Check to see if we are doing a cold or warm boot */
957 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
958 GMU_WARM_BOOT : GMU_COLD_BOOT;
961 * Warm boot path does not work on newer GPUs
962 * Presumably this is because icache/dcache regions must be restored
965 status = GMU_COLD_BOOT;
967 ret = a6xx_gmu_fw_start(gmu, status);
971 ret = a6xx_hfi_start(gmu, status);
976 * Turn on the GMU firmware fault interrupt after we know the boot
977 * sequence is successful
979 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
980 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
981 enable_irq(gmu->hfi_irq);
983 /* Set the GPU to the current freq */
984 a6xx_gmu_set_initial_freq(gpu, gmu);
987 /* On failure, shut down the GMU to leave it in a good state */
989 disable_irq(gmu->gmu_irq);
991 pm_runtime_put(gmu->gxpd);
992 pm_runtime_put(gmu->dev);
998 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
1002 if (!gmu->initialized)
1005 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
1007 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
1013 #define GBIF_CLIENT_HALT_MASK BIT(0)
1014 #define GBIF_ARB_HALT_MASK BIT(1)
1016 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
1018 struct msm_gpu *gpu = &adreno_gpu->base;
1020 if (!a6xx_has_gbif(adreno_gpu)) {
1021 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
1022 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
1024 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
1029 /* Halt new client requests on GBIF */
1030 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1031 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1032 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1034 /* Halt all AXI requests on GBIF */
1035 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1036 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1037 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
1039 /* The GBIF halt needs to be explicitly cleared */
1040 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1043 /* Gracefully try to shut down the GMU and by extension the GPU */
1044 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1046 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1047 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1051 * The GMU may still be in slumber unless the GPU started so check and
1052 * skip putting it back into slumber if so
1054 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1057 int ret = a6xx_gmu_wait_for_idle(gmu);
1059 /* If the GMU isn't responding assume it is hung */
1061 a6xx_gmu_force_off(gmu);
1065 a6xx_bus_clear_pending_transactions(adreno_gpu);
1067 /* tell the GMU we want to slumber */
1068 a6xx_gmu_notify_slumber(gmu);
1070 ret = gmu_poll_timeout(gmu,
1071 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1072 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1076 * Let the user know we failed to slumber but don't worry too
1077 * much because we are powering down anyway
1081 DRM_DEV_ERROR(gmu->dev,
1082 "Unable to slumber GMU: status = 0%x/0%x\n",
1084 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1086 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1092 /* Stop the interrupts and mask the hardware */
1093 a6xx_gmu_irq_disable(gmu);
1095 /* Tell RPMh to power off the GPU */
1096 a6xx_rpmh_stop(gmu);
1100 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1102 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1103 struct msm_gpu *gpu = &a6xx_gpu->base.base;
1105 if (!pm_runtime_active(gmu->dev))
1109 * Force the GMU off if we detected a hang, otherwise try to shut it
1113 a6xx_gmu_force_off(gmu);
1115 a6xx_gmu_shutdown(gmu);
1117 /* Remove the bus vote */
1118 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1121 * Make sure the GX domain is off before turning off the GMU (CX)
1122 * domain. Usually the GMU does this but only if the shutdown sequence
1125 if (!IS_ERR_OR_NULL(gmu->gxpd))
1126 pm_runtime_put_sync(gmu->gxpd);
1128 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1130 pm_runtime_put_sync(gmu->dev);
1135 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1137 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
1138 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1139 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
1140 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
1141 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
1142 msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
1144 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1145 msm_gem_address_space_put(gmu->aspace);
1148 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1149 size_t size, u64 iova)
1151 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1152 struct drm_device *dev = a6xx_gpu->base.base.dev;
1153 uint32_t flags = MSM_BO_WC;
1154 u64 range_start, range_end;
1157 size = PAGE_ALIGN(size);
1159 /* no fixed address - use GMU's uncached range */
1160 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1161 range_end = 0x80000000;
1163 /* range for fixed address */
1165 range_end = iova + size;
1166 /* use IOMMU_PRIV for icache/dcache */
1167 flags |= MSM_BO_MAP_PRIV;
1170 bo->obj = msm_gem_new(dev, size, flags);
1171 if (IS_ERR(bo->obj))
1172 return PTR_ERR(bo->obj);
1174 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1175 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT);
1177 drm_gem_object_put(bo->obj);
1181 bo->virt = msm_gem_get_vaddr(bo->obj);
1187 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1189 struct iommu_domain *domain;
1190 struct msm_mmu *mmu;
1192 domain = iommu_domain_alloc(&platform_bus_type);
1196 mmu = msm_iommu_new(gmu->dev, domain);
1197 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1198 if (IS_ERR(gmu->aspace)) {
1199 iommu_domain_free(domain);
1200 return PTR_ERR(gmu->aspace);
1206 /* Return the 'arc-level' for the given frequency */
1207 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1210 struct dev_pm_opp *opp;
1216 opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1220 val = dev_pm_opp_get_level(opp);
1222 dev_pm_opp_put(opp);
1227 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1228 unsigned long *freqs, int freqs_count, const char *id)
1231 const u16 *pri, *sec;
1232 size_t pri_count, sec_count;
1234 pri = cmd_db_read_aux_data(id, &pri_count);
1236 return PTR_ERR(pri);
1238 * The data comes back as an array of unsigned shorts so adjust the
1245 sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1247 return PTR_ERR(sec);
1253 /* Construct a vote for each frequency */
1254 for (i = 0; i < freqs_count; i++) {
1255 u8 pindex = 0, sindex = 0;
1256 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1258 /* Get the primary index that matches the arc level */
1259 for (j = 0; j < pri_count; j++) {
1260 if (pri[j] >= level) {
1266 if (j == pri_count) {
1268 "Level %u not found in the RPMh list\n",
1270 DRM_DEV_ERROR(dev, "Available levels:\n");
1271 for (j = 0; j < pri_count; j++)
1272 DRM_DEV_ERROR(dev, " %u\n", pri[j]);
1278 * Look for a level in in the secondary list that matches. If
1279 * nothing fits, use the maximum non zero vote
1282 for (j = 0; j < sec_count; j++) {
1283 if (sec[j] >= level) {
1286 } else if (sec[j]) {
1291 /* Construct the vote */
1292 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1293 (sindex << 8) | pindex;
1300 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1301 * to construct the list of votes on the CPU and send it over. Query the RPMh
1302 * voltage levels and build the votes
1305 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1307 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1308 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1309 struct msm_gpu *gpu = &adreno_gpu->base;
1312 /* Build the GX votes */
1313 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1314 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1316 /* Build the CX votes */
1317 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1318 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1323 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1326 int count = dev_pm_opp_get_opp_count(dev);
1327 struct dev_pm_opp *opp;
1329 unsigned long freq = 1;
1332 * The OPP table doesn't contain the "off" frequency level so we need to
1333 * add 1 to the table size to account for it
1336 if (WARN(count + 1 > size,
1337 "The GMU frequency table is being truncated\n"))
1340 /* Set the "off" frequency */
1343 for (i = 0; i < count; i++) {
1344 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1348 dev_pm_opp_put(opp);
1349 freqs[index++] = freq++;
1355 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1357 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1358 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1359 struct msm_gpu *gpu = &adreno_gpu->base;
1364 * The GMU handles its own frequency switching so build a list of
1365 * available frequencies to send during initialization
1367 ret = devm_pm_opp_of_add_table(gmu->dev);
1369 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1373 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1374 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1377 * The GMU also handles GPU frequency switching so build a list
1378 * from the GPU OPP table
1380 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1381 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1383 gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1385 /* Build the list of RPMh votes that we'll send to the GMU */
1386 return a6xx_gmu_rpmh_votes_init(gmu);
1389 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1391 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1396 gmu->nr_clocks = ret;
1398 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1399 gmu->nr_clocks, "gmu");
1401 gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,
1402 gmu->nr_clocks, "hub");
1407 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1411 struct resource *res = platform_get_resource_byname(pdev,
1412 IORESOURCE_MEM, name);
1415 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1416 return ERR_PTR(-EINVAL);
1419 ret = ioremap(res->start, resource_size(res));
1421 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1422 return ERR_PTR(-EINVAL);
1428 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1429 const char *name, irq_handler_t handler)
1433 irq = platform_get_irq_byname(pdev, name);
1435 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1437 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1447 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1449 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1450 struct platform_device *pdev = to_platform_device(gmu->dev);
1452 if (!gmu->initialized)
1455 pm_runtime_force_suspend(gmu->dev);
1457 if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1458 pm_runtime_disable(gmu->gxpd);
1459 dev_pm_domain_detach(gmu->gxpd, false);
1463 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1468 a6xx_gmu_memory_free(gmu);
1470 free_irq(gmu->gmu_irq, gmu);
1471 free_irq(gmu->hfi_irq, gmu);
1473 /* Drop reference taken in of_find_device_by_node */
1474 put_device(gmu->dev);
1476 gmu->initialized = false;
1479 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1481 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1482 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1483 struct platform_device *pdev = of_find_device_by_node(node);
1489 mutex_init(&gmu->lock);
1491 gmu->dev = &pdev->dev;
1493 of_dma_configure(gmu->dev, node, true);
1495 /* Fow now, don't do anything fancy until we get our feet under us */
1496 gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1498 pm_runtime_enable(gmu->dev);
1500 /* Get the list of clocks */
1501 ret = a6xx_gmu_clocks_probe(gmu);
1503 goto err_put_device;
1505 ret = a6xx_gmu_memory_probe(gmu);
1507 goto err_put_device;
1510 /* A660 now requires handling "prealloc requests" in GMU firmware
1511 * For now just hardcode allocations based on the known firmware.
1512 * note: there is no indication that these correspond to "dummy" or
1513 * "debug" regions, but this "guess" allows reusing these BOs which
1514 * are otherwise unused by a660.
1516 gmu->dummy.size = SZ_4K;
1517 if (adreno_is_a660_family(adreno_gpu)) {
1518 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);
1522 gmu->dummy.size = SZ_8K;
1525 /* Allocate memory for the GMU dummy page */
1526 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000);
1530 if (adreno_is_a650_family(adreno_gpu)) {
1531 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1532 SZ_16M - SZ_16K, 0x04000);
1535 } else if (adreno_is_a640_family(adreno_gpu)) {
1536 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1537 SZ_256K - SZ_16K, 0x04000);
1541 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1542 SZ_256K - SZ_16K, 0x44000);
1546 /* HFI v1, has sptprac */
1549 /* Allocate memory for the GMU debug region */
1550 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0);
1555 /* Allocate memory for for the HFI queues */
1556 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0);
1560 /* Allocate memory for the GMU log region */
1561 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0);
1565 /* Map the GMU registers */
1566 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1567 if (IS_ERR(gmu->mmio)) {
1568 ret = PTR_ERR(gmu->mmio);
1572 if (adreno_is_a650_family(adreno_gpu)) {
1573 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1574 if (IS_ERR(gmu->rscc))
1577 gmu->rscc = gmu->mmio + 0x23000;
1580 /* Get the HFI and GMU interrupts */
1581 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1582 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1584 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
1588 * Get a link to the GX power domain to reset the GPU in case of GMU
1591 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1593 /* Get the power levels for the GMU and GPU */
1594 a6xx_gmu_pwrlevels_probe(gmu);
1596 /* Set up the HFI queues */
1599 gmu->initialized = true;
1605 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1607 free_irq(gmu->gmu_irq, gmu);
1608 free_irq(gmu->hfi_irq, gmu);
1613 a6xx_gmu_memory_free(gmu);
1615 /* Drop reference taken in of_find_device_by_node */
1616 put_device(gmu->dev);