drivers/gpu/drm/mgag200/mgag200_mode.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2010 Matt Turner.
   4  * Copyright 2012 Red Hat
   5  *
   6  * Authors: Matthew Garrett
   7  *          Matt Turner
   8  *          Dave Airlie
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/pci.h>
  13
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_atomic_state_helper.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_damage_helper.h>
  18 #include <drm/drm_format_helper.h>
  19 #include <drm/drm_fourcc.h>
  20 #include <drm/drm_gem_framebuffer_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22 #include <drm/drm_print.h>
  23 #include <drm/drm_probe_helper.h>
  24 #include <drm/drm_simple_kms_helper.h>
  25
  26 #include "mgag200_drv.h"
  27
  28 #define MGAG200_LUT_SIZE 256
  29
  30 /*
  31  * This file contains setup code for the CRTC.
  32  */
  33
  34 static void mga_crtc_load_lut(struct drm_crtc *crtc)
  35 {
  36         struct drm_device *dev = crtc->dev;
  37         struct mga_device *mdev = to_mga_device(dev);
  38         struct drm_framebuffer *fb;
  39         u16 *r_ptr, *g_ptr, *b_ptr;
  40         int i;
  41
  42         if (!crtc->enabled)
  43                 return;
  44
  45         if (!mdev->display_pipe.plane.state)
  46                 return;
  47
  48         fb = mdev->display_pipe.plane.state->fb;
  49
  50         r_ptr = crtc->gamma_store;
  51         g_ptr = r_ptr + crtc->gamma_size;
  52         b_ptr = g_ptr + crtc->gamma_size;
  53
  54         WREG8(DAC_INDEX + MGA1064_INDEX, 0);
  55
  56         if (fb && fb->format->cpp[0] * 8 == 16) {
  57                 int inc = (fb->format->depth == 15) ? 8 : 4;
  58                 u8 r, b;
  59                 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
  60                         if (fb->format->depth == 16) {
  61                                 if (i > (MGAG200_LUT_SIZE >> 1)) {
  62                                         r = b = 0;
  63                                 } else {
  64                                         r = *r_ptr++ >> 8;
  65                                         b = *b_ptr++ >> 8;
  66                                         r_ptr++;
  67                                         b_ptr++;
  68                                 }
  69                         } else {
  70                                 r = *r_ptr++ >> 8;
  71                                 b = *b_ptr++ >> 8;
  72                         }
  73                         /* VGA registers */
  74                         WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
  75                         WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
  76                         WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
  77                 }
  78                 return;
  79         }
  80         for (i = 0; i < MGAG200_LUT_SIZE; i++) {
  81                 /* VGA registers */
  82                 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
  83                 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
  84                 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
  85         }
  86 }
  87
  88 static inline void mga_wait_vsync(struct mga_device *mdev)
  89 {
  90         unsigned long timeout = jiffies + HZ/10;
  91         unsigned int status = 0;
  92
  93         do {
  94                 status = RREG32(MGAREG_Status);
  95         } while ((status & 0x08) && time_before(jiffies, timeout));
  96         timeout = jiffies + HZ/10;
  97         status = 0;
  98         do {
  99                 status = RREG32(MGAREG_Status);
 100         } while (!(status & 0x08) && time_before(jiffies, timeout));
 101 }
 102
 103 static inline void mga_wait_busy(struct mga_device *mdev)
 104 {
 105         unsigned long timeout = jiffies + HZ;
 106         unsigned int status = 0;
 107         do {
 108                 status = RREG8(MGAREG_Status + 2);
 109         } while ((status & 0x01) && time_before(jiffies, timeout));
 110 }
 111
 112 #define P_ARRAY_SIZE 9
 113
 114 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
 115 {
 116         unsigned int vcomax, vcomin, pllreffreq;
 117         unsigned int delta, tmpdelta, permitteddelta;
 118         unsigned int testp, testm, testn;
 119         unsigned int p, m, n;
 120         unsigned int computed;
 121         unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
 122         unsigned int fvv;
 123         unsigned int i;
 124
 125         if (mdev->unique_rev_id <= 0x03) {
 126
 127                 m = n = p = 0;
 128                 vcomax = 320000;
 129                 vcomin = 160000;
 130                 pllreffreq = 25000;
 131
 132                 delta = 0xffffffff;
 133                 permitteddelta = clock * 5 / 1000;
 134
 135                 for (testp = 8; testp > 0; testp /= 2) {
 136                         if (clock * testp > vcomax)
 137                                 continue;
 138                         if (clock * testp < vcomin)
 139                                 continue;
 140
 141                         for (testn = 17; testn < 256; testn++) {
 142                                 for (testm = 1; testm < 32; testm++) {
 143                                         computed = (pllreffreq * testn) /
 144                                                 (testm * testp);
 145                                         if (computed > clock)
 146                                                 tmpdelta = computed - clock;
 147                                         else
 148                                                 tmpdelta = clock - computed;
 149                                         if (tmpdelta < delta) {
 150                                                 delta = tmpdelta;
 151                                                 m = testm - 1;
 152                                                 n = testn - 1;
 153                                                 p = testp - 1;
 154                                         }
 155                                 }
 156                         }
 157                 }
 158         } else {
 159
 160
 161                 m = n = p = 0;
 162                 vcomax        = 1600000;
 163                 vcomin        = 800000;
 164                 pllreffreq    = 25000;
 165
 166                 if (clock < 25000)
 167                         clock = 25000;
 168
 169                 clock = clock * 2;
 170
 171                 delta = 0xFFFFFFFF;
 172                 /* Permited delta is 0.5% as VESA Specification */
 173                 permitteddelta = clock * 5 / 1000;
 174
 175                 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
 176                         testp = pvalues_e4[i];
 177
 178                         if ((clock * testp) > vcomax)
 179                                 continue;
 180                         if ((clock * testp) < vcomin)
 181                                 continue;
 182
 183                         for (testn = 50; testn <= 256; testn++) {
 184                                 for (testm = 1; testm <= 32; testm++) {
 185                                         computed = (pllreffreq * testn) /
 186                                                 (testm * testp);
 187                                         if (computed > clock)
 188                                                 tmpdelta = computed - clock;
 189                                         else
 190                                                 tmpdelta = clock - computed;
 191
 192                                         if (tmpdelta < delta) {
 193                                                 delta = tmpdelta;
 194                                                 m = testm - 1;
 195                                                 n = testn - 1;
 196                                                 p = testp - 1;
 197                                         }
 198                                 }
 199                         }
 200                 }
 201
 202                 fvv = pllreffreq * (n + 1) / (m + 1);
 203                 fvv = (fvv - 800000) / 50000;
 204
 205                 if (fvv > 15)
 206                         fvv = 15;
 207
 208                 p |= (fvv << 4);
 209                 m |= 0x80;
 210
 211                 clock = clock / 2;
 212         }
 213
 214         if (delta > permitteddelta) {
 215                 pr_warn("PLL delta too large\n");
 216                 return 1;
 217         }
 218
 219         WREG_DAC(MGA1064_PIX_PLLC_M, m);
 220         WREG_DAC(MGA1064_PIX_PLLC_N, n);
 221         WREG_DAC(MGA1064_PIX_PLLC_P, p);
 222
 223         if (mdev->unique_rev_id >= 0x04) {
 224                 WREG_DAC(0x1a, 0x09);
 225                 msleep(20);
 226                 WREG_DAC(0x1a, 0x01);
 227
 228         }
 229
 230         return 0;
 231 }
 232
 233 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
 234 {
 235         unsigned int vcomax, vcomin, pllreffreq;
 236         unsigned int delta, tmpdelta;
 237         unsigned int testp, testm, testn, testp2;
 238         unsigned int p, m, n;
 239         unsigned int computed;
 240         int i, j, tmpcount, vcount;
 241         bool pll_locked = false;
 242         u8 tmp;
 243
 244         m = n = p = 0;
 245
 246         delta = 0xffffffff;
 247
 248         if (mdev->type == G200_EW3) {
 249
 250                 vcomax = 800000;
 251                 vcomin = 400000;
 252                 pllreffreq = 25000;
 253
 254                 for (testp = 1; testp < 8; testp++) {
 255                         for (testp2 = 1; testp2 < 8; testp2++) {
 256                                 if (testp < testp2)
 257                                         continue;
 258                                 if ((clock * testp * testp2) > vcomax)
 259                                         continue;
 260                                 if ((clock * testp * testp2) < vcomin)
 261                                         continue;
 262                                 for (testm = 1; testm < 26; testm++) {
 263                                         for (testn = 32; testn < 2048 ; testn++) {
 264                                                 computed = (pllreffreq * testn) /
 265                                                         (testm * testp * testp2);
 266                                                 if (computed > clock)
 267                                                         tmpdelta = computed - clock;
 268                                                 else
 269                                                         tmpdelta = clock - computed;
 270                                                 if (tmpdelta < delta) {
 271                                                         delta = tmpdelta;
 272                                                         m = ((testn & 0x100) >> 1) |
 273                                                                 (testm);
 274                                                         n = (testn & 0xFF);
 275                                                         p = ((testn & 0x600) >> 3) |
 276                                                                 (testp2 << 3) |
 277                                                                 (testp);
 278                                                 }
 279                                         }
 280                                 }
 281                         }
 282                 }
 283         } else {
 284
 285                 vcomax = 550000;
 286                 vcomin = 150000;
 287                 pllreffreq = 48000;
 288
 289                 for (testp = 1; testp < 9; testp++) {
 290                         if (clock * testp > vcomax)
 291                                 continue;
 292                         if (clock * testp < vcomin)
 293                                 continue;
 294
 295                         for (testm = 1; testm < 17; testm++) {
 296                                 for (testn = 1; testn < 151; testn++) {
 297                                         computed = (pllreffreq * testn) /
 298                                                 (testm * testp);
 299                                         if (computed > clock)
 300                                                 tmpdelta = computed - clock;
 301                                         else
 302                                                 tmpdelta = clock - computed;
 303                                         if (tmpdelta < delta) {
 304                                                 delta = tmpdelta;
 305                                                 n = testn - 1;
 306                                                 m = (testm - 1) |
 307                                                         ((n >> 1) & 0x80);
 308                                                 p = testp - 1;
 309                                         }
 310                                 }
 311                         }
 312                 }
 313         }
 314
 315         for (i = 0; i <= 32 && pll_locked == false; i++) {
 316                 if (i > 0) {
 317                         WREG8(MGAREG_CRTC_INDEX, 0x1e);
 318                         tmp = RREG8(MGAREG_CRTC_DATA);
 319                         if (tmp < 0xff)
 320                                 WREG8(MGAREG_CRTC_DATA, tmp+1);
 321                 }
 322
 323                 /* set pixclkdis to 1 */
 324                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 325                 tmp = RREG8(DAC_DATA);
 326                 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 327                 WREG8(DAC_DATA, tmp);
 328
 329                 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 330                 tmp = RREG8(DAC_DATA);
 331                 tmp |= MGA1064_REMHEADCTL_CLKDIS;
 332                 WREG8(DAC_DATA, tmp);
 333
 334                 /* select PLL Set C */
 335                 tmp = RREG8(MGAREG_MEM_MISC_READ);
 336                 tmp |= 0x3 << 2;
 337                 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 338
 339                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 340                 tmp = RREG8(DAC_DATA);
 341                 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
 342                 WREG8(DAC_DATA, tmp);
 343
 344                 udelay(500);
 345
 346                 /* reset the PLL */
 347                 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
 348                 tmp = RREG8(DAC_DATA);
 349                 tmp &= ~0x04;
 350                 WREG8(DAC_DATA, tmp);
 351
 352                 udelay(50);
 353
 354                 /* program pixel pll register */
 355                 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
 356                 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
 357                 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
 358
 359                 udelay(50);
 360
 361                 /* turn pll on */
 362                 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
 363                 tmp = RREG8(DAC_DATA);
 364                 tmp |= 0x04;
 365                 WREG_DAC(MGA1064_VREF_CTL, tmp);
 366
 367                 udelay(500);
 368
 369                 /* select the pixel pll */
 370                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 371                 tmp = RREG8(DAC_DATA);
 372                 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
 373                 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
 374                 WREG8(DAC_DATA, tmp);
 375
 376                 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 377                 tmp = RREG8(DAC_DATA);
 378                 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
 379                 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
 380                 WREG8(DAC_DATA, tmp);
 381
 382                 /* reset dotclock rate bit */
 383                 WREG8(MGAREG_SEQ_INDEX, 1);
 384                 tmp = RREG8(MGAREG_SEQ_DATA);
 385                 tmp &= ~0x8;
 386                 WREG8(MGAREG_SEQ_DATA, tmp);
 387
 388                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 389                 tmp = RREG8(DAC_DATA);
 390                 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 391                 WREG8(DAC_DATA, tmp);
 392
 393                 vcount = RREG8(MGAREG_VCOUNT);
 394
 395                 for (j = 0; j < 30 && pll_locked == false; j++) {
 396                         tmpcount = RREG8(MGAREG_VCOUNT);
 397                         if (tmpcount < vcount)
 398                                 vcount = 0;
 399                         if ((tmpcount - vcount) > 2)
 400                                 pll_locked = true;
 401                         else
 402                                 udelay(5);
 403                 }
 404         }
 405         WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 406         tmp = RREG8(DAC_DATA);
 407         tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
 408         WREG_DAC(MGA1064_REMHEADCTL, tmp);
 409         return 0;
 410 }
 411
 412 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
 413 {
 414         unsigned int vcomax, vcomin, pllreffreq;
 415         unsigned int delta, tmpdelta;
 416         unsigned int testp, testm, testn;
 417         unsigned int p, m, n;
 418         unsigned int computed;
 419         u8 tmp;
 420
 421         m = n = p = 0;
 422         vcomax = 550000;
 423         vcomin = 150000;
 424         pllreffreq = 50000;
 425
 426         delta = 0xffffffff;
 427
 428         for (testp = 16; testp > 0; testp--) {
 429                 if (clock * testp > vcomax)
 430                         continue;
 431                 if (clock * testp < vcomin)
 432                         continue;
 433
 434                 for (testn = 1; testn < 257; testn++) {
 435                         for (testm = 1; testm < 17; testm++) {
 436                                 computed = (pllreffreq * testn) /
 437                                         (testm * testp);
 438                                 if (computed > clock)
 439                                         tmpdelta = computed - clock;
 440                                 else
 441                                         tmpdelta = clock - computed;
 442                                 if (tmpdelta < delta) {
 443                                         delta = tmpdelta;
 444                                         n = testn - 1;
 445                                         m = testm - 1;
 446                                         p = testp - 1;
 447                                 }
 448                         }
 449                 }
 450         }
 451
 452         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 453         tmp = RREG8(DAC_DATA);
 454         tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 455         WREG8(DAC_DATA, tmp);
 456
 457         tmp = RREG8(MGAREG_MEM_MISC_READ);
 458         tmp |= 0x3 << 2;
 459         WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 460
 461         WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
 462         tmp = RREG8(DAC_DATA);
 463         WREG8(DAC_DATA, tmp & ~0x40);
 464
 465         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 466         tmp = RREG8(DAC_DATA);
 467         tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 468         WREG8(DAC_DATA, tmp);
 469
 470         WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
 471         WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
 472         WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
 473
 474         udelay(50);
 475
 476         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 477         tmp = RREG8(DAC_DATA);
 478         tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 479         WREG8(DAC_DATA, tmp);
 480
 481         udelay(500);
 482
 483         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 484         tmp = RREG8(DAC_DATA);
 485         tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
 486         tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
 487         WREG8(DAC_DATA, tmp);
 488
 489         WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
 490         tmp = RREG8(DAC_DATA);
 491         WREG8(DAC_DATA, tmp | 0x40);
 492
 493         tmp = RREG8(MGAREG_MEM_MISC_READ);
 494         tmp |= (0x3 << 2);
 495         WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 496
 497         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 498         tmp = RREG8(DAC_DATA);
 499         tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 500         WREG8(DAC_DATA, tmp);
 501
 502         return 0;
 503 }
 504
 505 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
 506 {
 507         unsigned int vcomax, vcomin, pllreffreq;
 508         unsigned int delta, tmpdelta;
 509         unsigned int testp, testm, testn;
 510         unsigned int p, m, n;
 511         unsigned int computed;
 512         int i, j, tmpcount, vcount;
 513         u8 tmp;
 514         bool pll_locked = false;
 515
 516         m = n = p = 0;
 517
 518         if (mdev->type == G200_EH3) {
 519                 vcomax = 3000000;
 520                 vcomin = 1500000;
 521                 pllreffreq = 25000;
 522
 523                 delta = 0xffffffff;
 524
 525                 testp = 0;
 526
 527                 for (testm = 150; testm >= 6; testm--) {
 528                         if (clock * testm > vcomax)
 529                                 continue;
 530                         if (clock * testm < vcomin)
 531                                 continue;
 532                         for (testn = 120; testn >= 60; testn--) {
 533                                 computed = (pllreffreq * testn) / testm;
 534                                 if (computed > clock)
 535                                         tmpdelta = computed - clock;
 536                                 else
 537                                         tmpdelta = clock - computed;
 538                                 if (tmpdelta < delta) {
 539                                         delta = tmpdelta;
 540                                         n = testn;
 541                                         m = testm;
 542                                         p = testp;
 543                                 }
 544                                 if (delta == 0)
 545                                         break;
 546                         }
 547                         if (delta == 0)
 548                                 break;
 549                 }
 550         } else {
 551
 552                 vcomax = 800000;
 553                 vcomin = 400000;
 554                 pllreffreq = 33333;
 555
 556                 delta = 0xffffffff;
 557
 558                 for (testp = 16; testp > 0; testp >>= 1) {
 559                         if (clock * testp > vcomax)
 560                                 continue;
 561                         if (clock * testp < vcomin)
 562                                 continue;
 563
 564                         for (testm = 1; testm < 33; testm++) {
 565                                 for (testn = 17; testn < 257; testn++) {
 566                                         computed = (pllreffreq * testn) /
 567                                                 (testm * testp);
 568                                         if (computed > clock)
 569                                                 tmpdelta = computed - clock;
 570                                         else
 571                                                 tmpdelta = clock - computed;
 572                                         if (tmpdelta < delta) {
 573                                                 delta = tmpdelta;
 574                                                 n = testn - 1;
 575                                                 m = (testm - 1);
 576                                                 p = testp - 1;
 577                                         }
 578                                         if ((clock * testp) >= 600000)
 579                                                 p |= 0x80;
 580                                 }
 581                         }
 582                 }
 583         }
 584         for (i = 0; i <= 32 && pll_locked == false; i++) {
 585                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 586                 tmp = RREG8(DAC_DATA);
 587                 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 588                 WREG8(DAC_DATA, tmp);
 589
 590                 tmp = RREG8(MGAREG_MEM_MISC_READ);
 591                 tmp |= 0x3 << 2;
 592                 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 593
 594                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 595                 tmp = RREG8(DAC_DATA);
 596                 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 597                 WREG8(DAC_DATA, tmp);
 598
 599                 udelay(500);
 600
 601                 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
 602                 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
 603                 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
 604
 605                 udelay(500);
 606
 607                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 608                 tmp = RREG8(DAC_DATA);
 609                 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
 610                 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
 611                 WREG8(DAC_DATA, tmp);
 612
 613                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 614                 tmp = RREG8(DAC_DATA);
 615                 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 616                 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 617                 WREG8(DAC_DATA, tmp);
 618
 619                 vcount = RREG8(MGAREG_VCOUNT);
 620
 621                 for (j = 0; j < 30 && pll_locked == false; j++) {
 622                         tmpcount = RREG8(MGAREG_VCOUNT);
 623                         if (tmpcount < vcount)
 624                                 vcount = 0;
 625                         if ((tmpcount - vcount) > 2)
 626                                 pll_locked = true;
 627                         else
 628                                 udelay(5);
 629                 }
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
 636 {
 637         unsigned int vcomax, vcomin, pllreffreq;
 638         unsigned int delta, tmpdelta;
 639         int testr, testn, testm, testo;
 640         unsigned int p, m, n;
 641         unsigned int computed, vco;
 642         int tmp;
 643         const unsigned int m_div_val[] = { 1, 2, 4, 8 };
 644
 645         m = n = p = 0;
 646         vcomax = 1488000;
 647         vcomin = 1056000;
 648         pllreffreq = 48000;
 649
 650         delta = 0xffffffff;
 651
 652         for (testr = 0; testr < 4; testr++) {
 653                 if (delta == 0)
 654                         break;
 655                 for (testn = 5; testn < 129; testn++) {
 656                         if (delta == 0)
 657                                 break;
 658                         for (testm = 3; testm >= 0; testm--) {
 659                                 if (delta == 0)
 660                                         break;
 661                                 for (testo = 5; testo < 33; testo++) {
 662                                         vco = pllreffreq * (testn + 1) /
 663                                                 (testr + 1);
 664                                         if (vco < vcomin)
 665                                                 continue;
 666                                         if (vco > vcomax)
 667                                                 continue;
 668                                         computed = vco / (m_div_val[testm] * (testo + 1));
 669                                         if (computed > clock)
 670                                                 tmpdelta = computed - clock;
 671                                         else
 672                                                 tmpdelta = clock - computed;
 673                                         if (tmpdelta < delta) {
 674                                                 delta = tmpdelta;
 675                                                 m = testm | (testo << 3);
 676                                                 n = testn;
 677                                                 p = testr | (testr << 3);
 678                                         }
 679                                 }
 680                         }
 681                 }
 682         }
 683
 684         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 685         tmp = RREG8(DAC_DATA);
 686         tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 687         WREG8(DAC_DATA, tmp);
 688
 689         WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 690         tmp = RREG8(DAC_DATA);
 691         tmp |= MGA1064_REMHEADCTL_CLKDIS;
 692         WREG8(DAC_DATA, tmp);
 693
 694         tmp = RREG8(MGAREG_MEM_MISC_READ);
 695         tmp |= (0x3<<2) | 0xc0;
 696         WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 697
 698         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 699         tmp = RREG8(DAC_DATA);
 700         tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 701         tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 702         WREG8(DAC_DATA, tmp);
 703
 704         udelay(500);
 705
 706         WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
 707         WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
 708         WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
 709
 710         udelay(50);
 711
 712         return 0;
 713 }
 714
 715 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
 716 {
 717         u8 misc;
 718
 719         switch(mdev->type) {
 720         case G200_SE_A:
 721         case G200_SE_B:
 722                 return mga_g200se_set_plls(mdev, clock);
 723                 break;
 724         case G200_WB:
 725         case G200_EW3:
 726                 return mga_g200wb_set_plls(mdev, clock);
 727                 break;
 728         case G200_EV:
 729                 return mga_g200ev_set_plls(mdev, clock);
 730                 break;
 731         case G200_EH:
 732         case G200_EH3:
 733                 return mga_g200eh_set_plls(mdev, clock);
 734                 break;
 735         case G200_ER:
 736                 return mga_g200er_set_plls(mdev, clock);
 737                 break;
 738         }
 739
 740         misc = RREG8(MGA_MISC_IN);
 741         misc &= ~MGAREG_MISC_CLK_SEL_MASK;
 742         misc |= MGAREG_MISC_CLK_SEL_MGA_MSK;
 743         WREG8(MGA_MISC_OUT, misc);
 744
 745         return 0;
 746 }
 747
 748 static void mga_g200wb_prepare(struct drm_crtc *crtc)
 749 {
 750         struct mga_device *mdev = to_mga_device(crtc->dev);
 751         u8 tmp;
 752         int iter_max;
 753
 754         /* 1- The first step is to warn the BMC of an upcoming mode change.
 755          * We are putting the misc<0> to output.*/
 756
 757         WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
 758         tmp = RREG8(DAC_DATA);
 759         tmp |= 0x10;
 760         WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
 761
 762         /* we are putting a 1 on the misc<0> line */
 763         WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
 764         tmp = RREG8(DAC_DATA);
 765         tmp |= 0x10;
 766         WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
 767
 768         /* 2- Second step to mask and further scan request
 769          * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
 770          */
 771         WREG8(DAC_INDEX, MGA1064_SPAREREG);
 772         tmp = RREG8(DAC_DATA);
 773         tmp |= 0x80;
 774         WREG_DAC(MGA1064_SPAREREG, tmp);
 775
 776         /* 3a- the third step is to verifu if there is an active scan
 777          * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
 778          */
 779         iter_max = 300;
 780         while (!(tmp & 0x1) && iter_max) {
 781                 WREG8(DAC_INDEX, MGA1064_SPAREREG);
 782                 tmp = RREG8(DAC_DATA);
 783                 udelay(1000);
 784                 iter_max--;
 785         }
 786
 787         /* 3b- this step occurs only if the remove is actually scanning
 788          * we are waiting for the end of the frame which is a 1 on
 789          * remvsyncsts (XSPAREREG<1>)
 790          */
 791         if (iter_max) {
 792                 iter_max = 300;
 793                 while ((tmp & 0x2) && iter_max) {
 794                         WREG8(DAC_INDEX, MGA1064_SPAREREG);
 795                         tmp = RREG8(DAC_DATA);
 796                         udelay(1000);
 797                         iter_max--;
 798                 }
 799         }
 800 }
 801
 802 static void mga_g200wb_commit(struct drm_crtc *crtc)
 803 {
 804         u8 tmp;
 805         struct mga_device *mdev = to_mga_device(crtc->dev);
 806
 807         /* 1- The first step is to ensure that the vrsten and hrsten are set */
 808         WREG8(MGAREG_CRTCEXT_INDEX, 1);
 809         tmp = RREG8(MGAREG_CRTCEXT_DATA);
 810         WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
 811
 812         /* 2- second step is to assert the rstlvl2 */
 813         WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
 814         tmp = RREG8(DAC_DATA);
 815         tmp |= 0x8;
 816         WREG8(DAC_DATA, tmp);
 817
 818         /* wait 10 us */
 819         udelay(10);
 820
 821         /* 3- deassert rstlvl2 */
 822         tmp &= ~0x08;
 823         WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
 824         WREG8(DAC_DATA, tmp);
 825
 826         /* 4- remove mask of scan request */
 827         WREG8(DAC_INDEX, MGA1064_SPAREREG);
 828         tmp = RREG8(DAC_DATA);
 829         tmp &= ~0x80;
 830         WREG8(DAC_DATA, tmp);
 831
 832         /* 5- put back a 0 on the misc<0> line */
 833         WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
 834         tmp = RREG8(DAC_DATA);
 835         tmp &= ~0x10;
 836         WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
 837 }
 838
 839 /*
 840  * This is how the framebuffer base address is stored in g200 cards:
 841  *   * Assume @offset is the gpu_addr variable of the framebuffer object
 842  *   * Then addr is the number of _pixels_ (not bytes) from the start of
 843  *     VRAM to the first pixel we want to display. (divided by 2 for 32bit
 844  *     framebuffers)
 845  *   * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
 846  *      addr<20> -> CRTCEXT0<6>
 847  *      addr<19-16> -> CRTCEXT0<3-0>
 848  *      addr<15-8> -> CRTCC<7-0>
 849  *      addr<7-0> -> CRTCD<7-0>
 850  *
 851  *  CRTCEXT0 has to be programmed last to trigger an update and make the
 852  *  new addr variable take effect.
 853  */
 854 static void mgag200_set_startadd(struct mga_device *mdev,
 855                                  unsigned long offset)
 856 {
 857         struct drm_device *dev = &mdev->base;
 858         u32 startadd;
 859         u8 crtcc, crtcd, crtcext0;
 860
 861         startadd = offset / 8;
 862
 863         /*
 864          * Can't store addresses any higher than that, but we also
 865          * don't have more than 16 MiB of memory, so it should be fine.
 866          */
 867         drm_WARN_ON(dev, startadd > 0x1fffff);
 868
 869         RREG_ECRT(0x00, crtcext0);
 870
 871         crtcc = (startadd >> 8) & 0xff;
 872         crtcd = startadd & 0xff;
 873         crtcext0 &= 0xb0;
 874         crtcext0 |= ((startadd >> 14) & BIT(6)) |
 875                     ((startadd >> 16) & 0x0f);
 876
 877         WREG_CRT(0x0c, crtcc);
 878         WREG_CRT(0x0d, crtcd);
 879         WREG_ECRT(0x00, crtcext0);
 880 }
 881
 882 static void mgag200_set_pci_regs(struct mga_device *mdev)
 883 {
 884         uint32_t option = 0, option2 = 0;
 885         struct drm_device *dev = &mdev->base;
 886
 887         switch (mdev->type) {
 888         case G200_SE_A:
 889         case G200_SE_B:
 890                 if (mdev->has_sdram)
 891                         option = 0x40049120;
 892                 else
 893                         option = 0x4004d120;
 894                 option2 = 0x00008000;
 895                 break;
 896         case G200_WB:
 897         case G200_EW3:
 898                 option = 0x41049120;
 899                 option2 = 0x0000b000;
 900                 break;
 901         case G200_EV:
 902                 option = 0x00000120;
 903                 option2 = 0x0000b000;
 904                 break;
 905         case G200_EH:
 906         case G200_EH3:
 907                 option = 0x00000120;
 908                 option2 = 0x0000b000;
 909                 break;
 910         case G200_ER:
 911                 break;
 912         }
 913
 914         if (option)
 915                 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
 916
 917         if (option2)
 918                 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
 919 }
 920
 921 static void mgag200_set_dac_regs(struct mga_device *mdev)
 922 {
 923         size_t i;
 924         u8 dacvalue[] = {
 925                 /* 0x00: */        0,    0,    0,    0,    0,    0, 0x00,    0,
 926                 /* 0x08: */        0,    0,    0,    0,    0,    0,    0,    0,
 927                 /* 0x10: */        0,    0,    0,    0,    0,    0,    0,    0,
 928                 /* 0x18: */     0x00,    0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
 929                 /* 0x20: */     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 930                 /* 0x28: */     0x00, 0x00, 0x00, 0x00,    0,    0,    0, 0x40,
 931                 /* 0x30: */     0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
 932                 /* 0x38: */     0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
 933                 /* 0x40: */        0,    0,    0,    0,    0,    0,    0,    0,
 934                 /* 0x48: */        0,    0,    0,    0,    0,    0,    0,    0
 935         };
 936
 937         switch (mdev->type) {
 938         case G200_SE_A:
 939         case G200_SE_B:
 940                 dacvalue[MGA1064_VREF_CTL] = 0x03;
 941                 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
 942                 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
 943                                              MGA1064_MISC_CTL_VGA8 |
 944                                              MGA1064_MISC_CTL_DAC_RAM_CS;
 945                 break;
 946         case G200_WB:
 947         case G200_EW3:
 948                 dacvalue[MGA1064_VREF_CTL] = 0x07;
 949                 break;
 950         case G200_EV:
 951                 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
 952                 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
 953                                              MGA1064_MISC_CTL_DAC_RAM_CS;
 954                 break;
 955         case G200_EH:
 956         case G200_EH3:
 957                 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
 958                                              MGA1064_MISC_CTL_DAC_RAM_CS;
 959                 break;
 960         case G200_ER:
 961                 break;
 962         }
 963
 964         for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
 965                 if ((i <= 0x17) ||
 966                     (i == 0x1b) ||
 967                     (i == 0x1c) ||
 968                     ((i >= 0x1f) && (i <= 0x29)) ||
 969                     ((i >= 0x30) && (i <= 0x37)))
 970                         continue;
 971                 if (IS_G200_SE(mdev) &&
 972                     ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
 973                         continue;
 974                 if ((mdev->type == G200_EV ||
 975                     mdev->type == G200_WB ||
 976                     mdev->type == G200_EH ||
 977                     mdev->type == G200_EW3 ||
 978                     mdev->type == G200_EH3) &&
 979                     (i >= 0x44) && (i <= 0x4e))
 980                         continue;
 981
 982                 WREG_DAC(i, dacvalue[i]);
 983         }
 984
 985         if (mdev->type == G200_ER)
 986                 WREG_DAC(0x90, 0);
 987 }
 988
 989 static void mgag200_init_regs(struct mga_device *mdev)
 990 {
 991         u8 crtcext3, crtcext4, misc;
 992
 993         mgag200_set_pci_regs(mdev);
 994         mgag200_set_dac_regs(mdev);
 995
 996         WREG_SEQ(2, 0x0f);
 997         WREG_SEQ(3, 0x00);
 998         WREG_SEQ(4, 0x0e);
 999
1000         WREG_CRT(10, 0);
1001         WREG_CRT(11, 0);
1002         WREG_CRT(12, 0);
1003         WREG_CRT(13, 0);
1004         WREG_CRT(14, 0);
1005         WREG_CRT(15, 0);
1006
1007         RREG_ECRT(0x03, crtcext3);
1008
1009         crtcext3 |= BIT(7); /* enable MGA mode */
1010         crtcext4 = 0x00;
1011
1012         WREG_ECRT(0x03, crtcext3);
1013         WREG_ECRT(0x04, crtcext4);
1014
1015         if (mdev->type == G200_ER)
1016                 WREG_ECRT(0x24, 0x5);
1017
1018         if (mdev->type == G200_EW3)
1019                 WREG_ECRT(0x34, 0x5);
1020
1021         misc = RREG8(MGA_MISC_IN);
1022         misc |= MGAREG_MISC_IOADSEL |
1023                 MGAREG_MISC_RAMMAPEN |
1024                 MGAREG_MISC_HIGH_PG_SEL;
1025         WREG8(MGA_MISC_OUT, misc);
1026 }
1027
1028 static void mgag200_set_mode_regs(struct mga_device *mdev,
1029                                   const struct drm_display_mode *mode)
1030 {
1031         unsigned int hdisplay, hsyncstart, hsyncend, htotal;
1032         unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
1033         u8 misc, crtcext1, crtcext2, crtcext5;
1034
1035         hdisplay = mode->hdisplay / 8 - 1;
1036         hsyncstart = mode->hsync_start / 8 - 1;
1037         hsyncend = mode->hsync_end / 8 - 1;
1038         htotal = mode->htotal / 8 - 1;
1039
1040         /* Work around hardware quirk */
1041         if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1042                 htotal++;
1043
1044         vdisplay = mode->vdisplay - 1;
1045         vsyncstart = mode->vsync_start - 1;
1046         vsyncend = mode->vsync_end - 1;
1047         vtotal = mode->vtotal - 2;
1048
1049         misc = RREG8(MGA_MISC_IN);
1050
1051         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1052                 misc |= MGAREG_MISC_HSYNCPOL;
1053         else
1054                 misc &= ~MGAREG_MISC_HSYNCPOL;
1055
1056         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1057                 misc |= MGAREG_MISC_VSYNCPOL;
1058         else
1059                 misc &= ~MGAREG_MISC_VSYNCPOL;
1060
1061         crtcext1 = (((htotal - 4) & 0x100) >> 8) |
1062                    ((hdisplay & 0x100) >> 7) |
1063                    ((hsyncstart & 0x100) >> 6) |
1064                     (htotal & 0x40);
1065         if (mdev->type == G200_WB || mdev->type == G200_EW3)
1066                 crtcext1 |= BIT(7) | /* vrsten */
1067                             BIT(3); /* hrsten */
1068
1069         crtcext2 = ((vtotal & 0xc00) >> 10) |
1070                    ((vdisplay & 0x400) >> 8) |
1071                    ((vdisplay & 0xc00) >> 7) |
1072                    ((vsyncstart & 0xc00) >> 5) |
1073                    ((vdisplay & 0x400) >> 3);
1074         crtcext5 = 0x00;
1075
1076         WREG_CRT(0, htotal - 4);
1077         WREG_CRT(1, hdisplay);
1078         WREG_CRT(2, hdisplay);
1079         WREG_CRT(3, (htotal & 0x1F) | 0x80);
1080         WREG_CRT(4, hsyncstart);
1081         WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1082         WREG_CRT(6, vtotal & 0xFF);
1083         WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1084                  ((vdisplay & 0x100) >> 7) |
1085                  ((vsyncstart & 0x100) >> 6) |
1086                  ((vdisplay & 0x100) >> 5) |
1087                  ((vdisplay & 0x100) >> 4) | /* linecomp */
1088                  ((vtotal & 0x200) >> 4) |
1089                  ((vdisplay & 0x200) >> 3) |
1090                  ((vsyncstart & 0x200) >> 2));
1091         WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1092                  ((vdisplay & 0x200) >> 3));
1093         WREG_CRT(16, vsyncstart & 0xFF);
1094         WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1095         WREG_CRT(18, vdisplay & 0xFF);
1096         WREG_CRT(20, 0);
1097         WREG_CRT(21, vdisplay & 0xFF);
1098         WREG_CRT(22, (vtotal + 1) & 0xFF);
1099         WREG_CRT(23, 0xc3);
1100         WREG_CRT(24, vdisplay & 0xFF);
1101
1102         WREG_ECRT(0x01, crtcext1);
1103         WREG_ECRT(0x02, crtcext2);
1104         WREG_ECRT(0x05, crtcext5);
1105
1106         WREG8(MGA_MISC_OUT, misc);
1107
1108         mga_crtc_set_plls(mdev, mode->clock);
1109 }
1110
1111 static u8 mgag200_get_bpp_shift(struct mga_device *mdev,
1112                                 const struct drm_format_info *format)
1113 {
1114         return mdev->bpp_shifts[format->cpp[0] - 1];
1115 }
1116
1117 /*
1118  * Calculates the HW offset value from the framebuffer's pitch. The
1119  * offset is a multiple of the pixel size and depends on the display
1120  * format.
1121  */
1122 static u32 mgag200_calculate_offset(struct mga_device *mdev,
1123                                     const struct drm_framebuffer *fb)
1124 {
1125         u32 offset = fb->pitches[0] / fb->format->cpp[0];
1126         u8 bppshift = mgag200_get_bpp_shift(mdev, fb->format);
1127
1128         if (fb->format->cpp[0] * 8 == 24)
1129                 offset = (offset * 3) >> (4 - bppshift);
1130         else
1131                 offset = offset >> (4 - bppshift);
1132
1133         return offset;
1134 }
1135
1136 static void mgag200_set_offset(struct mga_device *mdev,
1137                                const struct drm_framebuffer *fb)
1138 {
1139         u8 crtc13, crtcext0;
1140         u32 offset = mgag200_calculate_offset(mdev, fb);
1141
1142         RREG_ECRT(0, crtcext0);
1143
1144         crtc13 = offset & 0xff;
1145
1146         crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
1147         crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
1148
1149         WREG_CRT(0x13, crtc13);
1150         WREG_ECRT(0x00, crtcext0);
1151 }
1152
1153 static void mgag200_set_format_regs(struct mga_device *mdev,
1154                                     const struct drm_framebuffer *fb)
1155 {
1156         struct drm_device *dev = &mdev->base;
1157         const struct drm_format_info *format = fb->format;
1158         unsigned int bpp, bppshift, scale;
1159         u8 crtcext3, xmulctrl;
1160
1161         bpp = format->cpp[0] * 8;
1162
1163         bppshift = mgag200_get_bpp_shift(mdev, format);
1164         switch (bpp) {
1165         case 24:
1166                 scale = ((1 << bppshift) * 3) - 1;
1167                 break;
1168         default:
1169                 scale = (1 << bppshift) - 1;
1170                 break;
1171         }
1172
1173         RREG_ECRT(3, crtcext3);
1174
1175         switch (bpp) {
1176         case 8:
1177                 xmulctrl = MGA1064_MUL_CTL_8bits;
1178                 break;
1179         case 16:
1180                 if (format->depth == 15)
1181                         xmulctrl = MGA1064_MUL_CTL_15bits;
1182                 else
1183                         xmulctrl = MGA1064_MUL_CTL_16bits;
1184                 break;
1185         case 24:
1186                 xmulctrl = MGA1064_MUL_CTL_24bits;
1187                 break;
1188         case 32:
1189                 xmulctrl = MGA1064_MUL_CTL_32_24bits;
1190                 break;
1191         default:
1192                 /* BUG: We should have caught this problem already. */
1193                 drm_WARN_ON(dev, "invalid format depth\n");
1194                 return;
1195         }
1196
1197         crtcext3 &= ~GENMASK(2, 0);
1198         crtcext3 |= scale;
1199
1200         WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
1201
1202         WREG_GFX(0, 0x00);
1203         WREG_GFX(1, 0x00);
1204         WREG_GFX(2, 0x00);
1205         WREG_GFX(3, 0x00);
1206         WREG_GFX(4, 0x00);
1207         WREG_GFX(5, 0x40);
1208         WREG_GFX(6, 0x05);
1209         WREG_GFX(7, 0x0f);
1210         WREG_GFX(8, 0x0f);
1211
1212         WREG_ECRT(3, crtcext3);
1213 }
1214
1215 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev)
1216 {
1217         static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */
1218         u8 seq1;
1219         u32 memctl;
1220
1221         /* screen off */
1222         RREG_SEQ(0x01, seq1);
1223         seq1 |= MGAREG_SEQ1_SCROFF;
1224         WREG_SEQ(0x01, seq1);
1225
1226         memctl = RREG32(MGAREG_MEMCTL);
1227
1228         memctl |= RESET_FLAG;
1229         WREG32(MGAREG_MEMCTL, memctl);
1230
1231         udelay(1000);
1232
1233         memctl &= ~RESET_FLAG;
1234         WREG32(MGAREG_MEMCTL, memctl);
1235
1236         /* screen on */
1237         RREG_SEQ(0x01, seq1);
1238         seq1 &= ~MGAREG_SEQ1_SCROFF;
1239         WREG_SEQ(0x01, seq1);
1240 }
1241
1242 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev,
1243                                         const struct drm_display_mode *mode,
1244                                         const struct drm_framebuffer *fb)
1245 {
1246         unsigned int hiprilvl;
1247         u8 crtcext6;
1248
1249         if  (mdev->unique_rev_id >= 0x04) {
1250                 hiprilvl = 0;
1251         } else if (mdev->unique_rev_id >= 0x02) {
1252                 unsigned int bpp;
1253                 unsigned long mb;
1254
1255                 if (fb->format->cpp[0] * 8 > 16)
1256                         bpp = 32;
1257                 else if (fb->format->cpp[0] * 8 > 8)
1258                         bpp = 16;
1259                 else
1260                         bpp = 8;
1261
1262                 mb = (mode->clock * bpp) / 1000;
1263                 if (mb > 3100)
1264                         hiprilvl = 0;
1265                 else if (mb > 2600)
1266                         hiprilvl = 1;
1267                 else if (mb > 1900)
1268                         hiprilvl = 2;
1269                 else if (mb > 1160)
1270                         hiprilvl = 3;
1271                 else if (mb > 440)
1272                         hiprilvl = 4;
1273                 else
1274                         hiprilvl = 5;
1275
1276         } else if (mdev->unique_rev_id >= 0x01) {
1277                 hiprilvl = 3;
1278         } else {
1279                 hiprilvl = 4;
1280         }
1281
1282         crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */
1283
1284         WREG_ECRT(0x06, crtcext6);
1285 }
1286
1287 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
1288 {
1289         WREG_ECRT(0x06, 0x00);
1290 }
1291
1292 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1293 {
1294         struct drm_device *dev = crtc->dev;
1295         struct mga_device *mdev = to_mga_device(dev);
1296         u8 seq1 = 0, crtcext1 = 0;
1297
1298         switch (mode) {
1299         case DRM_MODE_DPMS_ON:
1300                 seq1 = 0;
1301                 crtcext1 = 0;
1302                 mga_crtc_load_lut(crtc);
1303                 break;
1304         case DRM_MODE_DPMS_STANDBY:
1305                 seq1 = 0x20;
1306                 crtcext1 = 0x10;
1307                 break;
1308         case DRM_MODE_DPMS_SUSPEND:
1309                 seq1 = 0x20;
1310                 crtcext1 = 0x20;
1311                 break;
1312         case DRM_MODE_DPMS_OFF:
1313                 seq1 = 0x20;
1314                 crtcext1 = 0x30;
1315                 break;
1316         }
1317
1318         WREG8(MGAREG_SEQ_INDEX, 0x01);
1319         seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1320         mga_wait_vsync(mdev);
1321         mga_wait_busy(mdev);
1322         WREG8(MGAREG_SEQ_DATA, seq1);
1323         msleep(20);
1324         WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1325         crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1326         WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1327 }
1328
1329 /*
1330  * This is called before a mode is programmed. A typical use might be to
1331  * enable DPMS during the programming to avoid seeing intermediate stages,
1332  * but that's not relevant to us
1333  */
1334 static void mga_crtc_prepare(struct drm_crtc *crtc)
1335 {
1336         struct drm_device *dev = crtc->dev;
1337         struct mga_device *mdev = to_mga_device(dev);
1338         u8 tmp;
1339
1340         /*      mga_resume(crtc);*/
1341
1342         WREG8(MGAREG_CRTC_INDEX, 0x11);
1343         tmp = RREG8(MGAREG_CRTC_DATA);
1344         WREG_CRT(0x11, tmp | 0x80);
1345
1346         if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1347                 WREG_SEQ(0, 1);
1348                 msleep(50);
1349                 WREG_SEQ(1, 0x20);
1350                 msleep(20);
1351         } else {
1352                 WREG8(MGAREG_SEQ_INDEX, 0x1);
1353                 tmp = RREG8(MGAREG_SEQ_DATA);
1354
1355                 /* start sync reset */
1356                 WREG_SEQ(0, 1);
1357                 WREG_SEQ(1, tmp | 0x20);
1358         }
1359
1360         if (mdev->type == G200_WB || mdev->type == G200_EW3)
1361                 mga_g200wb_prepare(crtc);
1362
1363         WREG_CRT(17, 0);
1364 }
1365
1366 /*
1367  * This is called after a mode is programmed. It should reverse anything done
1368  * by the prepare function
1369  */
1370 static void mga_crtc_commit(struct drm_crtc *crtc)
1371 {
1372         struct drm_device *dev = crtc->dev;
1373         struct mga_device *mdev = to_mga_device(dev);
1374         u8 tmp;
1375
1376         if (mdev->type == G200_WB || mdev->type == G200_EW3)
1377                 mga_g200wb_commit(crtc);
1378
1379         if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1380                 msleep(50);
1381                 WREG_SEQ(1, 0x0);
1382                 msleep(20);
1383                 WREG_SEQ(0, 0x3);
1384         } else {
1385                 WREG8(MGAREG_SEQ_INDEX, 0x1);
1386                 tmp = RREG8(MGAREG_SEQ_DATA);
1387
1388                 tmp &= ~0x20;
1389                 WREG_SEQ(0x1, tmp);
1390                 WREG_SEQ(0, 3);
1391         }
1392         mga_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1393 }
1394
1395 /*
1396  * Connector
1397  */
1398
1399 static int mga_vga_get_modes(struct drm_connector *connector)
1400 {
1401         struct mga_connector *mga_connector = to_mga_connector(connector);
1402         struct edid *edid;
1403         int ret = 0;
1404
1405         edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1406         if (edid) {
1407                 drm_connector_update_edid_property(connector, edid);
1408                 ret = drm_add_edid_modes(connector, edid);
1409                 kfree(edid);
1410         }
1411         return ret;
1412 }
1413
1414 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1415                                                         int bits_per_pixel)
1416 {
1417         uint32_t total_area, divisor;
1418         uint64_t active_area, pixels_per_second, bandwidth;
1419         uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1420
1421         divisor = 1024;
1422
1423         if (!mode->htotal || !mode->vtotal || !mode->clock)
1424                 return 0;
1425
1426         active_area = mode->hdisplay * mode->vdisplay;
1427         total_area = mode->htotal * mode->vtotal;
1428
1429         pixels_per_second = active_area * mode->clock * 1000;
1430         do_div(pixels_per_second, total_area);
1431
1432         bandwidth = pixels_per_second * bytes_per_pixel * 100;
1433         do_div(bandwidth, divisor);
1434
1435         return (uint32_t)(bandwidth);
1436 }
1437
1438 #define MODE_BANDWIDTH  MODE_BAD
1439
1440 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
1441                                  struct drm_display_mode *mode)
1442 {
1443         struct drm_device *dev = connector->dev;
1444         struct mga_device *mdev = to_mga_device(dev);
1445         int bpp = 32;
1446
1447         if (IS_G200_SE(mdev)) {
1448                 if (mdev->unique_rev_id == 0x01) {
1449                         if (mode->hdisplay > 1600)
1450                                 return MODE_VIRTUAL_X;
1451                         if (mode->vdisplay > 1200)
1452                                 return MODE_VIRTUAL_Y;
1453                         if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1454                                 > (24400 * 1024))
1455                                 return MODE_BANDWIDTH;
1456                 } else if (mdev->unique_rev_id == 0x02) {
1457                         if (mode->hdisplay > 1920)
1458                                 return MODE_VIRTUAL_X;
1459                         if (mode->vdisplay > 1200)
1460                                 return MODE_VIRTUAL_Y;
1461                         if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1462                                 > (30100 * 1024))
1463                                 return MODE_BANDWIDTH;
1464                 } else {
1465                         if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1466                                 > (55000 * 1024))
1467                                 return MODE_BANDWIDTH;
1468                 }
1469         } else if (mdev->type == G200_WB) {
1470                 if (mode->hdisplay > 1280)
1471                         return MODE_VIRTUAL_X;
1472                 if (mode->vdisplay > 1024)
1473                         return MODE_VIRTUAL_Y;
1474                 if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
1475                     (31877 * 1024))
1476                         return MODE_BANDWIDTH;
1477         } else if (mdev->type == G200_EV &&
1478                 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1479                         > (32700 * 1024))) {
1480                 return MODE_BANDWIDTH;
1481         } else if (mdev->type == G200_EH &&
1482                 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1483                         > (37500 * 1024))) {
1484                 return MODE_BANDWIDTH;
1485         } else if (mdev->type == G200_ER &&
1486                 (mga_vga_calculate_mode_bandwidth(mode,
1487                         bpp) > (55000 * 1024))) {
1488                 return MODE_BANDWIDTH;
1489         }
1490
1491         if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1492             (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1493                 return MODE_H_ILLEGAL;
1494         }
1495
1496         if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1497             mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1498             mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1499             mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1500                 return MODE_BAD;
1501         }
1502
1503         /* Validate the mode input by the user */
1504         if (connector->cmdline_mode.specified) {
1505                 if (connector->cmdline_mode.bpp_specified)
1506                         bpp = connector->cmdline_mode.bpp;
1507         }
1508
1509         if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) {
1510                 if (connector->cmdline_mode.specified)
1511                         connector->cmdline_mode.specified = false;
1512                 return MODE_BAD;
1513         }
1514
1515         return MODE_OK;
1516 }
1517
1518 static void mga_connector_destroy(struct drm_connector *connector)
1519 {
1520         struct mga_connector *mga_connector = to_mga_connector(connector);
1521         mgag200_i2c_destroy(mga_connector->i2c);
1522         drm_connector_cleanup(connector);
1523 }
1524
1525 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1526         .get_modes  = mga_vga_get_modes,
1527         .mode_valid = mga_vga_mode_valid,
1528 };
1529
1530 static const struct drm_connector_funcs mga_vga_connector_funcs = {
1531         .reset                  = drm_atomic_helper_connector_reset,
1532         .fill_modes             = drm_helper_probe_single_connector_modes,
1533         .destroy                = mga_connector_destroy,
1534         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1535         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
1536 };
1537
1538 static int mgag200_vga_connector_init(struct mga_device *mdev)
1539 {
1540         struct drm_device *dev = &mdev->base;
1541         struct mga_connector *mconnector = &mdev->connector;
1542         struct drm_connector *connector = &mconnector->base;
1543         struct mga_i2c_chan *i2c;
1544         int ret;
1545
1546         i2c = mgag200_i2c_create(dev);
1547         if (!i2c)
1548                 drm_warn(dev, "failed to add DDC bus\n");
1549
1550         ret = drm_connector_init_with_ddc(dev, connector,
1551                                           &mga_vga_connector_funcs,
1552                                           DRM_MODE_CONNECTOR_VGA,
1553                                           &i2c->adapter);
1554         if (ret)
1555                 goto err_mgag200_i2c_destroy;
1556         drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1557
1558         mconnector->i2c = i2c;
1559
1560         return 0;
1561
1562 err_mgag200_i2c_destroy:
1563         mgag200_i2c_destroy(i2c);
1564         return ret;
1565 }
1566
1567 /*
1568  * Simple Display Pipe
1569  */
1570
1571 static enum drm_mode_status
1572 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
1573                                        const struct drm_display_mode *mode)
1574 {
1575         return MODE_OK;
1576 }
1577
1578 static void
1579 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb,
1580                       struct drm_rect *clip)
1581 {
1582         struct drm_device *dev = &mdev->base;
1583         void *vmap;
1584
1585         vmap = drm_gem_shmem_vmap(fb->obj[0]);
1586         if (drm_WARN_ON(dev, !vmap))
1587                 return; /* BUG: SHMEM BO should always be vmapped */
1588
1589         drm_fb_memcpy_dstclip(mdev->vram, vmap, fb, clip);
1590
1591         drm_gem_shmem_vunmap(fb->obj[0], vmap);
1592
1593         /* Always scanout image at VRAM offset 0 */
1594         mgag200_set_startadd(mdev, (u32)0);
1595         mgag200_set_offset(mdev, fb);
1596 }
1597
1598 static void
1599 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
1600                                    struct drm_crtc_state *crtc_state,
1601                                    struct drm_plane_state *plane_state)
1602 {
1603         struct drm_crtc *crtc = &pipe->crtc;
1604         struct drm_device *dev = crtc->dev;
1605         struct mga_device *mdev = to_mga_device(dev);
1606         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1607         struct drm_framebuffer *fb = plane_state->fb;
1608         struct drm_rect fullscreen = {
1609                 .x1 = 0,
1610                 .x2 = fb->width,
1611                 .y1 = 0,
1612                 .y2 = fb->height,
1613         };
1614
1615         mga_crtc_prepare(crtc);
1616
1617         mgag200_set_format_regs(mdev, fb);
1618         mgag200_set_mode_regs(mdev, adjusted_mode);
1619
1620         if (mdev->type == G200_ER)
1621                 mgag200_g200er_reset_tagfifo(mdev);
1622
1623         if (IS_G200_SE(mdev))
1624                 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb);
1625         else if (mdev->type == G200_EV)
1626                 mgag200_g200ev_set_hiprilvl(mdev);
1627
1628         mga_crtc_commit(crtc);
1629
1630         mgag200_handle_damage(mdev, fb, &fullscreen);
1631 }
1632
1633 static void
1634 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
1635 {
1636         struct drm_crtc *crtc = &pipe->crtc;
1637
1638         mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1639 }
1640
1641 static int
1642 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe,
1643                                   struct drm_plane_state *plane_state,
1644                                   struct drm_crtc_state *crtc_state)
1645 {
1646         struct drm_plane *plane = plane_state->plane;
1647         struct drm_framebuffer *new_fb = plane_state->fb;
1648         struct drm_framebuffer *fb = NULL;
1649
1650         if (!new_fb)
1651                 return 0;
1652
1653         if (plane->state)
1654                 fb = plane->state->fb;
1655
1656         if (!fb || (fb->format != new_fb->format))
1657                 crtc_state->mode_changed = true; /* update PLL settings */
1658
1659         return 0;
1660 }
1661
1662 static void
1663 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
1664                                    struct drm_plane_state *old_state)
1665 {
1666         struct drm_plane *plane = &pipe->plane;
1667         struct drm_device *dev = plane->dev;
1668         struct mga_device *mdev = to_mga_device(dev);
1669         struct drm_plane_state *state = plane->state;
1670         struct drm_framebuffer *fb = state->fb;
1671         struct drm_rect damage;
1672
1673         if (!fb)
1674                 return;
1675
1676         if (drm_atomic_helper_damage_merged(old_state, state, &damage))
1677                 mgag200_handle_damage(mdev, fb, &damage);
1678 }
1679
1680 static const struct drm_simple_display_pipe_funcs
1681 mgag200_simple_display_pipe_funcs = {
1682         .mode_valid = mgag200_simple_display_pipe_mode_valid,
1683         .enable     = mgag200_simple_display_pipe_enable,
1684         .disable    = mgag200_simple_display_pipe_disable,
1685         .check      = mgag200_simple_display_pipe_check,
1686         .update     = mgag200_simple_display_pipe_update,
1687         .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
1688 };
1689
1690 static const uint32_t mgag200_simple_display_pipe_formats[] = {
1691         DRM_FORMAT_XRGB8888,
1692         DRM_FORMAT_RGB565,
1693         DRM_FORMAT_RGB888,
1694 };
1695
1696 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = {
1697         DRM_FORMAT_MOD_LINEAR,
1698         DRM_FORMAT_MOD_INVALID
1699 };
1700
1701 /*
1702  * Mode config
1703  */
1704
1705 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
1706         .fb_create     = drm_gem_fb_create_with_dirty,
1707         .atomic_check  = drm_atomic_helper_check,
1708         .atomic_commit = drm_atomic_helper_commit,
1709 };
1710
1711 static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
1712 {
1713         if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024))
1714                 return 16;
1715         else
1716                 return 32;
1717 }
1718
1719 int mgag200_modeset_init(struct mga_device *mdev)
1720 {
1721         struct drm_device *dev = &mdev->base;
1722         struct drm_connector *connector = &mdev->connector.base;
1723         struct drm_simple_display_pipe *pipe = &mdev->display_pipe;
1724         size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats);
1725         int ret;
1726
1727         mdev->bpp_shifts[0] = 0;
1728         mdev->bpp_shifts[1] = 1;
1729         mdev->bpp_shifts[2] = 0;
1730         mdev->bpp_shifts[3] = 2;
1731
1732         mgag200_init_regs(mdev);
1733
1734         ret = drmm_mode_config_init(dev);
1735         if (ret) {
1736                 drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
1737                         ret);
1738                 return ret;
1739         }
1740
1741         dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1742         dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1743
1744         dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev);
1745
1746         dev->mode_config.fb_base = mdev->mc.vram_base;
1747
1748         dev->mode_config.funcs = &mgag200_mode_config_funcs;
1749
1750         ret = mgag200_vga_connector_init(mdev);
1751         if (ret) {
1752                 drm_err(dev,
1753                         "mgag200_vga_connector_init() failed, error %d\n",
1754                         ret);
1755                 return ret;
1756         }
1757
1758         ret = drm_simple_display_pipe_init(dev, pipe,
1759                                            &mgag200_simple_display_pipe_funcs,
1760                                            mgag200_simple_display_pipe_formats,
1761                                            format_count,
1762                                            mgag200_simple_display_pipe_fmtmods,
1763                                            connector);
1764         if (ret) {
1765                 drm_err(dev,
1766                         "drm_simple_display_pipe_init() failed, error %d\n",
1767                         ret);
1768                 return ret;
1769         }
1770
1771         /* FIXME: legacy gamma tables; convert to CRTC state */
1772         drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE);
1773
1774         drm_mode_config_reset(dev);
1775
1776         return 0;
1777 }