2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
9 * Authors: Matthew Garrett
14 #include <linux/delay.h>
18 #include "drm_crtc_helper.h"
20 #include "mgag200_drv.h"
22 #define MGAG200_LUT_SIZE 256
25 * This file contains setup code for the CRTC.
28 static void mga_crtc_load_lut(struct drm_crtc *crtc)
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
38 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
40 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
42 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
43 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
44 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
48 static inline void mga_wait_vsync(struct mga_device *mdev)
50 unsigned int count = 0;
51 unsigned int status = 0;
54 status = RREG32(MGAREG_Status);
56 } while ((status & 0x08) && (count < 250000));
60 status = RREG32(MGAREG_Status);
62 } while (!(status & 0x08) && (count < 250000));
65 static inline void mga_wait_busy(struct mga_device *mdev)
67 unsigned int count = 0;
68 unsigned int status = 0;
70 status = RREG8(MGAREG_Status + 2);
72 } while ((status & 0x01) && (count < 500000));
76 * The core passes the desired mode to the CRTC code to see whether any
77 * CRTC-specific modifications need to be made to it. We're in a position
78 * to just pass that straight through, so this does nothing
80 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
81 const struct drm_display_mode *mode,
82 struct drm_display_mode *adjusted_mode)
87 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
89 unsigned int vcomax, vcomin, pllreffreq;
90 unsigned int delta, tmpdelta, permitteddelta;
91 unsigned int testp, testm, testn;
93 unsigned int computed;
101 permitteddelta = clock * 5 / 1000;
103 for (testp = 8; testp > 0; testp /= 2) {
104 if (clock * testp > vcomax)
106 if (clock * testp < vcomin)
109 for (testn = 17; testn < 256; testn++) {
110 for (testm = 1; testm < 32; testm++) {
111 computed = (pllreffreq * testn) /
113 if (computed > clock)
114 tmpdelta = computed - clock;
116 tmpdelta = clock - computed;
117 if (tmpdelta < delta) {
127 if (delta > permitteddelta) {
128 printk(KERN_WARNING "PLL delta too large\n");
132 WREG_DAC(MGA1064_PIX_PLLC_M, m);
133 WREG_DAC(MGA1064_PIX_PLLC_N, n);
134 WREG_DAC(MGA1064_PIX_PLLC_P, p);
138 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
140 unsigned int vcomax, vcomin, pllreffreq;
141 unsigned int delta, tmpdelta, permitteddelta;
142 unsigned int testp, testm, testn;
143 unsigned int p, m, n;
144 unsigned int computed;
145 int i, j, tmpcount, vcount;
146 bool pll_locked = false;
155 permitteddelta = clock * 5 / 1000;
157 for (testp = 1; testp < 9; testp++) {
158 if (clock * testp > vcomax)
160 if (clock * testp < vcomin)
163 for (testm = 1; testm < 17; testm++) {
164 for (testn = 1; testn < 151; testn++) {
165 computed = (pllreffreq * testn) /
167 if (computed > clock)
168 tmpdelta = computed - clock;
170 tmpdelta = clock - computed;
171 if (tmpdelta < delta) {
174 m = (testm - 1) | ((n >> 1) & 0x80);
181 for (i = 0; i <= 32 && pll_locked == false; i++) {
183 WREG8(MGAREG_CRTC_INDEX, 0x1e);
184 tmp = RREG8(MGAREG_CRTC_DATA);
186 WREG8(MGAREG_CRTC_DATA, tmp+1);
189 /* set pixclkdis to 1 */
190 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
191 tmp = RREG8(DAC_DATA);
192 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
193 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
195 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
196 tmp = RREG8(DAC_DATA);
197 tmp |= MGA1064_REMHEADCTL_CLKDIS;
198 WREG_DAC(MGA1064_REMHEADCTL, tmp);
200 /* select PLL Set C */
201 tmp = RREG8(MGAREG_MEM_MISC_READ);
203 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
205 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
206 tmp = RREG8(DAC_DATA);
207 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
208 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
213 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
214 tmp = RREG8(DAC_DATA);
216 WREG_DAC(MGA1064_VREF_CTL, tmp);
220 /* program pixel pll register */
221 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
222 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
223 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
228 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
229 tmp = RREG8(DAC_DATA);
231 WREG_DAC(MGA1064_VREF_CTL, tmp);
235 /* select the pixel pll */
236 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
237 tmp = RREG8(DAC_DATA);
238 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
239 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
240 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
242 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
243 tmp = RREG8(DAC_DATA);
244 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
245 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
246 WREG_DAC(MGA1064_REMHEADCTL, tmp);
248 /* reset dotclock rate bit */
249 WREG8(MGAREG_SEQ_INDEX, 1);
250 tmp = RREG8(MGAREG_SEQ_DATA);
252 WREG8(MGAREG_SEQ_DATA, tmp);
254 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
255 tmp = RREG8(DAC_DATA);
256 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
257 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
259 vcount = RREG8(MGAREG_VCOUNT);
261 for (j = 0; j < 30 && pll_locked == false; j++) {
262 tmpcount = RREG8(MGAREG_VCOUNT);
263 if (tmpcount < vcount)
265 if ((tmpcount - vcount) > 2)
271 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
272 tmp = RREG8(DAC_DATA);
273 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
274 WREG_DAC(MGA1064_REMHEADCTL, tmp);
278 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
280 unsigned int vcomax, vcomin, pllreffreq;
281 unsigned int delta, tmpdelta, permitteddelta;
282 unsigned int testp, testm, testn;
283 unsigned int p, m, n;
284 unsigned int computed;
293 permitteddelta = clock * 5 / 1000;
295 for (testp = 16; testp > 0; testp--) {
296 if (clock * testp > vcomax)
298 if (clock * testp < vcomin)
301 for (testn = 1; testn < 257; testn++) {
302 for (testm = 1; testm < 17; testm++) {
303 computed = (pllreffreq * testn) /
305 if (computed > clock)
306 tmpdelta = computed - clock;
308 tmpdelta = clock - computed;
309 if (tmpdelta < delta) {
319 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
320 tmp = RREG8(DAC_DATA);
321 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
322 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
324 tmp = RREG8(MGAREG_MEM_MISC_READ);
326 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
328 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
329 tmp = RREG8(DAC_DATA);
330 WREG_DAC(MGA1064_PIX_PLL_STAT, tmp & ~0x40);
332 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
333 tmp = RREG8(DAC_DATA);
334 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
335 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
337 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
338 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
339 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
343 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
344 tmp = RREG8(DAC_DATA);
345 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
346 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
350 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
351 tmp = RREG8(DAC_DATA);
352 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
353 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
354 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
356 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
357 tmp = RREG8(DAC_DATA);
358 WREG_DAC(MGA1064_PIX_PLL_STAT, tmp | 0x40);
360 tmp = RREG8(MGAREG_MEM_MISC_READ);
362 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
364 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
365 tmp = RREG8(DAC_DATA);
366 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
367 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
372 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
374 unsigned int vcomax, vcomin, pllreffreq;
375 unsigned int delta, tmpdelta, permitteddelta;
376 unsigned int testp, testm, testn;
377 unsigned int p, m, n;
378 unsigned int computed;
379 int i, j, tmpcount, vcount;
381 bool pll_locked = false;
389 permitteddelta = clock * 5 / 1000;
391 for (testp = 16; testp > 0; testp--) {
392 if (clock * testp > vcomax)
394 if (clock * testp < vcomin)
397 for (testm = 1; testm < 33; testm++) {
398 for (testn = 1; testn < 257; testn++) {
399 computed = (pllreffreq * testn) /
401 if (computed > clock)
402 tmpdelta = computed - clock;
404 tmpdelta = clock - computed;
405 if (tmpdelta < delta) {
408 m = (testm - 1) | ((n >> 1) & 0x80);
411 if ((clock * testp) >= 600000)
416 for (i = 0; i <= 32 && pll_locked == false; i++) {
417 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
418 tmp = RREG8(DAC_DATA);
419 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
420 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
422 tmp = RREG8(MGAREG_MEM_MISC_READ);
424 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
426 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
427 tmp = RREG8(DAC_DATA);
428 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
429 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
433 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
434 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
435 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
439 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
440 tmp = RREG8(DAC_DATA);
441 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
442 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
443 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
445 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
446 tmp = RREG8(DAC_DATA);
447 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
448 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
449 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
451 vcount = RREG8(MGAREG_VCOUNT);
453 for (j = 0; j < 30 && pll_locked == false; j++) {
454 tmpcount = RREG8(MGAREG_VCOUNT);
455 if (tmpcount < vcount)
457 if ((tmpcount - vcount) > 2)
467 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
469 unsigned int vcomax, vcomin, pllreffreq;
470 unsigned int delta, tmpdelta;
471 int testr, testn, testm, testo;
472 unsigned int p, m, n;
473 unsigned int computed, vco;
475 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
484 for (testr = 0; testr < 4; testr++) {
487 for (testn = 5; testn < 129; testn++) {
490 for (testm = 3; testm >= 0; testm--) {
493 for (testo = 5; testo < 33; testo++) {
494 vco = pllreffreq * (testn + 1) /
500 computed = vco / (m_div_val[testm] * (testo + 1));
501 if (computed > clock)
502 tmpdelta = computed - clock;
504 tmpdelta = clock - computed;
505 if (tmpdelta < delta) {
507 m = testm | (testo << 3);
509 p = testr | (testr << 3);
516 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
517 tmp = RREG8(DAC_DATA);
518 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
519 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
521 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
522 tmp = RREG8(DAC_DATA);
523 tmp |= MGA1064_REMHEADCTL_CLKDIS;
524 WREG_DAC(MGA1064_REMHEADCTL, tmp);
526 tmp = RREG8(MGAREG_MEM_MISC_READ);
527 tmp |= (0x3<<2) | 0xc0;
528 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
530 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
531 tmp = RREG8(DAC_DATA);
532 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
533 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
534 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
538 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
539 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
540 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
547 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
552 return mga_g200se_set_plls(mdev, clock);
555 return mga_g200wb_set_plls(mdev, clock);
558 return mga_g200ev_set_plls(mdev, clock);
561 return mga_g200eh_set_plls(mdev, clock);
564 return mga_g200er_set_plls(mdev, clock);
570 static void mga_g200wb_prepare(struct drm_crtc *crtc)
572 struct mga_device *mdev = crtc->dev->dev_private;
576 /* 1- The first step is to warn the BMC of an upcoming mode change.
577 * We are putting the misc<0> to output.*/
579 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
580 tmp = RREG8(DAC_DATA);
582 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
584 /* we are putting a 1 on the misc<0> line */
585 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
586 tmp = RREG8(DAC_DATA);
588 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
590 /* 2- Second step to mask and further scan request
591 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
593 WREG8(DAC_INDEX, MGA1064_SPAREREG);
594 tmp = RREG8(DAC_DATA);
596 WREG_DAC(MGA1064_SPAREREG, tmp);
598 /* 3a- the third step is to verifu if there is an active scan
599 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
602 while (!(tmp & 0x1) && iter_max) {
603 WREG8(DAC_INDEX, MGA1064_SPAREREG);
604 tmp = RREG8(DAC_DATA);
609 /* 3b- this step occurs only if the remove is actually scanning
610 * we are waiting for the end of the frame which is a 1 on
611 * remvsyncsts (XSPAREREG<1>)
615 while ((tmp & 0x2) && iter_max) {
616 WREG8(DAC_INDEX, MGA1064_SPAREREG);
617 tmp = RREG8(DAC_DATA);
624 static void mga_g200wb_commit(struct drm_crtc *crtc)
627 struct mga_device *mdev = crtc->dev->dev_private;
629 /* 1- The first step is to ensure that the vrsten and hrsten are set */
630 WREG8(MGAREG_CRTCEXT_INDEX, 1);
631 tmp = RREG8(MGAREG_CRTCEXT_DATA);
632 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
634 /* 2- second step is to assert the rstlvl2 */
635 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
636 tmp = RREG8(DAC_DATA);
638 WREG8(DAC_DATA, tmp);
643 /* 3- deassert rstlvl2 */
645 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
646 WREG8(DAC_DATA, tmp);
648 /* 4- remove mask of scan request */
649 WREG8(DAC_INDEX, MGA1064_SPAREREG);
650 tmp = RREG8(DAC_DATA);
652 WREG8(DAC_DATA, tmp);
654 /* 5- put back a 0 on the misc<0> line */
655 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
656 tmp = RREG8(DAC_DATA);
658 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
662 void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
664 struct mga_device *mdev = crtc->dev->dev_private;
668 while (RREG8(0x1fda) & 0x08);
669 while (!(RREG8(0x1fda) & 0x08));
671 count = RREG8(MGAREG_VCOUNT) + 2;
672 while (RREG8(MGAREG_VCOUNT) < count);
675 WREG_CRT(0x0d, (u8)(addr & 0xff));
676 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
677 WREG_CRT(0xaf, (u8)(addr >> 16) & 0xf);
681 /* ast is different - we will force move buffers out of VRAM */
682 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
683 struct drm_framebuffer *fb,
684 int x, int y, int atomic)
686 struct mga_device *mdev = crtc->dev->dev_private;
687 struct drm_gem_object *obj;
688 struct mga_framebuffer *mga_fb;
689 struct mgag200_bo *bo;
693 /* push the previous fb to system ram */
695 mga_fb = to_mga_framebuffer(fb);
697 bo = gem_to_mga_bo(obj);
698 ret = mgag200_bo_reserve(bo, false);
701 mgag200_bo_push_sysram(bo);
702 mgag200_bo_unreserve(bo);
705 mga_fb = to_mga_framebuffer(crtc->fb);
707 bo = gem_to_mga_bo(obj);
709 ret = mgag200_bo_reserve(bo, false);
713 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
715 mgag200_bo_unreserve(bo);
719 if (&mdev->mfbdev->mfb == mga_fb) {
720 /* if pushing console in kmap it */
721 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
723 DRM_ERROR("failed to kmap fbcon\n");
726 mgag200_bo_unreserve(bo);
728 DRM_INFO("mga base %llx\n", gpu_addr);
730 mga_set_start_address(crtc, (u32)gpu_addr);
735 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
736 struct drm_framebuffer *old_fb)
738 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
741 static int mga_crtc_mode_set(struct drm_crtc *crtc,
742 struct drm_display_mode *mode,
743 struct drm_display_mode *adjusted_mode,
744 int x, int y, struct drm_framebuffer *old_fb)
746 struct drm_device *dev = crtc->dev;
747 struct mga_device *mdev = dev->dev_private;
748 int hdisplay, hsyncstart, hsyncend, htotal;
749 int vdisplay, vsyncstart, vsyncend, vtotal;
751 int option = 0, option2 = 0;
753 unsigned char misc = 0;
754 unsigned char ext_vga[6];
755 unsigned char ext_vga_index24;
756 unsigned char dac_index90 = 0;
759 static unsigned char dacvalue[] = {
760 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
761 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
762 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
763 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
764 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
766 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
767 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
768 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
769 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
772 bppshift = mdev->bpp_shifts[(crtc->fb->bits_per_pixel >> 3) - 1];
774 switch (mdev->type) {
777 dacvalue[MGA1064_VREF_CTL] = 0x03;
778 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
779 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
780 MGA1064_MISC_CTL_VGA8 |
781 MGA1064_MISC_CTL_DAC_RAM_CS;
786 option2 = 0x00008000;
789 dacvalue[MGA1064_VREF_CTL] = 0x07;
791 option2 = 0x0000b000;
794 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
795 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
796 MGA1064_MISC_CTL_DAC_RAM_CS;
798 option2 = 0x0000b000;
801 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
802 MGA1064_MISC_CTL_DAC_RAM_CS;
804 option2 = 0x0000b000;
811 switch (crtc->fb->bits_per_pixel) {
813 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
816 if (crtc->fb->depth == 15)
817 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
819 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
822 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
825 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
829 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
831 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
835 for (i = 0; i < sizeof(dacvalue); i++) {
840 ((i >= 0x13) && (i <= 0x17)) ||
843 ((i >= 0x1f) && (i <= 0x29)) ||
844 ((i >= 0x30) && (i <= 0x37)))
846 if (IS_G200_SE(mdev) &&
847 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
849 if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) &&
850 (i >= 0x44) && (i <= 0x4e))
853 WREG_DAC(i, dacvalue[i]);
856 if (mdev->type == G200_ER) {
857 WREG_DAC(0x90, dac_index90);
862 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
864 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
870 pitch = crtc->fb->pitches[0] / (crtc->fb->bits_per_pixel / 8);
871 if (crtc->fb->bits_per_pixel == 24)
872 pitch = pitch >> (4 - bppshift);
874 pitch = pitch >> (4 - bppshift);
876 hdisplay = mode->hdisplay / 8 - 1;
877 hsyncstart = mode->hsync_start / 8 - 1;
878 hsyncend = mode->hsync_end / 8 - 1;
879 htotal = mode->htotal / 8 - 1;
881 /* Work around hardware quirk */
882 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
885 vdisplay = mode->vdisplay - 1;
886 vsyncstart = mode->vsync_start - 1;
887 vsyncend = mode->vsync_end - 1;
888 vtotal = mode->vtotal - 2;
900 WREG_CRT(0, htotal - 4);
901 WREG_CRT(1, hdisplay);
902 WREG_CRT(2, hdisplay);
903 WREG_CRT(3, (htotal & 0x1F) | 0x80);
904 WREG_CRT(4, hsyncstart);
905 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
906 WREG_CRT(6, vtotal & 0xFF);
907 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
908 ((vdisplay & 0x100) >> 7) |
909 ((vsyncstart & 0x100) >> 6) |
910 ((vdisplay & 0x100) >> 5) |
911 ((vdisplay & 0x100) >> 4) | /* linecomp */
912 ((vtotal & 0x200) >> 4)|
913 ((vdisplay & 0x200) >> 3) |
914 ((vsyncstart & 0x200) >> 2));
915 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
916 ((vdisplay & 0x200) >> 3));
923 WREG_CRT(16, vsyncstart & 0xFF);
924 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
925 WREG_CRT(18, vdisplay & 0xFF);
926 WREG_CRT(19, pitch & 0xFF);
928 WREG_CRT(21, vdisplay & 0xFF);
929 WREG_CRT(22, (vtotal + 1) & 0xFF);
931 WREG_CRT(24, vdisplay & 0xFF);
938 ext_vga[0] |= (pitch & 0x300) >> 4;
939 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
940 ((hdisplay & 0x100) >> 7) |
941 ((hsyncstart & 0x100) >> 6) |
943 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
944 ((vdisplay & 0x400) >> 8) |
945 ((vdisplay & 0xc00) >> 7) |
946 ((vsyncstart & 0xc00) >> 5) |
947 ((vdisplay & 0x400) >> 3);
948 if (crtc->fb->bits_per_pixel == 24)
949 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
951 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
953 if (mdev->type == G200_WB)
956 ext_vga_index24 = 0x05;
958 /* Set pixel clocks */
960 WREG8(MGA_MISC_OUT, misc);
962 mga_crtc_set_plls(mdev, mode->clock);
964 for (i = 0; i < 6; i++) {
965 WREG_ECRT(i, ext_vga[i]);
968 if (mdev->type == G200_ER)
969 WREG_ECRT(24, ext_vga_index24);
971 if (mdev->type == G200_EV) {
975 WREG_ECRT(0, ext_vga[0]);
976 /* Enable mga pixel clock */
979 WREG8(MGA_MISC_OUT, misc);
982 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
984 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
987 if (mdev->type == G200_ER) {
988 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
992 WREG8(MGAREG_SEQ_INDEX, 0x01);
993 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
994 WREG8(MGAREG_SEQ_DATA, seq1);
996 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
998 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1000 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1004 if (IS_G200_SE(mdev)) {
1005 if (mdev->reg_1e24 >= 0x02) {
1010 if (crtc->fb->bits_per_pixel > 16)
1012 else if (crtc->fb->bits_per_pixel > 8)
1017 mb = (mode->clock * bpp) / 1000;
1031 WREG8(0x1fde, 0x06);
1032 WREG8(0x1fdf, hi_pri_lvl);
1034 if (mdev->reg_1e24 >= 0x01)
1035 WREG8(0x1fdf, 0x03);
1037 WREG8(0x1fdf, 0x04);
1043 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1044 static int mga_suspend(struct drm_crtc *crtc)
1046 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1047 struct drm_device *dev = crtc->dev;
1048 struct mga_device *mdev = dev->dev_private;
1049 struct pci_dev *pdev = dev->pdev;
1052 if (mdev->suspended)
1057 /* Disable the pixel clock */
1058 WREG_DAC(0x1a, 0x05);
1059 /* Power down the DAC */
1060 WREG_DAC(0x1e, 0x18);
1061 /* Power down the pixel PLL */
1062 WREG_DAC(0x1a, 0x0d);
1064 /* Disable PLLs and clocks */
1065 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1066 option &= ~(0x1F8024);
1067 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1068 pci_set_power_state(pdev, PCI_D3hot);
1069 pci_disable_device(pdev);
1071 mdev->suspended = true;
1076 static int mga_resume(struct drm_crtc *crtc)
1078 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1079 struct drm_device *dev = crtc->dev;
1080 struct mga_device *mdev = dev->dev_private;
1081 struct pci_dev *pdev = dev->pdev;
1084 if (!mdev->suspended)
1087 pci_set_power_state(pdev, PCI_D0);
1088 pci_enable_device(pdev);
1090 /* Disable sysclk */
1091 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1093 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1095 mdev->suspended = false;
1102 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1104 struct drm_device *dev = crtc->dev;
1105 struct mga_device *mdev = dev->dev_private;
1106 u8 seq1 = 0, crtcext1 = 0;
1109 case DRM_MODE_DPMS_ON:
1112 mga_crtc_load_lut(crtc);
1114 case DRM_MODE_DPMS_STANDBY:
1118 case DRM_MODE_DPMS_SUSPEND:
1122 case DRM_MODE_DPMS_OFF:
1129 if (mode == DRM_MODE_DPMS_OFF) {
1133 WREG8(MGAREG_SEQ_INDEX, 0x01);
1134 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1135 mga_wait_vsync(mdev);
1136 mga_wait_busy(mdev);
1137 WREG8(MGAREG_SEQ_DATA, seq1);
1139 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1140 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1141 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1144 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1146 drm_helper_resume_force_mode(dev);
1152 * This is called before a mode is programmed. A typical use might be to
1153 * enable DPMS during the programming to avoid seeing intermediate stages,
1154 * but that's not relevant to us
1156 static void mga_crtc_prepare(struct drm_crtc *crtc)
1158 struct drm_device *dev = crtc->dev;
1159 struct mga_device *mdev = dev->dev_private;
1162 /* mga_resume(crtc);*/
1164 WREG8(MGAREG_CRTC_INDEX, 0x11);
1165 tmp = RREG8(MGAREG_CRTC_DATA);
1166 WREG_CRT(0x11, tmp | 0x80);
1168 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1174 WREG8(MGAREG_SEQ_INDEX, 0x1);
1175 tmp = RREG8(MGAREG_SEQ_DATA);
1177 /* start sync reset */
1179 WREG_SEQ(1, tmp | 0x20);
1182 if (mdev->type == G200_WB)
1183 mga_g200wb_prepare(crtc);
1189 * This is called after a mode is programmed. It should reverse anything done
1190 * by the prepare function
1192 static void mga_crtc_commit(struct drm_crtc *crtc)
1194 struct drm_device *dev = crtc->dev;
1195 struct mga_device *mdev = dev->dev_private;
1196 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1199 if (mdev->type == G200_WB)
1200 mga_g200wb_commit(crtc);
1202 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1208 WREG8(MGAREG_SEQ_INDEX, 0x1);
1209 tmp = RREG8(MGAREG_SEQ_DATA);
1215 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1219 * The core can pass us a set of gamma values to program. We actually only
1220 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1221 * but it's a requirement that we provide the function
1223 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1224 u16 *blue, uint32_t start, uint32_t size)
1226 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1227 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1230 for (i = start; i < end; i++) {
1231 mga_crtc->lut_r[i] = red[i] >> 8;
1232 mga_crtc->lut_g[i] = green[i] >> 8;
1233 mga_crtc->lut_b[i] = blue[i] >> 8;
1235 mga_crtc_load_lut(crtc);
1238 /* Simple cleanup function */
1239 static void mga_crtc_destroy(struct drm_crtc *crtc)
1241 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1243 drm_crtc_cleanup(crtc);
1247 /* These provide the minimum set of functions required to handle a CRTC */
1248 static const struct drm_crtc_funcs mga_crtc_funcs = {
1249 .gamma_set = mga_crtc_gamma_set,
1250 .set_config = drm_crtc_helper_set_config,
1251 .destroy = mga_crtc_destroy,
1254 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1255 .dpms = mga_crtc_dpms,
1256 .mode_fixup = mga_crtc_mode_fixup,
1257 .mode_set = mga_crtc_mode_set,
1258 .mode_set_base = mga_crtc_mode_set_base,
1259 .prepare = mga_crtc_prepare,
1260 .commit = mga_crtc_commit,
1261 .load_lut = mga_crtc_load_lut,
1265 static void mga_crtc_init(struct drm_device *dev)
1267 struct mga_device *mdev = dev->dev_private;
1268 struct mga_crtc *mga_crtc;
1271 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1272 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1275 if (mga_crtc == NULL)
1278 drm_crtc_init(dev, &mga_crtc->base, &mga_crtc_funcs);
1280 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1281 mdev->mode_info.crtc = mga_crtc;
1283 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1284 mga_crtc->lut_r[i] = i;
1285 mga_crtc->lut_g[i] = i;
1286 mga_crtc->lut_b[i] = i;
1289 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1292 /** Sets the color ramps on behalf of fbcon */
1293 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1294 u16 blue, int regno)
1296 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1298 mga_crtc->lut_r[regno] = red >> 8;
1299 mga_crtc->lut_g[regno] = green >> 8;
1300 mga_crtc->lut_b[regno] = blue >> 8;
1303 /** Gets the color ramps on behalf of fbcon */
1304 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1305 u16 *blue, int regno)
1307 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1309 *red = (u16)mga_crtc->lut_r[regno] << 8;
1310 *green = (u16)mga_crtc->lut_g[regno] << 8;
1311 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1315 * The encoder comes after the CRTC in the output pipeline, but before
1316 * the connector. It's responsible for ensuring that the digital
1317 * stream is appropriately converted into the output format. Setup is
1318 * very simple in this case - all we have to do is inform qemu of the
1319 * colour depth in order to ensure that it displays appropriately
1323 * These functions are analagous to those in the CRTC code, but are intended
1324 * to handle any encoder-specific limitations
1326 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
1327 const struct drm_display_mode *mode,
1328 struct drm_display_mode *adjusted_mode)
1333 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1334 struct drm_display_mode *mode,
1335 struct drm_display_mode *adjusted_mode)
1340 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1345 static void mga_encoder_prepare(struct drm_encoder *encoder)
1349 static void mga_encoder_commit(struct drm_encoder *encoder)
1353 void mga_encoder_destroy(struct drm_encoder *encoder)
1355 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1356 drm_encoder_cleanup(encoder);
1360 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1361 .dpms = mga_encoder_dpms,
1362 .mode_fixup = mga_encoder_mode_fixup,
1363 .mode_set = mga_encoder_mode_set,
1364 .prepare = mga_encoder_prepare,
1365 .commit = mga_encoder_commit,
1368 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1369 .destroy = mga_encoder_destroy,
1372 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1374 struct drm_encoder *encoder;
1375 struct mga_encoder *mga_encoder;
1377 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1381 encoder = &mga_encoder->base;
1382 encoder->possible_crtcs = 0x1;
1384 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1385 DRM_MODE_ENCODER_DAC);
1386 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1392 static int mga_vga_get_modes(struct drm_connector *connector)
1394 struct mga_connector *mga_connector = to_mga_connector(connector);
1398 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1400 drm_mode_connector_update_edid_property(connector, edid);
1401 ret = drm_add_edid_modes(connector, edid);
1402 connector->display_info.raw_edid = NULL;
1408 static int mga_vga_mode_valid(struct drm_connector *connector,
1409 struct drm_display_mode *mode)
1411 /* FIXME: Add bandwidth and g200se limitations */
1413 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1414 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1415 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1416 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1423 struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1426 int enc_id = connector->encoder_ids[0];
1427 struct drm_mode_object *obj;
1428 struct drm_encoder *encoder;
1430 /* pick the encoder ids */
1433 drm_mode_object_find(connector->dev, enc_id,
1434 DRM_MODE_OBJECT_ENCODER);
1437 encoder = obj_to_encoder(obj);
1443 static enum drm_connector_status mga_vga_detect(struct drm_connector
1444 *connector, bool force)
1446 return connector_status_connected;
1449 static void mga_connector_destroy(struct drm_connector *connector)
1451 struct mga_connector *mga_connector = to_mga_connector(connector);
1452 mgag200_i2c_destroy(mga_connector->i2c);
1453 drm_connector_cleanup(connector);
1457 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1458 .get_modes = mga_vga_get_modes,
1459 .mode_valid = mga_vga_mode_valid,
1460 .best_encoder = mga_connector_best_encoder,
1463 struct drm_connector_funcs mga_vga_connector_funcs = {
1464 .dpms = drm_helper_connector_dpms,
1465 .detect = mga_vga_detect,
1466 .fill_modes = drm_helper_probe_single_connector_modes,
1467 .destroy = mga_connector_destroy,
1470 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1472 struct drm_connector *connector;
1473 struct mga_connector *mga_connector;
1475 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1479 connector = &mga_connector->base;
1481 drm_connector_init(dev, connector,
1482 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1484 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1486 mga_connector->i2c = mgag200_i2c_create(dev);
1487 if (!mga_connector->i2c)
1488 DRM_ERROR("failed to add ddc bus\n");
1494 int mgag200_modeset_init(struct mga_device *mdev)
1496 struct drm_encoder *encoder;
1497 struct drm_connector *connector;
1500 mdev->mode_info.mode_config_initialized = true;
1502 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1503 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1505 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1507 mga_crtc_init(mdev->dev);
1509 encoder = mga_encoder_init(mdev->dev);
1511 DRM_ERROR("mga_encoder_init failed\n");
1515 connector = mga_vga_init(mdev->dev);
1517 DRM_ERROR("mga_vga_init failed\n");
1521 drm_mode_connector_attach_encoder(connector, encoder);
1523 ret = mgag200_fbdev_init(mdev);
1525 DRM_ERROR("mga_fbdev_init failed\n");
1532 void mgag200_modeset_fini(struct mga_device *mdev)