drivers/gpu/drm/mgag200/mgag200_drv.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2010 Matt Turner.
   4  * Copyright 2012 Red Hat
   5  *
   6  * Authors: Matthew Garrett
   7  *          Matt Turner
   8  *          Dave Airlie
   9  */
  10 #ifndef __MGAG200_DRV_H__
  11 #define __MGAG200_DRV_H__
  12
  13 #include <linux/i2c-algo-bit.h>
  14 #include <linux/i2c.h>
  15
  16 #include <video/vga.h>
  17
  18 #include <drm/drm_encoder.h>
  19 #include <drm/drm_fb_helper.h>
  20 #include <drm/drm_gem.h>
  21 #include <drm/drm_gem_shmem_helper.h>
  22 #include <drm/drm_simple_kms_helper.h>
  23
  24 #include "mgag200_reg.h"
  25
  26 #define DRIVER_AUTHOR           "Matthew Garrett"
  27
  28 #define DRIVER_NAME             "mgag200"
  29 #define DRIVER_DESC             "MGA G200 SE"
  30 #define DRIVER_DATE             "20110418"
  31
  32 #define DRIVER_MAJOR            1
  33 #define DRIVER_MINOR            0
  34 #define DRIVER_PATCHLEVEL       0
  35
  36 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
  37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
  38 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
  39 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
  40
  41 #define ATTR_INDEX 0x1fc0
  42 #define ATTR_DATA 0x1fc1
  43
  44 #define WREG_ATTR(reg, v)                                       \
  45         do {                                                    \
  46                 RREG8(0x1fda);                                  \
  47                 WREG8(ATTR_INDEX, reg);                         \
  48                 WREG8(ATTR_DATA, v);                            \
  49         } while (0)                                             \
  50
  51 #define RREG_SEQ(reg, v)                                        \
  52         do {                                                    \
  53                 WREG8(MGAREG_SEQ_INDEX, reg);                   \
  54                 v = RREG8(MGAREG_SEQ_DATA);                     \
  55         } while (0)                                             \
  56
  57 #define WREG_SEQ(reg, v)                                        \
  58         do {                                                    \
  59                 WREG8(MGAREG_SEQ_INDEX, reg);                   \
  60                 WREG8(MGAREG_SEQ_DATA, v);                      \
  61         } while (0)                                             \
  62
  63 #define WREG_CRT(reg, v)                                        \
  64         do {                                                    \
  65                 WREG8(MGAREG_CRTC_INDEX, reg);                  \
  66                 WREG8(MGAREG_CRTC_DATA, v);                     \
  67         } while (0)                                             \
  68
  69 #define RREG_ECRT(reg, v)                                       \
  70         do {                                                    \
  71                 WREG8(MGAREG_CRTCEXT_INDEX, reg);               \
  72                 v = RREG8(MGAREG_CRTCEXT_DATA);                 \
  73         } while (0)                                             \
  74
  75 #define WREG_ECRT(reg, v)                                       \
  76         do {                                                    \
  77                 WREG8(MGAREG_CRTCEXT_INDEX, reg);                               \
  78                 WREG8(MGAREG_CRTCEXT_DATA, v);                          \
  79         } while (0)                                             \
  80
  81 #define GFX_INDEX 0x1fce
  82 #define GFX_DATA 0x1fcf
  83
  84 #define WREG_GFX(reg, v)                                        \
  85         do {                                                    \
  86                 WREG8(GFX_INDEX, reg);                          \
  87                 WREG8(GFX_DATA, v);                             \
  88         } while (0)                                             \
  89
  90 #define DAC_INDEX 0x3c00
  91 #define DAC_DATA 0x3c0a
  92
  93 #define WREG_DAC(reg, v)                                        \
  94         do {                                                    \
  95                 WREG8(DAC_INDEX, reg);                          \
  96                 WREG8(DAC_DATA, v);                             \
  97         } while (0)                                             \
  98
  99 #define MGA_MISC_OUT 0x1fc2
 100 #define MGA_MISC_IN 0x1fcc
 101
 102 #define MGAG200_MAX_FB_HEIGHT 4096
 103 #define MGAG200_MAX_FB_WIDTH 4096
 104
 105 #define to_mga_connector(x) container_of(x, struct mga_connector, base)
 106
 107 struct mga_i2c_chan {
 108         struct i2c_adapter adapter;
 109         struct drm_device *dev;
 110         struct i2c_algo_bit_data bit;
 111         int data, clock;
 112 };
 113
 114 struct mga_connector {
 115         struct drm_connector base;
 116         struct mga_i2c_chan *i2c;
 117 };
 118
 119 struct mga_mc {
 120         resource_size_t                 vram_size;
 121         resource_size_t                 vram_base;
 122         resource_size_t                 vram_window;
 123 };
 124
 125 enum mga_type {
 126         G200_SE_A,
 127         G200_SE_B,
 128         G200_WB,
 129         G200_EV,
 130         G200_EH,
 131         G200_EH3,
 132         G200_ER,
 133         G200_EW3,
 134 };
 135
 136 /* HW does not handle 'startadd' field correct. */
 137 #define MGAG200_FLAG_HW_BUG_NO_STARTADD (1ul << 8)
 138
 139 #define MGAG200_TYPE_MASK       (0x000000ff)
 140 #define MGAG200_FLAG_MASK       (0x00ffff00)
 141
 142 #define IS_G200_SE(mdev) (mdev->type == G200_SE_A || mdev->type == G200_SE_B)
 143
 144 struct mga_device {
 145         struct drm_device               base;
 146         unsigned long                   flags;
 147
 148         resource_size_t                 rmmio_base;
 149         resource_size_t                 rmmio_size;
 150         void __iomem                    *rmmio;
 151
 152         struct mga_mc                   mc;
 153
 154         void __iomem                    *vram;
 155         size_t                          vram_fb_available;
 156
 157         enum mga_type                   type;
 158         int                             has_sdram;
 159
 160         int bpp_shifts[4];
 161
 162         int fb_mtrr;
 163
 164         /* SE model number stored in reg 0x1e24 */
 165         u32 unique_rev_id;
 166
 167         struct mga_connector connector;
 168         struct drm_simple_display_pipe display_pipe;
 169 };
 170
 171 static inline struct mga_device *to_mga_device(struct drm_device *dev)
 172 {
 173         return container_of(dev, struct mga_device, base);
 174 }
 175
 176 static inline enum mga_type
 177 mgag200_type_from_driver_data(kernel_ulong_t driver_data)
 178 {
 179         return (enum mga_type)(driver_data & MGAG200_TYPE_MASK);
 180 }
 181
 182 static inline unsigned long
 183 mgag200_flags_from_driver_data(kernel_ulong_t driver_data)
 184 {
 185         return driver_data & MGAG200_FLAG_MASK;
 186 }
 187
 188                                 /* mgag200_mode.c */
 189 int mgag200_modeset_init(struct mga_device *mdev);
 190
 191                                 /* mgag200_i2c.c */
 192 struct mga_i2c_chan *mgag200_i2c_create(struct drm_device *dev);
 193 void mgag200_i2c_destroy(struct mga_i2c_chan *i2c);
 194
 195                                 /* mgag200_mm.c */
 196 int mgag200_mm_init(struct mga_device *mdev);
 197
 198 #endif                          /* __MGAG200_DRV_H__ */