1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
8 #include <linux/kernel.h>
9 #include <linux/module.h>
11 #include "meson_drv.h"
12 #include "meson_venc.h"
13 #include "meson_vpp.h"
14 #include "meson_vclk.h"
15 #include "meson_registers.h"
20 * VENC Handle the pixels encoding to the output formats.
21 * We handle the following encodings :
23 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
24 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
25 * - Setup of more clock rates for HDMI modes
29 * - LCD Panel encoding via ENCL
30 * - TV Panel encoding via ENCT
36 * _____ _____ ____________________
37 * vd1---| |-| | | VENC /---------|----VDAC
38 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
39 * osd1--| |-| | | \ | X--HDMI-TX
40 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
42 * | \--ENCL-----------|----LVDS
43 * |____________________|
45 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
46 * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI.
47 * The ENCP is designed for Progressive encoding but can also generate
48 * 1080i interlaced pixels, and was initialy desined to encode pixels for
49 * VDAC to output RGB ou YUV analog outputs.
50 * It's output is only used through the ENCP_DVI encoder for HDMI.
51 * The ENCL LVDS encoder is not implemented.
53 * The ENCI and ENCP encoders needs specially defined parameters for each
54 * supported mode and thus cannot be determined from standard video timings.
56 * The ENCI end ENCP DVI encoders are more generic and can generate any timings
57 * from the pixel data generated by ENCI or ENCP, so can use the standard video
58 * timings are source for HW parameters.
62 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
63 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
64 #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */
65 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
66 #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */
67 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
69 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
70 .mode_tag = MESON_VENC_MODE_CVBS_PAL,
76 .video_prog_mode = 0xff,
82 .top_field_line_start = 22,
83 .top_field_line_end = 310,
84 .bottom_field_line_start = 23,
85 .bottom_field_line_end = 311,
86 .video_saturation = 9,
88 .video_brightness = 0,
90 .analog_sync_adj = 0x8080,
93 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
94 .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
100 .video_prog_mode = 0xf0,
106 .top_field_line_start = 18,
107 .top_field_line_end = 258,
108 .bottom_field_line_start = 19,
109 .bottom_field_line_end = 259,
110 .video_saturation = 18,
112 .video_brightness = 0,
114 .analog_sync_adj = 0x9c00,
117 union meson_hdmi_venc_mode {
119 unsigned int mode_tag;
120 unsigned int hso_begin;
121 unsigned int hso_end;
122 unsigned int vso_even;
123 unsigned int vso_odd;
124 unsigned int macv_max_amp;
125 unsigned int video_prog_mode;
126 unsigned int video_mode;
127 unsigned int sch_adjust;
128 unsigned int yc_delay;
129 unsigned int pixel_start;
130 unsigned int pixel_end;
131 unsigned int top_field_line_start;
132 unsigned int top_field_line_end;
133 unsigned int bottom_field_line_start;
134 unsigned int bottom_field_line_end;
137 unsigned int dvi_settings;
138 unsigned int video_mode;
139 unsigned int video_mode_adv;
140 unsigned int video_prog_mode;
141 bool video_prog_mode_present;
142 unsigned int video_sync_mode;
143 bool video_sync_mode_present;
144 unsigned int video_yc_dly;
145 bool video_yc_dly_present;
146 unsigned int video_rgb_ctrl;
147 bool video_rgb_ctrl_present;
148 unsigned int video_filt_ctrl;
149 bool video_filt_ctrl_present;
150 unsigned int video_ofld_voav_ofst;
151 bool video_ofld_voav_ofst_present;
152 unsigned int yfp1_htime;
153 unsigned int yfp2_htime;
154 unsigned int max_pxcnt;
155 unsigned int hspuls_begin;
156 unsigned int hspuls_end;
157 unsigned int hspuls_switch;
158 unsigned int vspuls_begin;
159 unsigned int vspuls_end;
160 unsigned int vspuls_bline;
161 unsigned int vspuls_eline;
162 unsigned int eqpuls_begin;
163 bool eqpuls_begin_present;
164 unsigned int eqpuls_end;
165 bool eqpuls_end_present;
166 unsigned int eqpuls_bline;
167 bool eqpuls_bline_present;
168 unsigned int eqpuls_eline;
169 bool eqpuls_eline_present;
170 unsigned int havon_begin;
171 unsigned int havon_end;
172 unsigned int vavon_bline;
173 unsigned int vavon_eline;
174 unsigned int hso_begin;
175 unsigned int hso_end;
176 unsigned int vso_begin;
177 unsigned int vso_end;
178 unsigned int vso_bline;
179 unsigned int vso_eline;
180 bool vso_eline_present;
183 unsigned int sy2_val;
184 bool sy2_val_present;
185 unsigned int max_lncnt;
189 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
195 .macv_max_amp = 0x810b,
196 .video_prog_mode = 0xf0,
202 .top_field_line_start = 18,
203 .top_field_line_end = 258,
204 .bottom_field_line_start = 19,
205 .bottom_field_line_end = 259,
209 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
215 .macv_max_amp = 8107,
216 .video_prog_mode = 0xff,
222 .top_field_line_start = 22,
223 .top_field_line_end = 310,
224 .bottom_field_line_start = 23,
225 .bottom_field_line_end = 311,
229 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
231 .dvi_settings = 0x21,
232 .video_mode = 0x4000,
233 .video_mode_adv = 0x9,
234 .video_prog_mode = 0,
235 .video_prog_mode_present = true,
236 .video_sync_mode = 7,
237 .video_sync_mode_present = true,
240 .video_filt_ctrl = 0x2052,
241 .video_filt_ctrl_present = true,
242 /* video_ofld_voav_ofst */
246 .hspuls_begin = 0x22,
268 .sy_val_present = true,
270 .sy2_val_present = true,
275 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
277 .dvi_settings = 0x21,
278 .video_mode = 0x4000,
279 .video_mode_adv = 0x9,
280 .video_prog_mode = 0,
281 .video_prog_mode_present = true,
282 .video_sync_mode = 7,
283 .video_sync_mode_present = true,
286 .video_filt_ctrl = 0x52,
287 .video_filt_ctrl_present = true,
288 /* video_ofld_voav_ofst */
314 .sy_val_present = true,
316 .sy2_val_present = true,
321 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
323 .dvi_settings = 0x2029,
324 .video_mode = 0x4040,
325 .video_mode_adv = 0x19,
326 /* video_prog_mode */
327 /* video_sync_mode */
330 /* video_filt_ctrl */
331 /* video_ofld_voav_ofst */
356 .vso_eline_present = true,
363 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
365 .dvi_settings = 0x202d,
366 .video_mode = 0x4040,
367 .video_mode_adv = 0x19,
368 .video_prog_mode = 0x100,
369 .video_prog_mode_present = true,
370 .video_sync_mode = 0x407,
371 .video_sync_mode_present = true,
373 .video_yc_dly_present = true,
375 /* video_filt_ctrl */
376 /* video_ofld_voav_ofst */
401 .vso_eline_present = true,
408 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
410 .dvi_settings = 0x2029,
411 .video_mode = 0x5ffc,
412 .video_mode_adv = 0x19,
413 .video_prog_mode = 0x100,
414 .video_prog_mode_present = true,
415 .video_sync_mode = 0x207,
416 .video_sync_mode_present = true,
419 /* video_filt_ctrl */
420 .video_ofld_voav_ofst = 0x11,
421 .video_ofld_voav_ofst_present = true,
436 .eqpuls_begin = 2288,
437 .eqpuls_begin_present = true,
439 .eqpuls_end_present = true,
441 .eqpuls_bline_present = true,
443 .eqpuls_eline_present = true,
450 .vso_eline_present = true,
457 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
459 .dvi_settings = 0x202d,
460 .video_mode = 0x5ffc,
461 .video_mode_adv = 0x19,
462 .video_prog_mode = 0x100,
463 .video_prog_mode_present = true,
464 .video_sync_mode = 0x7,
465 .video_sync_mode_present = true,
468 /* video_filt_ctrl */
469 .video_ofld_voav_ofst = 0x11,
470 .video_ofld_voav_ofst_present = true,
485 .eqpuls_begin = 2288,
486 .eqpuls_begin_present = true,
488 .eqpuls_end_present = true,
490 .eqpuls_bline_present = true,
492 .eqpuls_eline_present = true,
499 .vso_eline_present = true,
506 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
509 .video_mode = 0x4040,
510 .video_mode_adv = 0x18,
511 .video_prog_mode = 0x100,
512 .video_prog_mode_present = true,
513 .video_sync_mode = 0x7,
514 .video_sync_mode_present = true,
516 .video_yc_dly_present = true,
518 .video_rgb_ctrl_present = true,
519 .video_filt_ctrl = 0x1052,
520 .video_filt_ctrl_present = true,
521 /* video_ofld_voav_ofst */
539 .eqpuls_bline_present = true,
541 .eqpuls_eline_present = true,
548 .vso_eline_present = true,
555 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
558 .video_mode = 0x4040,
559 .video_mode_adv = 0x18,
560 .video_prog_mode = 0x100,
561 .video_prog_mode_present = true,
562 /* video_sync_mode */
565 .video_filt_ctrl = 0x1052,
566 .video_filt_ctrl_present = true,
567 /* video_ofld_voav_ofst */
571 .hspuls_begin = 2156,
592 .vso_eline_present = true,
599 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
602 .video_mode = 0x4040,
603 .video_mode_adv = 0x18,
604 .video_prog_mode = 0x100,
605 .video_prog_mode_present = true,
606 .video_sync_mode = 0x7,
607 .video_sync_mode_present = true,
609 .video_yc_dly_present = true,
611 .video_rgb_ctrl_present = true,
612 /* video_filt_ctrl */
613 /* video_ofld_voav_ofst */
631 .eqpuls_bline_present = true,
633 .eqpuls_eline_present = true,
640 .vso_eline_present = true,
647 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
650 .video_mode = 0x4040,
651 .video_mode_adv = 0x18,
652 .video_prog_mode = 0x100,
653 .video_prog_mode_present = true,
654 /* video_sync_mode */
657 .video_filt_ctrl = 0x1052,
658 .video_filt_ctrl_present = true,
659 /* video_ofld_voav_ofst */
663 .hspuls_begin = 2156,
684 .vso_eline_present = true,
691 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {
694 .video_mode = 0x4040,
695 .video_mode_adv = 0x8,
696 /* video_sync_mode */
699 .video_filt_ctrl = 0x1000,
700 .video_filt_ctrl_present = true,
701 /* video_ofld_voav_ofst */
703 .yfp2_htime = 140+3840,
704 .max_pxcnt = 3840+1660-1,
705 .hspuls_begin = 2156+1920,
709 .vspuls_end = 2059+1920,
721 .hso_end = 2156+1920,
722 .vso_begin = 2100+1920,
723 .vso_end = 2164+1920,
726 .vso_eline_present = true,
733 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {
736 .video_mode = 0x4040,
737 .video_mode_adv = 0x8,
738 /* video_sync_mode */
741 .video_filt_ctrl = 0x1000,
742 .video_filt_ctrl_present = true,
743 /* video_ofld_voav_ofst */
745 .yfp2_htime = 140+3840,
746 .max_pxcnt = 3840+1440-1,
747 .hspuls_begin = 2156+1920,
751 .vspuls_end = 2059+1920,
763 .hso_end = 2156+1920,
764 .vso_begin = 2100+1920,
765 .vso_end = 2164+1920,
768 .vso_eline_present = true,
775 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
778 .video_mode = 0x4040,
779 .video_mode_adv = 0x8,
780 /* video_sync_mode */
783 .video_filt_ctrl = 0x1000,
784 .video_filt_ctrl_present = true,
785 /* video_ofld_voav_ofst */
787 .yfp2_htime = 140+3840,
788 .max_pxcnt = 3840+560-1,
789 .hspuls_begin = 2156+1920,
793 .vspuls_end = 2059+1920,
805 .hso_end = 2156+1920,
806 .vso_begin = 2100+1920,
807 .vso_end = 2164+1920,
810 .vso_eline_present = true,
817 struct meson_hdmi_venc_vic_mode {
819 union meson_hdmi_venc_mode *mode;
820 } meson_hdmi_venc_vic_modes[] = {
821 { 6, &meson_hdmi_enci_mode_480i },
822 { 7, &meson_hdmi_enci_mode_480i },
823 { 21, &meson_hdmi_enci_mode_576i },
824 { 22, &meson_hdmi_enci_mode_576i },
825 { 2, &meson_hdmi_encp_mode_480p },
826 { 3, &meson_hdmi_encp_mode_480p },
827 { 17, &meson_hdmi_encp_mode_576p },
828 { 18, &meson_hdmi_encp_mode_576p },
829 { 4, &meson_hdmi_encp_mode_720p60 },
830 { 19, &meson_hdmi_encp_mode_720p50 },
831 { 5, &meson_hdmi_encp_mode_1080i60 },
832 { 20, &meson_hdmi_encp_mode_1080i50 },
833 { 32, &meson_hdmi_encp_mode_1080p24 },
834 { 33, &meson_hdmi_encp_mode_1080p50 },
835 { 34, &meson_hdmi_encp_mode_1080p30 },
836 { 31, &meson_hdmi_encp_mode_1080p50 },
837 { 16, &meson_hdmi_encp_mode_1080p60 },
838 { 93, &meson_hdmi_encp_mode_2160p24 },
839 { 94, &meson_hdmi_encp_mode_2160p25 },
840 { 95, &meson_hdmi_encp_mode_2160p30 },
841 { 96, &meson_hdmi_encp_mode_2160p25 },
842 { 97, &meson_hdmi_encp_mode_2160p30 },
843 { 0, NULL}, /* sentinel */
846 static signed int to_signed(unsigned int a)
854 static unsigned long modulo(unsigned long a, unsigned long b)
863 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
865 if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
866 DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
869 if (mode->hdisplay < 640 || mode->hdisplay > 1920)
870 return MODE_BAD_HVALUE;
872 if (mode->vdisplay < 480 || mode->vdisplay > 1200)
873 return MODE_BAD_VVALUE;
877 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode);
879 bool meson_venc_hdmi_supported_vic(int vic)
881 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
883 while (vmode->vic && vmode->mode) {
884 if (vmode->vic == vic)
891 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic);
893 void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode,
894 union meson_hdmi_venc_mode *dmt_mode)
896 memset(dmt_mode, 0, sizeof(*dmt_mode));
898 dmt_mode->encp.dvi_settings = 0x21;
899 dmt_mode->encp.video_mode = 0x4040;
900 dmt_mode->encp.video_mode_adv = 0x18;
901 dmt_mode->encp.max_pxcnt = mode->htotal - 1;
902 dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start;
903 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin +
905 dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start;
906 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline +
908 dmt_mode->encp.hso_begin = 0;
909 dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start;
910 dmt_mode->encp.vso_begin = 30;
911 dmt_mode->encp.vso_end = 50;
912 dmt_mode->encp.vso_bline = 0;
913 dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start;
914 dmt_mode->encp.vso_eline_present = true;
915 dmt_mode->encp.max_lncnt = mode->vtotal - 1;
918 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
920 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
922 while (vmode->vic && vmode->mode) {
923 if (vmode->vic == vic)
931 bool meson_venc_hdmi_venc_repeat(int vic)
933 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
934 if (vic == 6 || vic == 7 || /* 480i */
935 vic == 21 || vic == 22 || /* 576i */
936 vic == 17 || vic == 18 || /* 576p */
937 vic == 2 || vic == 3 || /* 480p */
938 vic == 4 || /* 720p60 */
939 vic == 19 || /* 720p50 */
940 vic == 5 || /* 1080i60 */
941 vic == 20) /* 1080i50 */
946 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
948 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
949 struct drm_display_mode *mode)
951 union meson_hdmi_venc_mode *vmode = NULL;
952 union meson_hdmi_venc_mode vmode_dmt;
953 bool use_enci = false;
954 bool venc_repeat = false;
955 bool hdmi_repeat = false;
956 unsigned int venc_hdmi_latency = 2;
957 unsigned long total_pixels_venc = 0;
958 unsigned long active_pixels_venc = 0;
959 unsigned long front_porch_venc = 0;
960 unsigned long hsync_pixels_venc = 0;
961 unsigned long de_h_begin = 0;
962 unsigned long de_h_end = 0;
963 unsigned long de_v_begin_even = 0;
964 unsigned long de_v_end_even = 0;
965 unsigned long de_v_begin_odd = 0;
966 unsigned long de_v_end_odd = 0;
967 unsigned long hs_begin = 0;
968 unsigned long hs_end = 0;
969 unsigned long vs_adjust = 0;
970 unsigned long vs_bline_evn = 0;
971 unsigned long vs_eline_evn = 0;
972 unsigned long vs_bline_odd = 0;
973 unsigned long vs_eline_odd = 0;
974 unsigned long vso_begin_evn = 0;
975 unsigned long vso_begin_odd = 0;
976 unsigned int eof_lines;
977 unsigned int sof_lines;
978 unsigned int vsync_lines;
980 /* Use VENCI for 480i and 576i and double HDMI pixels */
981 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
984 venc_hdmi_latency = 1;
987 if (meson_venc_hdmi_supported_vic(vic)) {
988 vmode = meson_venc_hdmi_get_vic_vmode(vic);
990 dev_err(priv->dev, "%s: Fatal Error, unsupported mode "
991 DRM_MODE_FMT "\n", __func__,
996 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
1001 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
1002 if (meson_venc_hdmi_venc_repeat(vic))
1005 eof_lines = mode->vsync_start - mode->vdisplay;
1006 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1008 sof_lines = mode->vtotal - mode->vsync_end;
1009 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1011 vsync_lines = mode->vsync_end - mode->vsync_start;
1012 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1015 total_pixels_venc = mode->htotal;
1017 total_pixels_venc /= 2;
1019 total_pixels_venc *= 2;
1021 active_pixels_venc = mode->hdisplay;
1023 active_pixels_venc /= 2;
1025 active_pixels_venc *= 2;
1027 front_porch_venc = (mode->hsync_start - mode->hdisplay);
1029 front_porch_venc /= 2;
1031 front_porch_venc *= 2;
1033 hsync_pixels_venc = (mode->hsync_end - mode->hsync_start);
1035 hsync_pixels_venc /= 2;
1037 hsync_pixels_venc *= 2;
1040 writel_bits_relaxed(0xff, 0xff,
1041 priv->io_base + _REG(VENC_VDAC_SETTING));
1043 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1044 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1047 unsigned int lines_f0;
1048 unsigned int lines_f1;
1050 /* CVBS Filter settings */
1051 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1052 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1054 /* Digital Video Select : Interlace, clk27 clk, external */
1055 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1057 /* Reset Video Mode */
1058 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1059 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1061 /* Horizontal sync signal output */
1062 writel_relaxed(vmode->enci.hso_begin,
1063 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1064 writel_relaxed(vmode->enci.hso_end,
1065 priv->io_base + _REG(ENCI_SYNC_HSO_END));
1067 /* Vertical Sync lines */
1068 writel_relaxed(vmode->enci.vso_even,
1069 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1070 writel_relaxed(vmode->enci.vso_odd,
1071 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1073 /* Macrovision max amplitude change */
1074 writel_relaxed(vmode->enci.macv_max_amp,
1075 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1078 writel_relaxed(vmode->enci.video_prog_mode,
1079 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1080 writel_relaxed(vmode->enci.video_mode,
1081 priv->io_base + _REG(ENCI_VIDEO_MODE));
1083 /* Advanced Video Mode :
1084 * Demux shifting 0x2
1085 * Blank line end at line17/22
1086 * High bandwidth Luma Filter
1087 * Low bandwidth Chroma Filter
1088 * Bypass luma low pass filter
1089 * No macrovision on CSYNC
1091 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1093 writel(vmode->enci.sch_adjust,
1094 priv->io_base + _REG(ENCI_VIDEO_SCH));
1096 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1097 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1099 if (vmode->enci.yc_delay)
1100 writel_relaxed(vmode->enci.yc_delay,
1101 priv->io_base + _REG(ENCI_YC_DELAY));
1104 /* UNreset Interlaced TV Encoder */
1105 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1107 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1108 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1111 writel_relaxed(vmode->enci.pixel_start,
1112 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1113 writel_relaxed(vmode->enci.pixel_end,
1114 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1116 writel_relaxed(vmode->enci.top_field_line_start,
1117 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1118 writel_relaxed(vmode->enci.top_field_line_end,
1119 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1121 writel_relaxed(vmode->enci.bottom_field_line_start,
1122 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1123 writel_relaxed(vmode->enci.bottom_field_line_end,
1124 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1126 /* Select ENCI for VIU */
1127 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1129 /* Interlace video enable */
1130 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1132 lines_f0 = mode->vtotal >> 1;
1133 lines_f1 = lines_f0 + 1;
1135 de_h_begin = modulo(readl_relaxed(priv->io_base +
1136 _REG(ENCI_VFIFO2VD_PIXEL_START))
1137 + venc_hdmi_latency,
1139 de_h_end = modulo(de_h_begin + active_pixels_venc,
1142 writel_relaxed(de_h_begin,
1143 priv->io_base + _REG(ENCI_DE_H_BEGIN));
1144 writel_relaxed(de_h_end,
1145 priv->io_base + _REG(ENCI_DE_H_END));
1147 de_v_begin_even = readl_relaxed(priv->io_base +
1148 _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1149 de_v_end_even = de_v_begin_even + mode->vdisplay;
1150 de_v_begin_odd = readl_relaxed(priv->io_base +
1151 _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1152 de_v_end_odd = de_v_begin_odd + mode->vdisplay;
1154 writel_relaxed(de_v_begin_even,
1155 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
1156 writel_relaxed(de_v_end_even,
1157 priv->io_base + _REG(ENCI_DE_V_END_EVEN));
1158 writel_relaxed(de_v_begin_odd,
1159 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
1160 writel_relaxed(de_v_end_odd,
1161 priv->io_base + _REG(ENCI_DE_V_END_ODD));
1163 /* Program Hsync timing */
1164 hs_begin = de_h_end + front_porch_venc;
1165 if (de_h_end + front_porch_venc >= total_pixels_venc) {
1166 hs_begin -= total_pixels_venc;
1169 hs_begin = de_h_end + front_porch_venc;
1173 hs_end = modulo(hs_begin + hsync_pixels_venc,
1175 writel_relaxed(hs_begin,
1176 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
1177 writel_relaxed(hs_end,
1178 priv->io_base + _REG(ENCI_DVI_HSO_END));
1180 /* Program Vsync timing for even field */
1181 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
1182 vs_bline_evn = (de_v_end_odd - 1)
1186 vs_eline_evn = vs_bline_evn + vsync_lines;
1188 writel_relaxed(vs_bline_evn,
1189 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1191 writel_relaxed(vs_eline_evn,
1192 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
1194 writel_relaxed(hs_begin,
1195 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1196 writel_relaxed(hs_begin,
1197 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
1199 vs_bline_odd = (de_v_end_odd - 1)
1203 writel_relaxed(vs_bline_odd,
1204 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1206 writel_relaxed(hs_begin,
1207 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1209 if ((vs_bline_odd + vsync_lines) >= lines_f1) {
1210 vs_eline_evn = vs_bline_odd
1214 writel_relaxed(vs_eline_evn, priv->io_base
1215 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1217 writel_relaxed(hs_begin, priv->io_base
1218 + _REG(ENCI_DVI_VSO_END_EVN));
1220 vs_eline_odd = vs_bline_odd
1223 writel_relaxed(vs_eline_odd, priv->io_base
1224 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1226 writel_relaxed(hs_begin, priv->io_base
1227 + _REG(ENCI_DVI_VSO_END_ODD));
1231 /* Program Vsync timing for odd field */
1232 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
1233 vs_bline_odd = (de_v_end_even - 1)
1236 vs_eline_odd = vs_bline_odd + vsync_lines;
1238 writel_relaxed(vs_bline_odd,
1239 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1241 writel_relaxed(vs_eline_odd,
1242 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
1244 vso_begin_odd = modulo(hs_begin
1245 + (total_pixels_venc >> 1),
1248 writel_relaxed(vso_begin_odd,
1249 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1250 writel_relaxed(vso_begin_odd,
1251 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
1253 vs_bline_evn = (de_v_end_even - 1)
1256 writel_relaxed(vs_bline_evn,
1257 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1259 vso_begin_evn = modulo(hs_begin
1260 + (total_pixels_venc >> 1),
1263 writel_relaxed(vso_begin_evn, priv->io_base
1264 + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1266 if (vs_bline_evn + vsync_lines >= lines_f0) {
1267 vs_eline_odd = vs_bline_evn
1271 writel_relaxed(vs_eline_odd, priv->io_base
1272 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1274 writel_relaxed(vso_begin_evn, priv->io_base
1275 + _REG(ENCI_DVI_VSO_END_ODD));
1277 vs_eline_evn = vs_bline_evn + vsync_lines;
1279 writel_relaxed(vs_eline_evn, priv->io_base
1280 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1282 writel_relaxed(vso_begin_evn, priv->io_base
1283 + _REG(ENCI_DVI_VSO_END_EVN));
1287 writel_relaxed(vmode->encp.dvi_settings,
1288 priv->io_base + _REG(VENC_DVI_SETTING));
1289 writel_relaxed(vmode->encp.video_mode,
1290 priv->io_base + _REG(ENCP_VIDEO_MODE));
1291 writel_relaxed(vmode->encp.video_mode_adv,
1292 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
1293 if (vmode->encp.video_prog_mode_present)
1294 writel_relaxed(vmode->encp.video_prog_mode,
1295 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1296 if (vmode->encp.video_sync_mode_present)
1297 writel_relaxed(vmode->encp.video_sync_mode,
1298 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
1299 if (vmode->encp.video_yc_dly_present)
1300 writel_relaxed(vmode->encp.video_yc_dly,
1301 priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
1302 if (vmode->encp.video_rgb_ctrl_present)
1303 writel_relaxed(vmode->encp.video_rgb_ctrl,
1304 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
1305 if (vmode->encp.video_filt_ctrl_present)
1306 writel_relaxed(vmode->encp.video_filt_ctrl,
1307 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
1308 if (vmode->encp.video_ofld_voav_ofst_present)
1309 writel_relaxed(vmode->encp.video_ofld_voav_ofst,
1311 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1312 writel_relaxed(vmode->encp.yfp1_htime,
1313 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
1314 writel_relaxed(vmode->encp.yfp2_htime,
1315 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
1316 writel_relaxed(vmode->encp.max_pxcnt,
1317 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
1318 writel_relaxed(vmode->encp.hspuls_begin,
1319 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
1320 writel_relaxed(vmode->encp.hspuls_end,
1321 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
1322 writel_relaxed(vmode->encp.hspuls_switch,
1323 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
1324 writel_relaxed(vmode->encp.vspuls_begin,
1325 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
1326 writel_relaxed(vmode->encp.vspuls_end,
1327 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
1328 writel_relaxed(vmode->encp.vspuls_bline,
1329 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
1330 writel_relaxed(vmode->encp.vspuls_eline,
1331 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
1332 if (vmode->encp.eqpuls_begin_present)
1333 writel_relaxed(vmode->encp.eqpuls_begin,
1334 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
1335 if (vmode->encp.eqpuls_end_present)
1336 writel_relaxed(vmode->encp.eqpuls_end,
1337 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
1338 if (vmode->encp.eqpuls_bline_present)
1339 writel_relaxed(vmode->encp.eqpuls_bline,
1340 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
1341 if (vmode->encp.eqpuls_eline_present)
1342 writel_relaxed(vmode->encp.eqpuls_eline,
1343 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
1344 writel_relaxed(vmode->encp.havon_begin,
1345 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
1346 writel_relaxed(vmode->encp.havon_end,
1347 priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
1348 writel_relaxed(vmode->encp.vavon_bline,
1349 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
1350 writel_relaxed(vmode->encp.vavon_eline,
1351 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
1352 writel_relaxed(vmode->encp.hso_begin,
1353 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
1354 writel_relaxed(vmode->encp.hso_end,
1355 priv->io_base + _REG(ENCP_VIDEO_HSO_END));
1356 writel_relaxed(vmode->encp.vso_begin,
1357 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
1358 writel_relaxed(vmode->encp.vso_end,
1359 priv->io_base + _REG(ENCP_VIDEO_VSO_END));
1360 writel_relaxed(vmode->encp.vso_bline,
1361 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
1362 if (vmode->encp.vso_eline_present)
1363 writel_relaxed(vmode->encp.vso_eline,
1364 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
1365 if (vmode->encp.sy_val_present)
1366 writel_relaxed(vmode->encp.sy_val,
1367 priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
1368 if (vmode->encp.sy2_val_present)
1369 writel_relaxed(vmode->encp.sy2_val,
1370 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
1371 writel_relaxed(vmode->encp.max_lncnt,
1372 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
1374 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
1376 /* Set DE signal’s polarity is active high */
1377 writel_bits_relaxed(BIT(14), BIT(14),
1378 priv->io_base + _REG(ENCP_VIDEO_MODE));
1380 /* Program DE timing */
1381 de_h_begin = modulo(readl_relaxed(priv->io_base +
1382 _REG(ENCP_VIDEO_HAVON_BEGIN))
1383 + venc_hdmi_latency,
1385 de_h_end = modulo(de_h_begin + active_pixels_venc,
1388 writel_relaxed(de_h_begin,
1389 priv->io_base + _REG(ENCP_DE_H_BEGIN));
1390 writel_relaxed(de_h_end,
1391 priv->io_base + _REG(ENCP_DE_H_END));
1393 /* Program DE timing for even field */
1394 de_v_begin_even = readl_relaxed(priv->io_base
1395 + _REG(ENCP_VIDEO_VAVON_BLINE));
1396 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1397 de_v_end_even = de_v_begin_even +
1398 (mode->vdisplay / 2);
1400 de_v_end_even = de_v_begin_even + mode->vdisplay;
1402 writel_relaxed(de_v_begin_even,
1403 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
1404 writel_relaxed(de_v_end_even,
1405 priv->io_base + _REG(ENCP_DE_V_END_EVEN));
1407 /* Program DE timing for odd field if needed */
1408 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1409 unsigned int ofld_voav_ofst =
1410 readl_relaxed(priv->io_base +
1411 _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1412 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
1414 + ((mode->vtotal - 1) / 2);
1415 de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2);
1417 writel_relaxed(de_v_begin_odd,
1418 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
1419 writel_relaxed(de_v_end_odd,
1420 priv->io_base + _REG(ENCP_DE_V_END_ODD));
1423 /* Program Hsync timing */
1424 if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
1427 - total_pixels_venc;
1435 hs_end = modulo(hs_begin + hsync_pixels_venc,
1438 writel_relaxed(hs_begin,
1439 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
1440 writel_relaxed(hs_end,
1441 priv->io_base + _REG(ENCP_DVI_HSO_END));
1443 /* Program Vsync timing for even field */
1444 if (de_v_begin_even >=
1445 (sof_lines + vsync_lines + (1 - vs_adjust)))
1446 vs_bline_evn = de_v_begin_even
1451 vs_bline_evn = mode->vtotal
1457 vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
1460 writel_relaxed(vs_bline_evn,
1461 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
1462 writel_relaxed(vs_eline_evn,
1463 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
1465 vso_begin_evn = hs_begin;
1466 writel_relaxed(vso_begin_evn,
1467 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
1468 writel_relaxed(vso_begin_evn,
1469 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
1471 /* Program Vsync timing for odd field if needed */
1472 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1473 vs_bline_odd = (de_v_begin_odd - 1)
1476 vs_eline_odd = (de_v_begin_odd - 1)
1478 vso_begin_odd = modulo(hs_begin
1479 + (total_pixels_venc >> 1),
1482 writel_relaxed(vs_bline_odd,
1483 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
1484 writel_relaxed(vs_eline_odd,
1485 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
1486 writel_relaxed(vso_begin_odd,
1487 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
1488 writel_relaxed(vso_begin_odd,
1489 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
1492 /* Select ENCP for VIU */
1493 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
1496 writel_relaxed((use_enci ? 1 : 2) |
1497 (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
1498 (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
1500 (venc_repeat ? 1 << 8 : 0) |
1501 (hdmi_repeat ? 1 << 12 : 0),
1502 priv->io_base + _REG(VPU_HDMI_SETTING));
1504 priv->venc.hdmi_repeat = hdmi_repeat;
1505 priv->venc.venc_repeat = venc_repeat;
1506 priv->venc.hdmi_use_enci = use_enci;
1508 priv->venc.current_mode = MESON_VENC_MODE_HDMI;
1510 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
1512 void meson_venci_cvbs_mode_set(struct meson_drm *priv,
1513 struct meson_cvbs_enci_mode *mode)
1515 if (mode->mode_tag == priv->venc.current_mode)
1518 /* CVBS Filter settings */
1519 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1520 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1522 /* Digital Video Select : Interlace, clk27 clk, external */
1523 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1525 /* Reset Video Mode */
1526 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1527 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1529 /* Horizontal sync signal output */
1530 writel_relaxed(mode->hso_begin,
1531 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1532 writel_relaxed(mode->hso_end,
1533 priv->io_base + _REG(ENCI_SYNC_HSO_END));
1535 /* Vertical Sync lines */
1536 writel_relaxed(mode->vso_even,
1537 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1538 writel_relaxed(mode->vso_odd,
1539 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1541 /* Macrovision max amplitude change */
1542 writel_relaxed(0x8100 + mode->macv_max_amp,
1543 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1546 writel_relaxed(mode->video_prog_mode,
1547 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1548 writel_relaxed(mode->video_mode,
1549 priv->io_base + _REG(ENCI_VIDEO_MODE));
1551 /* Advanced Video Mode :
1552 * Demux shifting 0x2
1553 * Blank line end at line17/22
1554 * High bandwidth Luma Filter
1555 * Low bandwidth Chroma Filter
1556 * Bypass luma low pass filter
1557 * No macrovision on CSYNC
1559 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1561 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
1563 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1564 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1566 /* 0x3 Y, C, and Component Y delay */
1567 writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
1570 writel_relaxed(mode->pixel_start,
1571 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1572 writel_relaxed(mode->pixel_end,
1573 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1575 writel_relaxed(mode->top_field_line_start,
1576 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1577 writel_relaxed(mode->top_field_line_end,
1578 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1580 writel_relaxed(mode->bottom_field_line_start,
1581 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1582 writel_relaxed(mode->bottom_field_line_end,
1583 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1585 /* Internal Venc, Internal VIU Sync, Internal Vencoder */
1586 writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
1588 /* UNreset Interlaced TV Encoder */
1589 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1591 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1592 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1595 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
1597 /* Video Upsampling */
1598 writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1599 writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1600 writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1602 /* Select Interlace Y DACs */
1603 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
1604 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
1605 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
1606 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
1607 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
1608 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
1610 /* Select ENCI for VIU */
1611 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1613 /* Enable ENCI FIFO */
1614 writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1616 /* Select ENCI DACs 0, 1, 4, and 5 */
1617 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
1618 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
1620 /* Interlace video enable */
1621 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1623 /* Configure Video Saturation / Contrast / Brightness / Hue */
1624 writel_relaxed(mode->video_saturation,
1625 priv->io_base + _REG(ENCI_VIDEO_SAT));
1626 writel_relaxed(mode->video_contrast,
1627 priv->io_base + _REG(ENCI_VIDEO_CONT));
1628 writel_relaxed(mode->video_brightness,
1629 priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
1630 writel_relaxed(mode->video_hue,
1631 priv->io_base + _REG(ENCI_VIDEO_HUE));
1633 /* Enable DAC0 Filter */
1634 writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1635 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
1637 /* 0 in Macrovision register 0 */
1638 writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
1640 /* Analog Synchronization and color burst value adjust */
1641 writel_relaxed(mode->analog_sync_adj,
1642 priv->io_base + _REG(ENCI_SYNC_ADJ));
1644 priv->venc.current_mode = mode->mode_tag;
1647 /* Returns the current ENCI field polarity */
1648 unsigned int meson_venci_get_field(struct meson_drm *priv)
1650 return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29);
1653 void meson_venc_enable_vsync(struct meson_drm *priv)
1655 writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
1656 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
1659 void meson_venc_disable_vsync(struct meson_drm *priv)
1661 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
1662 writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
1665 void meson_venc_init(struct meson_drm *priv)
1667 /* Disable CVBS VDAC */
1668 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
1669 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
1670 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8);
1672 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
1673 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
1676 /* Power Down Dacs */
1677 writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
1679 /* Disable HDMI PHY */
1680 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
1683 writel_bits_relaxed(0x3, 0,
1684 priv->io_base + _REG(VPU_HDMI_SETTING));
1686 /* Disable all encoders */
1687 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1688 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1689 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
1691 /* Disable VSync IRQ */
1692 meson_venc_disable_vsync(priv);
1694 priv->venc.current_mode = MESON_VENC_MODE_NONE;