drivers/gpu/drm/meson/meson_plane.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2016 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   6  * Copyright (C) 2014 Endless Mobile
   7  *
   8  * Written by:
   9  *     Jasper St. Pierre <jstpierre@mecheye.net>
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/mutex.h>
  15 #include <linux/bitfield.h>
  16 #include <linux/platform_device.h>
  17 #include <drm/drmP.h>
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_fb_cma_helper.h>
  23 #include <drm/drm_gem_framebuffer_helper.h>
  24 #include <drm/drm_rect.h>
  25
  26 #include "meson_plane.h"
  27 #include "meson_vpp.h"
  28 #include "meson_viu.h"
  29 #include "meson_registers.h"
  30
  31 /* OSD_SCI_WH_M1 */
  32 #define SCI_WH_M1_W(w)                  FIELD_PREP(GENMASK(28, 16), w)
  33 #define SCI_WH_M1_H(h)                  FIELD_PREP(GENMASK(12, 0), h)
  34
  35 /* OSD_SCO_H_START_END */
  36 /* OSD_SCO_V_START_END */
  37 #define SCO_HV_START(start)             FIELD_PREP(GENMASK(27, 16), start)
  38 #define SCO_HV_END(end)                 FIELD_PREP(GENMASK(11, 0), end)
  39
  40 /* OSD_SC_CTRL0 */
  41 #define SC_CTRL0_PATH_EN                BIT(3)
  42 #define SC_CTRL0_SEL_OSD1               BIT(2)
  43
  44 /* OSD_VSC_CTRL0 */
  45 #define VSC_BANK_LEN(value)             FIELD_PREP(GENMASK(2, 0), value)
  46 #define VSC_TOP_INI_RCV_NUM(value)      FIELD_PREP(GENMASK(6, 3), value)
  47 #define VSC_TOP_RPT_L0_NUM(value)       FIELD_PREP(GENMASK(9, 8), value)
  48 #define VSC_BOT_INI_RCV_NUM(value)      FIELD_PREP(GENMASK(14, 11), value)
  49 #define VSC_BOT_RPT_L0_NUM(value)       FIELD_PREP(GENMASK(17, 16), value)
  50 #define VSC_PROG_INTERLACE              BIT(23)
  51 #define VSC_VERTICAL_SCALER_EN          BIT(24)
  52
  53 /* OSD_VSC_INI_PHASE */
  54 #define VSC_INI_PHASE_BOT(bottom)       FIELD_PREP(GENMASK(31, 16), bottom)
  55 #define VSC_INI_PHASE_TOP(top)          FIELD_PREP(GENMASK(15, 0), top)
  56
  57 /* OSD_HSC_CTRL0 */
  58 #define HSC_BANK_LENGTH(value)          FIELD_PREP(GENMASK(2, 0), value)
  59 #define HSC_INI_RCV_NUM0(value)         FIELD_PREP(GENMASK(6, 3), value)
  60 #define HSC_RPT_P0_NUM0(value)          FIELD_PREP(GENMASK(9, 8), value)
  61 #define HSC_HORIZ_SCALER_EN             BIT(22)
  62
  63 /* VPP_OSD_VSC_PHASE_STEP */
  64 /* VPP_OSD_HSC_PHASE_STEP */
  65 #define SC_PHASE_STEP(value)            FIELD_PREP(GENMASK(27, 0), value)
  66
  67 struct meson_plane {
  68         struct drm_plane base;
  69         struct meson_drm *priv;
  70         bool enabled;
  71 };
  72 #define to_meson_plane(x) container_of(x, struct meson_plane, base)
  73
  74 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
  75
  76 static int meson_plane_atomic_check(struct drm_plane *plane,
  77                                     struct drm_plane_state *state)
  78 {
  79         struct drm_crtc_state *crtc_state;
  80
  81         if (!state->crtc)
  82                 return 0;
  83
  84         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
  85         if (IS_ERR(crtc_state))
  86                 return PTR_ERR(crtc_state);
  87
  88         /*
  89          * Only allow :
  90          * - Upscaling up to 5x, vertical and horizontal
  91          * - Final coordinates must match crtc size
  92          */
  93         return drm_atomic_helper_check_plane_state(state, crtc_state,
  94                                                    FRAC_16_16(1, 5),
  95                                                    DRM_PLANE_HELPER_NO_SCALING,
  96                                                    false, true);
  97 }
  98
  99 /* Takes a fixed 16.16 number and converts it to integer. */
 100 static inline int64_t fixed16_to_int(int64_t value)
 101 {
 102         return value >> 16;
 103 }
 104
 105 static void meson_plane_atomic_update(struct drm_plane *plane,
 106                                       struct drm_plane_state *old_state)
 107 {
 108         struct meson_plane *meson_plane = to_meson_plane(plane);
 109         struct drm_plane_state *state = plane->state;
 110         struct drm_rect dest = drm_plane_state_dest(state);
 111         struct meson_drm *priv = meson_plane->priv;
 112         struct drm_framebuffer *fb = state->fb;
 113         struct drm_gem_cma_object *gem;
 114         unsigned long flags;
 115         int vsc_ini_rcv_num, vsc_ini_rpt_p0_num;
 116         int vsc_bot_rcv_num, vsc_bot_rpt_p0_num;
 117         int hsc_ini_rcv_num, hsc_ini_rpt_p0_num;
 118         int hf_phase_step, vf_phase_step;
 119         int src_w, src_h, dst_w, dst_h;
 120         int bot_ini_phase;
 121         int hf_bank_len;
 122         int vf_bank_len;
 123         u8 canvas_id_osd1;
 124
 125         /*
 126          * Update Coordinates
 127          * Update Formats
 128          * Update Buffer
 129          * Enable Plane
 130          */
 131         spin_lock_irqsave(&priv->drm->event_lock, flags);
 132
 133         /* Enable OSD and BLK0, set max global alpha */
 134         priv->viu.osd1_ctrl_stat = OSD_ENABLE |
 135                                    (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
 136                                    OSD_BLK0_ENABLE;
 137
 138         canvas_id_osd1 = priv->canvas_id_osd1;
 139
 140         /* Set up BLK0 to point to the right canvas */
 141         priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) |
 142                                       OSD_ENDIANNESS_LE);
 143
 144         /* On GXBB, Use the old non-HDR RGB2YUV converter */
 145         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 146                 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
 147
 148         switch (fb->format->format) {
 149         case DRM_FORMAT_XRGB8888:
 150                 /* For XRGB, replace the pixel's alpha by 0xFF */
 151                 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
 152                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 153                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 154                                               OSD_COLOR_MATRIX_32_ARGB;
 155                 break;
 156         case DRM_FORMAT_XBGR8888:
 157                 /* For XRGB, replace the pixel's alpha by 0xFF */
 158                 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
 159                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 160                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 161                                               OSD_COLOR_MATRIX_32_ABGR;
 162                 break;
 163         case DRM_FORMAT_ARGB8888:
 164                 /* For ARGB, use the pixel's alpha */
 165                 writel_bits_relaxed(OSD_REPLACE_EN, 0,
 166                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 167                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 168                                               OSD_COLOR_MATRIX_32_ARGB;
 169                 break;
 170         case DRM_FORMAT_ABGR8888:
 171                 /* For ARGB, use the pixel's alpha */
 172                 writel_bits_relaxed(OSD_REPLACE_EN, 0,
 173                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 174                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 175                                               OSD_COLOR_MATRIX_32_ABGR;
 176                 break;
 177         case DRM_FORMAT_RGB888:
 178                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
 179                                               OSD_COLOR_MATRIX_24_RGB;
 180                 break;
 181         case DRM_FORMAT_RGB565:
 182                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
 183                                               OSD_COLOR_MATRIX_16_RGB565;
 184                 break;
 185         };
 186
 187         /* Default scaler parameters */
 188         vsc_bot_rcv_num = 0;
 189         vsc_bot_rpt_p0_num = 0;
 190         hf_bank_len = 4;
 191         vf_bank_len = 4;
 192
 193         if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
 194                 vsc_bot_rcv_num = 6;
 195                 vsc_bot_rpt_p0_num = 2;
 196         }
 197
 198         hsc_ini_rcv_num = hf_bank_len;
 199         vsc_ini_rcv_num = vf_bank_len;
 200         hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1;
 201         vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1;
 202
 203         src_w = fixed16_to_int(state->src_w);
 204         src_h = fixed16_to_int(state->src_h);
 205         dst_w = state->crtc_w;
 206         dst_h = state->crtc_h;
 207
 208         /*
 209          * When the output is interlaced, the OSD must switch between
 210          * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
 211          * at each vsync.
 212          * But the vertical scaler can provide such funtionnality if
 213          * is configured for 2:1 scaling with interlace options enabled.
 214          */
 215         if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
 216                 dest.y1 /= 2;
 217                 dest.y2 /= 2;
 218                 dst_h /= 2;
 219         }
 220
 221         hf_phase_step = ((src_w << 18) / dst_w) << 6;
 222         vf_phase_step = (src_h << 20) / dst_h;
 223
 224         if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 225                 bot_ini_phase = ((vf_phase_step / 2) >> 4);
 226         else
 227                 bot_ini_phase = 0;
 228
 229         vf_phase_step = (vf_phase_step << 4);
 230
 231         /* In interlaced mode, scaler is always active */
 232         if (src_h != dst_h || src_w != dst_w) {
 233                 priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
 234                                            SCI_WH_M1_H(src_h - 1);
 235                 priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
 236                                                  SCO_HV_END(dest.x2 - 1);
 237                 priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
 238                                                  SCO_HV_END(dest.y2 - 1);
 239                 /* Enable OSD Scaler */
 240                 priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
 241         } else {
 242                 priv->viu.osd_sc_i_wh_m1 = 0;
 243                 priv->viu.osd_sc_o_h_start_end = 0;
 244                 priv->viu.osd_sc_o_v_start_end = 0;
 245                 priv->viu.osd_sc_ctrl0 = 0;
 246         }
 247
 248         /* In interlaced mode, vertical scaler is always active */
 249         if (src_h != dst_h) {
 250                 priv->viu.osd_sc_v_ctrl0 =
 251                                         VSC_BANK_LEN(vf_bank_len) |
 252                                         VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) |
 253                                         VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) |
 254                                         VSC_VERTICAL_SCALER_EN;
 255
 256                 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 257                         priv->viu.osd_sc_v_ctrl0 |=
 258                                         VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) |
 259                                         VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) |
 260                                         VSC_PROG_INTERLACE;
 261
 262                 priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
 263                 priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
 264         } else {
 265                 priv->viu.osd_sc_v_ctrl0 = 0;
 266                 priv->viu.osd_sc_v_phase_step = 0;
 267                 priv->viu.osd_sc_v_ini_phase = 0;
 268         }
 269
 270         /* Horizontal scaler is only used if width does not match */
 271         if (src_w != dst_w) {
 272                 priv->viu.osd_sc_h_ctrl0 =
 273                                         HSC_BANK_LENGTH(hf_bank_len) |
 274                                         HSC_INI_RCV_NUM0(hsc_ini_rcv_num) |
 275                                         HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) |
 276                                         HSC_HORIZ_SCALER_EN;
 277                 priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
 278                 priv->viu.osd_sc_h_ini_phase = 0;
 279         } else {
 280                 priv->viu.osd_sc_h_ctrl0 = 0;
 281                 priv->viu.osd_sc_h_phase_step = 0;
 282                 priv->viu.osd_sc_h_ini_phase = 0;
 283         }
 284
 285         /*
 286          * The format of these registers is (x2 << 16 | x1),
 287          * where x2 is exclusive.
 288          * e.g. +30x1920 would be (1919 << 16) | 30
 289          */
 290         priv->viu.osd1_blk0_cfg[1] =
 291                                 ((fixed16_to_int(state->src.x2) - 1) << 16) |
 292                                 fixed16_to_int(state->src.x1);
 293         priv->viu.osd1_blk0_cfg[2] =
 294                                 ((fixed16_to_int(state->src.y2) - 1) << 16) |
 295                                 fixed16_to_int(state->src.y1);
 296         priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
 297         priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
 298
 299         if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
 300                 priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
 301                 priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
 302                 priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
 303                 priv->viu.osb_blend1_size = dst_h << 16 | dst_w;
 304         }
 305
 306         /* Update Canvas with buffer address */
 307         gem = drm_fb_cma_get_gem_obj(fb, 0);
 308
 309         priv->viu.osd1_addr = gem->paddr;
 310         priv->viu.osd1_stride = fb->pitches[0];
 311         priv->viu.osd1_height = fb->height;
 312
 313         if (!meson_plane->enabled) {
 314                 /* Reset OSD1 before enabling it on GXL+ SoCs */
 315                 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 316                     meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 317                         meson_viu_osd1_reset(priv);
 318
 319                 meson_plane->enabled = true;
 320         }
 321
 322         priv->viu.osd1_enabled = true;
 323
 324         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 325 }
 326
 327 static void meson_plane_atomic_disable(struct drm_plane *plane,
 328                                        struct drm_plane_state *old_state)
 329 {
 330         struct meson_plane *meson_plane = to_meson_plane(plane);
 331         struct meson_drm *priv = meson_plane->priv;
 332
 333         /* Disable OSD1 */
 334         if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 335                 writel_bits_relaxed(3 << 8, 0,
 336                                     priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
 337         else
 338                 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
 339                                     priv->io_base + _REG(VPP_MISC));
 340
 341         meson_plane->enabled = false;
 342         priv->viu.osd1_enabled = false;
 343 }
 344
 345 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
 346         .atomic_check   = meson_plane_atomic_check,
 347         .atomic_disable = meson_plane_atomic_disable,
 348         .atomic_update  = meson_plane_atomic_update,
 349         .prepare_fb     = drm_gem_fb_prepare_fb,
 350 };
 351
 352 static const struct drm_plane_funcs meson_plane_funcs = {
 353         .update_plane           = drm_atomic_helper_update_plane,
 354         .disable_plane          = drm_atomic_helper_disable_plane,
 355         .destroy                = drm_plane_cleanup,
 356         .reset                  = drm_atomic_helper_plane_reset,
 357         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 358         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 359 };
 360
 361 static const uint32_t supported_drm_formats[] = {
 362         DRM_FORMAT_ARGB8888,
 363         DRM_FORMAT_ABGR8888,
 364         DRM_FORMAT_XRGB8888,
 365         DRM_FORMAT_XBGR8888,
 366         DRM_FORMAT_RGB888,
 367         DRM_FORMAT_RGB565,
 368 };
 369
 370 int meson_plane_create(struct meson_drm *priv)
 371 {
 372         struct meson_plane *meson_plane;
 373         struct drm_plane *plane;
 374
 375         meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
 376                                    GFP_KERNEL);
 377         if (!meson_plane)
 378                 return -ENOMEM;
 379
 380         meson_plane->priv = priv;
 381         plane = &meson_plane->base;
 382
 383         drm_universal_plane_init(priv->drm, plane, 0xFF,
 384                                  &meson_plane_funcs,
 385                                  supported_drm_formats,
 386                                  ARRAY_SIZE(supported_drm_formats),
 387                                  NULL,
 388                                  DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
 389
 390         drm_plane_helper_add(plane, &meson_plane_helper_funcs);
 391
 392         /* For now, OSD Primary plane is always on the front */
 393         drm_plane_create_zpos_immutable_property(plane, 1);
 394
 395         priv->primary_plane = plane;
 396
 397         return 0;
 398 }