1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
10 #include <linux/device.h>
12 #include <linux/regmap.h>
21 void __iomem *io_base;
25 struct meson_canvas *canvas;
31 struct drm_device *drm;
32 struct drm_crtc *crtc;
33 struct drm_plane *primary_plane;
34 struct drm_plane *overlay_plane;
41 uint32_t osd1_ctrl_stat;
42 uint32_t osd1_blk0_cfg[5];
46 uint32_t osd_sc_ctrl0;
47 uint32_t osd_sc_i_wh_m1;
48 uint32_t osd_sc_o_h_start_end;
49 uint32_t osd_sc_o_v_start_end;
50 uint32_t osd_sc_v_ini_phase;
51 uint32_t osd_sc_v_phase_step;
52 uint32_t osd_sc_h_ini_phase;
53 uint32_t osd_sc_h_phase_step;
54 uint32_t osd_sc_h_ctrl0;
55 uint32_t osd_sc_v_ctrl0;
56 uint32_t osd_blend_din0_scope_h;
57 uint32_t osd_blend_din0_scope_v;
58 uint32_t osb_blend0_size;
59 uint32_t osb_blend1_size;
63 unsigned int vd1_planes;
64 uint32_t vd1_if0_gen_reg;
65 uint32_t vd1_if0_luma_x0;
66 uint32_t vd1_if0_luma_y0;
67 uint32_t vd1_if0_chroma_x0;
68 uint32_t vd1_if0_chroma_y0;
69 uint32_t vd1_if0_repeat_loop;
70 uint32_t vd1_if0_luma0_rpt_pat;
71 uint32_t vd1_if0_chroma0_rpt_pat;
72 uint32_t vd1_range_map_y;
73 uint32_t vd1_range_map_cb;
74 uint32_t vd1_range_map_cr;
75 uint32_t viu_vd1_fmt_w;
76 uint32_t vd1_if0_canvas0;
77 uint32_t vd1_if0_gen_reg2;
78 uint32_t viu_vd1_fmt_ctrl;
88 uint32_t vpp_pic_in_height;
89 uint32_t vpp_postblend_vd1_h_start_end;
90 uint32_t vpp_postblend_vd1_v_start_end;
91 uint32_t vpp_hsc_region12_startp;
92 uint32_t vpp_hsc_region34_startp;
93 uint32_t vpp_hsc_region4_endp;
94 uint32_t vpp_hsc_start_phase_step;
95 uint32_t vpp_hsc_region1_phase_slope;
96 uint32_t vpp_hsc_region3_phase_slope;
97 uint32_t vpp_line_in_length;
98 uint32_t vpp_preblend_h_size;
99 uint32_t vpp_vsc_region12_startp;
100 uint32_t vpp_vsc_region34_startp;
101 uint32_t vpp_vsc_region4_endp;
102 uint32_t vpp_vsc_start_phase_step;
103 uint32_t vpp_vsc_ini_phase;
104 uint32_t vpp_vsc_phase_ctrl;
105 uint32_t vpp_hsc_phase_ctrl;
106 uint32_t vpp_blend_vd2_h_start_end;
107 uint32_t vpp_blend_vd2_v_start_end;
111 unsigned int current_mode;
118 static inline int meson_vpu_is_compatible(struct meson_drm *priv,
121 return of_device_is_compatible(priv->dev->of_node, compat);
124 #endif /* __MESON_DRV_H */