drivers/gpu/drm/mediatek/mtk_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/iopoll.h>
   9 #include <linux/irq.h>
  10 #include <linux/of.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/phy/phy.h>
  13 #include <linux/platform_device.h>
  14
  15 #include <video/mipi_display.h>
  16 #include <video/videomode.h>
  17
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_bridge.h>
  20 #include <drm/drm_mipi_dsi.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_panel.h>
  23 #include <drm/drm_print.h>
  24 #include <drm/drm_probe_helper.h>
  25
  26 #include "mtk_drm_ddp_comp.h"
  27
  28 #define DSI_START               0x00
  29
  30 #define DSI_INTEN               0x08
  31
  32 #define DSI_INTSTA              0x0c
  33 #define LPRX_RD_RDY_INT_FLAG            BIT(0)
  34 #define CMD_DONE_INT_FLAG               BIT(1)
  35 #define TE_RDY_INT_FLAG                 BIT(2)
  36 #define VM_DONE_INT_FLAG                BIT(3)
  37 #define EXT_TE_RDY_INT_FLAG             BIT(4)
  38 #define DSI_BUSY                        BIT(31)
  39
  40 #define DSI_CON_CTRL            0x10
  41 #define DSI_RESET                       BIT(0)
  42 #define DSI_EN                          BIT(1)
  43 #define DPHY_RESET                      BIT(2)
  44
  45 #define DSI_MODE_CTRL           0x14
  46 #define MODE                            (3)
  47 #define CMD_MODE                        0
  48 #define SYNC_PULSE_MODE                 1
  49 #define SYNC_EVENT_MODE                 2
  50 #define BURST_MODE                      3
  51 #define FRM_MODE                        BIT(16)
  52 #define MIX_MODE                        BIT(17)
  53
  54 #define DSI_TXRX_CTRL           0x18
  55 #define VC_NUM                          BIT(1)
  56 #define LANE_NUM                        (0xf << 2)
  57 #define DIS_EOT                         BIT(6)
  58 #define NULL_EN                         BIT(7)
  59 #define TE_FREERUN                      BIT(8)
  60 #define EXT_TE_EN                       BIT(9)
  61 #define EXT_TE_EDGE                     BIT(10)
  62 #define MAX_RTN_SIZE                    (0xf << 12)
  63 #define HSTX_CKLP_EN                    BIT(16)
  64
  65 #define DSI_PSCTRL              0x1c
  66 #define DSI_PS_WC                       0x3fff
  67 #define DSI_PS_SEL                      (3 << 16)
  68 #define PACKED_PS_16BIT_RGB565          (0 << 16)
  69 #define LOOSELY_PS_18BIT_RGB666         (1 << 16)
  70 #define PACKED_PS_18BIT_RGB666          (2 << 16)
  71 #define PACKED_PS_24BIT_RGB888          (3 << 16)
  72
  73 #define DSI_VSA_NL              0x20
  74 #define DSI_VBP_NL              0x24
  75 #define DSI_VFP_NL              0x28
  76 #define DSI_VACT_NL             0x2C
  77 #define DSI_SIZE_CON            0x38
  78 #define DSI_HSA_WC              0x50
  79 #define DSI_HBP_WC              0x54
  80 #define DSI_HFP_WC              0x58
  81
  82 #define DSI_CMDQ_SIZE           0x60
  83 #define CMDQ_SIZE                       0x3f
  84
  85 #define DSI_HSTX_CKL_WC         0x64
  86
  87 #define DSI_RX_DATA0            0x74
  88 #define DSI_RX_DATA1            0x78
  89 #define DSI_RX_DATA2            0x7c
  90 #define DSI_RX_DATA3            0x80
  91
  92 #define DSI_RACK                0x84
  93 #define RACK                            BIT(0)
  94
  95 #define DSI_PHY_LCCON           0x104
  96 #define LC_HS_TX_EN                     BIT(0)
  97 #define LC_ULPM_EN                      BIT(1)
  98 #define LC_WAKEUP_EN                    BIT(2)
  99
 100 #define DSI_PHY_LD0CON          0x108
 101 #define LD0_HS_TX_EN                    BIT(0)
 102 #define LD0_ULPM_EN                     BIT(1)
 103 #define LD0_WAKEUP_EN                   BIT(2)
 104
 105 #define DSI_PHY_TIMECON0        0x110
 106 #define LPX                             (0xff << 0)
 107 #define HS_PREP                         (0xff << 8)
 108 #define HS_ZERO                         (0xff << 16)
 109 #define HS_TRAIL                        (0xff << 24)
 110
 111 #define DSI_PHY_TIMECON1        0x114
 112 #define TA_GO                           (0xff << 0)
 113 #define TA_SURE                         (0xff << 8)
 114 #define TA_GET                          (0xff << 16)
 115 #define DA_HS_EXIT                      (0xff << 24)
 116
 117 #define DSI_PHY_TIMECON2        0x118
 118 #define CONT_DET                        (0xff << 0)
 119 #define CLK_ZERO                        (0xff << 16)
 120 #define CLK_TRAIL                       (0xff << 24)
 121
 122 #define DSI_PHY_TIMECON3        0x11c
 123 #define CLK_HS_PREP                     (0xff << 0)
 124 #define CLK_HS_POST                     (0xff << 8)
 125 #define CLK_HS_EXIT                     (0xff << 16)
 126
 127 #define DSI_VM_CMD_CON          0x130
 128 #define VM_CMD_EN                       BIT(0)
 129 #define TS_VFP_EN                       BIT(5)
 130
 131 #define DSI_SHADOW_DEBUG        0x190U
 132 #define FORCE_COMMIT                    BIT(0)
 133 #define BYPASS_SHADOW                   BIT(1)
 134
 135 #define CONFIG                          (0xff << 0)
 136 #define SHORT_PACKET                    0
 137 #define LONG_PACKET                     2
 138 #define BTA                             BIT(2)
 139 #define DATA_ID                         (0xff << 8)
 140 #define DATA_0                          (0xff << 16)
 141 #define DATA_1                          (0xff << 24)
 142
 143 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 144
 145 #define MTK_DSI_HOST_IS_READ(type) \
 146         ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
 147         (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
 148         (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
 149         (type == MIPI_DSI_DCS_READ))
 150
 151 struct mtk_phy_timing {
 152         u32 lpx;
 153         u32 da_hs_prepare;
 154         u32 da_hs_zero;
 155         u32 da_hs_trail;
 156
 157         u32 ta_go;
 158         u32 ta_sure;
 159         u32 ta_get;
 160         u32 da_hs_exit;
 161
 162         u32 clk_hs_zero;
 163         u32 clk_hs_trail;
 164
 165         u32 clk_hs_prepare;
 166         u32 clk_hs_post;
 167         u32 clk_hs_exit;
 168 };
 169
 170 struct phy;
 171
 172 struct mtk_dsi_driver_data {
 173         const u32 reg_cmdq_off;
 174         bool has_shadow_ctl;
 175         bool has_size_ctl;
 176 };
 177
 178 struct mtk_dsi {
 179         struct mtk_ddp_comp ddp_comp;
 180         struct device *dev;
 181         struct mipi_dsi_host host;
 182         struct drm_encoder encoder;
 183         struct drm_connector conn;
 184         struct drm_panel *panel;
 185         struct drm_bridge *bridge;
 186         struct phy *phy;
 187
 188         void __iomem *regs;
 189
 190         struct clk *engine_clk;
 191         struct clk *digital_clk;
 192         struct clk *hs_clk;
 193
 194         u32 data_rate;
 195
 196         unsigned long mode_flags;
 197         enum mipi_dsi_pixel_format format;
 198         unsigned int lanes;
 199         struct videomode vm;
 200         struct mtk_phy_timing phy_timing;
 201         int refcount;
 202         bool enabled;
 203         u32 irq_data;
 204         wait_queue_head_t irq_wait_queue;
 205         const struct mtk_dsi_driver_data *driver_data;
 206 };
 207
 208 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
 209 {
 210         return container_of(e, struct mtk_dsi, encoder);
 211 }
 212
 213 static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
 214 {
 215         return container_of(c, struct mtk_dsi, conn);
 216 }
 217
 218 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
 219 {
 220         return container_of(h, struct mtk_dsi, host);
 221 }
 222
 223 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
 224 {
 225         u32 temp = readl(dsi->regs + offset);
 226
 227         writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 228 }
 229
 230 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 231 {
 232         u32 timcon0, timcon1, timcon2, timcon3;
 233         u32 ui, cycle_time;
 234         struct mtk_phy_timing *timing = &dsi->phy_timing;
 235
 236         ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
 237         cycle_time = div_u64(8000000000ULL, dsi->data_rate);
 238
 239         timing->lpx = NS_TO_CYCLE(60, cycle_time);
 240         timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
 241         timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
 242         timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
 243
 244         timing->ta_go = 4 * timing->lpx;
 245         timing->ta_sure = 3 * timing->lpx / 2;
 246         timing->ta_get = 5 * timing->lpx;
 247         timing->da_hs_exit = 2 * timing->lpx;
 248
 249         timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
 250         timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
 251
 252         timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
 253         timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
 254         timing->clk_hs_exit = 2 * timing->lpx;
 255
 256         timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
 257                   timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
 258         timcon1 = timing->ta_go | timing->ta_sure << 8 |
 259                   timing->ta_get << 16 | timing->da_hs_exit << 24;
 260         timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
 261                   timing->clk_hs_trail << 24;
 262         timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
 263                   timing->clk_hs_exit << 16;
 264
 265         writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
 266         writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
 267         writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
 268         writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
 269 }
 270
 271 static void mtk_dsi_enable(struct mtk_dsi *dsi)
 272 {
 273         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
 274 }
 275
 276 static void mtk_dsi_disable(struct mtk_dsi *dsi)
 277 {
 278         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 279 }
 280
 281 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 282 {
 283         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
 284         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 285 }
 286
 287 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
 288 {
 289         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
 290         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
 291 }
 292
 293 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 294 {
 295         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 296         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 297 }
 298
 299 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 300 {
 301         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 302         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
 303         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 304 }
 305
 306 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 307 {
 308         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
 309         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 310 }
 311
 312 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 313 {
 314         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 315         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
 316         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 317 }
 318
 319 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 320 {
 321         u32 tmp_reg1;
 322
 323         tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
 324         return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 325 }
 326
 327 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 328 {
 329         if (enter && !mtk_dsi_clk_hs_state(dsi))
 330                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
 331         else if (!enter && mtk_dsi_clk_hs_state(dsi))
 332                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 333 }
 334
 335 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 336 {
 337         u32 vid_mode = CMD_MODE;
 338
 339         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 340                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 341                         vid_mode = BURST_MODE;
 342                 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 343                         vid_mode = SYNC_PULSE_MODE;
 344                 else
 345                         vid_mode = SYNC_EVENT_MODE;
 346         }
 347
 348         writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 349 }
 350
 351 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
 352 {
 353         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
 354         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
 355 }
 356
 357 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 358 {
 359         struct videomode *vm = &dsi->vm;
 360         u32 dsi_buf_bpp, ps_wc;
 361         u32 ps_bpp_mode;
 362
 363         if (dsi->format == MIPI_DSI_FMT_RGB565)
 364                 dsi_buf_bpp = 2;
 365         else
 366                 dsi_buf_bpp = 3;
 367
 368         ps_wc = vm->hactive * dsi_buf_bpp;
 369         ps_bpp_mode = ps_wc;
 370
 371         switch (dsi->format) {
 372         case MIPI_DSI_FMT_RGB888:
 373                 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
 374                 break;
 375         case MIPI_DSI_FMT_RGB666:
 376                 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
 377                 break;
 378         case MIPI_DSI_FMT_RGB666_PACKED:
 379                 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
 380                 break;
 381         case MIPI_DSI_FMT_RGB565:
 382                 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
 383                 break;
 384         }
 385
 386         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 387         writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
 388         writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 389 }
 390
 391 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 392 {
 393         u32 tmp_reg;
 394
 395         switch (dsi->lanes) {
 396         case 1:
 397                 tmp_reg = 1 << 2;
 398                 break;
 399         case 2:
 400                 tmp_reg = 3 << 2;
 401                 break;
 402         case 3:
 403                 tmp_reg = 7 << 2;
 404                 break;
 405         case 4:
 406                 tmp_reg = 0xf << 2;
 407                 break;
 408         default:
 409                 tmp_reg = 0xf << 2;
 410                 break;
 411         }
 412
 413         tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
 414         tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
 415
 416         writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 417 }
 418
 419 static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
 420 {
 421         u32 dsi_tmp_buf_bpp;
 422         u32 tmp_reg;
 423
 424         switch (dsi->format) {
 425         case MIPI_DSI_FMT_RGB888:
 426                 tmp_reg = PACKED_PS_24BIT_RGB888;
 427                 dsi_tmp_buf_bpp = 3;
 428                 break;
 429         case MIPI_DSI_FMT_RGB666:
 430                 tmp_reg = LOOSELY_PS_18BIT_RGB666;
 431                 dsi_tmp_buf_bpp = 3;
 432                 break;
 433         case MIPI_DSI_FMT_RGB666_PACKED:
 434                 tmp_reg = PACKED_PS_18BIT_RGB666;
 435                 dsi_tmp_buf_bpp = 3;
 436                 break;
 437         case MIPI_DSI_FMT_RGB565:
 438                 tmp_reg = PACKED_PS_16BIT_RGB565;
 439                 dsi_tmp_buf_bpp = 2;
 440                 break;
 441         default:
 442                 tmp_reg = PACKED_PS_24BIT_RGB888;
 443                 dsi_tmp_buf_bpp = 3;
 444                 break;
 445         }
 446
 447         tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
 448         writel(tmp_reg, dsi->regs + DSI_PSCTRL);
 449 }
 450
 451 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 452 {
 453         u32 horizontal_sync_active_byte;
 454         u32 horizontal_backporch_byte;
 455         u32 horizontal_frontporch_byte;
 456         u32 dsi_tmp_buf_bpp, data_phy_cycles;
 457         struct mtk_phy_timing *timing = &dsi->phy_timing;
 458
 459         struct videomode *vm = &dsi->vm;
 460
 461         if (dsi->format == MIPI_DSI_FMT_RGB565)
 462                 dsi_tmp_buf_bpp = 2;
 463         else
 464                 dsi_tmp_buf_bpp = 3;
 465
 466         writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
 467         writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
 468         writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
 469         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 470
 471         if (dsi->driver_data->has_size_ctl)
 472                 writel(vm->vactive << 16 | vm->hactive,
 473                        dsi->regs + DSI_SIZE_CON);
 474
 475         horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 476
 477         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 478                 horizontal_backporch_byte =
 479                         (vm->hback_porch * dsi_tmp_buf_bpp - 10);
 480         else
 481                 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
 482                         dsi_tmp_buf_bpp - 10);
 483
 484         data_phy_cycles = timing->lpx + timing->da_hs_prepare +
 485                                   timing->da_hs_zero + timing->da_hs_exit + 2;
 486
 487         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 488                 if (vm->hfront_porch * dsi_tmp_buf_bpp >
 489                     data_phy_cycles * dsi->lanes + 18) {
 490                         horizontal_frontporch_byte = vm->hfront_porch *
 491                                                      dsi_tmp_buf_bpp -
 492                                                      data_phy_cycles *
 493                                                      dsi->lanes - 18;
 494                 } else {
 495                         DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
 496                         horizontal_frontporch_byte = vm->hfront_porch *
 497                                                      dsi_tmp_buf_bpp;
 498                 }
 499         } else {
 500                 if (vm->hfront_porch * dsi_tmp_buf_bpp >
 501                     data_phy_cycles * dsi->lanes + 12) {
 502                         horizontal_frontporch_byte = vm->hfront_porch *
 503                                                      dsi_tmp_buf_bpp -
 504                                                      data_phy_cycles *
 505                                                      dsi->lanes - 12;
 506                 } else {
 507                         DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
 508                         horizontal_frontporch_byte = vm->hfront_porch *
 509                                                      dsi_tmp_buf_bpp;
 510                 }
 511         }
 512
 513         writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 514         writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 515         writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
 516
 517         mtk_dsi_ps_control(dsi);
 518 }
 519
 520 static void mtk_dsi_start(struct mtk_dsi *dsi)
 521 {
 522         writel(0, dsi->regs + DSI_START);
 523         writel(1, dsi->regs + DSI_START);
 524 }
 525
 526 static void mtk_dsi_stop(struct mtk_dsi *dsi)
 527 {
 528         writel(0, dsi->regs + DSI_START);
 529 }
 530
 531 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
 532 {
 533         writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
 534 }
 535
 536 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 537 {
 538         u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 539
 540         writel(inten, dsi->regs + DSI_INTEN);
 541 }
 542
 543 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 544 {
 545         dsi->irq_data |= irq_bit;
 546 }
 547
 548 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 549 {
 550         dsi->irq_data &= ~irq_bit;
 551 }
 552
 553 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 554                                      unsigned int timeout)
 555 {
 556         s32 ret = 0;
 557         unsigned long jiffies = msecs_to_jiffies(timeout);
 558
 559         ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
 560                                                dsi->irq_data & irq_flag,
 561                                                jiffies);
 562         if (ret == 0) {
 563                 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
 564
 565                 mtk_dsi_enable(dsi);
 566                 mtk_dsi_reset_engine(dsi);
 567         }
 568
 569         return ret;
 570 }
 571
 572 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
 573 {
 574         struct mtk_dsi *dsi = dev_id;
 575         u32 status, tmp;
 576         u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 577
 578         status = readl(dsi->regs + DSI_INTSTA) & flag;
 579
 580         if (status) {
 581                 do {
 582                         mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
 583                         tmp = readl(dsi->regs + DSI_INTSTA);
 584                 } while (tmp & DSI_BUSY);
 585
 586                 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
 587                 mtk_dsi_irq_data_set(dsi, status);
 588                 wake_up_interruptible(&dsi->irq_wait_queue);
 589         }
 590
 591         return IRQ_HANDLED;
 592 }
 593
 594 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
 595 {
 596         mtk_dsi_irq_data_clear(dsi, irq_flag);
 597         mtk_dsi_set_cmd_mode(dsi);
 598
 599         if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
 600                 DRM_ERROR("failed to switch cmd mode\n");
 601                 return -ETIME;
 602         } else {
 603                 return 0;
 604         }
 605 }
 606
 607 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 608 {
 609         struct device *dev = dsi->host.dev;
 610         int ret;
 611         u32 bit_per_pixel;
 612
 613         if (++dsi->refcount != 1)
 614                 return 0;
 615
 616         switch (dsi->format) {
 617         case MIPI_DSI_FMT_RGB565:
 618                 bit_per_pixel = 16;
 619                 break;
 620         case MIPI_DSI_FMT_RGB666_PACKED:
 621                 bit_per_pixel = 18;
 622                 break;
 623         case MIPI_DSI_FMT_RGB666:
 624         case MIPI_DSI_FMT_RGB888:
 625         default:
 626                 bit_per_pixel = 24;
 627                 break;
 628         }
 629
 630         dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
 631                                           dsi->lanes);
 632
 633         ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
 634         if (ret < 0) {
 635                 dev_err(dev, "Failed to set data rate: %d\n", ret);
 636                 goto err_refcount;
 637         }
 638
 639         phy_power_on(dsi->phy);
 640
 641         ret = clk_prepare_enable(dsi->engine_clk);
 642         if (ret < 0) {
 643                 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
 644                 goto err_phy_power_off;
 645         }
 646
 647         ret = clk_prepare_enable(dsi->digital_clk);
 648         if (ret < 0) {
 649                 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
 650                 goto err_disable_engine_clk;
 651         }
 652
 653         mtk_dsi_enable(dsi);
 654
 655         if (dsi->driver_data->has_shadow_ctl)
 656                 writel(FORCE_COMMIT | BYPASS_SHADOW,
 657                        dsi->regs + DSI_SHADOW_DEBUG);
 658
 659         mtk_dsi_reset_engine(dsi);
 660         mtk_dsi_phy_timconfig(dsi);
 661
 662         mtk_dsi_rxtx_control(dsi);
 663         usleep_range(30, 100);
 664         mtk_dsi_reset_dphy(dsi);
 665         mtk_dsi_ps_control_vact(dsi);
 666         mtk_dsi_set_vm_cmd(dsi);
 667         mtk_dsi_config_vdo_timing(dsi);
 668         mtk_dsi_set_interrupt_enable(dsi);
 669
 670         mtk_dsi_clk_ulp_mode_leave(dsi);
 671         mtk_dsi_lane0_ulp_mode_leave(dsi);
 672         mtk_dsi_clk_hs_mode(dsi, 0);
 673
 674         if (dsi->panel) {
 675                 if (drm_panel_prepare(dsi->panel)) {
 676                         DRM_ERROR("failed to prepare the panel\n");
 677                         goto err_disable_digital_clk;
 678                 }
 679         }
 680
 681         return 0;
 682 err_disable_digital_clk:
 683         clk_disable_unprepare(dsi->digital_clk);
 684 err_disable_engine_clk:
 685         clk_disable_unprepare(dsi->engine_clk);
 686 err_phy_power_off:
 687         phy_power_off(dsi->phy);
 688 err_refcount:
 689         dsi->refcount--;
 690         return ret;
 691 }
 692
 693 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 694 {
 695         if (WARN_ON(dsi->refcount == 0))
 696                 return;
 697
 698         if (--dsi->refcount != 0)
 699                 return;
 700
 701         /*
 702          * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
 703          * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
 704          * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
 705          * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
 706          * after dsi is fully set.
 707          */
 708         mtk_dsi_stop(dsi);
 709
 710         if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
 711                 if (dsi->panel) {
 712                         if (drm_panel_unprepare(dsi->panel)) {
 713                                 DRM_ERROR("failed to unprepare the panel\n");
 714                                 return;
 715                         }
 716                 }
 717         }
 718
 719         mtk_dsi_reset_engine(dsi);
 720         mtk_dsi_lane0_ulp_mode_enter(dsi);
 721         mtk_dsi_clk_ulp_mode_enter(dsi);
 722
 723         mtk_dsi_disable(dsi);
 724
 725         clk_disable_unprepare(dsi->engine_clk);
 726         clk_disable_unprepare(dsi->digital_clk);
 727
 728         phy_power_off(dsi->phy);
 729 }
 730
 731 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 732 {
 733         int ret;
 734
 735         if (dsi->enabled)
 736                 return;
 737
 738         ret = mtk_dsi_poweron(dsi);
 739         if (ret < 0) {
 740                 DRM_ERROR("failed to power on dsi\n");
 741                 return;
 742         }
 743
 744         mtk_dsi_set_mode(dsi);
 745         mtk_dsi_clk_hs_mode(dsi, 1);
 746
 747         mtk_dsi_start(dsi);
 748
 749         if (dsi->panel) {
 750                 if (drm_panel_enable(dsi->panel)) {
 751                         DRM_ERROR("failed to enable the panel\n");
 752                         goto err_dsi_power_off;
 753                 }
 754         }
 755
 756         dsi->enabled = true;
 757
 758         return;
 759 err_dsi_power_off:
 760         mtk_dsi_stop(dsi);
 761         mtk_dsi_poweroff(dsi);
 762 }
 763
 764 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 765 {
 766         if (!dsi->enabled)
 767                 return;
 768
 769         if (dsi->panel) {
 770                 if (drm_panel_disable(dsi->panel)) {
 771                         DRM_ERROR("failed to disable the panel\n");
 772                         return;
 773                 }
 774         }
 775
 776         mtk_dsi_poweroff(dsi);
 777
 778         dsi->enabled = false;
 779 }
 780
 781 static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
 782 {
 783         drm_encoder_cleanup(encoder);
 784 }
 785
 786 static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
 787         .destroy = mtk_dsi_encoder_destroy,
 788 };
 789
 790 static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 791                                        const struct drm_display_mode *mode,
 792                                        struct drm_display_mode *adjusted_mode)
 793 {
 794         return true;
 795 }
 796
 797 static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
 798                                      struct drm_display_mode *mode,
 799                                      struct drm_display_mode *adjusted)
 800 {
 801         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 802
 803         drm_display_mode_to_videomode(adjusted, &dsi->vm);
 804 }
 805
 806 static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
 807 {
 808         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 809
 810         mtk_output_dsi_disable(dsi);
 811 }
 812
 813 static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
 814 {
 815         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 816
 817         mtk_output_dsi_enable(dsi);
 818 }
 819
 820 static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
 821 {
 822         struct mtk_dsi *dsi = connector_to_dsi(connector);
 823
 824         return drm_panel_get_modes(dsi->panel, connector);
 825 }
 826
 827 static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
 828         .mode_fixup = mtk_dsi_encoder_mode_fixup,
 829         .mode_set = mtk_dsi_encoder_mode_set,
 830         .disable = mtk_dsi_encoder_disable,
 831         .enable = mtk_dsi_encoder_enable,
 832 };
 833
 834 static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
 835         .fill_modes = drm_helper_probe_single_connector_modes,
 836         .destroy = drm_connector_cleanup,
 837         .reset = drm_atomic_helper_connector_reset,
 838         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 839         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 840 };
 841
 842 static const struct drm_connector_helper_funcs
 843         mtk_dsi_connector_helper_funcs = {
 844         .get_modes = mtk_dsi_connector_get_modes,
 845 };
 846
 847 static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
 848 {
 849         int ret;
 850
 851         ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
 852                                  DRM_MODE_CONNECTOR_DSI);
 853         if (ret) {
 854                 DRM_ERROR("Failed to connector init to drm\n");
 855                 return ret;
 856         }
 857
 858         drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
 859
 860         dsi->conn.dpms = DRM_MODE_DPMS_OFF;
 861         drm_connector_attach_encoder(&dsi->conn, &dsi->encoder);
 862
 863         if (dsi->panel) {
 864                 ret = drm_panel_attach(dsi->panel, &dsi->conn);
 865                 if (ret) {
 866                         DRM_ERROR("Failed to attach panel to drm\n");
 867                         goto err_connector_cleanup;
 868                 }
 869         }
 870
 871         return 0;
 872
 873 err_connector_cleanup:
 874         drm_connector_cleanup(&dsi->conn);
 875         return ret;
 876 }
 877
 878 static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
 879 {
 880         int ret;
 881
 882         ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
 883                                DRM_MODE_ENCODER_DSI, NULL);
 884         if (ret) {
 885                 DRM_ERROR("Failed to encoder init to drm\n");
 886                 return ret;
 887         }
 888         drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
 889
 890         /*
 891          * Currently display data paths are statically assigned to a crtc each.
 892          * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
 893          */
 894         dsi->encoder.possible_crtcs = 1;
 895
 896         /* If there's a bridge, attach to it and let it create the connector */
 897         if (dsi->bridge) {
 898                 ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
 899                 if (ret) {
 900                         DRM_ERROR("Failed to attach bridge to drm\n");
 901                         goto err_encoder_cleanup;
 902                 }
 903         } else {
 904                 /* Otherwise create our own connector and attach to a panel */
 905                 ret = mtk_dsi_create_connector(drm, dsi);
 906                 if (ret)
 907                         goto err_encoder_cleanup;
 908         }
 909
 910         return 0;
 911
 912 err_encoder_cleanup:
 913         drm_encoder_cleanup(&dsi->encoder);
 914         return ret;
 915 }
 916
 917 static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
 918 {
 919         drm_encoder_cleanup(&dsi->encoder);
 920         /* Skip connector cleanup if creation was delegated to the bridge */
 921         if (dsi->conn.dev)
 922                 drm_connector_cleanup(&dsi->conn);
 923         if (dsi->panel)
 924                 drm_panel_detach(dsi->panel);
 925 }
 926
 927 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
 928 {
 929         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 930
 931         mtk_dsi_poweron(dsi);
 932 }
 933
 934 static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
 935 {
 936         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 937
 938         mtk_dsi_poweroff(dsi);
 939 }
 940
 941 static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
 942         .start = mtk_dsi_ddp_start,
 943         .stop = mtk_dsi_ddp_stop,
 944 };
 945
 946 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 947                                struct mipi_dsi_device *device)
 948 {
 949         struct mtk_dsi *dsi = host_to_dsi(host);
 950
 951         dsi->lanes = device->lanes;
 952         dsi->format = device->format;
 953         dsi->mode_flags = device->mode_flags;
 954
 955         if (dsi->conn.dev)
 956                 drm_helper_hpd_irq_event(dsi->conn.dev);
 957
 958         return 0;
 959 }
 960
 961 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 962                                struct mipi_dsi_device *device)
 963 {
 964         struct mtk_dsi *dsi = host_to_dsi(host);
 965
 966         if (dsi->conn.dev)
 967                 drm_helper_hpd_irq_event(dsi->conn.dev);
 968
 969         return 0;
 970 }
 971
 972 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
 973 {
 974         int ret;
 975         u32 val;
 976
 977         ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
 978                                  4, 2000000);
 979         if (ret) {
 980                 DRM_WARN("polling dsi wait not busy timeout!\n");
 981
 982                 mtk_dsi_enable(dsi);
 983                 mtk_dsi_reset_engine(dsi);
 984         }
 985 }
 986
 987 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
 988 {
 989         switch (type) {
 990         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
 991         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
 992                 return 1;
 993         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
 994         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
 995                 return 2;
 996         case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
 997         case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
 998                 return read_data[1] + read_data[2] * 16;
 999         case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1000                 DRM_INFO("type is 0x02, try again\n");
1001                 break;
1002         default:
1003                 DRM_INFO("type(0x%x) not recognized\n", type);
1004                 break;
1005         }
1006
1007         return 0;
1008 }
1009
1010 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
1011 {
1012         const char *tx_buf = msg->tx_buf;
1013         u8 config, cmdq_size, cmdq_off, type = msg->type;
1014         u32 reg_val, cmdq_mask, i;
1015         u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
1016
1017         if (MTK_DSI_HOST_IS_READ(type))
1018                 config = BTA;
1019         else
1020                 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
1021
1022         if (msg->tx_len > 2) {
1023                 cmdq_size = 1 + (msg->tx_len + 3) / 4;
1024                 cmdq_off = 4;
1025                 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
1026                 reg_val = (msg->tx_len << 16) | (type << 8) | config;
1027         } else {
1028                 cmdq_size = 1;
1029                 cmdq_off = 2;
1030                 cmdq_mask = CONFIG | DATA_ID;
1031                 reg_val = (type << 8) | config;
1032         }
1033
1034         for (i = 0; i < msg->tx_len; i++)
1035                 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
1036                              (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
1037                              tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
1038
1039         mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
1040         mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
1041 }
1042
1043 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1044                                      const struct mipi_dsi_msg *msg, u8 flag)
1045 {
1046         mtk_dsi_wait_for_idle(dsi);
1047         mtk_dsi_irq_data_clear(dsi, flag);
1048         mtk_dsi_cmdq(dsi, msg);
1049         mtk_dsi_start(dsi);
1050
1051         if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
1052                 return -ETIME;
1053         else
1054                 return 0;
1055 }
1056
1057 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
1058                                      const struct mipi_dsi_msg *msg)
1059 {
1060         struct mtk_dsi *dsi = host_to_dsi(host);
1061         u32 recv_cnt, i;
1062         u8 read_data[16];
1063         void *src_addr;
1064         u8 irq_flag = CMD_DONE_INT_FLAG;
1065
1066         if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
1067                 DRM_ERROR("dsi engine is not command mode\n");
1068                 return -EINVAL;
1069         }
1070
1071         if (MTK_DSI_HOST_IS_READ(msg->type))
1072                 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1073
1074         if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
1075                 return -ETIME;
1076
1077         if (!MTK_DSI_HOST_IS_READ(msg->type))
1078                 return 0;
1079
1080         if (!msg->rx_buf) {
1081                 DRM_ERROR("dsi receive buffer size may be NULL\n");
1082                 return -EINVAL;
1083         }
1084
1085         for (i = 0; i < 16; i++)
1086                 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1087
1088         recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1089
1090         if (recv_cnt > 2)
1091                 src_addr = &read_data[4];
1092         else
1093                 src_addr = &read_data[1];
1094
1095         if (recv_cnt > 10)
1096                 recv_cnt = 10;
1097
1098         if (recv_cnt > msg->rx_len)
1099                 recv_cnt = msg->rx_len;
1100
1101         if (recv_cnt)
1102                 memcpy(msg->rx_buf, src_addr, recv_cnt);
1103
1104         DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1105                  recv_cnt, *((u8 *)(msg->tx_buf)));
1106
1107         return recv_cnt;
1108 }
1109
1110 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1111         .attach = mtk_dsi_host_attach,
1112         .detach = mtk_dsi_host_detach,
1113         .transfer = mtk_dsi_host_transfer,
1114 };
1115
1116 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
1117 {
1118         int ret;
1119         struct drm_device *drm = data;
1120         struct mtk_dsi *dsi = dev_get_drvdata(dev);
1121
1122         ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1123         if (ret < 0) {
1124                 dev_err(dev, "Failed to register component %pOF: %d\n",
1125                         dev->of_node, ret);
1126                 return ret;
1127         }
1128
1129         ret = mtk_dsi_create_conn_enc(drm, dsi);
1130         if (ret) {
1131                 DRM_ERROR("Encoder create failed with %d\n", ret);
1132                 goto err_unregister;
1133         }
1134
1135         return 0;
1136
1137 err_unregister:
1138         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1139         return ret;
1140 }
1141
1142 static void mtk_dsi_unbind(struct device *dev, struct device *master,
1143                            void *data)
1144 {
1145         struct drm_device *drm = data;
1146         struct mtk_dsi *dsi = dev_get_drvdata(dev);
1147
1148         mtk_dsi_destroy_conn_enc(dsi);
1149         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1150 }
1151
1152 static const struct component_ops mtk_dsi_component_ops = {
1153         .bind = mtk_dsi_bind,
1154         .unbind = mtk_dsi_unbind,
1155 };
1156
1157 static int mtk_dsi_probe(struct platform_device *pdev)
1158 {
1159         struct mtk_dsi *dsi;
1160         struct device *dev = &pdev->dev;
1161         struct resource *regs;
1162         int irq_num;
1163         int comp_id;
1164         int ret;
1165
1166         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1167         if (!dsi)
1168                 return -ENOMEM;
1169
1170         dsi->host.ops = &mtk_dsi_ops;
1171         dsi->host.dev = dev;
1172         ret = mipi_dsi_host_register(&dsi->host);
1173         if (ret < 0) {
1174                 dev_err(dev, "failed to register DSI host: %d\n", ret);
1175                 return ret;
1176         }
1177
1178         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1179                                           &dsi->panel, &dsi->bridge);
1180         if (ret)
1181                 goto err_unregister_host;
1182
1183         dsi->driver_data = of_device_get_match_data(dev);
1184
1185         dsi->engine_clk = devm_clk_get(dev, "engine");
1186         if (IS_ERR(dsi->engine_clk)) {
1187                 ret = PTR_ERR(dsi->engine_clk);
1188                 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1189                 goto err_unregister_host;
1190         }
1191
1192         dsi->digital_clk = devm_clk_get(dev, "digital");
1193         if (IS_ERR(dsi->digital_clk)) {
1194                 ret = PTR_ERR(dsi->digital_clk);
1195                 dev_err(dev, "Failed to get digital clock: %d\n", ret);
1196                 goto err_unregister_host;
1197         }
1198
1199         dsi->hs_clk = devm_clk_get(dev, "hs");
1200         if (IS_ERR(dsi->hs_clk)) {
1201                 ret = PTR_ERR(dsi->hs_clk);
1202                 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1203                 goto err_unregister_host;
1204         }
1205
1206         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207         dsi->regs = devm_ioremap_resource(dev, regs);
1208         if (IS_ERR(dsi->regs)) {
1209                 ret = PTR_ERR(dsi->regs);
1210                 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1211                 goto err_unregister_host;
1212         }
1213
1214         dsi->phy = devm_phy_get(dev, "dphy");
1215         if (IS_ERR(dsi->phy)) {
1216                 ret = PTR_ERR(dsi->phy);
1217                 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1218                 goto err_unregister_host;
1219         }
1220
1221         comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1222         if (comp_id < 0) {
1223                 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1224                 ret = comp_id;
1225                 goto err_unregister_host;
1226         }
1227
1228         ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1229                                 &mtk_dsi_funcs);
1230         if (ret) {
1231                 dev_err(dev, "Failed to initialize component: %d\n", ret);
1232                 goto err_unregister_host;
1233         }
1234
1235         irq_num = platform_get_irq(pdev, 0);
1236         if (irq_num < 0) {
1237                 dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num);
1238                 ret = irq_num;
1239                 goto err_unregister_host;
1240         }
1241
1242         irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1243         ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1244                                IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1245         if (ret) {
1246                 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1247                 goto err_unregister_host;
1248         }
1249
1250         init_waitqueue_head(&dsi->irq_wait_queue);
1251
1252         platform_set_drvdata(pdev, dsi);
1253
1254         ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
1255         if (ret) {
1256                 dev_err(&pdev->dev, "failed to add component: %d\n", ret);
1257                 goto err_unregister_host;
1258         }
1259
1260         return 0;
1261
1262 err_unregister_host:
1263         mipi_dsi_host_unregister(&dsi->host);
1264         return ret;
1265 }
1266
1267 static int mtk_dsi_remove(struct platform_device *pdev)
1268 {
1269         struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1270
1271         mtk_output_dsi_disable(dsi);
1272         component_del(&pdev->dev, &mtk_dsi_component_ops);
1273         mipi_dsi_host_unregister(&dsi->host);
1274
1275         return 0;
1276 }
1277
1278 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1279         .reg_cmdq_off = 0x200,
1280 };
1281
1282 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1283         .reg_cmdq_off = 0x180,
1284 };
1285
1286 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1287         .reg_cmdq_off = 0x200,
1288         .has_shadow_ctl = true,
1289         .has_size_ctl = true,
1290 };
1291
1292 static const struct of_device_id mtk_dsi_of_match[] = {
1293         { .compatible = "mediatek,mt2701-dsi",
1294           .data = &mt2701_dsi_driver_data },
1295         { .compatible = "mediatek,mt8173-dsi",
1296           .data = &mt8173_dsi_driver_data },
1297         { .compatible = "mediatek,mt8183-dsi",
1298           .data = &mt8183_dsi_driver_data },
1299         { },
1300 };
1301
1302 struct platform_driver mtk_dsi_driver = {
1303         .probe = mtk_dsi_probe,
1304         .remove = mtk_dsi_remove,
1305         .driver = {
1306                 .name = "mtk-dsi",
1307                 .of_match_table = mtk_dsi_of_match,
1308         },
1309 };