1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
8 #include <linux/component.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/media-bus-format.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/soc/mediatek/mtk-mmsys.h>
18 #include <linux/types.h>
20 #include <video/videomode.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_bridge.h>
24 #include <drm/drm_bridge_connector.h>
25 #include <drm/drm_crtc.h>
26 #include <drm/drm_edid.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_simple_kms_helper.h>
30 #include "mtk_disp_drv.h"
31 #include "mtk_dpi_regs.h"
32 #include "mtk_drm_ddp_comp.h"
33 #include "mtk_drm_drv.h"
35 enum mtk_dpi_out_bit_num {
36 MTK_DPI_OUT_BIT_NUM_8BITS,
37 MTK_DPI_OUT_BIT_NUM_10BITS,
38 MTK_DPI_OUT_BIT_NUM_12BITS,
39 MTK_DPI_OUT_BIT_NUM_16BITS
42 enum mtk_dpi_out_yc_map {
43 MTK_DPI_OUT_YC_MAP_RGB,
44 MTK_DPI_OUT_YC_MAP_CYCY,
45 MTK_DPI_OUT_YC_MAP_YCYC,
46 MTK_DPI_OUT_YC_MAP_CY,
50 enum mtk_dpi_out_channel_swap {
51 MTK_DPI_OUT_CHANNEL_SWAP_RGB,
52 MTK_DPI_OUT_CHANNEL_SWAP_GBR,
53 MTK_DPI_OUT_CHANNEL_SWAP_BRG,
54 MTK_DPI_OUT_CHANNEL_SWAP_RBG,
55 MTK_DPI_OUT_CHANNEL_SWAP_GRB,
56 MTK_DPI_OUT_CHANNEL_SWAP_BGR
59 enum mtk_dpi_out_color_format {
60 MTK_DPI_COLOR_FORMAT_RGB,
61 MTK_DPI_COLOR_FORMAT_YCBCR_422
65 struct drm_encoder encoder;
66 struct drm_bridge bridge;
67 struct drm_bridge *next_bridge;
68 struct drm_connector *connector;
71 struct device *mmsys_dev;
72 struct clk *engine_clk;
73 struct clk *pixel_clk;
76 struct drm_display_mode mode;
77 const struct mtk_dpi_conf *conf;
78 enum mtk_dpi_out_color_format color_format;
79 enum mtk_dpi_out_yc_map yc_map;
80 enum mtk_dpi_out_bit_num bit_num;
81 enum mtk_dpi_out_channel_swap channel_swap;
82 struct pinctrl *pinctrl;
83 struct pinctrl_state *pins_gpio;
84 struct pinctrl_state *pins_dpi;
89 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
91 return container_of(b, struct mtk_dpi, bridge);
94 enum mtk_dpi_polarity {
95 MTK_DPI_POLARITY_RISING,
96 MTK_DPI_POLARITY_FALLING,
99 struct mtk_dpi_polarities {
100 enum mtk_dpi_polarity de_pol;
101 enum mtk_dpi_polarity ck_pol;
102 enum mtk_dpi_polarity hsync_pol;
103 enum mtk_dpi_polarity vsync_pol;
106 struct mtk_dpi_sync_param {
110 bool shift_half_line;
113 struct mtk_dpi_yc_limit {
121 * struct mtk_dpi_conf - Configuration of mediatek dpi.
122 * @cal_factor: Callback function to calculate factor value.
123 * @reg_h_fre_con: Register address of frequency control.
124 * @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
125 * @edge_sel_en: Enable of edge selection.
126 * @output_fmts: Array of supported output formats.
127 * @num_output_fmts: Quantity of supported output formats.
128 * @is_ck_de_pol: Support CK/DE polarity.
129 * @swap_input_support: Support input swap function.
130 * @support_direct_pin: IP supports direct connection to dpi panels.
131 * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
132 * config to enable this feature.
133 * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
135 * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
136 * @channel_swap_shift: Shift value of channel swap.
137 * @yuv422_en_bit: Enable bit of yuv422.
138 * @csc_enable_bit: Enable bit of CSC.
139 * @pixels_per_iter: Quantity of transferred pixels per iteration.
140 * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
142 struct mtk_dpi_conf {
143 unsigned int (*cal_factor)(int clock);
147 const u32 *output_fmts;
150 bool swap_input_support;
151 bool support_direct_pin;
155 u32 channel_swap_shift;
159 bool edge_cfg_in_mmsys;
162 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
164 u32 tmp = readl(dpi->regs + offset) & ~mask;
167 writel(tmp, dpi->regs + offset);
170 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
172 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
175 static void mtk_dpi_enable(struct mtk_dpi *dpi)
177 mtk_dpi_mask(dpi, DPI_EN, EN, EN);
180 static void mtk_dpi_disable(struct mtk_dpi *dpi)
182 mtk_dpi_mask(dpi, DPI_EN, 0, EN);
185 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
186 struct mtk_dpi_sync_param *sync)
188 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW,
189 dpi->conf->dimension_mask << HPW);
190 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP,
191 dpi->conf->dimension_mask << HBP);
192 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
193 dpi->conf->dimension_mask << HFP);
196 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
197 struct mtk_dpi_sync_param *sync,
198 u32 width_addr, u32 porch_addr)
200 mtk_dpi_mask(dpi, width_addr,
201 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
202 VSYNC_HALF_LINE_MASK);
203 mtk_dpi_mask(dpi, width_addr,
204 sync->sync_width << VSYNC_WIDTH_SHIFT,
205 dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT);
206 mtk_dpi_mask(dpi, porch_addr,
207 sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
208 dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT);
209 mtk_dpi_mask(dpi, porch_addr,
210 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
211 dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT);
214 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
215 struct mtk_dpi_sync_param *sync)
217 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
220 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
221 struct mtk_dpi_sync_param *sync)
223 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
224 DPI_TGEN_VPORCH_LEVEN);
227 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi,
228 struct mtk_dpi_sync_param *sync)
230 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD,
231 DPI_TGEN_VPORCH_RODD);
234 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi,
235 struct mtk_dpi_sync_param *sync)
237 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN,
238 DPI_TGEN_VPORCH_REVEN);
241 static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
242 struct mtk_dpi_polarities *dpi_pol)
247 mask = HSYNC_POL | VSYNC_POL;
248 pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
249 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
250 if (dpi->conf->is_ck_de_pol) {
251 mask |= CK_POL | DE_POL;
252 pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ?
254 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ?
258 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask);
261 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
263 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
266 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
268 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN);
271 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
273 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE,
274 dpi->conf->hvsize_mask << HSIZE);
275 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE,
276 dpi->conf->hvsize_mask << VSIZE);
279 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi)
281 struct mtk_dpi_yc_limit limit;
283 if (drm_default_rgb_quant_range(&dpi->mode) ==
284 HDMI_QUANTIZATION_RANGE_LIMITED) {
285 limit.y_bottom = 0x10;
287 limit.c_bottom = 0x10;
296 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT,
298 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP,
300 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT,
302 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP,
306 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi,
307 enum mtk_dpi_out_bit_num num)
312 case MTK_DPI_OUT_BIT_NUM_8BITS:
315 case MTK_DPI_OUT_BIT_NUM_10BITS:
318 case MTK_DPI_OUT_BIT_NUM_12BITS:
321 case MTK_DPI_OUT_BIT_NUM_16BITS:
328 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT,
332 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi,
333 enum mtk_dpi_out_yc_map map)
338 case MTK_DPI_OUT_YC_MAP_RGB:
341 case MTK_DPI_OUT_YC_MAP_CYCY:
344 case MTK_DPI_OUT_YC_MAP_YCYC:
347 case MTK_DPI_OUT_YC_MAP_CY:
350 case MTK_DPI_OUT_YC_MAP_YC:
358 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK);
361 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
362 enum mtk_dpi_out_channel_swap swap)
367 case MTK_DPI_OUT_CHANNEL_SWAP_RGB:
370 case MTK_DPI_OUT_CHANNEL_SWAP_GBR:
373 case MTK_DPI_OUT_CHANNEL_SWAP_BRG:
376 case MTK_DPI_OUT_CHANNEL_SWAP_RBG:
379 case MTK_DPI_OUT_CHANNEL_SWAP_GRB:
382 case MTK_DPI_OUT_CHANNEL_SWAP_BGR:
390 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
391 val << dpi->conf->channel_swap_shift,
392 CH_SWAP_MASK << dpi->conf->channel_swap_shift);
395 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
397 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0,
398 dpi->conf->yuv422_en_bit);
401 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
403 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0,
404 dpi->conf->csc_enable_bit);
407 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
409 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP);
412 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
414 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
417 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
419 if (dpi->conf->edge_sel_en)
420 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
423 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
424 enum mtk_dpi_out_color_format format)
426 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
428 if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) {
429 mtk_dpi_config_yuv422_enable(dpi, true);
430 mtk_dpi_config_csc_enable(dpi, true);
433 * If height is smaller than 720, we need to use RGB_TO_BT601
434 * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG.
436 mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ?
437 MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG,
438 INT_MATRIX_SEL_MASK);
440 mtk_dpi_config_yuv422_enable(dpi, false);
441 mtk_dpi_config_csc_enable(dpi, false);
442 if (dpi->conf->swap_input_support)
443 mtk_dpi_config_swap_input(dpi, false);
447 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
449 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
450 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
451 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
452 DDR_EN | DDR_4PHASE);
453 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
454 dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ?
455 EDGE_SEL : 0, EDGE_SEL);
456 if (dpi->conf->edge_cfg_in_mmsys)
457 mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_DDR_CON);
459 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
460 if (dpi->conf->edge_cfg_in_mmsys)
461 mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_SDR_CON);
465 static void mtk_dpi_power_off(struct mtk_dpi *dpi)
467 if (WARN_ON(dpi->refcount == 0))
470 if (--dpi->refcount != 0)
473 mtk_dpi_disable(dpi);
474 clk_disable_unprepare(dpi->pixel_clk);
475 clk_disable_unprepare(dpi->engine_clk);
478 static int mtk_dpi_power_on(struct mtk_dpi *dpi)
482 if (++dpi->refcount != 1)
485 ret = clk_prepare_enable(dpi->engine_clk);
487 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
491 ret = clk_prepare_enable(dpi->pixel_clk);
493 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
500 clk_disable_unprepare(dpi->engine_clk);
506 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
507 struct drm_display_mode *mode)
509 struct mtk_dpi_polarities dpi_pol;
510 struct mtk_dpi_sync_param hsync;
511 struct mtk_dpi_sync_param vsync_lodd = { 0 };
512 struct mtk_dpi_sync_param vsync_leven = { 0 };
513 struct mtk_dpi_sync_param vsync_rodd = { 0 };
514 struct mtk_dpi_sync_param vsync_reven = { 0 };
515 struct videomode vm = { 0 };
516 unsigned long pll_rate;
519 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
520 factor = dpi->conf->cal_factor(mode->clock);
521 drm_display_mode_to_videomode(mode, &vm);
522 pll_rate = vm.pixelclock * factor;
524 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
525 pll_rate, vm.pixelclock);
527 clk_set_rate(dpi->tvd_clk, pll_rate);
528 pll_rate = clk_get_rate(dpi->tvd_clk);
531 * Depending on the IP version, we may output a different amount of
532 * pixels for each iteration: divide the clock by this number and
533 * adjust the display porches accordingly.
535 vm.pixelclock = pll_rate / factor;
536 vm.pixelclock /= dpi->conf->pixels_per_iter;
538 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
539 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
540 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
542 clk_set_rate(dpi->pixel_clk, vm.pixelclock);
545 vm.pixelclock = clk_get_rate(dpi->pixel_clk);
547 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
548 pll_rate, vm.pixelclock);
550 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
551 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
552 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
553 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
554 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
555 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
558 * Depending on the IP version, we may output a different amount of
559 * pixels for each iteration: divide the clock by this number and
560 * adjust the display porches accordingly.
562 hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter;
563 hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter;
564 hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter;
566 hsync.shift_half_line = false;
567 vsync_lodd.sync_width = vm.vsync_len;
568 vsync_lodd.back_porch = vm.vback_porch;
569 vsync_lodd.front_porch = vm.vfront_porch;
570 vsync_lodd.shift_half_line = false;
572 if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
573 mode->flags & DRM_MODE_FLAG_3D_MASK) {
574 vsync_leven = vsync_lodd;
575 vsync_rodd = vsync_lodd;
576 vsync_reven = vsync_lodd;
577 vsync_leven.shift_half_line = true;
578 vsync_reven.shift_half_line = true;
579 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
580 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) {
581 vsync_leven = vsync_lodd;
582 vsync_leven.shift_half_line = true;
583 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) &&
584 mode->flags & DRM_MODE_FLAG_3D_MASK) {
585 vsync_rodd = vsync_lodd;
587 mtk_dpi_sw_reset(dpi, true);
588 mtk_dpi_config_pol(dpi, &dpi_pol);
590 mtk_dpi_config_hsync(dpi, &hsync);
591 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
592 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
593 mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
594 mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
596 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
597 mtk_dpi_config_interface(dpi, !!(vm.flags &
598 DISPLAY_FLAGS_INTERLACED));
599 if (vm.flags & DISPLAY_FLAGS_INTERLACED)
600 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1);
602 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
604 mtk_dpi_config_channel_limit(dpi);
605 mtk_dpi_config_bit_num(dpi, dpi->bit_num);
606 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
607 mtk_dpi_config_color_format(dpi, dpi->color_format);
608 if (dpi->conf->support_direct_pin) {
609 mtk_dpi_config_yc_map(dpi, dpi->yc_map);
610 mtk_dpi_config_2n_h_fre(dpi);
611 mtk_dpi_dual_edge(dpi);
612 mtk_dpi_config_disable_edge(dpi);
614 if (dpi->conf->input_2pixel) {
615 mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
618 mtk_dpi_sw_reset(dpi, false);
623 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
624 struct drm_bridge_state *bridge_state,
625 struct drm_crtc_state *crtc_state,
626 struct drm_connector_state *conn_state,
627 unsigned int *num_output_fmts)
629 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
632 *num_output_fmts = 0;
634 if (!dpi->conf->output_fmts) {
635 dev_err(dpi->dev, "output_fmts should not be null\n");
639 output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts),
644 *num_output_fmts = dpi->conf->num_output_fmts;
646 memcpy(output_fmts, dpi->conf->output_fmts,
647 sizeof(*output_fmts) * dpi->conf->num_output_fmts);
652 static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
653 struct drm_bridge_state *bridge_state,
654 struct drm_crtc_state *crtc_state,
655 struct drm_connector_state *conn_state,
657 unsigned int *num_input_fmts)
663 input_fmts = kcalloc(1, sizeof(*input_fmts),
669 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
674 static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
675 struct drm_bridge_state *bridge_state,
676 struct drm_crtc_state *crtc_state,
677 struct drm_connector_state *conn_state)
679 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
680 unsigned int out_bus_format;
682 out_bus_format = bridge_state->output_bus_cfg.format;
684 if (out_bus_format == MEDIA_BUS_FMT_FIXED)
685 if (dpi->conf->num_output_fmts)
686 out_bus_format = dpi->conf->output_fmts[0];
688 dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
689 bridge_state->input_bus_cfg.format,
690 bridge_state->output_bus_cfg.format);
692 dpi->output_fmt = out_bus_format;
693 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
694 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
695 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
696 if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
697 dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422;
699 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
704 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
705 enum drm_bridge_attach_flags flags)
707 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
709 return drm_bridge_attach(bridge->encoder, dpi->next_bridge,
710 &dpi->bridge, flags);
713 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge,
714 const struct drm_display_mode *mode,
715 const struct drm_display_mode *adjusted_mode)
717 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
719 drm_mode_copy(&dpi->mode, adjusted_mode);
722 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge)
724 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
726 mtk_dpi_power_off(dpi);
728 if (dpi->pinctrl && dpi->pins_gpio)
729 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
732 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
734 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
736 if (dpi->pinctrl && dpi->pins_dpi)
737 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
739 mtk_dpi_power_on(dpi);
740 mtk_dpi_set_display_mode(dpi, &dpi->mode);
744 static enum drm_mode_status
745 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
746 const struct drm_display_info *info,
747 const struct drm_display_mode *mode)
749 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
751 if (mode->clock > dpi->conf->max_clock_khz)
752 return MODE_CLOCK_HIGH;
757 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
758 .attach = mtk_dpi_bridge_attach,
759 .mode_set = mtk_dpi_bridge_mode_set,
760 .mode_valid = mtk_dpi_bridge_mode_valid,
761 .disable = mtk_dpi_bridge_disable,
762 .enable = mtk_dpi_bridge_enable,
763 .atomic_check = mtk_dpi_bridge_atomic_check,
764 .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
765 .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
766 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
767 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
768 .atomic_reset = drm_atomic_helper_bridge_reset,
771 void mtk_dpi_start(struct device *dev)
773 struct mtk_dpi *dpi = dev_get_drvdata(dev);
775 mtk_dpi_power_on(dpi);
778 void mtk_dpi_stop(struct device *dev)
780 struct mtk_dpi *dpi = dev_get_drvdata(dev);
782 mtk_dpi_power_off(dpi);
785 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
787 struct mtk_dpi *dpi = dev_get_drvdata(dev);
788 struct drm_device *drm_dev = data;
789 struct mtk_drm_private *priv = drm_dev->dev_private;
792 dpi->mmsys_dev = priv->mmsys_dev;
793 ret = drm_simple_encoder_init(drm_dev, &dpi->encoder,
794 DRM_MODE_ENCODER_TMDS);
796 dev_err(dev, "Failed to initialize decoder: %d\n", ret);
800 dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev);
802 ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL,
803 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
807 dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder);
808 if (IS_ERR(dpi->connector)) {
809 dev_err(dev, "Unable to create bridge connector\n");
810 ret = PTR_ERR(dpi->connector);
813 drm_connector_attach_encoder(dpi->connector, &dpi->encoder);
818 drm_encoder_cleanup(&dpi->encoder);
822 static void mtk_dpi_unbind(struct device *dev, struct device *master,
825 struct mtk_dpi *dpi = dev_get_drvdata(dev);
827 drm_encoder_cleanup(&dpi->encoder);
830 static const struct component_ops mtk_dpi_component_ops = {
831 .bind = mtk_dpi_bind,
832 .unbind = mtk_dpi_unbind,
835 static unsigned int mt8173_calculate_factor(int clock)
839 else if (clock <= 84000)
841 else if (clock <= 167000)
847 static unsigned int mt2701_calculate_factor(int clock)
851 else if (clock <= 128000)
857 static unsigned int mt8183_calculate_factor(int clock)
861 else if (clock <= 167000)
867 static unsigned int mt8195_dpintf_calculate_factor(int clock)
871 else if (clock < 200000)
877 static const u32 mt8173_output_fmts[] = {
878 MEDIA_BUS_FMT_RGB888_1X24,
881 static const u32 mt8183_output_fmts[] = {
882 MEDIA_BUS_FMT_RGB888_2X12_LE,
883 MEDIA_BUS_FMT_RGB888_2X12_BE,
886 static const u32 mt8195_output_fmts[] = {
887 MEDIA_BUS_FMT_RGB888_1X24,
888 MEDIA_BUS_FMT_YUYV8_1X16,
891 static const struct mtk_dpi_conf mt8173_conf = {
892 .cal_factor = mt8173_calculate_factor,
893 .reg_h_fre_con = 0xe0,
894 .max_clock_khz = 300000,
895 .output_fmts = mt8173_output_fmts,
896 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
897 .pixels_per_iter = 1,
898 .is_ck_de_pol = true,
899 .swap_input_support = true,
900 .support_direct_pin = true,
901 .dimension_mask = HPW_MASK,
902 .hvsize_mask = HSIZE_MASK,
903 .channel_swap_shift = CH_SWAP,
904 .yuv422_en_bit = YUV422_EN,
905 .csc_enable_bit = CSC_ENABLE,
908 static const struct mtk_dpi_conf mt2701_conf = {
909 .cal_factor = mt2701_calculate_factor,
910 .reg_h_fre_con = 0xb0,
912 .max_clock_khz = 150000,
913 .output_fmts = mt8173_output_fmts,
914 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
915 .pixels_per_iter = 1,
916 .is_ck_de_pol = true,
917 .swap_input_support = true,
918 .support_direct_pin = true,
919 .dimension_mask = HPW_MASK,
920 .hvsize_mask = HSIZE_MASK,
921 .channel_swap_shift = CH_SWAP,
922 .yuv422_en_bit = YUV422_EN,
923 .csc_enable_bit = CSC_ENABLE,
926 static const struct mtk_dpi_conf mt8183_conf = {
927 .cal_factor = mt8183_calculate_factor,
928 .reg_h_fre_con = 0xe0,
929 .max_clock_khz = 100000,
930 .output_fmts = mt8183_output_fmts,
931 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
932 .pixels_per_iter = 1,
933 .is_ck_de_pol = true,
934 .swap_input_support = true,
935 .support_direct_pin = true,
936 .dimension_mask = HPW_MASK,
937 .hvsize_mask = HSIZE_MASK,
938 .channel_swap_shift = CH_SWAP,
939 .yuv422_en_bit = YUV422_EN,
940 .csc_enable_bit = CSC_ENABLE,
943 static const struct mtk_dpi_conf mt8186_conf = {
944 .cal_factor = mt8183_calculate_factor,
945 .reg_h_fre_con = 0xe0,
946 .max_clock_khz = 150000,
947 .output_fmts = mt8183_output_fmts,
948 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
949 .edge_cfg_in_mmsys = true,
950 .pixels_per_iter = 1,
951 .is_ck_de_pol = true,
952 .swap_input_support = true,
953 .support_direct_pin = true,
954 .dimension_mask = HPW_MASK,
955 .hvsize_mask = HSIZE_MASK,
956 .channel_swap_shift = CH_SWAP,
957 .yuv422_en_bit = YUV422_EN,
958 .csc_enable_bit = CSC_ENABLE,
961 static const struct mtk_dpi_conf mt8188_dpintf_conf = {
962 .cal_factor = mt8195_dpintf_calculate_factor,
963 .max_clock_khz = 600000,
964 .output_fmts = mt8195_output_fmts,
965 .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
966 .pixels_per_iter = 4,
967 .input_2pixel = false,
968 .dimension_mask = DPINTF_HPW_MASK,
969 .hvsize_mask = DPINTF_HSIZE_MASK,
970 .channel_swap_shift = DPINTF_CH_SWAP,
971 .yuv422_en_bit = DPINTF_YUV422_EN,
972 .csc_enable_bit = DPINTF_CSC_ENABLE,
975 static const struct mtk_dpi_conf mt8192_conf = {
976 .cal_factor = mt8183_calculate_factor,
977 .reg_h_fre_con = 0xe0,
978 .max_clock_khz = 150000,
979 .output_fmts = mt8183_output_fmts,
980 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
981 .pixels_per_iter = 1,
982 .is_ck_de_pol = true,
983 .swap_input_support = true,
984 .support_direct_pin = true,
985 .dimension_mask = HPW_MASK,
986 .hvsize_mask = HSIZE_MASK,
987 .channel_swap_shift = CH_SWAP,
988 .yuv422_en_bit = YUV422_EN,
989 .csc_enable_bit = CSC_ENABLE,
992 static const struct mtk_dpi_conf mt8195_dpintf_conf = {
993 .cal_factor = mt8195_dpintf_calculate_factor,
994 .max_clock_khz = 600000,
995 .output_fmts = mt8195_output_fmts,
996 .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
997 .pixels_per_iter = 4,
998 .input_2pixel = true,
999 .dimension_mask = DPINTF_HPW_MASK,
1000 .hvsize_mask = DPINTF_HSIZE_MASK,
1001 .channel_swap_shift = DPINTF_CH_SWAP,
1002 .yuv422_en_bit = DPINTF_YUV422_EN,
1003 .csc_enable_bit = DPINTF_CSC_ENABLE,
1006 static int mtk_dpi_probe(struct platform_device *pdev)
1008 struct device *dev = &pdev->dev;
1009 struct mtk_dpi *dpi;
1010 struct resource *mem;
1013 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
1018 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
1019 dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
1021 dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
1022 if (IS_ERR(dpi->pinctrl)) {
1023 dpi->pinctrl = NULL;
1024 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n");
1027 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep");
1028 if (IS_ERR(dpi->pins_gpio)) {
1029 dpi->pins_gpio = NULL;
1030 dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n");
1033 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
1035 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default");
1036 if (IS_ERR(dpi->pins_dpi)) {
1037 dpi->pins_dpi = NULL;
1038 dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n");
1041 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1042 dpi->regs = devm_ioremap_resource(dev, mem);
1043 if (IS_ERR(dpi->regs)) {
1044 ret = PTR_ERR(dpi->regs);
1045 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret);
1049 dpi->engine_clk = devm_clk_get(dev, "engine");
1050 if (IS_ERR(dpi->engine_clk)) {
1051 ret = PTR_ERR(dpi->engine_clk);
1052 if (ret != -EPROBE_DEFER)
1053 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1058 dpi->pixel_clk = devm_clk_get(dev, "pixel");
1059 if (IS_ERR(dpi->pixel_clk)) {
1060 ret = PTR_ERR(dpi->pixel_clk);
1061 if (ret != -EPROBE_DEFER)
1062 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1067 dpi->tvd_clk = devm_clk_get(dev, "pll");
1068 if (IS_ERR(dpi->tvd_clk)) {
1069 ret = PTR_ERR(dpi->tvd_clk);
1070 if (ret != -EPROBE_DEFER)
1071 dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
1076 dpi->irq = platform_get_irq(pdev, 0);
1080 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1081 NULL, &dpi->next_bridge);
1085 dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node);
1087 platform_set_drvdata(pdev, dpi);
1089 dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
1090 dpi->bridge.of_node = dev->of_node;
1091 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
1093 drm_bridge_add(&dpi->bridge);
1095 ret = component_add(dev, &mtk_dpi_component_ops);
1097 drm_bridge_remove(&dpi->bridge);
1098 dev_err(dev, "Failed to add component: %d\n", ret);
1105 static int mtk_dpi_remove(struct platform_device *pdev)
1107 struct mtk_dpi *dpi = platform_get_drvdata(pdev);
1109 component_del(&pdev->dev, &mtk_dpi_component_ops);
1110 drm_bridge_remove(&dpi->bridge);
1115 static const struct of_device_id mtk_dpi_of_ids[] = {
1116 { .compatible = "mediatek,mt2701-dpi",
1117 .data = &mt2701_conf,
1119 { .compatible = "mediatek,mt8173-dpi",
1120 .data = &mt8173_conf,
1122 { .compatible = "mediatek,mt8183-dpi",
1123 .data = &mt8183_conf,
1125 { .compatible = "mediatek,mt8186-dpi",
1126 .data = &mt8186_conf,
1128 { .compatible = "mediatek,mt8188-dp-intf",
1129 .data = &mt8188_dpintf_conf,
1131 { .compatible = "mediatek,mt8192-dpi",
1132 .data = &mt8192_conf,
1134 { .compatible = "mediatek,mt8195-dp-intf",
1135 .data = &mt8195_dpintf_conf,
1139 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
1141 struct platform_driver mtk_dpi_driver = {
1142 .probe = mtk_dpi_probe,
1143 .remove = mtk_dpi_remove,
1145 .name = "mediatek-dpi",
1146 .of_match_table = mtk_dpi_of_ids,