1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
6 #include <drm/drm_fourcc.h>
9 #include <linux/component.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/of_irq.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/soc/mediatek/mtk-cmdq.h>
17 #include "mtk_disp_drv.h"
18 #include "mtk_drm_crtc.h"
19 #include "mtk_drm_ddp_comp.h"
20 #include "mtk_drm_drv.h"
22 #define DISP_REG_RDMA_INT_ENABLE 0x0000
23 #define DISP_REG_RDMA_INT_STATUS 0x0004
24 #define RDMA_TARGET_LINE_INT BIT(5)
25 #define RDMA_FIFO_UNDERFLOW_INT BIT(4)
26 #define RDMA_EOF_ABNORMAL_INT BIT(3)
27 #define RDMA_FRAME_END_INT BIT(2)
28 #define RDMA_FRAME_START_INT BIT(1)
29 #define RDMA_REG_UPDATE_INT BIT(0)
30 #define DISP_REG_RDMA_GLOBAL_CON 0x0010
31 #define RDMA_ENGINE_EN BIT(0)
32 #define RDMA_MODE_MEMORY BIT(1)
33 #define DISP_REG_RDMA_SIZE_CON_0 0x0014
34 #define RDMA_MATRIX_ENABLE BIT(17)
35 #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
36 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20)
37 #define DISP_REG_RDMA_SIZE_CON_1 0x0018
38 #define DISP_REG_RDMA_TARGET_LINE 0x001c
39 #define DISP_RDMA_MEM_CON 0x0024
40 #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4)
41 #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
42 #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
43 #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
44 #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
45 #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
46 #define MEM_MODE_INPUT_SWAP BIT(8)
47 #define DISP_RDMA_MEM_SRC_PITCH 0x002c
48 #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
49 #define DISP_REG_RDMA_FIFO_CON 0x0040
50 #define RDMA_FIFO_UNDERFLOW_EN BIT(31)
51 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
52 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
53 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
54 #define DISP_RDMA_MEM_START_ADDR 0x0f00
56 #define RDMA_MEM_GMC 0x40402020
58 static const u32 mt8173_formats[] = {
72 struct mtk_disp_rdma_data {
73 unsigned int fifo_size;
79 * struct mtk_disp_rdma - DISP_RDMA driver structure
80 * @data: local driver data
82 struct mtk_disp_rdma {
85 struct cmdq_client_reg cmdq_reg;
86 const struct mtk_disp_rdma_data *data;
87 void (*vblank_cb)(void *data);
92 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
94 struct mtk_disp_rdma *priv = dev_id;
96 /* Clear frame completion interrupt */
97 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
102 priv->vblank_cb(priv->vblank_cb_data);
107 static void rdma_update_bits(struct device *dev, unsigned int reg,
108 unsigned int mask, unsigned int val)
110 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
111 unsigned int tmp = readl(rdma->regs + reg);
113 tmp = (tmp & ~mask) | (val & mask);
114 writel(tmp, rdma->regs + reg);
117 void mtk_rdma_register_vblank_cb(struct device *dev,
118 void (*vblank_cb)(void *),
119 void *vblank_cb_data)
121 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
123 rdma->vblank_cb = vblank_cb;
124 rdma->vblank_cb_data = vblank_cb_data;
127 void mtk_rdma_unregister_vblank_cb(struct device *dev)
129 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
131 rdma->vblank_cb = NULL;
132 rdma->vblank_cb_data = NULL;
135 void mtk_rdma_enable_vblank(struct device *dev)
137 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
141 void mtk_rdma_disable_vblank(struct device *dev)
143 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
146 const u32 *mtk_rdma_get_formats(struct device *dev)
148 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
150 return rdma->data->formats;
153 size_t mtk_rdma_get_num_formats(struct device *dev)
155 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
157 return rdma->data->num_formats;
160 int mtk_rdma_clk_enable(struct device *dev)
162 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
164 return clk_prepare_enable(rdma->clk);
167 void mtk_rdma_clk_disable(struct device *dev)
169 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
171 clk_disable_unprepare(rdma->clk);
174 void mtk_rdma_start(struct device *dev)
176 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
180 void mtk_rdma_stop(struct device *dev)
182 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
185 void mtk_rdma_config(struct device *dev, unsigned int width,
186 unsigned int height, unsigned int vrefresh,
187 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
189 unsigned int threshold;
191 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
194 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
195 DISP_REG_RDMA_SIZE_CON_0, 0xfff);
196 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
197 DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
200 rdma_fifo_size = rdma->fifo_size;
202 rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
205 * Enable FIFO underflow since DSI and DPI can't be blocked.
206 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
207 * output threshold to 70% of max fifo size to make sure the
208 * threhold will not overflow
210 threshold = rdma_fifo_size * 7 / 10;
211 reg = RDMA_FIFO_UNDERFLOW_EN |
212 RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
213 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
214 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
217 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
220 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
221 * is defined in mediatek HW data sheet.
222 * The alphabet order in XXX is no relation to data
223 * arrangement in memory.
227 case DRM_FORMAT_RGB565:
228 return MEM_MODE_INPUT_FORMAT_RGB565;
229 case DRM_FORMAT_BGR565:
230 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
231 case DRM_FORMAT_RGB888:
232 return MEM_MODE_INPUT_FORMAT_RGB888;
233 case DRM_FORMAT_BGR888:
234 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
235 case DRM_FORMAT_RGBX8888:
236 case DRM_FORMAT_RGBA8888:
237 return MEM_MODE_INPUT_FORMAT_ARGB8888;
238 case DRM_FORMAT_BGRX8888:
239 case DRM_FORMAT_BGRA8888:
240 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
241 case DRM_FORMAT_XRGB8888:
242 case DRM_FORMAT_ARGB8888:
243 return MEM_MODE_INPUT_FORMAT_RGBA8888;
244 case DRM_FORMAT_XBGR8888:
245 case DRM_FORMAT_ABGR8888:
246 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
247 case DRM_FORMAT_UYVY:
248 return MEM_MODE_INPUT_FORMAT_UYVY;
249 case DRM_FORMAT_YUYV:
250 return MEM_MODE_INPUT_FORMAT_YUYV;
254 unsigned int mtk_rdma_layer_nr(struct device *dev)
259 void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
260 struct mtk_plane_state *state,
261 struct cmdq_pkt *cmdq_pkt)
263 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
264 struct mtk_plane_pending_state *pending = &state->pending;
265 unsigned int addr = pending->addr;
266 unsigned int pitch = pending->pitch & 0xffff;
267 unsigned int fmt = pending->format;
270 con = rdma_fmt_convert(rdma, fmt);
271 mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
273 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
274 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
275 DISP_REG_RDMA_SIZE_CON_0,
277 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
278 &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
279 RDMA_MATRIX_INT_MTX_SEL);
281 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
282 DISP_REG_RDMA_SIZE_CON_0,
285 mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
286 DISP_RDMA_MEM_START_ADDR);
287 mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
288 DISP_RDMA_MEM_SRC_PITCH);
289 mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
290 DISP_RDMA_MEM_GMC_SETTING_0);
291 mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
292 DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
296 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
303 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
308 static const struct component_ops mtk_disp_rdma_component_ops = {
309 .bind = mtk_disp_rdma_bind,
310 .unbind = mtk_disp_rdma_unbind,
313 static int mtk_disp_rdma_probe(struct platform_device *pdev)
315 struct device *dev = &pdev->dev;
316 struct mtk_disp_rdma *priv;
317 struct resource *res;
321 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
325 irq = platform_get_irq(pdev, 0);
329 priv->clk = devm_clk_get(dev, NULL);
330 if (IS_ERR(priv->clk)) {
331 dev_err(dev, "failed to get rdma clk\n");
332 return PTR_ERR(priv->clk);
335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
336 priv->regs = devm_ioremap_resource(dev, res);
337 if (IS_ERR(priv->regs)) {
338 dev_err(dev, "failed to ioremap rdma\n");
339 return PTR_ERR(priv->regs);
341 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
342 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
344 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
347 if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
348 ret = of_property_read_u32(dev->of_node,
349 "mediatek,rdma-fifo-size",
352 dev_err(dev, "Failed to get rdma fifo size\n");
357 /* Disable and clear pending interrupts */
358 writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
359 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
361 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
362 IRQF_TRIGGER_NONE, dev_name(dev), priv);
364 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
368 priv->data = of_device_get_match_data(dev);
370 platform_set_drvdata(pdev, priv);
372 pm_runtime_enable(dev);
374 ret = component_add(dev, &mtk_disp_rdma_component_ops);
376 pm_runtime_disable(dev);
377 dev_err(dev, "Failed to add component: %d\n", ret);
383 static int mtk_disp_rdma_remove(struct platform_device *pdev)
385 component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
387 pm_runtime_disable(&pdev->dev);
392 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
394 .formats = mt8173_formats,
395 .num_formats = ARRAY_SIZE(mt8173_formats),
398 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
400 .formats = mt8173_formats,
401 .num_formats = ARRAY_SIZE(mt8173_formats),
404 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
405 .fifo_size = 5 * SZ_1K,
406 .formats = mt8173_formats,
407 .num_formats = ARRAY_SIZE(mt8173_formats),
410 static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
412 .formats = mt8173_formats,
413 .num_formats = ARRAY_SIZE(mt8173_formats),
416 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
417 { .compatible = "mediatek,mt2701-disp-rdma",
418 .data = &mt2701_rdma_driver_data},
419 { .compatible = "mediatek,mt8173-disp-rdma",
420 .data = &mt8173_rdma_driver_data},
421 { .compatible = "mediatek,mt8183-disp-rdma",
422 .data = &mt8183_rdma_driver_data},
423 { .compatible = "mediatek,mt8195-disp-rdma",
424 .data = &mt8195_rdma_driver_data},
427 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
429 struct platform_driver mtk_disp_rdma_driver = {
430 .probe = mtk_disp_rdma_probe,
431 .remove = mtk_disp_rdma_remove,
433 .name = "mediatek-disp-rdma",
434 .owner = THIS_MODULE,
435 .of_match_table = mtk_disp_rdma_driver_dt_match,