drivers/gpu/drm/mediatek/mtk_disp_rdma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <drm/drm_fourcc.h>
   7
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/soc/mediatek/mtk-cmdq.h>
  16
  17 #include "mtk_disp_drv.h"
  18 #include "mtk_drm_crtc.h"
  19 #include "mtk_drm_ddp_comp.h"
  20 #include "mtk_drm_drv.h"
  21
  22 #define DISP_REG_RDMA_INT_ENABLE                0x0000
  23 #define DISP_REG_RDMA_INT_STATUS                0x0004
  24 #define RDMA_TARGET_LINE_INT                            BIT(5)
  25 #define RDMA_FIFO_UNDERFLOW_INT                         BIT(4)
  26 #define RDMA_EOF_ABNORMAL_INT                           BIT(3)
  27 #define RDMA_FRAME_END_INT                              BIT(2)
  28 #define RDMA_FRAME_START_INT                            BIT(1)
  29 #define RDMA_REG_UPDATE_INT                             BIT(0)
  30 #define DISP_REG_RDMA_GLOBAL_CON                0x0010
  31 #define RDMA_ENGINE_EN                                  BIT(0)
  32 #define RDMA_MODE_MEMORY                                BIT(1)
  33 #define DISP_REG_RDMA_SIZE_CON_0                0x0014
  34 #define RDMA_MATRIX_ENABLE                              BIT(17)
  35 #define RDMA_MATRIX_INT_MTX_SEL                         GENMASK(23, 20)
  36 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB                (6 << 20)
  37 #define DISP_REG_RDMA_SIZE_CON_1                0x0018
  38 #define DISP_REG_RDMA_TARGET_LINE               0x001c
  39 #define DISP_RDMA_MEM_CON                       0x0024
  40 #define MEM_MODE_INPUT_FORMAT_RGB565                    (0x000 << 4)
  41 #define MEM_MODE_INPUT_FORMAT_RGB888                    (0x001 << 4)
  42 #define MEM_MODE_INPUT_FORMAT_RGBA8888                  (0x002 << 4)
  43 #define MEM_MODE_INPUT_FORMAT_ARGB8888                  (0x003 << 4)
  44 #define MEM_MODE_INPUT_FORMAT_UYVY                      (0x004 << 4)
  45 #define MEM_MODE_INPUT_FORMAT_YUYV                      (0x005 << 4)
  46 #define MEM_MODE_INPUT_SWAP                             BIT(8)
  47 #define DISP_RDMA_MEM_SRC_PITCH                 0x002c
  48 #define DISP_RDMA_MEM_GMC_SETTING_0             0x0030
  49 #define DISP_REG_RDMA_FIFO_CON                  0x0040
  50 #define RDMA_FIFO_UNDERFLOW_EN                          BIT(31)
  51 #define RDMA_FIFO_PSEUDO_SIZE(bytes)                    (((bytes) / 16) << 16)
  52 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)         ((bytes) / 16)
  53 #define RDMA_FIFO_SIZE(rdma)                    ((rdma)->data->fifo_size)
  54 #define DISP_RDMA_MEM_START_ADDR                0x0f00
  55
  56 #define RDMA_MEM_GMC                            0x40402020
  57
  58 static const u32 mt8173_formats[] = {
  59         DRM_FORMAT_XRGB8888,
  60         DRM_FORMAT_ARGB8888,
  61         DRM_FORMAT_BGRX8888,
  62         DRM_FORMAT_BGRA8888,
  63         DRM_FORMAT_ABGR8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_RGB888,
  66         DRM_FORMAT_BGR888,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_UYVY,
  69         DRM_FORMAT_YUYV,
  70 };
  71
  72 struct mtk_disp_rdma_data {
  73         unsigned int fifo_size;
  74         const u32 *formats;
  75         size_t num_formats;
  76 };
  77
  78 /*
  79  * struct mtk_disp_rdma - DISP_RDMA driver structure
  80  * @data: local driver data
  81  */
  82 struct mtk_disp_rdma {
  83         struct clk                      *clk;
  84         void __iomem                    *regs;
  85         struct cmdq_client_reg          cmdq_reg;
  86         const struct mtk_disp_rdma_data *data;
  87         void                            (*vblank_cb)(void *data);
  88         void                            *vblank_cb_data;
  89         u32                             fifo_size;
  90 };
  91
  92 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
  93 {
  94         struct mtk_disp_rdma *priv = dev_id;
  95
  96         /* Clear frame completion interrupt */
  97         writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
  98
  99         if (!priv->vblank_cb)
 100                 return IRQ_NONE;
 101
 102         priv->vblank_cb(priv->vblank_cb_data);
 103
 104         return IRQ_HANDLED;
 105 }
 106
 107 static void rdma_update_bits(struct device *dev, unsigned int reg,
 108                              unsigned int mask, unsigned int val)
 109 {
 110         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 111         unsigned int tmp = readl(rdma->regs + reg);
 112
 113         tmp = (tmp & ~mask) | (val & mask);
 114         writel(tmp, rdma->regs + reg);
 115 }
 116
 117 void mtk_rdma_register_vblank_cb(struct device *dev,
 118                                  void (*vblank_cb)(void *),
 119                                  void *vblank_cb_data)
 120 {
 121         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 122
 123         rdma->vblank_cb = vblank_cb;
 124         rdma->vblank_cb_data = vblank_cb_data;
 125 }
 126
 127 void mtk_rdma_unregister_vblank_cb(struct device *dev)
 128 {
 129         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 130
 131         rdma->vblank_cb = NULL;
 132         rdma->vblank_cb_data = NULL;
 133 }
 134
 135 void mtk_rdma_enable_vblank(struct device *dev)
 136 {
 137         rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
 138                          RDMA_FRAME_END_INT);
 139 }
 140
 141 void mtk_rdma_disable_vblank(struct device *dev)
 142 {
 143         rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
 144 }
 145
 146 const u32 *mtk_rdma_get_formats(struct device *dev)
 147 {
 148         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 149
 150         return rdma->data->formats;
 151 }
 152
 153 size_t mtk_rdma_get_num_formats(struct device *dev)
 154 {
 155         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 156
 157         return rdma->data->num_formats;
 158 }
 159
 160 int mtk_rdma_clk_enable(struct device *dev)
 161 {
 162         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 163
 164         return clk_prepare_enable(rdma->clk);
 165 }
 166
 167 void mtk_rdma_clk_disable(struct device *dev)
 168 {
 169         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 170
 171         clk_disable_unprepare(rdma->clk);
 172 }
 173
 174 void mtk_rdma_start(struct device *dev)
 175 {
 176         rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
 177                          RDMA_ENGINE_EN);
 178 }
 179
 180 void mtk_rdma_stop(struct device *dev)
 181 {
 182         rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
 183 }
 184
 185 void mtk_rdma_config(struct device *dev, unsigned int width,
 186                      unsigned int height, unsigned int vrefresh,
 187                      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 188 {
 189         unsigned int threshold;
 190         unsigned int reg;
 191         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 192         u32 rdma_fifo_size;
 193
 194         mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
 195                            DISP_REG_RDMA_SIZE_CON_0, 0xfff);
 196         mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
 197                            DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
 198
 199         if (rdma->fifo_size)
 200                 rdma_fifo_size = rdma->fifo_size;
 201         else
 202                 rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
 203
 204         /*
 205          * Enable FIFO underflow since DSI and DPI can't be blocked.
 206          * Keep the FIFO pseudo size reset default of 8 KiB. Set the
 207          * output threshold to 70% of max fifo size to make sure the
 208          * threhold will not overflow
 209          */
 210         threshold = rdma_fifo_size * 7 / 10;
 211         reg = RDMA_FIFO_UNDERFLOW_EN |
 212               RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
 213               RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
 214         mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
 215 }
 216
 217 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
 218                                      unsigned int fmt)
 219 {
 220         /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
 221          * is defined in mediatek HW data sheet.
 222          * The alphabet order in XXX is no relation to data
 223          * arrangement in memory.
 224          */
 225         switch (fmt) {
 226         default:
 227         case DRM_FORMAT_RGB565:
 228                 return MEM_MODE_INPUT_FORMAT_RGB565;
 229         case DRM_FORMAT_BGR565:
 230                 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
 231         case DRM_FORMAT_RGB888:
 232                 return MEM_MODE_INPUT_FORMAT_RGB888;
 233         case DRM_FORMAT_BGR888:
 234                 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
 235         case DRM_FORMAT_RGBX8888:
 236         case DRM_FORMAT_RGBA8888:
 237                 return MEM_MODE_INPUT_FORMAT_ARGB8888;
 238         case DRM_FORMAT_BGRX8888:
 239         case DRM_FORMAT_BGRA8888:
 240                 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
 241         case DRM_FORMAT_XRGB8888:
 242         case DRM_FORMAT_ARGB8888:
 243                 return MEM_MODE_INPUT_FORMAT_RGBA8888;
 244         case DRM_FORMAT_XBGR8888:
 245         case DRM_FORMAT_ABGR8888:
 246                 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
 247         case DRM_FORMAT_UYVY:
 248                 return MEM_MODE_INPUT_FORMAT_UYVY;
 249         case DRM_FORMAT_YUYV:
 250                 return MEM_MODE_INPUT_FORMAT_YUYV;
 251         }
 252 }
 253
 254 unsigned int mtk_rdma_layer_nr(struct device *dev)
 255 {
 256         return 1;
 257 }
 258
 259 void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
 260                            struct mtk_plane_state *state,
 261                            struct cmdq_pkt *cmdq_pkt)
 262 {
 263         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 264         struct mtk_plane_pending_state *pending = &state->pending;
 265         unsigned int addr = pending->addr;
 266         unsigned int pitch = pending->pitch & 0xffff;
 267         unsigned int fmt = pending->format;
 268         unsigned int con;
 269
 270         con = rdma_fmt_convert(rdma, fmt);
 271         mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
 272
 273         if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
 274                 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
 275                                    DISP_REG_RDMA_SIZE_CON_0,
 276                                    RDMA_MATRIX_ENABLE);
 277                 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
 278                                    &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
 279                                    RDMA_MATRIX_INT_MTX_SEL);
 280         } else {
 281                 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
 282                                    DISP_REG_RDMA_SIZE_CON_0,
 283                                    RDMA_MATRIX_ENABLE);
 284         }
 285         mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
 286                               DISP_RDMA_MEM_START_ADDR);
 287         mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
 288                               DISP_RDMA_MEM_SRC_PITCH);
 289         mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
 290                       DISP_RDMA_MEM_GMC_SETTING_0);
 291         mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
 292                            DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
 293
 294 }
 295
 296 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
 297                               void *data)
 298 {
 299         return 0;
 300
 301 }
 302
 303 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
 304                                  void *data)
 305 {
 306 }
 307
 308 static const struct component_ops mtk_disp_rdma_component_ops = {
 309         .bind   = mtk_disp_rdma_bind,
 310         .unbind = mtk_disp_rdma_unbind,
 311 };
 312
 313 static int mtk_disp_rdma_probe(struct platform_device *pdev)
 314 {
 315         struct device *dev = &pdev->dev;
 316         struct mtk_disp_rdma *priv;
 317         struct resource *res;
 318         int irq;
 319         int ret;
 320
 321         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 322         if (!priv)
 323                 return -ENOMEM;
 324
 325         irq = platform_get_irq(pdev, 0);
 326         if (irq < 0)
 327                 return irq;
 328
 329         priv->clk = devm_clk_get(dev, NULL);
 330         if (IS_ERR(priv->clk)) {
 331                 dev_err(dev, "failed to get rdma clk\n");
 332                 return PTR_ERR(priv->clk);
 333         }
 334
 335         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 336         priv->regs = devm_ioremap_resource(dev, res);
 337         if (IS_ERR(priv->regs)) {
 338                 dev_err(dev, "failed to ioremap rdma\n");
 339                 return PTR_ERR(priv->regs);
 340         }
 341 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 342         ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
 343         if (ret)
 344                 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
 345 #endif
 346
 347         if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
 348                 ret = of_property_read_u32(dev->of_node,
 349                                            "mediatek,rdma-fifo-size",
 350                                            &priv->fifo_size);
 351                 if (ret) {
 352                         dev_err(dev, "Failed to get rdma fifo size\n");
 353                         return ret;
 354                 }
 355         }
 356
 357         /* Disable and clear pending interrupts */
 358         writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
 359         writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
 360
 361         ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
 362                                IRQF_TRIGGER_NONE, dev_name(dev), priv);
 363         if (ret < 0) {
 364                 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
 365                 return ret;
 366         }
 367
 368         priv->data = of_device_get_match_data(dev);
 369
 370         platform_set_drvdata(pdev, priv);
 371
 372         pm_runtime_enable(dev);
 373
 374         ret = component_add(dev, &mtk_disp_rdma_component_ops);
 375         if (ret) {
 376                 pm_runtime_disable(dev);
 377                 dev_err(dev, "Failed to add component: %d\n", ret);
 378         }
 379
 380         return ret;
 381 }
 382
 383 static int mtk_disp_rdma_remove(struct platform_device *pdev)
 384 {
 385         component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
 386
 387         pm_runtime_disable(&pdev->dev);
 388
 389         return 0;
 390 }
 391
 392 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
 393         .fifo_size = SZ_4K,
 394         .formats = mt8173_formats,
 395         .num_formats = ARRAY_SIZE(mt8173_formats),
 396 };
 397
 398 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
 399         .fifo_size = SZ_8K,
 400         .formats = mt8173_formats,
 401         .num_formats = ARRAY_SIZE(mt8173_formats),
 402 };
 403
 404 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 405         .fifo_size = 5 * SZ_1K,
 406         .formats = mt8173_formats,
 407         .num_formats = ARRAY_SIZE(mt8173_formats),
 408 };
 409
 410 static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
 411         .fifo_size = 1920,
 412         .formats = mt8173_formats,
 413         .num_formats = ARRAY_SIZE(mt8173_formats),
 414 };
 415
 416 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 417         { .compatible = "mediatek,mt2701-disp-rdma",
 418           .data = &mt2701_rdma_driver_data},
 419         { .compatible = "mediatek,mt8173-disp-rdma",
 420           .data = &mt8173_rdma_driver_data},
 421         { .compatible = "mediatek,mt8183-disp-rdma",
 422           .data = &mt8183_rdma_driver_data},
 423         { .compatible = "mediatek,mt8195-disp-rdma",
 424           .data = &mt8195_rdma_driver_data},
 425         {},
 426 };
 427 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
 428
 429 struct platform_driver mtk_disp_rdma_driver = {
 430         .probe          = mtk_disp_rdma_probe,
 431         .remove         = mtk_disp_rdma_remove,
 432         .driver         = {
 433                 .name   = "mediatek-disp-rdma",
 434                 .owner  = THIS_MODULE,
 435                 .of_match_table = mtk_disp_rdma_driver_dt_match,
 436         },
 437 };