drivers/gpu/drm/mediatek/mtk_disp_ovl.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <drm/drm_blend.h>
   7 #include <drm/drm_fourcc.h>
   8 #include <drm/drm_framebuffer.h>
   9
  10 #include <linux/clk.h>
  11 #include <linux/component.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/soc/mediatek/mtk-cmdq.h>
  18
  19 #include "mtk_disp_drv.h"
  20 #include "mtk_drm_crtc.h"
  21 #include "mtk_drm_ddp_comp.h"
  22
  23 #define DISP_REG_OVL_INTEN                      0x0004
  24 #define OVL_FME_CPL_INT                                 BIT(1)
  25 #define DISP_REG_OVL_INTSTA                     0x0008
  26 #define DISP_REG_OVL_EN                         0x000c
  27 #define DISP_REG_OVL_RST                        0x0014
  28 #define DISP_REG_OVL_ROI_SIZE                   0x0020
  29 #define DISP_REG_OVL_DATAPATH_CON               0x0024
  30 #define OVL_LAYER_SMI_ID_EN                             BIT(0)
  31 #define OVL_BGCLR_SEL_IN                                BIT(2)
  32 #define DISP_REG_OVL_ROI_BGCLR                  0x0028
  33 #define DISP_REG_OVL_SRC_CON                    0x002c
  34 #define DISP_REG_OVL_CON(n)                     (0x0030 + 0x20 * (n))
  35 #define DISP_REG_OVL_SRC_SIZE(n)                (0x0038 + 0x20 * (n))
  36 #define DISP_REG_OVL_OFFSET(n)                  (0x003c + 0x20 * (n))
  37 #define DISP_REG_OVL_PITCH(n)                   (0x0044 + 0x20 * (n))
  38 #define DISP_REG_OVL_RDMA_CTRL(n)               (0x00c0 + 0x20 * (n))
  39 #define DISP_REG_OVL_RDMA_GMC(n)                (0x00c8 + 0x20 * (n))
  40 #define DISP_REG_OVL_ADDR_MT2701                0x0040
  41 #define DISP_REG_OVL_ADDR_MT8173                0x0f40
  42 #define DISP_REG_OVL_ADDR(ovl, n)               ((ovl)->data->addr + 0x20 * (n))
  43
  44 #define GMC_THRESHOLD_BITS      16
  45 #define GMC_THRESHOLD_HIGH      ((1 << GMC_THRESHOLD_BITS) / 4)
  46 #define GMC_THRESHOLD_LOW       ((1 << GMC_THRESHOLD_BITS) / 8)
  47
  48 #define OVL_CON_BYTE_SWAP       BIT(24)
  49 #define OVL_CON_MTX_YUV_TO_RGB  (6 << 16)
  50 #define OVL_CON_CLRFMT_RGB      (1 << 12)
  51 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
  52 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
  53 #define OVL_CON_CLRFMT_UYVY     (4 << 12)
  54 #define OVL_CON_CLRFMT_YUYV     (5 << 12)
  55 #define OVL_CON_CLRFMT_RGB565(ovl)      ((ovl)->data->fmt_rgb565_is_0 ? \
  56                                         0 : OVL_CON_CLRFMT_RGB)
  57 #define OVL_CON_CLRFMT_RGB888(ovl)      ((ovl)->data->fmt_rgb565_is_0 ? \
  58                                         OVL_CON_CLRFMT_RGB : 0)
  59 #define OVL_CON_AEN             BIT(8)
  60 #define OVL_CON_ALPHA           0xff
  61 #define OVL_CON_VIRT_FLIP       BIT(9)
  62 #define OVL_CON_HORZ_FLIP       BIT(10)
  63
  64 struct mtk_disp_ovl_data {
  65         unsigned int addr;
  66         unsigned int gmc_bits;
  67         unsigned int layer_nr;
  68         bool fmt_rgb565_is_0;
  69         bool smi_id_en;
  70 };
  71
  72 /*
  73  * struct mtk_disp_ovl - DISP_OVL driver structure
  74  * @crtc: associated crtc to report vblank events to
  75  * @data: platform data
  76  */
  77 struct mtk_disp_ovl {
  78         struct drm_crtc                 *crtc;
  79         struct clk                      *clk;
  80         void __iomem                    *regs;
  81         struct cmdq_client_reg          cmdq_reg;
  82         const struct mtk_disp_ovl_data  *data;
  83         void                            (*vblank_cb)(void *data);
  84         void                            *vblank_cb_data;
  85 };
  86
  87 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
  88 {
  89         struct mtk_disp_ovl *priv = dev_id;
  90
  91         /* Clear frame completion interrupt */
  92         writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);
  93
  94         if (!priv->vblank_cb)
  95                 return IRQ_NONE;
  96
  97         priv->vblank_cb(priv->vblank_cb_data);
  98
  99         return IRQ_HANDLED;
 100 }
 101
 102 void mtk_ovl_register_vblank_cb(struct device *dev,
 103                                 void (*vblank_cb)(void *),
 104                                 void *vblank_cb_data)
 105 {
 106         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 107
 108         ovl->vblank_cb = vblank_cb;
 109         ovl->vblank_cb_data = vblank_cb_data;
 110 }
 111
 112 void mtk_ovl_unregister_vblank_cb(struct device *dev)
 113 {
 114         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 115
 116         ovl->vblank_cb = NULL;
 117         ovl->vblank_cb_data = NULL;
 118 }
 119
 120 void mtk_ovl_enable_vblank(struct device *dev)
 121 {
 122         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 123
 124         writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
 125         writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);
 126 }
 127
 128 void mtk_ovl_disable_vblank(struct device *dev)
 129 {
 130         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 131
 132         writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
 133 }
 134
 135 int mtk_ovl_clk_enable(struct device *dev)
 136 {
 137         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 138
 139         return clk_prepare_enable(ovl->clk);
 140 }
 141
 142 void mtk_ovl_clk_disable(struct device *dev)
 143 {
 144         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 145
 146         clk_disable_unprepare(ovl->clk);
 147 }
 148
 149 void mtk_ovl_start(struct device *dev)
 150 {
 151         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 152
 153         if (ovl->data->smi_id_en) {
 154                 unsigned int reg;
 155
 156                 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 157                 reg = reg | OVL_LAYER_SMI_ID_EN;
 158                 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 159         }
 160         writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
 161 }
 162
 163 void mtk_ovl_stop(struct device *dev)
 164 {
 165         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 166
 167         writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
 168         if (ovl->data->smi_id_en) {
 169                 unsigned int reg;
 170
 171                 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 172                 reg = reg & ~OVL_LAYER_SMI_ID_EN;
 173                 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 174         }
 175
 176 }
 177
 178 void mtk_ovl_config(struct device *dev, unsigned int w,
 179                     unsigned int h, unsigned int vrefresh,
 180                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 181 {
 182         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 183
 184         if (w != 0 && h != 0)
 185                 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
 186                                       DISP_REG_OVL_ROI_SIZE);
 187         mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
 188
 189         mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
 190         mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
 191 }
 192
 193 unsigned int mtk_ovl_layer_nr(struct device *dev)
 194 {
 195         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 196
 197         return ovl->data->layer_nr;
 198 }
 199
 200 unsigned int mtk_ovl_supported_rotations(struct device *dev)
 201 {
 202         return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
 203                DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
 204 }
 205
 206 int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
 207                         struct mtk_plane_state *mtk_state)
 208 {
 209         struct drm_plane_state *state = &mtk_state->base;
 210         unsigned int rotation = 0;
 211
 212         rotation = drm_rotation_simplify(state->rotation,
 213                                          DRM_MODE_ROTATE_0 |
 214                                          DRM_MODE_REFLECT_X |
 215                                          DRM_MODE_REFLECT_Y);
 216         rotation &= ~DRM_MODE_ROTATE_0;
 217
 218         /* We can only do reflection, not rotation */
 219         if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
 220                 return -EINVAL;
 221
 222         /*
 223          * TODO: Rotating/reflecting YUV buffers is not supported at this time.
 224          *       Only RGB[AX] variants are supported.
 225          */
 226         if (state->fb->format->is_yuv && rotation != 0)
 227                 return -EINVAL;
 228
 229         state->rotation = rotation;
 230
 231         return 0;
 232 }
 233
 234 void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
 235                       struct cmdq_pkt *cmdq_pkt)
 236 {
 237         unsigned int gmc_thrshd_l;
 238         unsigned int gmc_thrshd_h;
 239         unsigned int gmc_value;
 240         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 241
 242         mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
 243                       DISP_REG_OVL_RDMA_CTRL(idx));
 244         gmc_thrshd_l = GMC_THRESHOLD_LOW >>
 245                       (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
 246         gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
 247                       (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
 248         if (ovl->data->gmc_bits == 10)
 249                 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
 250         else
 251                 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
 252                             gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
 253         mtk_ddp_write(cmdq_pkt, gmc_value,
 254                       &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
 255         mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
 256                            DISP_REG_OVL_SRC_CON, BIT(idx));
 257 }
 258
 259 void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
 260                        struct cmdq_pkt *cmdq_pkt)
 261 {
 262         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 263
 264         mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
 265                            DISP_REG_OVL_SRC_CON, BIT(idx));
 266         mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
 267                       DISP_REG_OVL_RDMA_CTRL(idx));
 268 }
 269
 270 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
 271 {
 272         /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
 273          * is defined in mediatek HW data sheet.
 274          * The alphabet order in XXX is no relation to data
 275          * arrangement in memory.
 276          */
 277         switch (fmt) {
 278         default:
 279         case DRM_FORMAT_RGB565:
 280                 return OVL_CON_CLRFMT_RGB565(ovl);
 281         case DRM_FORMAT_BGR565:
 282                 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
 283         case DRM_FORMAT_RGB888:
 284                 return OVL_CON_CLRFMT_RGB888(ovl);
 285         case DRM_FORMAT_BGR888:
 286                 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
 287         case DRM_FORMAT_RGBX8888:
 288         case DRM_FORMAT_RGBA8888:
 289                 return OVL_CON_CLRFMT_ARGB8888;
 290         case DRM_FORMAT_BGRX8888:
 291         case DRM_FORMAT_BGRA8888:
 292                 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
 293         case DRM_FORMAT_XRGB8888:
 294         case DRM_FORMAT_ARGB8888:
 295                 return OVL_CON_CLRFMT_RGBA8888;
 296         case DRM_FORMAT_XBGR8888:
 297         case DRM_FORMAT_ABGR8888:
 298                 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
 299         case DRM_FORMAT_UYVY:
 300                 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
 301         case DRM_FORMAT_YUYV:
 302                 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
 303         }
 304 }
 305
 306 void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 307                           struct mtk_plane_state *state,
 308                           struct cmdq_pkt *cmdq_pkt)
 309 {
 310         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 311         struct mtk_plane_pending_state *pending = &state->pending;
 312         unsigned int addr = pending->addr;
 313         unsigned int pitch = pending->pitch & 0xffff;
 314         unsigned int fmt = pending->format;
 315         unsigned int offset = (pending->y << 16) | pending->x;
 316         unsigned int src_size = (pending->height << 16) | pending->width;
 317         unsigned int con;
 318
 319         if (!pending->enable) {
 320                 mtk_ovl_layer_off(dev, idx, cmdq_pkt);
 321                 return;
 322         }
 323
 324         con = ovl_fmt_convert(ovl, fmt);
 325         if (state->base.fb && state->base.fb->format->has_alpha)
 326                 con |= OVL_CON_AEN | OVL_CON_ALPHA;
 327
 328         if (pending->rotation & DRM_MODE_REFLECT_Y) {
 329                 con |= OVL_CON_VIRT_FLIP;
 330                 addr += (pending->height - 1) * pending->pitch;
 331         }
 332
 333         if (pending->rotation & DRM_MODE_REFLECT_X) {
 334                 con |= OVL_CON_HORZ_FLIP;
 335                 addr += pending->pitch - 1;
 336         }
 337
 338         mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
 339                               DISP_REG_OVL_CON(idx));
 340         mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs,
 341                               DISP_REG_OVL_PITCH(idx));
 342         mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
 343                               DISP_REG_OVL_SRC_SIZE(idx));
 344         mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
 345                               DISP_REG_OVL_OFFSET(idx));
 346         mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
 347                               DISP_REG_OVL_ADDR(ovl, idx));
 348
 349         mtk_ovl_layer_on(dev, idx, cmdq_pkt);
 350 }
 351
 352 void mtk_ovl_bgclr_in_on(struct device *dev)
 353 {
 354         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 355         unsigned int reg;
 356
 357         reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 358         reg = reg | OVL_BGCLR_SEL_IN;
 359         writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 360 }
 361
 362 void mtk_ovl_bgclr_in_off(struct device *dev)
 363 {
 364         struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 365         unsigned int reg;
 366
 367         reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 368         reg = reg & ~OVL_BGCLR_SEL_IN;
 369         writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 370 }
 371
 372 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
 373                              void *data)
 374 {
 375         return 0;
 376 }
 377
 378 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
 379                                 void *data)
 380 {
 381 }
 382
 383 static const struct component_ops mtk_disp_ovl_component_ops = {
 384         .bind   = mtk_disp_ovl_bind,
 385         .unbind = mtk_disp_ovl_unbind,
 386 };
 387
 388 static int mtk_disp_ovl_probe(struct platform_device *pdev)
 389 {
 390         struct device *dev = &pdev->dev;
 391         struct mtk_disp_ovl *priv;
 392         struct resource *res;
 393         int irq;
 394         int ret;
 395
 396         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 397         if (!priv)
 398                 return -ENOMEM;
 399
 400         irq = platform_get_irq(pdev, 0);
 401         if (irq < 0)
 402                 return irq;
 403
 404         priv->clk = devm_clk_get(dev, NULL);
 405         if (IS_ERR(priv->clk)) {
 406                 dev_err(dev, "failed to get ovl clk\n");
 407                 return PTR_ERR(priv->clk);
 408         }
 409
 410         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 411         priv->regs = devm_ioremap_resource(dev, res);
 412         if (IS_ERR(priv->regs)) {
 413                 dev_err(dev, "failed to ioremap ovl\n");
 414                 return PTR_ERR(priv->regs);
 415         }
 416 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 417         ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
 418         if (ret)
 419                 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
 420 #endif
 421
 422         priv->data = of_device_get_match_data(dev);
 423         platform_set_drvdata(pdev, priv);
 424
 425         ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
 426                                IRQF_TRIGGER_NONE, dev_name(dev), priv);
 427         if (ret < 0) {
 428                 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
 429                 return ret;
 430         }
 431
 432         pm_runtime_enable(dev);
 433
 434         ret = component_add(dev, &mtk_disp_ovl_component_ops);
 435         if (ret) {
 436                 pm_runtime_disable(dev);
 437                 dev_err(dev, "Failed to add component: %d\n", ret);
 438         }
 439
 440         return ret;
 441 }
 442
 443 static int mtk_disp_ovl_remove(struct platform_device *pdev)
 444 {
 445         component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
 446         pm_runtime_disable(&pdev->dev);
 447
 448         return 0;
 449 }
 450
 451 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
 452         .addr = DISP_REG_OVL_ADDR_MT2701,
 453         .gmc_bits = 8,
 454         .layer_nr = 4,
 455         .fmt_rgb565_is_0 = false,
 456 };
 457
 458 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
 459         .addr = DISP_REG_OVL_ADDR_MT8173,
 460         .gmc_bits = 8,
 461         .layer_nr = 4,
 462         .fmt_rgb565_is_0 = true,
 463 };
 464
 465 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
 466         .addr = DISP_REG_OVL_ADDR_MT8173,
 467         .gmc_bits = 10,
 468         .layer_nr = 4,
 469         .fmt_rgb565_is_0 = true,
 470 };
 471
 472 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
 473         .addr = DISP_REG_OVL_ADDR_MT8173,
 474         .gmc_bits = 10,
 475         .layer_nr = 2,
 476         .fmt_rgb565_is_0 = true,
 477 };
 478
 479 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
 480         .addr = DISP_REG_OVL_ADDR_MT8173,
 481         .gmc_bits = 10,
 482         .layer_nr = 4,
 483         .fmt_rgb565_is_0 = true,
 484         .smi_id_en = true,
 485 };
 486
 487 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
 488         .addr = DISP_REG_OVL_ADDR_MT8173,
 489         .gmc_bits = 10,
 490         .layer_nr = 2,
 491         .fmt_rgb565_is_0 = true,
 492         .smi_id_en = true,
 493 };
 494
 495 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
 496         { .compatible = "mediatek,mt2701-disp-ovl",
 497           .data = &mt2701_ovl_driver_data},
 498         { .compatible = "mediatek,mt8173-disp-ovl",
 499           .data = &mt8173_ovl_driver_data},
 500         { .compatible = "mediatek,mt8183-disp-ovl",
 501           .data = &mt8183_ovl_driver_data},
 502         { .compatible = "mediatek,mt8183-disp-ovl-2l",
 503           .data = &mt8183_ovl_2l_driver_data},
 504         { .compatible = "mediatek,mt8192-disp-ovl",
 505           .data = &mt8192_ovl_driver_data},
 506         { .compatible = "mediatek,mt8192-disp-ovl-2l",
 507           .data = &mt8192_ovl_2l_driver_data},
 508         {},
 509 };
 510 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
 511
 512 struct platform_driver mtk_disp_ovl_driver = {
 513         .probe          = mtk_disp_ovl_probe,
 514         .remove         = mtk_disp_ovl_remove,
 515         .driver         = {
 516                 .name   = "mediatek-disp-ovl",
 517                 .owner  = THIS_MODULE,
 518                 .of_match_table = mtk_disp_ovl_driver_dt_match,
 519         },
 520 };