2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <drm/drm_managed.h>
25 #include <linux/pm_runtime.h>
27 #include "gt/intel_engine_regs.h"
28 #include "gt/intel_gt_regs.h"
31 #include "i915_iosf_mbi.h"
33 #include "i915_trace.h"
34 #include "i915_vgpu.h"
36 #define FORCEWAKE_ACK_TIMEOUT_MS 50
37 #define GT_FIFO_TIMEOUT_MS 10
39 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
42 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
44 uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
48 intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
50 spin_lock_init(&i915->mmio_debug.lock);
51 i915->mmio_debug.unclaimed_mmio_check = 1;
53 i915->uncore.debug = &i915->mmio_debug;
56 static void mmio_debug_suspend(struct intel_uncore *uncore)
61 spin_lock(&uncore->debug->lock);
63 /* Save and disable mmio debugging for the user bypass */
64 if (!uncore->debug->suspend_count++) {
65 uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check;
66 uncore->debug->unclaimed_mmio_check = 0;
69 spin_unlock(&uncore->debug->lock);
72 static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
74 static void mmio_debug_resume(struct intel_uncore *uncore)
79 spin_lock(&uncore->debug->lock);
81 if (!--uncore->debug->suspend_count)
82 uncore->debug->unclaimed_mmio_check = uncore->debug->saved_mmio_check;
84 if (check_for_unclaimed_mmio(uncore))
85 drm_info(&uncore->i915->drm,
86 "Invalid mmio detected during user access\n");
88 spin_unlock(&uncore->debug->lock);
91 static const char * const forcewake_domain_names[] = {
111 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
113 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
115 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
116 return forcewake_domain_names[id];
123 #define fw_ack(d) readl((d)->reg_ack)
124 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
125 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
128 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
131 * We don't really know if the powerwell for the forcewake domain we are
132 * trying to reset here does exist at this point (engines could be fused
133 * off in ICL+), so no waiting for acks
135 /* WaRsClearFWBitsAtReset */
136 if (GRAPHICS_VER(d->uncore->i915) >= 12)
143 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
145 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
146 d->uncore->fw_domains_timer |= d->mask;
148 hrtimer_start_range_ns(&d->timer,
155 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
159 return wait_for_atomic((fw_ack(d) & ack) == value,
160 FORCEWAKE_ACK_TIMEOUT_MS);
164 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
167 return __wait_for_ack(d, ack, 0);
171 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
174 return __wait_for_ack(d, ack, ack);
178 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
180 if (!wait_ack_clear(d, FORCEWAKE_KERNEL))
184 drm_err(&d->uncore->i915->drm,
185 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n",
186 intel_uncore_forcewake_domain_to_str(d->id));
188 drm_err(&d->uncore->i915->drm,
189 "%s: timed out waiting for forcewake ack to clear.\n",
190 intel_uncore_forcewake_domain_to_str(d->id));
192 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
201 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
202 const enum ack_type type)
204 const u32 ack_bit = FORCEWAKE_KERNEL;
205 const u32 value = type == ACK_SET ? ack_bit : 0;
210 * There is a possibility of driver's wake request colliding
211 * with hardware's own wake requests and that can cause
212 * hardware to not deliver the driver's ack message.
214 * Use a fallback bit toggle to kick the gpu state machine
215 * in the hope that the original ack will be delivered along with
218 * This workaround is described in HSDES #1604254524 and it's known as:
219 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
220 * although the name is a bit misleading.
225 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
227 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
228 /* Give gt some time to relax before the polling frenzy */
230 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
232 ack_detected = (fw_ack(d) & ack_bit) == value;
234 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
235 } while (!ack_detected && pass++ < 10);
237 drm_dbg(&d->uncore->i915->drm,
238 "%s had to use fallback to %s ack, 0x%x (passes %u)\n",
239 intel_uncore_forcewake_domain_to_str(d->id),
240 type == ACK_SET ? "set" : "clear",
244 return ack_detected ? 0 : -ETIMEDOUT;
248 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
250 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
253 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
254 fw_domain_wait_ack_clear(d);
258 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
260 fw_set(d, FORCEWAKE_KERNEL);
264 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
266 if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
267 drm_err(&d->uncore->i915->drm,
268 "%s: timed out waiting for forcewake ack request.\n",
269 intel_uncore_forcewake_domain_to_str(d->id));
270 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
275 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
277 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
280 if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
281 fw_domain_wait_ack_set(d);
285 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
287 fw_clear(d, FORCEWAKE_KERNEL);
291 fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
293 struct intel_uncore_forcewake_domain *d;
296 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
298 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
299 fw_domain_wait_ack_clear(d);
303 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
304 fw_domain_wait_ack_set(d);
306 uncore->fw_domains_active |= fw_domains;
310 fw_domains_get_with_fallback(struct intel_uncore *uncore,
311 enum forcewake_domains fw_domains)
313 struct intel_uncore_forcewake_domain *d;
316 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
318 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
319 fw_domain_wait_ack_clear_fallback(d);
323 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
324 fw_domain_wait_ack_set_fallback(d);
326 uncore->fw_domains_active |= fw_domains;
330 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
332 struct intel_uncore_forcewake_domain *d;
335 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
337 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
340 uncore->fw_domains_active &= ~fw_domains;
344 fw_domains_reset(struct intel_uncore *uncore,
345 enum forcewake_domains fw_domains)
347 struct intel_uncore_forcewake_domain *d;
353 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
355 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
359 static inline u32 gt_thread_status(struct intel_uncore *uncore)
363 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
364 val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
369 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
372 * w/a for a sporadic read returning 0 by waiting for the GT
375 drm_WARN_ONCE(&uncore->i915->drm,
376 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
377 "GT thread status wait timed out\n");
380 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
381 enum forcewake_domains fw_domains)
383 fw_domains_get_normal(uncore, fw_domains);
385 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
386 __gen6_gt_wait_for_thread_c0(uncore);
389 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
391 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
393 return count & GT_FIFO_FREE_ENTRIES_MASK;
396 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
400 /* On VLV, FIFO will be shared by both SW and HW.
401 * So, we need to read the FREE_ENTRIES everytime */
402 if (IS_VALLEYVIEW(uncore->i915))
403 n = fifo_free_entries(uncore);
405 n = uncore->fifo_count;
407 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
408 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
409 GT_FIFO_NUM_RESERVED_ENTRIES,
410 GT_FIFO_TIMEOUT_MS)) {
411 drm_dbg(&uncore->i915->drm,
412 "GT_FIFO timeout, entries: %u\n", n);
417 uncore->fifo_count = n - 1;
420 static enum hrtimer_restart
421 intel_uncore_fw_release_timer(struct hrtimer *timer)
423 struct intel_uncore_forcewake_domain *domain =
424 container_of(timer, struct intel_uncore_forcewake_domain, timer);
425 struct intel_uncore *uncore = domain->uncore;
426 unsigned long irqflags;
428 assert_rpm_device_not_suspended(uncore->rpm);
430 if (xchg(&domain->active, false))
431 return HRTIMER_RESTART;
433 spin_lock_irqsave(&uncore->lock, irqflags);
435 uncore->fw_domains_timer &= ~domain->mask;
437 GEM_BUG_ON(!domain->wake_count);
438 if (--domain->wake_count == 0)
439 fw_domains_put(uncore, domain->mask);
441 spin_unlock_irqrestore(&uncore->lock, irqflags);
443 return HRTIMER_NORESTART;
446 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
448 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
450 unsigned long irqflags;
451 struct intel_uncore_forcewake_domain *domain;
452 int retry_count = 100;
453 enum forcewake_domains fw, active_domains;
455 iosf_mbi_assert_punit_acquired();
457 /* Hold uncore.lock across reset to prevent any register access
458 * with forcewake not set correctly. Wait until all pending
459 * timers are run before holding.
466 for_each_fw_domain(domain, uncore, tmp) {
467 smp_store_mb(domain->active, false);
468 if (hrtimer_cancel(&domain->timer) == 0)
471 intel_uncore_fw_release_timer(&domain->timer);
474 spin_lock_irqsave(&uncore->lock, irqflags);
476 for_each_fw_domain(domain, uncore, tmp) {
477 if (hrtimer_active(&domain->timer))
478 active_domains |= domain->mask;
481 if (active_domains == 0)
484 if (--retry_count == 0) {
485 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
489 spin_unlock_irqrestore(&uncore->lock, irqflags);
493 drm_WARN_ON(&uncore->i915->drm, active_domains);
495 fw = uncore->fw_domains_active;
497 fw_domains_put(uncore, fw);
499 fw_domains_reset(uncore, uncore->fw_domains);
500 assert_forcewakes_inactive(uncore);
502 spin_unlock_irqrestore(&uncore->lock, irqflags);
504 return fw; /* track the lost user forcewake domains */
508 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
512 dbg = __raw_uncore_read32(uncore, FPGA_DBG);
513 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
517 * Bugs in PCI programming (or failing hardware) can occasionally cause
518 * us to lose access to the MMIO BAR. When this happens, register
519 * reads will come back with 0xFFFFFFFF for every register and things
520 * go bad very quickly. Let's try to detect that special case and at
521 * least try to print a more informative message about what has
524 * During normal operation the FPGA_DBG register has several unused
525 * bits that will always read back as 0's so we can use them as canaries
526 * to recognize when MMIO accesses are just busted.
528 if (unlikely(dbg == ~0))
529 drm_err(&uncore->i915->drm,
530 "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
532 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
538 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
542 cer = __raw_uncore_read32(uncore, CLAIM_ER);
543 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
546 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
552 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
556 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
558 if (unlikely(fifodbg)) {
559 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
560 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
567 check_for_unclaimed_mmio(struct intel_uncore *uncore)
571 lockdep_assert_held(&uncore->debug->lock);
573 if (uncore->debug->suspend_count)
576 if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
577 ret |= fpga_check_for_unclaimed_mmio(uncore);
579 if (intel_uncore_has_dbg_unclaimed(uncore))
580 ret |= vlv_check_for_unclaimed_mmio(uncore);
582 if (intel_uncore_has_fifo(uncore))
583 ret |= gen6_check_for_fifo_debug(uncore);
588 static void forcewake_early_sanitize(struct intel_uncore *uncore,
589 unsigned int restore_forcewake)
591 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
593 /* WaDisableShadowRegForCpd:chv */
594 if (IS_CHERRYVIEW(uncore->i915)) {
595 __raw_uncore_write32(uncore, GTFIFOCTL,
596 __raw_uncore_read32(uncore, GTFIFOCTL) |
597 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
598 GT_FIFO_CTL_RC6_POLICY_STALL);
601 iosf_mbi_punit_acquire();
602 intel_uncore_forcewake_reset(uncore);
603 if (restore_forcewake) {
604 spin_lock_irq(&uncore->lock);
605 fw_domains_get(uncore, restore_forcewake);
607 if (intel_uncore_has_fifo(uncore))
608 uncore->fifo_count = fifo_free_entries(uncore);
609 spin_unlock_irq(&uncore->lock);
611 iosf_mbi_punit_release();
614 void intel_uncore_suspend(struct intel_uncore *uncore)
616 if (!intel_uncore_has_forcewake(uncore))
619 iosf_mbi_punit_acquire();
620 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
621 &uncore->pmic_bus_access_nb);
622 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
623 iosf_mbi_punit_release();
626 void intel_uncore_resume_early(struct intel_uncore *uncore)
628 unsigned int restore_forcewake;
630 if (intel_uncore_unclaimed_mmio(uncore))
631 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
633 if (!intel_uncore_has_forcewake(uncore))
636 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
637 forcewake_early_sanitize(uncore, restore_forcewake);
639 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
642 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
644 if (!intel_uncore_has_forcewake(uncore))
647 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
650 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
651 enum forcewake_domains fw_domains)
653 struct intel_uncore_forcewake_domain *domain;
656 fw_domains &= uncore->fw_domains;
658 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
659 if (domain->wake_count++) {
660 fw_domains &= ~domain->mask;
661 domain->active = true;
666 fw_domains_get(uncore, fw_domains);
670 * intel_uncore_forcewake_get - grab forcewake domain references
671 * @uncore: the intel_uncore structure
672 * @fw_domains: forcewake domains to get reference on
674 * This function can be used get GT's forcewake domain references.
675 * Normal register access will handle the forcewake domains automatically.
676 * However if some sequence requires the GT to not power down a particular
677 * forcewake domains this function should be called at the beginning of the
678 * sequence. And subsequently the reference should be dropped by symmetric
679 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
680 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
682 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
683 enum forcewake_domains fw_domains)
685 unsigned long irqflags;
687 if (!uncore->fw_get_funcs)
690 assert_rpm_wakelock_held(uncore->rpm);
692 spin_lock_irqsave(&uncore->lock, irqflags);
693 __intel_uncore_forcewake_get(uncore, fw_domains);
694 spin_unlock_irqrestore(&uncore->lock, irqflags);
698 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
699 * @uncore: the intel_uncore structure
701 * This function is a wrapper around intel_uncore_forcewake_get() to acquire
702 * the GT powerwell and in the process disable our debugging for the
703 * duration of userspace's bypass.
705 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
707 spin_lock_irq(&uncore->lock);
708 if (!uncore->user_forcewake_count++) {
709 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
710 mmio_debug_suspend(uncore);
712 spin_unlock_irq(&uncore->lock);
716 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
717 * @uncore: the intel_uncore structure
719 * This function complements intel_uncore_forcewake_user_get() and releases
720 * the GT powerwell taken on behalf of the userspace bypass.
722 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
724 spin_lock_irq(&uncore->lock);
725 if (!--uncore->user_forcewake_count) {
726 mmio_debug_resume(uncore);
727 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
729 spin_unlock_irq(&uncore->lock);
733 * intel_uncore_forcewake_get__locked - grab forcewake domain references
734 * @uncore: the intel_uncore structure
735 * @fw_domains: forcewake domains to get reference on
737 * See intel_uncore_forcewake_get(). This variant places the onus
738 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
740 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
741 enum forcewake_domains fw_domains)
743 lockdep_assert_held(&uncore->lock);
745 if (!uncore->fw_get_funcs)
748 __intel_uncore_forcewake_get(uncore, fw_domains);
751 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
752 enum forcewake_domains fw_domains,
755 struct intel_uncore_forcewake_domain *domain;
758 fw_domains &= uncore->fw_domains;
760 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
761 GEM_BUG_ON(!domain->wake_count);
763 if (--domain->wake_count) {
764 domain->active = true;
769 !(domain->uncore->fw_domains_timer & domain->mask))
770 fw_domain_arm_timer(domain);
772 fw_domains_put(uncore, domain->mask);
777 * intel_uncore_forcewake_put - release a forcewake domain reference
778 * @uncore: the intel_uncore structure
779 * @fw_domains: forcewake domains to put references
781 * This function drops the device-level forcewakes for specified
782 * domains obtained by intel_uncore_forcewake_get().
784 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
785 enum forcewake_domains fw_domains)
787 unsigned long irqflags;
789 if (!uncore->fw_get_funcs)
792 spin_lock_irqsave(&uncore->lock, irqflags);
793 __intel_uncore_forcewake_put(uncore, fw_domains, false);
794 spin_unlock_irqrestore(&uncore->lock, irqflags);
797 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
798 enum forcewake_domains fw_domains)
800 unsigned long irqflags;
802 if (!uncore->fw_get_funcs)
805 spin_lock_irqsave(&uncore->lock, irqflags);
806 __intel_uncore_forcewake_put(uncore, fw_domains, true);
807 spin_unlock_irqrestore(&uncore->lock, irqflags);
811 * intel_uncore_forcewake_flush - flush the delayed release
812 * @uncore: the intel_uncore structure
813 * @fw_domains: forcewake domains to flush
815 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
816 enum forcewake_domains fw_domains)
818 struct intel_uncore_forcewake_domain *domain;
821 if (!uncore->fw_get_funcs)
824 fw_domains &= uncore->fw_domains;
825 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
826 WRITE_ONCE(domain->active, false);
827 if (hrtimer_cancel(&domain->timer))
828 intel_uncore_fw_release_timer(&domain->timer);
833 * intel_uncore_forcewake_put__locked - release forcewake domain references
834 * @uncore: the intel_uncore structure
835 * @fw_domains: forcewake domains to put references
837 * See intel_uncore_forcewake_put(). This variant places the onus
838 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
840 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
841 enum forcewake_domains fw_domains)
843 lockdep_assert_held(&uncore->lock);
845 if (!uncore->fw_get_funcs)
848 __intel_uncore_forcewake_put(uncore, fw_domains, false);
851 void assert_forcewakes_inactive(struct intel_uncore *uncore)
853 if (!uncore->fw_get_funcs)
856 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
857 "Expected all fw_domains to be inactive, but %08x are still on\n",
858 uncore->fw_domains_active);
861 void assert_forcewakes_active(struct intel_uncore *uncore,
862 enum forcewake_domains fw_domains)
864 struct intel_uncore_forcewake_domain *domain;
867 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
870 if (!uncore->fw_get_funcs)
873 spin_lock_irq(&uncore->lock);
875 assert_rpm_wakelock_held(uncore->rpm);
877 fw_domains &= uncore->fw_domains;
878 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active,
879 "Expected %08x fw_domains to be active, but %08x are off\n",
880 fw_domains, fw_domains & ~uncore->fw_domains_active);
883 * Check that the caller has an explicit wakeref and we don't mistake
884 * it for the auto wakeref.
886 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
887 unsigned int actual = READ_ONCE(domain->wake_count);
888 unsigned int expect = 1;
890 if (uncore->fw_domains_timer & domain->mask)
891 expect++; /* pending automatic release */
893 if (drm_WARN(&uncore->i915->drm, actual < expect,
894 "Expected domain %d to be held awake by caller, count=%d\n",
899 spin_unlock_irq(&uncore->lock);
903 * We give fast paths for the really cool registers. The second range includes
904 * media domains (and the GSC starting from Xe_LPM+)
906 #define NEEDS_FORCE_WAKE(reg) ({ \
908 __reg < 0x40000 || __reg >= 0x116000; \
911 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
913 if (offset < entry->start)
915 else if (offset > entry->end)
921 /* Copied and "macroized" from lib/bsearch.c */
922 #define BSEARCH(key, base, num, cmp) ({ \
923 unsigned int start__ = 0, end__ = (num); \
924 typeof(base) result__ = NULL; \
925 while (start__ < end__) { \
926 unsigned int mid__ = start__ + (end__ - start__) / 2; \
927 int ret__ = (cmp)((key), (base) + mid__); \
930 } else if (ret__ > 0) { \
931 start__ = mid__ + 1; \
933 result__ = (base) + mid__; \
940 static enum forcewake_domains
941 find_fw_domain(struct intel_uncore *uncore, u32 offset)
943 const struct intel_forcewake_range *entry;
945 if (IS_GSI_REG(offset))
946 offset += uncore->gsi_offset;
948 entry = BSEARCH(offset,
949 uncore->fw_domains_table,
950 uncore->fw_domains_table_entries,
957 * The list of FW domains depends on the SKU in gen11+ so we
958 * can't determine it statically. We use FORCEWAKE_ALL and
959 * translate it here to the list of available domains.
961 if (entry->domains == FORCEWAKE_ALL)
962 return uncore->fw_domains;
964 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains,
965 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
966 entry->domains & ~uncore->fw_domains, offset);
968 return entry->domains;
972 * Shadowed register tables describe special register ranges that i915 is
973 * allowed to write to without acquiring forcewake. If these registers' power
974 * wells are down, the hardware will save values written by i915 to a shadow
975 * copy and automatically transfer them into the real register the next time
976 * the power well is woken up. Shadowing only applies to writes; forcewake
977 * must still be acquired when reading from registers in these ranges.
979 * The documentation for shadowed registers is somewhat spotty on older
980 * platforms. However missing registers from these lists is non-fatal; it just
981 * means we'll wake up the hardware for some register accesses where we didn't
984 * The ranges listed in these tables must be sorted by offset.
986 * When adding new tables here, please also add them to
987 * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be
988 * scanned for obvious mistakes or typos by the selftests.
991 static const struct i915_range gen8_shadowed_regs[] = {
992 { .start = 0x2030, .end = 0x2030 },
993 { .start = 0xA008, .end = 0xA00C },
994 { .start = 0x12030, .end = 0x12030 },
995 { .start = 0x1a030, .end = 0x1a030 },
996 { .start = 0x22030, .end = 0x22030 },
999 static const struct i915_range gen11_shadowed_regs[] = {
1000 { .start = 0x2030, .end = 0x2030 },
1001 { .start = 0x2550, .end = 0x2550 },
1002 { .start = 0xA008, .end = 0xA00C },
1003 { .start = 0x22030, .end = 0x22030 },
1004 { .start = 0x22230, .end = 0x22230 },
1005 { .start = 0x22510, .end = 0x22550 },
1006 { .start = 0x1C0030, .end = 0x1C0030 },
1007 { .start = 0x1C0230, .end = 0x1C0230 },
1008 { .start = 0x1C0510, .end = 0x1C0550 },
1009 { .start = 0x1C4030, .end = 0x1C4030 },
1010 { .start = 0x1C4230, .end = 0x1C4230 },
1011 { .start = 0x1C4510, .end = 0x1C4550 },
1012 { .start = 0x1C8030, .end = 0x1C8030 },
1013 { .start = 0x1C8230, .end = 0x1C8230 },
1014 { .start = 0x1C8510, .end = 0x1C8550 },
1015 { .start = 0x1D0030, .end = 0x1D0030 },
1016 { .start = 0x1D0230, .end = 0x1D0230 },
1017 { .start = 0x1D0510, .end = 0x1D0550 },
1018 { .start = 0x1D4030, .end = 0x1D4030 },
1019 { .start = 0x1D4230, .end = 0x1D4230 },
1020 { .start = 0x1D4510, .end = 0x1D4550 },
1021 { .start = 0x1D8030, .end = 0x1D8030 },
1022 { .start = 0x1D8230, .end = 0x1D8230 },
1023 { .start = 0x1D8510, .end = 0x1D8550 },
1026 static const struct i915_range gen12_shadowed_regs[] = {
1027 { .start = 0x2030, .end = 0x2030 },
1028 { .start = 0x2510, .end = 0x2550 },
1029 { .start = 0xA008, .end = 0xA00C },
1030 { .start = 0xA188, .end = 0xA188 },
1031 { .start = 0xA278, .end = 0xA278 },
1032 { .start = 0xA540, .end = 0xA56C },
1033 { .start = 0xC4C8, .end = 0xC4C8 },
1034 { .start = 0xC4D4, .end = 0xC4D4 },
1035 { .start = 0xC600, .end = 0xC600 },
1036 { .start = 0x22030, .end = 0x22030 },
1037 { .start = 0x22510, .end = 0x22550 },
1038 { .start = 0x1C0030, .end = 0x1C0030 },
1039 { .start = 0x1C0510, .end = 0x1C0550 },
1040 { .start = 0x1C4030, .end = 0x1C4030 },
1041 { .start = 0x1C4510, .end = 0x1C4550 },
1042 { .start = 0x1C8030, .end = 0x1C8030 },
1043 { .start = 0x1C8510, .end = 0x1C8550 },
1044 { .start = 0x1D0030, .end = 0x1D0030 },
1045 { .start = 0x1D0510, .end = 0x1D0550 },
1046 { .start = 0x1D4030, .end = 0x1D4030 },
1047 { .start = 0x1D4510, .end = 0x1D4550 },
1048 { .start = 0x1D8030, .end = 0x1D8030 },
1049 { .start = 0x1D8510, .end = 0x1D8550 },
1052 * The rest of these ranges are specific to Xe_HP and beyond, but
1053 * are reserved/unused ranges on earlier gen12 platforms, so they can
1054 * be safely added to the gen12 table.
1056 { .start = 0x1E0030, .end = 0x1E0030 },
1057 { .start = 0x1E0510, .end = 0x1E0550 },
1058 { .start = 0x1E4030, .end = 0x1E4030 },
1059 { .start = 0x1E4510, .end = 0x1E4550 },
1060 { .start = 0x1E8030, .end = 0x1E8030 },
1061 { .start = 0x1E8510, .end = 0x1E8550 },
1062 { .start = 0x1F0030, .end = 0x1F0030 },
1063 { .start = 0x1F0510, .end = 0x1F0550 },
1064 { .start = 0x1F4030, .end = 0x1F4030 },
1065 { .start = 0x1F4510, .end = 0x1F4550 },
1066 { .start = 0x1F8030, .end = 0x1F8030 },
1067 { .start = 0x1F8510, .end = 0x1F8550 },
1070 static const struct i915_range dg2_shadowed_regs[] = {
1071 { .start = 0x2030, .end = 0x2030 },
1072 { .start = 0x2510, .end = 0x2550 },
1073 { .start = 0xA008, .end = 0xA00C },
1074 { .start = 0xA188, .end = 0xA188 },
1075 { .start = 0xA278, .end = 0xA278 },
1076 { .start = 0xA540, .end = 0xA56C },
1077 { .start = 0xC4C8, .end = 0xC4C8 },
1078 { .start = 0xC4E0, .end = 0xC4E0 },
1079 { .start = 0xC600, .end = 0xC600 },
1080 { .start = 0xC658, .end = 0xC658 },
1081 { .start = 0x22030, .end = 0x22030 },
1082 { .start = 0x22510, .end = 0x22550 },
1083 { .start = 0x1C0030, .end = 0x1C0030 },
1084 { .start = 0x1C0510, .end = 0x1C0550 },
1085 { .start = 0x1C4030, .end = 0x1C4030 },
1086 { .start = 0x1C4510, .end = 0x1C4550 },
1087 { .start = 0x1C8030, .end = 0x1C8030 },
1088 { .start = 0x1C8510, .end = 0x1C8550 },
1089 { .start = 0x1D0030, .end = 0x1D0030 },
1090 { .start = 0x1D0510, .end = 0x1D0550 },
1091 { .start = 0x1D4030, .end = 0x1D4030 },
1092 { .start = 0x1D4510, .end = 0x1D4550 },
1093 { .start = 0x1D8030, .end = 0x1D8030 },
1094 { .start = 0x1D8510, .end = 0x1D8550 },
1095 { .start = 0x1E0030, .end = 0x1E0030 },
1096 { .start = 0x1E0510, .end = 0x1E0550 },
1097 { .start = 0x1E4030, .end = 0x1E4030 },
1098 { .start = 0x1E4510, .end = 0x1E4550 },
1099 { .start = 0x1E8030, .end = 0x1E8030 },
1100 { .start = 0x1E8510, .end = 0x1E8550 },
1101 { .start = 0x1F0030, .end = 0x1F0030 },
1102 { .start = 0x1F0510, .end = 0x1F0550 },
1103 { .start = 0x1F4030, .end = 0x1F4030 },
1104 { .start = 0x1F4510, .end = 0x1F4550 },
1105 { .start = 0x1F8030, .end = 0x1F8030 },
1106 { .start = 0x1F8510, .end = 0x1F8550 },
1109 static const struct i915_range pvc_shadowed_regs[] = {
1110 { .start = 0x2030, .end = 0x2030 },
1111 { .start = 0x2510, .end = 0x2550 },
1112 { .start = 0xA008, .end = 0xA00C },
1113 { .start = 0xA188, .end = 0xA188 },
1114 { .start = 0xA278, .end = 0xA278 },
1115 { .start = 0xA540, .end = 0xA56C },
1116 { .start = 0xC4C8, .end = 0xC4C8 },
1117 { .start = 0xC4E0, .end = 0xC4E0 },
1118 { .start = 0xC600, .end = 0xC600 },
1119 { .start = 0xC658, .end = 0xC658 },
1120 { .start = 0x22030, .end = 0x22030 },
1121 { .start = 0x22510, .end = 0x22550 },
1122 { .start = 0x1C0030, .end = 0x1C0030 },
1123 { .start = 0x1C0510, .end = 0x1C0550 },
1124 { .start = 0x1C4030, .end = 0x1C4030 },
1125 { .start = 0x1C4510, .end = 0x1C4550 },
1126 { .start = 0x1C8030, .end = 0x1C8030 },
1127 { .start = 0x1C8510, .end = 0x1C8550 },
1128 { .start = 0x1D0030, .end = 0x1D0030 },
1129 { .start = 0x1D0510, .end = 0x1D0550 },
1130 { .start = 0x1D4030, .end = 0x1D4030 },
1131 { .start = 0x1D4510, .end = 0x1D4550 },
1132 { .start = 0x1D8030, .end = 0x1D8030 },
1133 { .start = 0x1D8510, .end = 0x1D8550 },
1134 { .start = 0x1E0030, .end = 0x1E0030 },
1135 { .start = 0x1E0510, .end = 0x1E0550 },
1136 { .start = 0x1E4030, .end = 0x1E4030 },
1137 { .start = 0x1E4510, .end = 0x1E4550 },
1138 { .start = 0x1E8030, .end = 0x1E8030 },
1139 { .start = 0x1E8510, .end = 0x1E8550 },
1140 { .start = 0x1F0030, .end = 0x1F0030 },
1141 { .start = 0x1F0510, .end = 0x1F0550 },
1142 { .start = 0x1F4030, .end = 0x1F4030 },
1143 { .start = 0x1F4510, .end = 0x1F4550 },
1144 { .start = 0x1F8030, .end = 0x1F8030 },
1145 { .start = 0x1F8510, .end = 0x1F8550 },
1148 static const struct i915_range mtl_shadowed_regs[] = {
1149 { .start = 0x2030, .end = 0x2030 },
1150 { .start = 0x2510, .end = 0x2550 },
1151 { .start = 0xA008, .end = 0xA00C },
1152 { .start = 0xA188, .end = 0xA188 },
1153 { .start = 0xA278, .end = 0xA278 },
1154 { .start = 0xA540, .end = 0xA56C },
1155 { .start = 0xC050, .end = 0xC050 },
1156 { .start = 0xC340, .end = 0xC340 },
1157 { .start = 0xC4C8, .end = 0xC4C8 },
1158 { .start = 0xC4E0, .end = 0xC4E0 },
1159 { .start = 0xC600, .end = 0xC600 },
1160 { .start = 0xC658, .end = 0xC658 },
1161 { .start = 0xCFD4, .end = 0xCFDC },
1162 { .start = 0x22030, .end = 0x22030 },
1163 { .start = 0x22510, .end = 0x22550 },
1166 static const struct i915_range xelpmp_shadowed_regs[] = {
1167 { .start = 0x1C0030, .end = 0x1C0030 },
1168 { .start = 0x1C0510, .end = 0x1C0550 },
1169 { .start = 0x1C8030, .end = 0x1C8030 },
1170 { .start = 0x1C8510, .end = 0x1C8550 },
1171 { .start = 0x1D0030, .end = 0x1D0030 },
1172 { .start = 0x1D0510, .end = 0x1D0550 },
1173 { .start = 0x38A008, .end = 0x38A00C },
1174 { .start = 0x38A188, .end = 0x38A188 },
1175 { .start = 0x38A278, .end = 0x38A278 },
1176 { .start = 0x38A540, .end = 0x38A56C },
1177 { .start = 0x38A618, .end = 0x38A618 },
1178 { .start = 0x38C050, .end = 0x38C050 },
1179 { .start = 0x38C340, .end = 0x38C340 },
1180 { .start = 0x38C4C8, .end = 0x38C4C8 },
1181 { .start = 0x38C4E0, .end = 0x38C4E4 },
1182 { .start = 0x38C600, .end = 0x38C600 },
1183 { .start = 0x38C658, .end = 0x38C658 },
1184 { .start = 0x38CFD4, .end = 0x38CFDC },
1187 static int mmio_range_cmp(u32 key, const struct i915_range *range)
1189 if (key < range->start)
1191 else if (key > range->end)
1197 static bool is_shadowed(struct intel_uncore *uncore, u32 offset)
1199 if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table))
1202 if (IS_GSI_REG(offset))
1203 offset += uncore->gsi_offset;
1205 return BSEARCH(offset,
1206 uncore->shadowed_reg_table,
1207 uncore->shadowed_reg_table_entries,
1211 static enum forcewake_domains
1212 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
1214 return FORCEWAKE_RENDER;
1217 #define __fwtable_reg_read_fw_domains(uncore, offset) \
1219 enum forcewake_domains __fwd = 0; \
1220 if (NEEDS_FORCE_WAKE((offset))) \
1221 __fwd = find_fw_domain(uncore, offset); \
1225 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1227 enum forcewake_domains __fwd = 0; \
1228 const u32 __offset = (offset); \
1229 if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
1230 __fwd = find_fw_domain(uncore, __offset); \
1234 #define GEN_FW_RANGE(s, e, d) \
1235 { .start = (s), .end = (e), .domains = (d) }
1238 * All platforms' forcewake tables below must be sorted by offset ranges.
1239 * Furthermore, new forcewake tables added should be "watertight" and have
1240 * no gaps between ranges.
1242 * When there are multiple consecutive ranges listed in the bspec with
1243 * the same forcewake domain, it is customary to combine them into a single
1244 * row in the tables below to keep the tables small and lookups fast.
1245 * Likewise, reserved/unused ranges may be combined with the preceding and/or
1246 * following ranges since the driver will never be making MMIO accesses in
1249 * For example, if the bspec were to list:
1252 * 0x1000 - 0x1fff: GT
1253 * 0x2000 - 0x2cff: GT
1254 * 0x2d00 - 0x2fff: unused/reserved
1255 * 0x3000 - 0xffff: GT
1258 * these could all be represented by a single line in the code:
1260 * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT)
1262 * When adding new forcewake tables here, please also add them to
1263 * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be
1264 * scanned for obvious mistakes or typos by the selftests.
1267 static const struct intel_forcewake_range __gen6_fw_ranges[] = {
1268 GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
1271 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
1272 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1273 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
1274 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
1275 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1276 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
1277 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
1278 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1281 static const struct intel_forcewake_range __chv_fw_ranges[] = {
1282 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1283 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1284 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1285 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1286 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1287 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1288 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1289 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1290 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1291 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1292 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1293 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1294 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1295 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1296 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1297 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1300 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1301 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
1302 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1303 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1304 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1305 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1306 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1307 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1308 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
1309 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1310 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1311 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1312 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1313 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1314 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1315 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
1316 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1317 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
1318 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1319 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1320 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1321 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
1322 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1323 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
1324 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1325 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
1326 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1327 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
1328 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1329 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
1330 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1331 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
1332 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1335 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1336 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
1337 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1338 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1339 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1340 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1341 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1342 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1343 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1344 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1345 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1346 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1347 GEN_FW_RANGE(0x8800, 0x8bff, 0),
1348 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1349 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
1350 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1351 GEN_FW_RANGE(0x9560, 0x95ff, 0),
1352 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
1353 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1354 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
1355 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1356 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
1357 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1358 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
1359 GEN_FW_RANGE(0x24000, 0x2407f, 0),
1360 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
1361 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
1362 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
1363 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
1364 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
1365 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1366 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1367 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1368 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
1369 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1370 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
1373 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1374 GEN_FW_RANGE(0x0, 0x1fff, 0), /*
1375 0x0 - 0xaff: reserved
1376 0xb00 - 0x1fff: always on */
1377 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1378 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT),
1379 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER),
1380 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT),
1381 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1382 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
1384 0x4900 - 0x51ff: reserved */
1385 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
1386 0x5200 - 0x53ff: render
1387 0x5400 - 0x54ff: reserved
1388 0x5500 - 0x7fff: render */
1389 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1390 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1391 GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
1392 0x8160 - 0x817f: reserved
1393 0x8180 - 0x81ff: always on */
1394 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
1395 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1396 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
1398 0x8800 - 0x8fff: reserved
1400 0x9480 - 0x94cf: reserved */
1401 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1402 GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
1403 0x9560 - 0x95ff: always on
1404 0x9600 - 0x97ff: reserved */
1405 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1406 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER),
1407 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /*
1409 0xb480 - 0xbfff: reserved
1410 0xc000 - 0xcfff: gt */
1411 GEN_FW_RANGE(0xd000, 0xd7ff, 0),
1412 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER),
1413 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT),
1414 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /*
1415 0xdc00 - 0xddff: render
1416 0xde00 - 0xde7f: reserved
1417 0xde80 - 0xe8ff: render
1418 0xe900 - 0xefff: reserved */
1419 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /*
1421 0x10000 - 0x147ff: reserved */
1422 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
1423 0x14800 - 0x14fff: render
1424 0x15000 - 0x16dff: reserved
1425 0x16e00 - 0x1bfff: render
1426 0x1c000 - 0x1ffff: reserved */
1427 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0),
1428 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2),
1429 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1430 GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1431 0x24000 - 0x2407f: always on
1432 0x24080 - 0x2417f: reserved */
1433 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
1434 0x24180 - 0x241ff: gt
1435 0x24200 - 0x249ff: reserved */
1436 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
1437 0x24a00 - 0x24a7f: render
1438 0x24a80 - 0x251ff: reserved */
1439 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /*
1440 0x25200 - 0x252ff: gt
1441 0x25300 - 0x255ff: reserved */
1442 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0),
1443 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /*
1444 0x25680 - 0x256ff: VD2
1445 0x25700 - 0x259ff: reserved */
1446 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0),
1447 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /*
1448 0x25a80 - 0x25aff: VD2
1449 0x25b00 - 0x2ffff: reserved */
1450 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1451 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1452 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1453 0x1c0000 - 0x1c2bff: VD0
1454 0x1c2c00 - 0x1c2cff: reserved
1455 0x1c2d00 - 0x1c2dff: VD0
1456 0x1c2e00 - 0x1c3eff: reserved
1457 0x1c3f00 - 0x1c3fff: VD0 */
1458 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1459 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1460 0x1c8000 - 0x1ca0ff: VE0
1461 0x1ca100 - 0x1cbeff: reserved
1462 0x1cbf00 - 0x1cbfff: VE0 */
1463 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
1464 0x1cc000 - 0x1ccfff: VD0
1465 0x1cd000 - 0x1cffff: reserved */
1466 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
1467 0x1d0000 - 0x1d2bff: VD2
1468 0x1d2c00 - 0x1d2cff: reserved
1469 0x1d2d00 - 0x1d2dff: VD2
1470 0x1d2e00 - 0x1d3eff: reserved
1471 0x1d3f00 - 0x1d3fff: VD2 */
1475 * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
1476 * switching it from the GT domain to the render domain.
1478 #define XEHP_FWRANGES(FW_RANGE_D800) \
1479 GEN_FW_RANGE(0x0, 0x1fff, 0), /* \
1480 0x0 - 0xaff: reserved \
1481 0xb00 - 0x1fff: always on */ \
1482 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), \
1483 GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), \
1484 GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* \
1485 0x4b00 - 0x4fff: reserved \
1486 0x5000 - 0x51ff: always on */ \
1487 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), \
1488 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), \
1489 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), \
1490 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* \
1491 0x8160 - 0x817f: reserved \
1492 0x8180 - 0x81ff: always on */ \
1493 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), \
1494 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), \
1495 GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* \
1496 0x8500 - 0x87ff: gt \
1497 0x8800 - 0x8c7f: reserved \
1498 0x8c80 - 0x8cff: gt (DG2 only) */ \
1499 GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* \
1500 0x8d00 - 0x8dff: render (DG2 only) \
1501 0x8e00 - 0x8fff: reserved */ \
1502 GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* \
1503 0x9000 - 0x947f: gt \
1504 0x9480 - 0x94cf: reserved */ \
1505 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), \
1506 GEN_FW_RANGE(0x9560, 0x967f, 0), /* \
1507 0x9560 - 0x95ff: always on \
1508 0x9600 - 0x967f: reserved */ \
1509 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* \
1510 0x9680 - 0x96ff: render (DG2 only) \
1511 0x9700 - 0x97ff: reserved */ \
1512 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* \
1513 0x9800 - 0xb4ff: gt \
1514 0xb500 - 0xbfff: reserved \
1515 0xc000 - 0xcfff: gt */ \
1516 GEN_FW_RANGE(0xd000, 0xd7ff, 0), \
1517 GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800), \
1518 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), \
1519 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), \
1520 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* \
1521 0xdd00 - 0xddff: gt \
1522 0xde00 - 0xde7f: reserved */ \
1523 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* \
1524 0xde80 - 0xdfff: render \
1525 0xe000 - 0xe0ff: reserved \
1526 0xe100 - 0xe8ff: render */ \
1527 GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* \
1528 0xe900 - 0xe9ff: gt \
1529 0xea00 - 0xefff: reserved \
1530 0xf000 - 0xffff: gt */ \
1531 GEN_FW_RANGE(0x10000, 0x12fff, 0), /* \
1532 0x10000 - 0x11fff: reserved \
1533 0x12000 - 0x127ff: always on \
1534 0x12800 - 0x12fff: reserved */ \
1535 GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \
1536 GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
1537 0x13200 - 0x133ff: VD2 (DG2 only) \
1538 0x13400 - 0x13fff: reserved */ \
1539 GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
1540 GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
1541 GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
1542 GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
1543 GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
1544 GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
1545 0x15000 - 0x15fff: gt (DG2 only) \
1546 0x16000 - 0x16dff: reserved */ \
1547 GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
1548 GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
1549 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
1550 0x21000 - 0x21fff: reserved */ \
1551 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
1552 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
1553 0x24000 - 0x2407f: always on \
1554 0x24080 - 0x2417f: reserved */ \
1555 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* \
1556 0x24180 - 0x241ff: gt \
1557 0x24200 - 0x249ff: reserved */ \
1558 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* \
1559 0x24a00 - 0x24a7f: render \
1560 0x24a80 - 0x251ff: reserved */ \
1561 GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* \
1562 0x25200 - 0x252ff: gt \
1563 0x25300 - 0x25fff: reserved */ \
1564 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* \
1565 0x26000 - 0x27fff: render \
1566 0x28000 - 0x29fff: reserved \
1567 0x2a000 - 0x2ffff: undocumented */ \
1568 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), \
1569 GEN_FW_RANGE(0x40000, 0x1bffff, 0), \
1570 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* \
1571 0x1c0000 - 0x1c2bff: VD0 \
1572 0x1c2c00 - 0x1c2cff: reserved \
1573 0x1c2d00 - 0x1c2dff: VD0 \
1574 0x1c2e00 - 0x1c3eff: VD0 (DG2 only) \
1575 0x1c3f00 - 0x1c3fff: VD0 */ \
1576 GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* \
1577 0x1c4000 - 0x1c6bff: VD1 \
1578 0x1c6c00 - 0x1c6cff: reserved \
1579 0x1c6d00 - 0x1c6dff: VD1 \
1580 0x1c6e00 - 0x1c7fff: reserved */ \
1581 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* \
1582 0x1c8000 - 0x1ca0ff: VE0 \
1583 0x1ca100 - 0x1cbfff: reserved */ \
1584 GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), \
1585 GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), \
1586 GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), \
1587 GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), \
1588 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* \
1589 0x1d0000 - 0x1d2bff: VD2 \
1590 0x1d2c00 - 0x1d2cff: reserved \
1591 0x1d2d00 - 0x1d2dff: VD2 \
1592 0x1d2e00 - 0x1d3dff: VD2 (DG2 only) \
1593 0x1d3e00 - 0x1d3eff: reserved \
1594 0x1d3f00 - 0x1d3fff: VD2 */ \
1595 GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* \
1596 0x1d4000 - 0x1d6bff: VD3 \
1597 0x1d6c00 - 0x1d6cff: reserved \
1598 0x1d6d00 - 0x1d6dff: VD3 \
1599 0x1d6e00 - 0x1d7fff: reserved */ \
1600 GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* \
1601 0x1d8000 - 0x1da0ff: VE1 \
1602 0x1da100 - 0x1dffff: reserved */ \
1603 GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* \
1604 0x1e0000 - 0x1e2bff: VD4 \
1605 0x1e2c00 - 0x1e2cff: reserved \
1606 0x1e2d00 - 0x1e2dff: VD4 \
1607 0x1e2e00 - 0x1e3eff: reserved \
1608 0x1e3f00 - 0x1e3fff: VD4 */ \
1609 GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* \
1610 0x1e4000 - 0x1e6bff: VD5 \
1611 0x1e6c00 - 0x1e6cff: reserved \
1612 0x1e6d00 - 0x1e6dff: VD5 \
1613 0x1e6e00 - 0x1e7fff: reserved */ \
1614 GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* \
1615 0x1e8000 - 0x1ea0ff: VE2 \
1616 0x1ea100 - 0x1effff: reserved */ \
1617 GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* \
1618 0x1f0000 - 0x1f2bff: VD6 \
1619 0x1f2c00 - 0x1f2cff: reserved \
1620 0x1f2d00 - 0x1f2dff: VD6 \
1621 0x1f2e00 - 0x1f3eff: reserved \
1622 0x1f3f00 - 0x1f3fff: VD6 */ \
1623 GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* \
1624 0x1f4000 - 0x1f6bff: VD7 \
1625 0x1f6c00 - 0x1f6cff: reserved \
1626 0x1f6d00 - 0x1f6dff: VD7 \
1627 0x1f6e00 - 0x1f7fff: reserved */ \
1628 GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
1630 static const struct intel_forcewake_range __xehp_fw_ranges[] = {
1631 XEHP_FWRANGES(FORCEWAKE_GT)
1634 static const struct intel_forcewake_range __dg2_fw_ranges[] = {
1635 XEHP_FWRANGES(FORCEWAKE_RENDER)
1638 static const struct intel_forcewake_range __pvc_fw_ranges[] = {
1639 GEN_FW_RANGE(0x0, 0xaff, 0),
1640 GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
1641 GEN_FW_RANGE(0xc00, 0xfff, 0),
1642 GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
1643 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1644 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1645 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1646 GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
1648 0x4b00 - 0x4fff: reserved
1650 0x5200 - 0x52ff: reserved
1652 0x5400 - 0x7fff: reserved
1653 0x8000 - 0x813f: gt */
1654 GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
1655 GEN_FW_RANGE(0x8180, 0x81ff, 0),
1656 GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
1658 0x8300 - 0x84ff: reserved
1660 0x8880 - 0x8a7f: reserved
1662 0x8b00 - 0x8fff: reserved
1664 0x9480 - 0x94cf: reserved */
1665 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1666 GEN_FW_RANGE(0x9560, 0x967f, 0), /*
1667 0x9560 - 0x95ff: always on
1668 0x9600 - 0x967f: reserved */
1669 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
1670 0x9680 - 0x96ff: render
1671 0x9700 - 0x97ff: reserved */
1672 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
1674 0xb500 - 0xbfff: reserved
1675 0xc000 - 0xcfff: gt */
1676 GEN_FW_RANGE(0xd000, 0xd3ff, 0),
1677 GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
1678 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
1679 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
1681 0xde00 - 0xde7f: reserved */
1682 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
1683 0xde80 - 0xdeff: render
1684 0xdf00 - 0xe1ff: reserved
1685 0xe200 - 0xe7ff: render
1686 0xe800 - 0xe8ff: reserved */
1687 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
1689 0xea00 - 0xebff: reserved
1691 0x10000 - 0x11fff: reserved */
1692 GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
1693 0x12000 - 0x127ff: always on
1694 0x12800 - 0x12fff: reserved */
1695 GEN_FW_RANGE(0x13000, 0x19fff, FORCEWAKE_GT), /*
1696 0x13000 - 0x135ff: gt
1697 0x13600 - 0x147ff: reserved
1698 0x14800 - 0x153ff: gt
1699 0x15400 - 0x19fff: reserved */
1700 GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
1701 0x1a000 - 0x1ffff: render
1702 0x20000 - 0x21fff: reserved */
1703 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1704 GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1705 24000 - 0x2407f: always on
1706 24080 - 0x2417f: reserved */
1707 GEN_FW_RANGE(0x24180, 0x25fff, FORCEWAKE_GT), /*
1708 0x24180 - 0x241ff: gt
1709 0x24200 - 0x251ff: reserved
1710 0x25200 - 0x252ff: gt
1711 0x25300 - 0x25fff: reserved */
1712 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
1713 0x26000 - 0x27fff: render
1714 0x28000 - 0x2ffff: reserved */
1715 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1716 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1717 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1718 0x1c0000 - 0x1c2bff: VD0
1719 0x1c2c00 - 0x1c2cff: reserved
1720 0x1c2d00 - 0x1c2dff: VD0
1721 0x1c2e00 - 0x1c3eff: reserved
1722 0x1c3f00 - 0x1c3fff: VD0 */
1723 GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
1724 0x1c4000 - 0x1c6aff: VD1
1725 0x1c6b00 - 0x1c7eff: reserved
1726 0x1c7f00 - 0x1c7fff: VD1
1727 0x1c8000 - 0x1cffff: reserved */
1728 GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
1729 0x1d0000 - 0x1d2aff: VD2
1730 0x1d2b00 - 0x1d3eff: reserved
1731 0x1d3f00 - 0x1d3fff: VD2
1732 0x1d4000 - 0x23ffff: reserved */
1733 GEN_FW_RANGE(0x240000, 0x3dffff, 0),
1734 GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
1737 static const struct intel_forcewake_range __mtl_fw_ranges[] = {
1738 GEN_FW_RANGE(0x0, 0xaff, 0),
1739 GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
1740 GEN_FW_RANGE(0xc00, 0xfff, 0),
1741 GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
1742 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1743 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1744 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1745 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
1746 0x4000 - 0x48ff: render
1747 0x4900 - 0x51ff: reserved */
1748 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
1749 0x5200 - 0x53ff: render
1750 0x5400 - 0x54ff: reserved
1751 0x5500 - 0x7fff: render */
1752 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1753 GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER), /*
1754 0x8140 - 0x815f: render
1755 0x8160 - 0x817f: reserved */
1756 GEN_FW_RANGE(0x8180, 0x81ff, 0),
1757 GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
1759 0x8800 - 0x8dff: reserved
1761 0x8f80 - 0x8fff: reserved
1763 0x9480 - 0x94cf: reserved */
1764 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1765 GEN_FW_RANGE(0x9560, 0x967f, 0), /*
1766 0x9560 - 0x95ff: always on
1767 0x9600 - 0x967f: reserved */
1768 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
1769 0x9680 - 0x96ff: render
1770 0x9700 - 0x97ff: reserved */
1771 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
1773 0xb500 - 0xbfff: reserved
1774 0xc000 - 0xcfff: gt */
1775 GEN_FW_RANGE(0xd000, 0xd7ff, 0), /*
1776 0xd000 - 0xd3ff: always on
1777 0xd400 - 0xd7ff: reserved */
1778 GEN_FW_RANGE(0xd800, 0xd87f, FORCEWAKE_RENDER),
1779 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT),
1780 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
1781 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
1783 0xde00 - 0xde7f: reserved */
1784 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
1785 0xde80 - 0xdfff: render
1786 0xe000 - 0xe0ff: reserved
1787 0xe100 - 0xe8ff: render */
1788 GEN_FW_RANGE(0xe900, 0xe9ff, FORCEWAKE_GT),
1789 GEN_FW_RANGE(0xea00, 0x147ff, 0), /*
1790 0xea00 - 0x11fff: reserved
1791 0x12000 - 0x127ff: always on
1792 0x12800 - 0x147ff: reserved */
1793 GEN_FW_RANGE(0x14800, 0x19fff, FORCEWAKE_GT), /*
1794 0x14800 - 0x153ff: gt
1795 0x15400 - 0x19fff: reserved */
1796 GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
1797 0x1a000 - 0x1bfff: render
1798 0x1c000 - 0x21fff: reserved */
1799 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1800 GEN_FW_RANGE(0x24000, 0x2ffff, 0), /*
1801 0x24000 - 0x2407f: always on
1802 0x24080 - 0x2ffff: reserved */
1803 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT)
1807 * Note that the register ranges here are the final offsets after
1808 * translation of the GSI block to the 0x380000 offset.
1810 * NOTE: There are a couple MCR ranges near the bottom of this table
1811 * that need to power up either VD0 or VD2 depending on which replicated
1812 * instance of the register we're trying to access. Our forcewake logic
1813 * at the moment doesn't have a good way to take steering into consideration,
1814 * and the driver doesn't even access any registers in those ranges today,
1815 * so for now we just mark those ranges as FORCEWAKE_ALL. That will ensure
1816 * proper operation if we do start using the ranges in the future, and we
1817 * can determine at that time whether it's worth adding extra complexity to
1818 * the forcewake handling to take steering into consideration.
1820 static const struct intel_forcewake_range __xelpmp_fw_ranges[] = {
1821 GEN_FW_RANGE(0x0, 0x115fff, 0), /* render GT range */
1822 GEN_FW_RANGE(0x116000, 0x11ffff, FORCEWAKE_GSC), /*
1823 0x116000 - 0x117fff: gsc
1824 0x118000 - 0x119fff: reserved
1825 0x11a000 - 0x11efff: gsc
1826 0x11f000 - 0x11ffff: reserved */
1827 GEN_FW_RANGE(0x120000, 0x1bffff, 0), /* non-GT range */
1828 GEN_FW_RANGE(0x1c0000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX0), /*
1829 0x1c0000 - 0x1c3dff: VD0
1830 0x1c3e00 - 0x1c3eff: reserved
1831 0x1c3f00 - 0x1c3fff: VD0
1832 0x1c4000 - 0x1c7fff: reserved */
1833 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1834 0x1c8000 - 0x1ca0ff: VE0
1835 0x1ca100 - 0x1cbfff: reserved */
1836 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
1837 0x1cc000 - 0x1cdfff: VD0
1838 0x1ce000 - 0x1cffff: reserved */
1839 GEN_FW_RANGE(0x1d0000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX2), /*
1840 0x1d0000 - 0x1d3dff: VD2
1841 0x1d3e00 - 0x1d3eff: reserved
1842 0x1d4000 - 0x1d7fff: VD2 */
1843 GEN_FW_RANGE(0x1d8000, 0x1da0ff, FORCEWAKE_MEDIA_VEBOX1),
1844 GEN_FW_RANGE(0x1da100, 0x380aff, 0), /*
1845 0x1da100 - 0x23ffff: reserved
1846 0x240000 - 0x37ffff: non-GT range
1847 0x380000 - 0x380aff: reserved */
1848 GEN_FW_RANGE(0x380b00, 0x380bff, FORCEWAKE_GT),
1849 GEN_FW_RANGE(0x380c00, 0x380fff, 0),
1850 GEN_FW_RANGE(0x381000, 0x38817f, FORCEWAKE_GT), /*
1851 0x381000 - 0x381fff: gt
1852 0x382000 - 0x383fff: reserved
1853 0x384000 - 0x384aff: gt
1854 0x384b00 - 0x3851ff: reserved
1855 0x385200 - 0x3871ff: gt
1856 0x387200 - 0x387fff: reserved
1857 0x388000 - 0x38813f: gt
1858 0x388140 - 0x38817f: reserved */
1859 GEN_FW_RANGE(0x388180, 0x3882ff, 0), /*
1860 0x388180 - 0x3881ff: always on
1861 0x388200 - 0x3882ff: reserved */
1862 GEN_FW_RANGE(0x388300, 0x38955f, FORCEWAKE_GT), /*
1863 0x388300 - 0x38887f: gt
1864 0x388880 - 0x388fff: reserved
1865 0x389000 - 0x38947f: gt
1866 0x389480 - 0x38955f: reserved */
1867 GEN_FW_RANGE(0x389560, 0x389fff, 0), /*
1868 0x389560 - 0x3895ff: always on
1869 0x389600 - 0x389fff: reserved */
1870 GEN_FW_RANGE(0x38a000, 0x38cfff, FORCEWAKE_GT), /*
1871 0x38a000 - 0x38afff: gt
1872 0x38b000 - 0x38bfff: reserved
1873 0x38c000 - 0x38cfff: gt */
1874 GEN_FW_RANGE(0x38d000, 0x38d11f, 0),
1875 GEN_FW_RANGE(0x38d120, 0x391fff, FORCEWAKE_GT), /*
1876 0x38d120 - 0x38dfff: gt
1877 0x38e000 - 0x38efff: reserved
1878 0x38f000 - 0x38ffff: gt
1879 0x389000 - 0x391fff: reserved */
1880 GEN_FW_RANGE(0x392000, 0x392fff, 0), /*
1881 0x392000 - 0x3927ff: always on
1882 0x392800 - 0x292fff: reserved */
1883 GEN_FW_RANGE(0x393000, 0x3931ff, FORCEWAKE_GT),
1884 GEN_FW_RANGE(0x393200, 0x39323f, FORCEWAKE_ALL), /* instance-based, see note above */
1885 GEN_FW_RANGE(0x393240, 0x3933ff, FORCEWAKE_GT),
1886 GEN_FW_RANGE(0x393400, 0x3934ff, FORCEWAKE_ALL), /* instance-based, see note above */
1887 GEN_FW_RANGE(0x393500, 0x393c7f, 0), /*
1888 0x393500 - 0x393bff: reserved
1889 0x393c00 - 0x393c7f: always on */
1890 GEN_FW_RANGE(0x393c80, 0x393dff, FORCEWAKE_GT),
1894 ilk_dummy_write(struct intel_uncore *uncore)
1896 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1897 * the chip from rc6 before touching it for real. MI_MODE is masked,
1898 * hence harmless to write 0 into. */
1899 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
1903 __unclaimed_reg_debug(struct intel_uncore *uncore,
1904 const i915_reg_t reg,
1907 if (drm_WARN(&uncore->i915->drm,
1908 check_for_unclaimed_mmio(uncore),
1909 "Unclaimed %s register 0x%x\n",
1910 read ? "read from" : "write to",
1911 i915_mmio_reg_offset(reg)))
1912 /* Only report the first N failures */
1913 uncore->i915->params.mmio_debug--;
1917 __unclaimed_previous_reg_debug(struct intel_uncore *uncore,
1918 const i915_reg_t reg,
1921 if (check_for_unclaimed_mmio(uncore))
1922 drm_dbg(&uncore->i915->drm,
1923 "Unclaimed access detected before %s register 0x%x\n",
1924 read ? "read from" : "write to",
1925 i915_mmio_reg_offset(reg));
1929 unclaimed_reg_debug(struct intel_uncore *uncore,
1930 const i915_reg_t reg,
1934 if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
1937 /* interrupts are disabled and re-enabled around uncore->lock usage */
1938 lockdep_assert_held(&uncore->lock);
1941 spin_lock(&uncore->debug->lock);
1942 __unclaimed_previous_reg_debug(uncore, reg, read);
1944 __unclaimed_reg_debug(uncore, reg, read);
1945 spin_unlock(&uncore->debug->lock);
1949 #define __vgpu_read(x) \
1951 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1952 u##x val = __raw_uncore_read##x(uncore, reg); \
1953 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1961 #define GEN2_READ_HEADER(x) \
1963 assert_rpm_wakelock_held(uncore->rpm);
1965 #define GEN2_READ_FOOTER \
1966 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1969 #define __gen2_read(x) \
1971 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1972 GEN2_READ_HEADER(x); \
1973 val = __raw_uncore_read##x(uncore, reg); \
1977 #define __gen5_read(x) \
1979 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1980 GEN2_READ_HEADER(x); \
1981 ilk_dummy_write(uncore); \
1982 val = __raw_uncore_read##x(uncore, reg); \
1998 #undef GEN2_READ_FOOTER
1999 #undef GEN2_READ_HEADER
2001 #define GEN6_READ_HEADER(x) \
2002 u32 offset = i915_mmio_reg_offset(reg); \
2003 unsigned long irqflags; \
2005 assert_rpm_wakelock_held(uncore->rpm); \
2006 spin_lock_irqsave(&uncore->lock, irqflags); \
2007 unclaimed_reg_debug(uncore, reg, true, true)
2009 #define GEN6_READ_FOOTER \
2010 unclaimed_reg_debug(uncore, reg, true, false); \
2011 spin_unlock_irqrestore(&uncore->lock, irqflags); \
2012 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
2015 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
2016 enum forcewake_domains fw_domains)
2018 struct intel_uncore_forcewake_domain *domain;
2021 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
2023 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
2024 fw_domain_arm_timer(domain);
2026 fw_domains_get(uncore, fw_domains);
2029 static inline void __force_wake_auto(struct intel_uncore *uncore,
2030 enum forcewake_domains fw_domains)
2032 GEM_BUG_ON(!fw_domains);
2034 /* Turn on all requested but inactive supported forcewake domains. */
2035 fw_domains &= uncore->fw_domains;
2036 fw_domains &= ~uncore->fw_domains_active;
2039 ___force_wake_auto(uncore, fw_domains);
2042 #define __gen_fwtable_read(x) \
2044 fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
2046 enum forcewake_domains fw_engine; \
2047 GEN6_READ_HEADER(x); \
2048 fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \
2050 __force_wake_auto(uncore, fw_engine); \
2051 val = __raw_uncore_read##x(uncore, reg); \
2055 static enum forcewake_domains
2056 fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
2057 return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));
2060 __gen_fwtable_read(8)
2061 __gen_fwtable_read(16)
2062 __gen_fwtable_read(32)
2063 __gen_fwtable_read(64)
2065 #undef __gen_fwtable_read
2066 #undef GEN6_READ_FOOTER
2067 #undef GEN6_READ_HEADER
2069 #define GEN2_WRITE_HEADER \
2070 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
2071 assert_rpm_wakelock_held(uncore->rpm); \
2073 #define GEN2_WRITE_FOOTER
2075 #define __gen2_write(x) \
2077 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
2078 GEN2_WRITE_HEADER; \
2079 __raw_uncore_write##x(uncore, reg, val); \
2080 GEN2_WRITE_FOOTER; \
2083 #define __gen5_write(x) \
2085 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
2086 GEN2_WRITE_HEADER; \
2087 ilk_dummy_write(uncore); \
2088 __raw_uncore_write##x(uncore, reg, val); \
2089 GEN2_WRITE_FOOTER; \
2102 #undef GEN2_WRITE_FOOTER
2103 #undef GEN2_WRITE_HEADER
2105 #define GEN6_WRITE_HEADER \
2106 u32 offset = i915_mmio_reg_offset(reg); \
2107 unsigned long irqflags; \
2108 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
2109 assert_rpm_wakelock_held(uncore->rpm); \
2110 spin_lock_irqsave(&uncore->lock, irqflags); \
2111 unclaimed_reg_debug(uncore, reg, false, true)
2113 #define GEN6_WRITE_FOOTER \
2114 unclaimed_reg_debug(uncore, reg, false, false); \
2115 spin_unlock_irqrestore(&uncore->lock, irqflags)
2117 #define __gen6_write(x) \
2119 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
2120 GEN6_WRITE_HEADER; \
2121 if (NEEDS_FORCE_WAKE(offset)) \
2122 __gen6_gt_wait_for_fifo(uncore); \
2123 __raw_uncore_write##x(uncore, reg, val); \
2124 GEN6_WRITE_FOOTER; \
2130 #define __gen_fwtable_write(x) \
2132 fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
2133 enum forcewake_domains fw_engine; \
2134 GEN6_WRITE_HEADER; \
2135 fw_engine = __fwtable_reg_write_fw_domains(uncore, offset); \
2137 __force_wake_auto(uncore, fw_engine); \
2138 __raw_uncore_write##x(uncore, reg, val); \
2139 GEN6_WRITE_FOOTER; \
2142 static enum forcewake_domains
2143 fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
2145 return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg));
2148 __gen_fwtable_write(8)
2149 __gen_fwtable_write(16)
2150 __gen_fwtable_write(32)
2152 #undef __gen_fwtable_write
2153 #undef GEN6_WRITE_FOOTER
2154 #undef GEN6_WRITE_HEADER
2156 #define __vgpu_write(x) \
2158 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
2159 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
2160 __raw_uncore_write##x(uncore, reg, val); \
2166 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
2168 (uncore)->funcs.mmio_writeb = x##_write8; \
2169 (uncore)->funcs.mmio_writew = x##_write16; \
2170 (uncore)->funcs.mmio_writel = x##_write32; \
2173 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
2175 (uncore)->funcs.mmio_readb = x##_read8; \
2176 (uncore)->funcs.mmio_readw = x##_read16; \
2177 (uncore)->funcs.mmio_readl = x##_read32; \
2178 (uncore)->funcs.mmio_readq = x##_read64; \
2181 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
2183 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
2184 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
2187 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
2189 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
2190 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
2193 static int __fw_domain_init(struct intel_uncore *uncore,
2194 enum forcewake_domain_id domain_id,
2198 struct intel_uncore_forcewake_domain *d;
2200 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
2201 GEM_BUG_ON(uncore->fw_domain[domain_id]);
2203 if (i915_inject_probe_failure(uncore->i915))
2206 d = kzalloc(sizeof(*d), GFP_KERNEL);
2210 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set));
2211 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack));
2215 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset;
2216 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset;
2220 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
2221 BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT));
2222 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
2223 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
2224 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
2225 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
2226 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
2227 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4));
2228 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5));
2229 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6));
2230 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7));
2231 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
2232 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
2233 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2));
2234 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3));
2235 BUILD_BUG_ON(FORCEWAKE_GSC != (1 << FW_DOMAIN_ID_GSC));
2237 d->mask = BIT(domain_id);
2239 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2240 d->timer.function = intel_uncore_fw_release_timer;
2242 uncore->fw_domains |= BIT(domain_id);
2246 uncore->fw_domain[domain_id] = d;
2251 static void fw_domain_fini(struct intel_uncore *uncore,
2252 enum forcewake_domain_id domain_id)
2254 struct intel_uncore_forcewake_domain *d;
2256 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
2258 d = fetch_and_zero(&uncore->fw_domain[domain_id]);
2262 uncore->fw_domains &= ~BIT(domain_id);
2263 drm_WARN_ON(&uncore->i915->drm, d->wake_count);
2264 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer));
2268 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
2270 struct intel_uncore_forcewake_domain *d;
2273 for_each_fw_domain(d, uncore, tmp)
2274 fw_domain_fini(uncore, d->id);
2277 static const struct intel_uncore_fw_get uncore_get_fallback = {
2278 .force_wake_get = fw_domains_get_with_fallback
2281 static const struct intel_uncore_fw_get uncore_get_normal = {
2282 .force_wake_get = fw_domains_get_normal,
2285 static const struct intel_uncore_fw_get uncore_get_thread_status = {
2286 .force_wake_get = fw_domains_get_with_thread_status
2289 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
2291 struct drm_i915_private *i915 = uncore->i915;
2294 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
2296 #define fw_domain_init(uncore__, id__, set__, ack__) \
2297 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
2299 if (GRAPHICS_VER(i915) >= 11) {
2300 intel_engine_mask_t emask;
2303 /* we'll prune the domains of missing engines later */
2304 emask = uncore->gt->info.engine_mask;
2306 uncore->fw_get_funcs = &uncore_get_fallback;
2307 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
2308 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
2310 FORCEWAKE_ACK_GT_MTL);
2312 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
2314 FORCEWAKE_ACK_GT_GEN9);
2316 if (RCS_MASK(uncore->gt) || CCS_MASK(uncore->gt))
2317 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2318 FORCEWAKE_RENDER_GEN9,
2319 FORCEWAKE_ACK_RENDER_GEN9);
2321 for (i = 0; i < I915_MAX_VCS; i++) {
2322 if (!__HAS_ENGINE(emask, _VCS(i)))
2325 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
2326 FORCEWAKE_MEDIA_VDBOX_GEN11(i),
2327 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
2329 for (i = 0; i < I915_MAX_VECS; i++) {
2330 if (!__HAS_ENGINE(emask, _VECS(i)))
2333 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
2334 FORCEWAKE_MEDIA_VEBOX_GEN11(i),
2335 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
2338 if (uncore->gt->type == GT_MEDIA)
2339 fw_domain_init(uncore, FW_DOMAIN_ID_GSC,
2340 FORCEWAKE_REQ_GSC, FORCEWAKE_ACK_GSC);
2341 } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
2342 uncore->fw_get_funcs = &uncore_get_fallback;
2343 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2344 FORCEWAKE_RENDER_GEN9,
2345 FORCEWAKE_ACK_RENDER_GEN9);
2346 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
2348 FORCEWAKE_ACK_GT_GEN9);
2349 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
2350 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
2351 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
2352 uncore->fw_get_funcs = &uncore_get_normal;
2353 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2354 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
2355 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
2356 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
2357 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2358 uncore->fw_get_funcs = &uncore_get_thread_status;
2359 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2360 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
2361 } else if (IS_IVYBRIDGE(i915)) {
2364 /* IVB configs may use multi-threaded forcewake */
2366 /* A small trick here - if the bios hasn't configured
2367 * MT forcewake, and if the device is in RC6, then
2368 * force_wake_mt_get will not wake the device and the
2369 * ECOBUS read will return zero. Which will be
2370 * (correctly) interpreted by the test below as MT
2371 * forcewake being disabled.
2373 uncore->fw_get_funcs = &uncore_get_thread_status;
2375 /* We need to init first for ECOBUS access and then
2376 * determine later if we want to reinit, in case of MT access is
2377 * not working. In this stage we don't know which flavour this
2378 * ivb is, so it is better to reset also the gen6 fw registers
2379 * before the ecobus check.
2382 __raw_uncore_write32(uncore, FORCEWAKE, 0);
2383 __raw_posting_read(uncore, ECOBUS);
2385 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2386 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
2390 spin_lock_irq(&uncore->lock);
2391 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
2392 ecobus = __raw_uncore_read32(uncore, ECOBUS);
2393 fw_domains_put(uncore, FORCEWAKE_RENDER);
2394 spin_unlock_irq(&uncore->lock);
2396 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
2397 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
2398 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
2399 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
2400 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2401 FORCEWAKE, FORCEWAKE_ACK);
2403 } else if (GRAPHICS_VER(i915) == 6) {
2404 uncore->fw_get_funcs = &uncore_get_thread_status;
2405 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2406 FORCEWAKE, FORCEWAKE_ACK);
2409 #undef fw_domain_init
2411 /* All future platforms are expected to require complex power gating */
2412 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0);
2416 intel_uncore_fw_domains_fini(uncore);
2421 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
2423 (uncore)->fw_domains_table = \
2424 (struct intel_forcewake_range *)(d); \
2425 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
2428 #define ASSIGN_SHADOW_TABLE(uncore, d) \
2430 (uncore)->shadowed_reg_table = d; \
2431 (uncore)->shadowed_reg_table_entries = ARRAY_SIZE((d)); \
2434 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
2435 unsigned long action, void *data)
2437 struct intel_uncore *uncore = container_of(nb,
2438 struct intel_uncore, pmic_bus_access_nb);
2441 case MBI_PMIC_BUS_ACCESS_BEGIN:
2443 * forcewake all now to make sure that we don't need to do a
2444 * forcewake later which on systems where this notifier gets
2445 * called requires the punit to access to the shared pmic i2c
2446 * bus, which will be busy after this notification, leading to:
2447 * "render: timed out waiting for forcewake ack request."
2450 * The notifier is unregistered during intel_runtime_suspend(),
2451 * so it's ok to access the HW here without holding a RPM
2452 * wake reference -> disable wakeref asserts for the time of
2455 disable_rpm_wakeref_asserts(uncore->rpm);
2456 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2457 enable_rpm_wakeref_asserts(uncore->rpm);
2459 case MBI_PMIC_BUS_ACCESS_END:
2460 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2467 static void uncore_unmap_mmio(struct drm_device *drm, void *regs)
2469 iounmap((void __iomem *)regs);
2472 int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
2474 struct drm_i915_private *i915 = uncore->i915;
2478 * Before gen4, the registers and the GTT are behind different BARs.
2479 * However, from gen4 onwards, the registers and the GTT are shared
2480 * in the same BAR, so we want to restrict this ioremap from
2481 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
2482 * the register BAR remains the same size for all the earlier
2483 * generations up to Ironlake.
2484 * For dgfx chips register range is expanded to 4MB, and this larger
2485 * range is also used for integrated gpus beginning with Meteor Lake.
2487 if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
2488 mmio_size = 4 * 1024 * 1024;
2489 else if (GRAPHICS_VER(i915) >= 5)
2490 mmio_size = 2 * 1024 * 1024;
2492 mmio_size = 512 * 1024;
2494 uncore->regs = ioremap(phys_addr, mmio_size);
2495 if (uncore->regs == NULL) {
2496 drm_err(&i915->drm, "failed to map registers\n");
2500 return drmm_add_action_or_reset(&i915->drm, uncore_unmap_mmio,
2501 (void __force *)uncore->regs);
2504 void intel_uncore_init_early(struct intel_uncore *uncore,
2505 struct intel_gt *gt)
2507 spin_lock_init(&uncore->lock);
2508 uncore->i915 = gt->i915;
2510 uncore->rpm = >->i915->runtime_pm;
2513 static void uncore_raw_init(struct intel_uncore *uncore)
2515 GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
2517 if (intel_vgpu_active(uncore->i915)) {
2518 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
2519 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
2520 } else if (GRAPHICS_VER(uncore->i915) == 5) {
2521 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
2522 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
2524 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
2525 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
2529 static int uncore_media_forcewake_init(struct intel_uncore *uncore)
2531 struct drm_i915_private *i915 = uncore->i915;
2533 if (MEDIA_VER(i915) >= 13) {
2534 ASSIGN_FW_DOMAINS_TABLE(uncore, __xelpmp_fw_ranges);
2535 ASSIGN_SHADOW_TABLE(uncore, xelpmp_shadowed_regs);
2536 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2538 MISSING_CASE(MEDIA_VER(i915));
2545 static int uncore_forcewake_init(struct intel_uncore *uncore)
2547 struct drm_i915_private *i915 = uncore->i915;
2550 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
2552 ret = intel_uncore_fw_domains_init(uncore);
2555 forcewake_early_sanitize(uncore, 0);
2557 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
2559 if (uncore->gt->type == GT_MEDIA)
2560 return uncore_media_forcewake_init(uncore);
2562 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
2563 ASSIGN_FW_DOMAINS_TABLE(uncore, __mtl_fw_ranges);
2564 ASSIGN_SHADOW_TABLE(uncore, mtl_shadowed_regs);
2565 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2566 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
2567 ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
2568 ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
2569 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2570 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
2571 ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
2572 ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
2573 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2574 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
2575 ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
2576 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
2577 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2578 } else if (GRAPHICS_VER(i915) >= 12) {
2579 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
2580 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
2581 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2582 } else if (GRAPHICS_VER(i915) == 11) {
2583 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
2584 ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);
2585 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2586 } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
2587 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
2588 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2589 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2590 } else if (IS_CHERRYVIEW(i915)) {
2591 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
2592 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2593 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2594 } else if (GRAPHICS_VER(i915) == 8) {
2595 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
2596 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2597 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2598 } else if (IS_VALLEYVIEW(i915)) {
2599 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
2600 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
2601 } else if (IS_GRAPHICS_VER(i915, 6, 7)) {
2602 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
2603 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
2606 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
2607 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
2612 static int sanity_check_mmio_access(struct intel_uncore *uncore)
2614 struct drm_i915_private *i915 = uncore->i915;
2616 if (GRAPHICS_VER(i915) < 8)
2620 * Sanitycheck that MMIO access to the device is working properly. If
2621 * the CPU is unable to communcate with a PCI device, BAR reads will
2622 * return 0xFFFFFFFF. Let's make sure the device isn't in this state
2623 * before we start trying to access registers.
2625 * We use the primary GT's forcewake register as our guinea pig since
2626 * it's been around since HSW and it's a masked register so the upper
2627 * 16 bits can never read back as 1's if device access is operating
2630 * If MMIO isn't working, we'll wait up to 2 seconds to see if it
2631 * recovers, then give up.
2633 #define COND (__raw_uncore_read32(uncore, FORCEWAKE_MT) != ~0)
2634 if (wait_for(COND, 2000) == -ETIMEDOUT) {
2635 drm_err(&i915->drm, "Device is non-operational; MMIO access returns 0xFFFFFFFF!\n");
2642 int intel_uncore_init_mmio(struct intel_uncore *uncore)
2644 struct drm_i915_private *i915 = uncore->i915;
2647 ret = sanity_check_mmio_access(uncore);
2652 * The boot firmware initializes local memory and assesses its health.
2653 * If memory training fails, the punit will have been instructed to
2654 * keep the GT powered down; we won't be able to communicate with it
2655 * and we should not continue with driver initialization.
2657 if (IS_DGFX(i915) &&
2658 !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
2659 drm_err(&i915->drm, "LMEM not initialized by firmware\n");
2663 if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
2664 uncore->flags |= UNCORE_HAS_FORCEWAKE;
2666 if (!intel_uncore_has_forcewake(uncore)) {
2667 uncore_raw_init(uncore);
2669 ret = uncore_forcewake_init(uncore);
2674 /* make sure fw funcs are set if and only if we have fw*/
2675 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs);
2676 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
2677 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
2679 if (HAS_FPGA_DBG_UNCLAIMED(i915))
2680 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
2682 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
2683 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
2685 if (IS_GRAPHICS_VER(i915, 6, 7))
2686 uncore->flags |= UNCORE_HAS_FIFO;
2688 /* clear out unclaimed reg detection bit */
2689 if (intel_uncore_unclaimed_mmio(uncore))
2690 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
2696 * We might have detected that some engines are fused off after we initialized
2697 * the forcewake domains. Prune them, to make sure they only reference existing
2700 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
2701 struct intel_gt *gt)
2703 enum forcewake_domains fw_domains = uncore->fw_domains;
2704 enum forcewake_domain_id domain_id;
2707 if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11)
2710 for (i = 0; i < I915_MAX_VCS; i++) {
2711 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
2713 if (HAS_ENGINE(gt, _VCS(i)))
2717 * Starting with XeHP, the power well for an even-numbered
2718 * VDBOX is also used for shared units within the
2719 * media slice such as SFC. So even if the engine
2720 * itself is fused off, we still need to initialize
2721 * the forcewake domain if any of the other engines
2722 * in the same media slice are present.
2724 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
2725 if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
2728 if (HAS_ENGINE(gt, _VECS(i / 2)))
2732 if (fw_domains & BIT(domain_id))
2733 fw_domain_fini(uncore, domain_id);
2736 for (i = 0; i < I915_MAX_VECS; i++) {
2737 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
2739 if (HAS_ENGINE(gt, _VECS(i)))
2742 if (fw_domains & BIT(domain_id))
2743 fw_domain_fini(uncore, domain_id);
2746 if ((fw_domains & BIT(FW_DOMAIN_ID_GSC)) && !HAS_ENGINE(gt, GSC0))
2747 fw_domain_fini(uncore, FW_DOMAIN_ID_GSC);
2751 * The driver-initiated FLR is the highest level of reset that we can trigger
2752 * from within the driver. It is different from the PCI FLR in that it doesn't
2753 * fully reset the SGUnit and doesn't modify the PCI config space and therefore
2754 * it doesn't require a re-enumeration of the PCI BARs. However, the
2755 * driver-initiated FLR does still cause a reset of both GT and display and a
2756 * memory wipe of local and stolen memory, so recovery would require a full HW
2757 * re-init and saving/restoring (or re-populating) the wiped memory. Since we
2758 * perform the FLR as the very last action before releasing access to the HW
2759 * during the driver release flow, we don't attempt recovery at all, because
2760 * if/when a new instance of i915 is bound to the device it will do a full
2763 static void driver_initiated_flr(struct intel_uncore *uncore)
2765 struct drm_i915_private *i915 = uncore->i915;
2766 const unsigned int flr_timeout_ms = 3000; /* specs recommend a 3s wait */
2769 drm_dbg(&i915->drm, "Triggering Driver-FLR\n");
2772 * Make sure any pending FLR requests have cleared by waiting for the
2773 * FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS
2774 * to make sure it's not still set from a prior attempt (it's a write to
2776 * Note that we should never be in a situation where a previous attempt
2777 * is still pending (unless the HW is totally dead), but better to be
2778 * safe in case something unexpected happens
2780 ret = intel_wait_for_register_fw(uncore, GU_CNTL, DRIVERFLR, 0, flr_timeout_ms);
2783 "Failed to wait for Driver-FLR bit to clear! %d\n",
2787 intel_uncore_write_fw(uncore, GU_DEBUG, DRIVERFLR_STATUS);
2789 /* Trigger the actual Driver-FLR */
2790 intel_uncore_rmw_fw(uncore, GU_CNTL, 0, DRIVERFLR);
2792 /* Wait for hardware teardown to complete */
2793 ret = intel_wait_for_register_fw(uncore, GU_CNTL,
2797 drm_err(&i915->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret);
2801 /* Wait for hardware/firmware re-init to complete */
2802 ret = intel_wait_for_register_fw(uncore, GU_DEBUG,
2803 DRIVERFLR_STATUS, DRIVERFLR_STATUS,
2806 drm_err(&i915->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret);
2810 /* Clear sticky completion status */
2811 intel_uncore_write_fw(uncore, GU_DEBUG, DRIVERFLR_STATUS);
2814 /* Called via drm-managed action */
2815 void intel_uncore_fini_mmio(struct drm_device *dev, void *data)
2817 struct intel_uncore *uncore = data;
2819 if (intel_uncore_has_forcewake(uncore)) {
2820 iosf_mbi_punit_acquire();
2821 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
2822 &uncore->pmic_bus_access_nb);
2823 intel_uncore_forcewake_reset(uncore);
2824 intel_uncore_fw_domains_fini(uncore);
2825 iosf_mbi_punit_release();
2828 if (intel_uncore_needs_flr_on_fini(uncore))
2829 driver_initiated_flr(uncore);
2833 * __intel_wait_for_register_fw - wait until register matches expected state
2834 * @uncore: the struct intel_uncore
2835 * @reg: the register to read
2836 * @mask: mask to apply to register value
2837 * @value: expected value
2838 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2839 * @slow_timeout_ms: slow timeout in millisecond
2840 * @out_value: optional placeholder to hold registry value
2842 * This routine waits until the target register @reg contains the expected
2843 * @value after applying the @mask, i.e. it waits until ::
2845 * (intel_uncore_read_fw(uncore, reg) & mask) == value
2847 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
2848 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
2849 * must be not larger than 20,0000 microseconds.
2851 * Note that this routine assumes the caller holds forcewake asserted, it is
2852 * not suitable for very long waits. See intel_wait_for_register() if you
2853 * wish to wait without holding forcewake for the duration (i.e. you expect
2854 * the wait to be slow).
2856 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2858 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
2862 unsigned int fast_timeout_us,
2863 unsigned int slow_timeout_ms,
2867 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2870 /* Catch any overuse of this function */
2871 might_sleep_if(slow_timeout_ms);
2872 GEM_BUG_ON(fast_timeout_us > 20000);
2873 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
2876 if (fast_timeout_us && fast_timeout_us <= 20000)
2877 ret = _wait_for_atomic(done, fast_timeout_us, 0);
2878 if (ret && slow_timeout_ms)
2879 ret = wait_for(done, slow_timeout_ms);
2882 *out_value = reg_value;
2889 * __intel_wait_for_register - wait until register matches expected state
2890 * @uncore: the struct intel_uncore
2891 * @reg: the register to read
2892 * @mask: mask to apply to register value
2893 * @value: expected value
2894 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2895 * @slow_timeout_ms: slow timeout in millisecond
2896 * @out_value: optional placeholder to hold registry value
2898 * This routine waits until the target register @reg contains the expected
2899 * @value after applying the @mask, i.e. it waits until ::
2901 * (intel_uncore_read(uncore, reg) & mask) == value
2903 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2905 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2907 int __intel_wait_for_register(struct intel_uncore *uncore,
2911 unsigned int fast_timeout_us,
2912 unsigned int slow_timeout_ms,
2916 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2920 might_sleep_if(slow_timeout_ms);
2922 spin_lock_irq(&uncore->lock);
2923 intel_uncore_forcewake_get__locked(uncore, fw);
2925 ret = __intel_wait_for_register_fw(uncore,
2927 fast_timeout_us, 0, ®_value);
2929 intel_uncore_forcewake_put__locked(uncore, fw);
2930 spin_unlock_irq(&uncore->lock);
2932 if (ret && slow_timeout_ms)
2933 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2935 (reg_value & mask) == value,
2936 slow_timeout_ms * 1000, 10, 1000);
2938 /* just trace the final value */
2939 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2942 *out_value = reg_value;
2947 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2954 spin_lock_irq(&uncore->debug->lock);
2955 ret = check_for_unclaimed_mmio(uncore);
2956 spin_unlock_irq(&uncore->debug->lock);
2962 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2966 if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug))
2969 spin_lock_irq(&uncore->debug->lock);
2971 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2974 if (unlikely(check_for_unclaimed_mmio(uncore))) {
2975 if (!uncore->i915->params.mmio_debug) {
2976 drm_dbg(&uncore->i915->drm,
2977 "Unclaimed register detected, "
2978 "enabling oneshot unclaimed register reporting. "
2979 "Please use i915.mmio_debug=N for more information.\n");
2980 uncore->i915->params.mmio_debug++;
2982 uncore->debug->unclaimed_mmio_check--;
2987 spin_unlock_irq(&uncore->debug->lock);
2993 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2995 * @uncore: pointer to struct intel_uncore
2996 * @reg: register in question
2997 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2999 * Returns a set of forcewake domains required to be taken with for example
3000 * intel_uncore_forcewake_get for the specified register to be accessible in the
3001 * specified mode (read, write or read/write) with raw mmio accessors.
3003 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
3004 * callers to do FIFO management on their own or risk losing writes.
3006 enum forcewake_domains
3007 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
3008 i915_reg_t reg, unsigned int op)
3010 enum forcewake_domains fw_domains = 0;
3012 drm_WARN_ON(&uncore->i915->drm, !op);
3014 if (!intel_uncore_has_forcewake(uncore))
3017 if (op & FW_REG_READ)
3018 fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
3020 if (op & FW_REG_WRITE)
3021 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
3023 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains);
3028 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3029 #include "selftests/mock_uncore.c"
3030 #include "selftests/intel_uncore.c"