drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <asm/iosf_mbi.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  32
  33 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  34
  35 static const char * const forcewake_domain_names[] = {
  36         "render",
  37         "blitter",
  38         "media",
  39 };
  40
  41 const char *
  42 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  43 {
  44         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  45
  46         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  47                 return forcewake_domain_names[id];
  48
  49         WARN_ON(id);
  50
  51         return "unknown";
  52 }
  53
  54 static inline void
  55 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  56 {
  57         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  58         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  59 }
  60
  61 static inline void
  62 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  63 {
  64         d->wake_count++;
  65         hrtimer_start_range_ns(&d->timer,
  66                                NSEC_PER_MSEC,
  67                                NSEC_PER_MSEC,
  68                                HRTIMER_MODE_REL);
  69 }
  70
  71 static inline void
  72 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  73 {
  74         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  75                              FORCEWAKE_KERNEL) == 0,
  76                             FORCEWAKE_ACK_TIMEOUT_MS))
  77                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  78                           intel_uncore_forcewake_domain_to_str(d->id));
  79 }
  80
  81 static inline void
  82 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  83 {
  84         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  85 }
  86
  87 static inline void
  88 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  89 {
  90         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  91                              FORCEWAKE_KERNEL),
  92                             FORCEWAKE_ACK_TIMEOUT_MS))
  93                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  94                           intel_uncore_forcewake_domain_to_str(d->id));
  95 }
  96
  97 static inline void
  98 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  99 {
 100         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 101 }
 102
 103 static inline void
 104 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 105 {
 106         /* something from same cacheline, but not from the set register */
 107         if (i915_mmio_reg_valid(d->reg_post))
 108                 __raw_posting_read(d->i915, d->reg_post);
 109 }
 110
 111 static void
 112 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 113 {
 114         struct intel_uncore_forcewake_domain *d;
 115
 116         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 117                 fw_domain_wait_ack_clear(d);
 118                 fw_domain_get(d);
 119         }
 120
 121         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 122                 fw_domain_wait_ack(d);
 123
 124         dev_priv->uncore.fw_domains_active |= fw_domains;
 125 }
 126
 127 static void
 128 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 129 {
 130         struct intel_uncore_forcewake_domain *d;
 131
 132         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 133                 fw_domain_put(d);
 134                 fw_domain_posting_read(d);
 135         }
 136
 137         dev_priv->uncore.fw_domains_active &= ~fw_domains;
 138 }
 139
 140 static void
 141 vgpu_fw_domains_nop(struct drm_i915_private *dev_priv,
 142                     enum forcewake_domains fw_domains)
 143 {
 144         /* Guest driver doesn't need to takes care forcewake. */
 145 }
 146
 147 static void
 148 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 149 {
 150         struct intel_uncore_forcewake_domain *d;
 151
 152         /* No need to do for all, just do for first found */
 153         for_each_fw_domain(d, dev_priv) {
 154                 fw_domain_posting_read(d);
 155                 break;
 156         }
 157 }
 158
 159 static void
 160 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 161 {
 162         struct intel_uncore_forcewake_domain *d;
 163
 164         if (dev_priv->uncore.fw_domains == 0)
 165                 return;
 166
 167         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 168                 fw_domain_reset(d);
 169
 170         fw_domains_posting_read(dev_priv);
 171 }
 172
 173 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 174 {
 175         /* w/a for a sporadic read returning 0 by waiting for the GT
 176          * thread to wake up.
 177          */
 178         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 179                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 180                 DRM_ERROR("GT thread status wait timed out\n");
 181 }
 182
 183 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 184                                               enum forcewake_domains fw_domains)
 185 {
 186         fw_domains_get(dev_priv, fw_domains);
 187
 188         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 189         __gen6_gt_wait_for_thread_c0(dev_priv);
 190 }
 191
 192 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 193 {
 194         u32 gtfifodbg;
 195
 196         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 197         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 198                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 199 }
 200
 201 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 202                                      enum forcewake_domains fw_domains)
 203 {
 204         fw_domains_put(dev_priv, fw_domains);
 205         gen6_gt_check_fifodbg(dev_priv);
 206 }
 207
 208 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 209 {
 210         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 211
 212         return count & GT_FIFO_FREE_ENTRIES_MASK;
 213 }
 214
 215 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 216 {
 217         int ret = 0;
 218
 219         /* On VLV, FIFO will be shared by both SW and HW.
 220          * So, we need to read the FREE_ENTRIES everytime */
 221         if (IS_VALLEYVIEW(dev_priv))
 222                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 223
 224         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 225                 int loop = 500;
 226                 u32 fifo = fifo_free_entries(dev_priv);
 227
 228                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 229                         udelay(10);
 230                         fifo = fifo_free_entries(dev_priv);
 231                 }
 232                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 233                         ++ret;
 234                 dev_priv->uncore.fifo_count = fifo;
 235         }
 236         dev_priv->uncore.fifo_count--;
 237
 238         return ret;
 239 }
 240
 241 static enum hrtimer_restart
 242 intel_uncore_fw_release_timer(struct hrtimer *timer)
 243 {
 244         struct intel_uncore_forcewake_domain *domain =
 245                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 246         struct drm_i915_private *dev_priv = domain->i915;
 247         unsigned long irqflags;
 248
 249         assert_rpm_device_not_suspended(dev_priv);
 250
 251         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 252         if (WARN_ON(domain->wake_count == 0))
 253                 domain->wake_count++;
 254
 255         if (--domain->wake_count == 0)
 256                 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
 257
 258         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 259
 260         return HRTIMER_NORESTART;
 261 }
 262
 263 static void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
 264                                          bool restore)
 265 {
 266         unsigned long irqflags;
 267         struct intel_uncore_forcewake_domain *domain;
 268         int retry_count = 100;
 269         enum forcewake_domains fw, active_domains;
 270
 271         /* Hold uncore.lock across reset to prevent any register access
 272          * with forcewake not set correctly. Wait until all pending
 273          * timers are run before holding.
 274          */
 275         while (1) {
 276                 active_domains = 0;
 277
 278                 for_each_fw_domain(domain, dev_priv) {
 279                         if (hrtimer_cancel(&domain->timer) == 0)
 280                                 continue;
 281
 282                         intel_uncore_fw_release_timer(&domain->timer);
 283                 }
 284
 285                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 286
 287                 for_each_fw_domain(domain, dev_priv) {
 288                         if (hrtimer_active(&domain->timer))
 289                                 active_domains |= domain->mask;
 290                 }
 291
 292                 if (active_domains == 0)
 293                         break;
 294
 295                 if (--retry_count == 0) {
 296                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 297                         break;
 298                 }
 299
 300                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 301                 cond_resched();
 302         }
 303
 304         WARN_ON(active_domains);
 305
 306         fw = dev_priv->uncore.fw_domains_active;
 307         if (fw)
 308                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 309
 310         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 311
 312         if (restore) { /* If reset with a user forcewake, try to restore */
 313                 if (fw)
 314                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 315
 316                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 317                         dev_priv->uncore.fifo_count =
 318                                 fifo_free_entries(dev_priv);
 319         }
 320
 321         if (!restore)
 322                 assert_forcewakes_inactive(dev_priv);
 323
 324         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 325 }
 326
 327 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
 328 {
 329         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
 330         const unsigned int sets[4] = { 1, 1, 2, 2 };
 331         const u32 cap = dev_priv->edram_cap;
 332
 333         return EDRAM_NUM_BANKS(cap) *
 334                 ways[EDRAM_WAYS_IDX(cap)] *
 335                 sets[EDRAM_SETS_IDX(cap)] *
 336                 1024 * 1024;
 337 }
 338
 339 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 340 {
 341         if (!HAS_EDRAM(dev_priv))
 342                 return 0;
 343
 344         /* The needed capability bits for size calculation
 345          * are not there with pre gen9 so return 128MB always.
 346          */
 347         if (INTEL_GEN(dev_priv) < 9)
 348                 return 128 * 1024 * 1024;
 349
 350         return gen9_edram_size(dev_priv);
 351 }
 352
 353 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 354 {
 355         if (IS_HASWELL(dev_priv) ||
 356             IS_BROADWELL(dev_priv) ||
 357             INTEL_GEN(dev_priv) >= 9) {
 358                 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
 359                                                         HSW_EDRAM_CAP);
 360
 361                 /* NB: We can't write IDICR yet because we do not have gt funcs
 362                  * set up */
 363         } else {
 364                 dev_priv->edram_cap = 0;
 365         }
 366
 367         if (HAS_EDRAM(dev_priv))
 368                 DRM_INFO("Found %lluMB of eDRAM\n",
 369                          intel_uncore_edram_size(dev_priv) / (1024 * 1024));
 370 }
 371
 372 static bool
 373 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 374 {
 375         u32 dbg;
 376
 377         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 378         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 379                 return false;
 380
 381         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 382
 383         return true;
 384 }
 385
 386 static bool
 387 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 388 {
 389         u32 cer;
 390
 391         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 392         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 393                 return false;
 394
 395         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 396
 397         return true;
 398 }
 399
 400 static bool
 401 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 402 {
 403         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 404                 return fpga_check_for_unclaimed_mmio(dev_priv);
 405
 406         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 407                 return vlv_check_for_unclaimed_mmio(dev_priv);
 408
 409         return false;
 410 }
 411
 412 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
 413                                           bool restore_forcewake)
 414 {
 415         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 416
 417         /* clear out unclaimed reg detection bit */
 418         if (check_for_unclaimed_mmio(dev_priv))
 419                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 420
 421         /* clear out old GT FIFO errors */
 422         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 423                 __raw_i915_write32(dev_priv, GTFIFODBG,
 424                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 425
 426         /* WaDisableShadowRegForCpd:chv */
 427         if (IS_CHERRYVIEW(dev_priv)) {
 428                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 429                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 430                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 431                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 432         }
 433
 434         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST))
 435                 info->has_decoupled_mmio = false;
 436
 437         intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
 438 }
 439
 440 void intel_uncore_suspend(struct drm_i915_private *dev_priv)
 441 {
 442         iosf_mbi_unregister_pmic_bus_access_notifier(
 443                 &dev_priv->uncore.pmic_bus_access_nb);
 444         intel_uncore_forcewake_reset(dev_priv, false);
 445 }
 446
 447 void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
 448 {
 449         __intel_uncore_early_sanitize(dev_priv, true);
 450         iosf_mbi_register_pmic_bus_access_notifier(
 451                 &dev_priv->uncore.pmic_bus_access_nb);
 452         i915_check_and_clear_faults(dev_priv);
 453 }
 454
 455 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 456 {
 457         i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
 458
 459         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 460         intel_sanitize_gt_powersave(dev_priv);
 461 }
 462
 463 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 464                                          enum forcewake_domains fw_domains)
 465 {
 466         struct intel_uncore_forcewake_domain *domain;
 467
 468         fw_domains &= dev_priv->uncore.fw_domains;
 469
 470         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 471                 if (domain->wake_count++)
 472                         fw_domains &= ~domain->mask;
 473         }
 474
 475         if (fw_domains)
 476                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 477 }
 478
 479 /**
 480  * intel_uncore_forcewake_get - grab forcewake domain references
 481  * @dev_priv: i915 device instance
 482  * @fw_domains: forcewake domains to get reference on
 483  *
 484  * This function can be used get GT's forcewake domain references.
 485  * Normal register access will handle the forcewake domains automatically.
 486  * However if some sequence requires the GT to not power down a particular
 487  * forcewake domains this function should be called at the beginning of the
 488  * sequence. And subsequently the reference should be dropped by symmetric
 489  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 490  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 491  */
 492 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 493                                 enum forcewake_domains fw_domains)
 494 {
 495         unsigned long irqflags;
 496
 497         if (!dev_priv->uncore.funcs.force_wake_get)
 498                 return;
 499
 500         assert_rpm_wakelock_held(dev_priv);
 501
 502         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 503         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 504         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 505 }
 506
 507 /**
 508  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 509  * @dev_priv: i915 device instance
 510  * @fw_domains: forcewake domains to get reference on
 511  *
 512  * See intel_uncore_forcewake_get(). This variant places the onus
 513  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 514  */
 515 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 516                                         enum forcewake_domains fw_domains)
 517 {
 518         lockdep_assert_held(&dev_priv->uncore.lock);
 519
 520         if (!dev_priv->uncore.funcs.force_wake_get)
 521                 return;
 522
 523         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 524 }
 525
 526 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 527                                          enum forcewake_domains fw_domains)
 528 {
 529         struct intel_uncore_forcewake_domain *domain;
 530
 531         fw_domains &= dev_priv->uncore.fw_domains;
 532
 533         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 534                 if (WARN_ON(domain->wake_count == 0))
 535                         continue;
 536
 537                 if (--domain->wake_count)
 538                         continue;
 539
 540                 fw_domain_arm_timer(domain);
 541         }
 542 }
 543
 544 /**
 545  * intel_uncore_forcewake_put - release a forcewake domain reference
 546  * @dev_priv: i915 device instance
 547  * @fw_domains: forcewake domains to put references
 548  *
 549  * This function drops the device-level forcewakes for specified
 550  * domains obtained by intel_uncore_forcewake_get().
 551  */
 552 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 553                                 enum forcewake_domains fw_domains)
 554 {
 555         unsigned long irqflags;
 556
 557         if (!dev_priv->uncore.funcs.force_wake_put)
 558                 return;
 559
 560         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 561         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 562         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 563 }
 564
 565 /**
 566  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 567  * @dev_priv: i915 device instance
 568  * @fw_domains: forcewake domains to get reference on
 569  *
 570  * See intel_uncore_forcewake_put(). This variant places the onus
 571  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 572  */
 573 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 574                                         enum forcewake_domains fw_domains)
 575 {
 576         lockdep_assert_held(&dev_priv->uncore.lock);
 577
 578         if (!dev_priv->uncore.funcs.force_wake_put)
 579                 return;
 580
 581         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 582 }
 583
 584 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 585 {
 586         if (!dev_priv->uncore.funcs.force_wake_get)
 587                 return;
 588
 589         WARN_ON(dev_priv->uncore.fw_domains_active);
 590 }
 591
 592 /* We give fast paths for the really cool registers */
 593 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 594
 595 #define __gen6_reg_read_fw_domains(offset) \
 596 ({ \
 597         enum forcewake_domains __fwd; \
 598         if (NEEDS_FORCE_WAKE(offset)) \
 599                 __fwd = FORCEWAKE_RENDER; \
 600         else \
 601                 __fwd = 0; \
 602         __fwd; \
 603 })
 604
 605 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 606 {
 607         if (offset < entry->start)
 608                 return -1;
 609         else if (offset > entry->end)
 610                 return 1;
 611         else
 612                 return 0;
 613 }
 614
 615 /* Copied and "macroized" from lib/bsearch.c */
 616 #define BSEARCH(key, base, num, cmp) ({                                 \
 617         unsigned int start__ = 0, end__ = (num);                        \
 618         typeof(base) result__ = NULL;                                   \
 619         while (start__ < end__) {                                       \
 620                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 621                 int ret__ = (cmp)((key), (base) + mid__);               \
 622                 if (ret__ < 0) {                                        \
 623                         end__ = mid__;                                  \
 624                 } else if (ret__ > 0) {                                 \
 625                         start__ = mid__ + 1;                            \
 626                 } else {                                                \
 627                         result__ = (base) + mid__;                      \
 628                         break;                                          \
 629                 }                                                       \
 630         }                                                               \
 631         result__;                                                       \
 632 })
 633
 634 static enum forcewake_domains
 635 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
 636 {
 637         const struct intel_forcewake_range *entry;
 638
 639         entry = BSEARCH(offset,
 640                         dev_priv->uncore.fw_domains_table,
 641                         dev_priv->uncore.fw_domains_table_entries,
 642                         fw_range_cmp);
 643
 644         if (!entry)
 645                 return 0;
 646
 647         WARN(entry->domains & ~dev_priv->uncore.fw_domains,
 648              "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 649              entry->domains & ~dev_priv->uncore.fw_domains, offset);
 650
 651         return entry->domains;
 652 }
 653
 654 #define GEN_FW_RANGE(s, e, d) \
 655         { .start = (s), .end = (e), .domains = (d) }
 656
 657 #define HAS_FWTABLE(dev_priv) \
 658         (IS_GEN9(dev_priv) || \
 659          IS_CHERRYVIEW(dev_priv) || \
 660          IS_VALLEYVIEW(dev_priv))
 661
 662 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 663 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 664         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 665         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 666         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 667         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 668         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 669         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 670         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 671 };
 672
 673 #define __fwtable_reg_read_fw_domains(offset) \
 674 ({ \
 675         enum forcewake_domains __fwd = 0; \
 676         if (NEEDS_FORCE_WAKE((offset))) \
 677                 __fwd = find_fw_domain(dev_priv, offset); \
 678         __fwd; \
 679 })
 680
 681 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 682 static const i915_reg_t gen8_shadowed_regs[] = {
 683         RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
 684         GEN6_RPNSWREQ,                  /* 0xA008 */
 685         GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
 686         RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
 687         RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
 688         RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
 689         /* TODO: Other registers are not yet used */
 690 };
 691
 692 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 693 {
 694         u32 offset = i915_mmio_reg_offset(*reg);
 695
 696         if (key < offset)
 697                 return -1;
 698         else if (key > offset)
 699                 return 1;
 700         else
 701                 return 0;
 702 }
 703
 704 static bool is_gen8_shadowed(u32 offset)
 705 {
 706         const i915_reg_t *regs = gen8_shadowed_regs;
 707
 708         return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
 709                        mmio_reg_cmp);
 710 }
 711
 712 #define __gen8_reg_write_fw_domains(offset) \
 713 ({ \
 714         enum forcewake_domains __fwd; \
 715         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 716                 __fwd = FORCEWAKE_RENDER; \
 717         else \
 718                 __fwd = 0; \
 719         __fwd; \
 720 })
 721
 722 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 723 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 724         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 725         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 726         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 727         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 728         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 729         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 730         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
 731         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 732         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 733         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 734         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
 735         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 736         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 737         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
 738         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
 739         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
 740 };
 741
 742 #define __fwtable_reg_write_fw_domains(offset) \
 743 ({ \
 744         enum forcewake_domains __fwd = 0; \
 745         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
 746                 __fwd = find_fw_domain(dev_priv, offset); \
 747         __fwd; \
 748 })
 749
 750 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 751 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 752         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 753         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 754         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 755         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 756         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 757         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 758         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 759         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
 760         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
 761         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
 762         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
 763         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 764         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
 765         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
 766         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
 767         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
 768         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
 769         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 770         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
 771         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 772         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
 773         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 774         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
 775         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
 776         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
 777         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 778         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
 779         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
 780         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
 781         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
 782         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
 783         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 784 };
 785
 786 static void
 787 ilk_dummy_write(struct drm_i915_private *dev_priv)
 788 {
 789         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 790          * the chip from rc6 before touching it for real. MI_MODE is masked,
 791          * hence harmless to write 0 into. */
 792         __raw_i915_write32(dev_priv, MI_MODE, 0);
 793 }
 794
 795 static void
 796 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 797                       const i915_reg_t reg,
 798                       const bool read,
 799                       const bool before)
 800 {
 801         if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
 802                  "Unclaimed %s register 0x%x\n",
 803                  read ? "read from" : "write to",
 804                  i915_mmio_reg_offset(reg)))
 805                 i915.mmio_debug--; /* Only report the first N failures */
 806 }
 807
 808 static inline void
 809 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 810                     const i915_reg_t reg,
 811                     const bool read,
 812                     const bool before)
 813 {
 814         if (likely(!i915.mmio_debug))
 815                 return;
 816
 817         __unclaimed_reg_debug(dev_priv, reg, read, before);
 818 }
 819
 820 static const enum decoupled_power_domain fw2dpd_domain[] = {
 821         GEN9_DECOUPLED_PD_RENDER,
 822         GEN9_DECOUPLED_PD_BLITTER,
 823         GEN9_DECOUPLED_PD_ALL,
 824         GEN9_DECOUPLED_PD_MEDIA,
 825         GEN9_DECOUPLED_PD_ALL,
 826         GEN9_DECOUPLED_PD_ALL,
 827         GEN9_DECOUPLED_PD_ALL
 828 };
 829
 830 /*
 831  * Decoupled MMIO access for only 1 DWORD
 832  */
 833 static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
 834                                          u32 reg,
 835                                          enum forcewake_domains fw_domain,
 836                                          enum decoupled_ops operation)
 837 {
 838         enum decoupled_power_domain dp_domain;
 839         u32 ctrl_reg_data = 0;
 840
 841         dp_domain = fw2dpd_domain[fw_domain - 1];
 842
 843         ctrl_reg_data |= reg;
 844         ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
 845         ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT);
 846         ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
 847         __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
 848
 849         if (wait_for_atomic((__raw_i915_read32(dev_priv,
 850                             GEN9_DECOUPLED_REG0_DW1) &
 851                             GEN9_DECOUPLED_DW1_GO) == 0,
 852                             FORCEWAKE_ACK_TIMEOUT_MS))
 853                 DRM_ERROR("Decoupled MMIO wait timed out\n");
 854 }
 855
 856 static inline u32
 857 __gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv,
 858                              u32 reg,
 859                              enum forcewake_domains fw_domain)
 860 {
 861         __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
 862                                      GEN9_DECOUPLED_OP_READ);
 863
 864         return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0);
 865 }
 866
 867 static inline void
 868 __gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv,
 869                             u32 reg, u32 data,
 870                             enum forcewake_domains fw_domain)
 871 {
 872
 873         __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data);
 874
 875         __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
 876                                      GEN9_DECOUPLED_OP_WRITE);
 877 }
 878
 879
 880 #define GEN2_READ_HEADER(x) \
 881         u##x val = 0; \
 882         assert_rpm_wakelock_held(dev_priv);
 883
 884 #define GEN2_READ_FOOTER \
 885         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 886         return val
 887
 888 #define __gen2_read(x) \
 889 static u##x \
 890 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 891         GEN2_READ_HEADER(x); \
 892         val = __raw_i915_read##x(dev_priv, reg); \
 893         GEN2_READ_FOOTER; \
 894 }
 895
 896 #define __gen5_read(x) \
 897 static u##x \
 898 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 899         GEN2_READ_HEADER(x); \
 900         ilk_dummy_write(dev_priv); \
 901         val = __raw_i915_read##x(dev_priv, reg); \
 902         GEN2_READ_FOOTER; \
 903 }
 904
 905 __gen5_read(8)
 906 __gen5_read(16)
 907 __gen5_read(32)
 908 __gen5_read(64)
 909 __gen2_read(8)
 910 __gen2_read(16)
 911 __gen2_read(32)
 912 __gen2_read(64)
 913
 914 #undef __gen5_read
 915 #undef __gen2_read
 916
 917 #undef GEN2_READ_FOOTER
 918 #undef GEN2_READ_HEADER
 919
 920 #define GEN6_READ_HEADER(x) \
 921         u32 offset = i915_mmio_reg_offset(reg); \
 922         unsigned long irqflags; \
 923         u##x val = 0; \
 924         assert_rpm_wakelock_held(dev_priv); \
 925         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 926         unclaimed_reg_debug(dev_priv, reg, true, true)
 927
 928 #define GEN6_READ_FOOTER \
 929         unclaimed_reg_debug(dev_priv, reg, true, false); \
 930         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 931         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 932         return val
 933
 934 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
 935                                         enum forcewake_domains fw_domains)
 936 {
 937         struct intel_uncore_forcewake_domain *domain;
 938
 939         for_each_fw_domain_masked(domain, fw_domains, dev_priv)
 940                 fw_domain_arm_timer(domain);
 941
 942         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 943 }
 944
 945 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
 946                                      enum forcewake_domains fw_domains)
 947 {
 948         if (WARN_ON(!fw_domains))
 949                 return;
 950
 951         /* Turn on all requested but inactive supported forcewake domains. */
 952         fw_domains &= dev_priv->uncore.fw_domains;
 953         fw_domains &= ~dev_priv->uncore.fw_domains_active;
 954
 955         if (fw_domains)
 956                 ___force_wake_auto(dev_priv, fw_domains);
 957 }
 958
 959 #define __gen_read(func, x) \
 960 static u##x \
 961 func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 962         enum forcewake_domains fw_engine; \
 963         GEN6_READ_HEADER(x); \
 964         fw_engine = __##func##_reg_read_fw_domains(offset); \
 965         if (fw_engine) \
 966                 __force_wake_auto(dev_priv, fw_engine); \
 967         val = __raw_i915_read##x(dev_priv, reg); \
 968         GEN6_READ_FOOTER; \
 969 }
 970 #define __gen6_read(x) __gen_read(gen6, x)
 971 #define __fwtable_read(x) __gen_read(fwtable, x)
 972
 973 #define __gen9_decoupled_read(x) \
 974 static u##x \
 975 gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \
 976                        i915_reg_t reg, bool trace) { \
 977         enum forcewake_domains fw_engine; \
 978         GEN6_READ_HEADER(x); \
 979         fw_engine = __fwtable_reg_read_fw_domains(offset); \
 980         if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \
 981                 unsigned i; \
 982                 u32 *ptr_data = (u32 *) &val; \
 983                 for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
 984                         *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \
 985                                                                  offset, \
 986                                                                  fw_engine); \
 987         } else { \
 988                 val = __raw_i915_read##x(dev_priv, reg); \
 989         } \
 990         GEN6_READ_FOOTER; \
 991 }
 992
 993 __gen9_decoupled_read(32)
 994 __gen9_decoupled_read(64)
 995 __fwtable_read(8)
 996 __fwtable_read(16)
 997 __fwtable_read(32)
 998 __fwtable_read(64)
 999 __gen6_read(8)
1000 __gen6_read(16)
1001 __gen6_read(32)
1002 __gen6_read(64)
1003
1004 #undef __fwtable_read
1005 #undef __gen6_read
1006 #undef GEN6_READ_FOOTER
1007 #undef GEN6_READ_HEADER
1008
1009 #define GEN2_WRITE_HEADER \
1010         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1011         assert_rpm_wakelock_held(dev_priv); \
1012
1013 #define GEN2_WRITE_FOOTER
1014
1015 #define __gen2_write(x) \
1016 static void \
1017 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1018         GEN2_WRITE_HEADER; \
1019         __raw_i915_write##x(dev_priv, reg, val); \
1020         GEN2_WRITE_FOOTER; \
1021 }
1022
1023 #define __gen5_write(x) \
1024 static void \
1025 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1026         GEN2_WRITE_HEADER; \
1027         ilk_dummy_write(dev_priv); \
1028         __raw_i915_write##x(dev_priv, reg, val); \
1029         GEN2_WRITE_FOOTER; \
1030 }
1031
1032 __gen5_write(8)
1033 __gen5_write(16)
1034 __gen5_write(32)
1035 __gen2_write(8)
1036 __gen2_write(16)
1037 __gen2_write(32)
1038
1039 #undef __gen5_write
1040 #undef __gen2_write
1041
1042 #undef GEN2_WRITE_FOOTER
1043 #undef GEN2_WRITE_HEADER
1044
1045 #define GEN6_WRITE_HEADER \
1046         u32 offset = i915_mmio_reg_offset(reg); \
1047         unsigned long irqflags; \
1048         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1049         assert_rpm_wakelock_held(dev_priv); \
1050         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1051         unclaimed_reg_debug(dev_priv, reg, false, true)
1052
1053 #define GEN6_WRITE_FOOTER \
1054         unclaimed_reg_debug(dev_priv, reg, false, false); \
1055         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1056
1057 #define __gen6_write(x) \
1058 static void \
1059 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1060         u32 __fifo_ret = 0; \
1061         GEN6_WRITE_HEADER; \
1062         if (NEEDS_FORCE_WAKE(offset)) { \
1063                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1064         } \
1065         __raw_i915_write##x(dev_priv, reg, val); \
1066         if (unlikely(__fifo_ret)) { \
1067                 gen6_gt_check_fifodbg(dev_priv); \
1068         } \
1069         GEN6_WRITE_FOOTER; \
1070 }
1071
1072 #define __gen_write(func, x) \
1073 static void \
1074 func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1075         enum forcewake_domains fw_engine; \
1076         GEN6_WRITE_HEADER; \
1077         fw_engine = __##func##_reg_write_fw_domains(offset); \
1078         if (fw_engine) \
1079                 __force_wake_auto(dev_priv, fw_engine); \
1080         __raw_i915_write##x(dev_priv, reg, val); \
1081         GEN6_WRITE_FOOTER; \
1082 }
1083 #define __gen8_write(x) __gen_write(gen8, x)
1084 #define __fwtable_write(x) __gen_write(fwtable, x)
1085
1086 #define __gen9_decoupled_write(x) \
1087 static void \
1088 gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \
1089                         i915_reg_t reg, u##x val, \
1090                 bool trace) { \
1091         enum forcewake_domains fw_engine; \
1092         GEN6_WRITE_HEADER; \
1093         fw_engine = __fwtable_reg_write_fw_domains(offset); \
1094         if (fw_engine & ~dev_priv->uncore.fw_domains_active) \
1095                 __gen9_decoupled_mmio_write(dev_priv, \
1096                                             offset, \
1097                                             val, \
1098                                             fw_engine); \
1099         else \
1100                 __raw_i915_write##x(dev_priv, reg, val); \
1101         GEN6_WRITE_FOOTER; \
1102 }
1103
1104 __gen9_decoupled_write(32)
1105 __fwtable_write(8)
1106 __fwtable_write(16)
1107 __fwtable_write(32)
1108 __gen8_write(8)
1109 __gen8_write(16)
1110 __gen8_write(32)
1111 __gen6_write(8)
1112 __gen6_write(16)
1113 __gen6_write(32)
1114
1115 #undef __fwtable_write
1116 #undef __gen8_write
1117 #undef __gen6_write
1118 #undef GEN6_WRITE_FOOTER
1119 #undef GEN6_WRITE_HEADER
1120
1121 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1122 do { \
1123         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1124         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1125         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1126 } while (0)
1127
1128 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1129 do { \
1130         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1131         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1132         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1133         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1134 } while (0)
1135
1136
1137 static void fw_domain_init(struct drm_i915_private *dev_priv,
1138                            enum forcewake_domain_id domain_id,
1139                            i915_reg_t reg_set,
1140                            i915_reg_t reg_ack)
1141 {
1142         struct intel_uncore_forcewake_domain *d;
1143
1144         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1145                 return;
1146
1147         d = &dev_priv->uncore.fw_domain[domain_id];
1148
1149         WARN_ON(d->wake_count);
1150
1151         d->wake_count = 0;
1152         d->reg_set = reg_set;
1153         d->reg_ack = reg_ack;
1154
1155         if (IS_GEN6(dev_priv)) {
1156                 d->val_reset = 0;
1157                 d->val_set = FORCEWAKE_KERNEL;
1158                 d->val_clear = 0;
1159         } else {
1160                 /* WaRsClearFWBitsAtReset:bdw,skl */
1161                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1162                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1163                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1164         }
1165
1166         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1167                 d->reg_post = FORCEWAKE_ACK_VLV;
1168         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1169                 d->reg_post = ECOBUS;
1170
1171         d->i915 = dev_priv;
1172         d->id = domain_id;
1173
1174         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1175         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1176         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1177
1178         d->mask = 1 << domain_id;
1179
1180         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1181         d->timer.function = intel_uncore_fw_release_timer;
1182
1183         dev_priv->uncore.fw_domains |= (1 << domain_id);
1184
1185         fw_domain_reset(d);
1186 }
1187
1188 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1189 {
1190         if (INTEL_INFO(dev_priv)->gen <= 5)
1191                 return;
1192
1193         if (IS_GEN9(dev_priv)) {
1194                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1195                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1196                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1197                                FORCEWAKE_RENDER_GEN9,
1198                                FORCEWAKE_ACK_RENDER_GEN9);
1199                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1200                                FORCEWAKE_BLITTER_GEN9,
1201                                FORCEWAKE_ACK_BLITTER_GEN9);
1202                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1203                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1204         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1205                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1206                 if (!IS_CHERRYVIEW(dev_priv))
1207                         dev_priv->uncore.funcs.force_wake_put =
1208                                 fw_domains_put_with_fifo;
1209                 else
1210                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1211                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1212                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1213                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1214                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1215         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1216                 dev_priv->uncore.funcs.force_wake_get =
1217                         fw_domains_get_with_thread_status;
1218                 if (IS_HASWELL(dev_priv))
1219                         dev_priv->uncore.funcs.force_wake_put =
1220                                 fw_domains_put_with_fifo;
1221                 else
1222                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1223                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1224                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1225         } else if (IS_IVYBRIDGE(dev_priv)) {
1226                 u32 ecobus;
1227
1228                 /* IVB configs may use multi-threaded forcewake */
1229
1230                 /* A small trick here - if the bios hasn't configured
1231                  * MT forcewake, and if the device is in RC6, then
1232                  * force_wake_mt_get will not wake the device and the
1233                  * ECOBUS read will return zero. Which will be
1234                  * (correctly) interpreted by the test below as MT
1235                  * forcewake being disabled.
1236                  */
1237                 dev_priv->uncore.funcs.force_wake_get =
1238                         fw_domains_get_with_thread_status;
1239                 dev_priv->uncore.funcs.force_wake_put =
1240                         fw_domains_put_with_fifo;
1241
1242                 /* We need to init first for ECOBUS access and then
1243                  * determine later if we want to reinit, in case of MT access is
1244                  * not working. In this stage we don't know which flavour this
1245                  * ivb is, so it is better to reset also the gen6 fw registers
1246                  * before the ecobus check.
1247                  */
1248
1249                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1250                 __raw_posting_read(dev_priv, ECOBUS);
1251
1252                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1253                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1254
1255                 spin_lock_irq(&dev_priv->uncore.lock);
1256                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1257                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1258                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1259                 spin_unlock_irq(&dev_priv->uncore.lock);
1260
1261                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1262                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1263                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1264                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1265                                        FORCEWAKE, FORCEWAKE_ACK);
1266                 }
1267         } else if (IS_GEN6(dev_priv)) {
1268                 dev_priv->uncore.funcs.force_wake_get =
1269                         fw_domains_get_with_thread_status;
1270                 dev_priv->uncore.funcs.force_wake_put =
1271                         fw_domains_put_with_fifo;
1272                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1273                                FORCEWAKE, FORCEWAKE_ACK);
1274         }
1275
1276         if (intel_vgpu_active(dev_priv)) {
1277                 dev_priv->uncore.funcs.force_wake_get = vgpu_fw_domains_nop;
1278                 dev_priv->uncore.funcs.force_wake_put = vgpu_fw_domains_nop;
1279         }
1280
1281         /* All future platforms are expected to require complex power gating */
1282         WARN_ON(dev_priv->uncore.fw_domains == 0);
1283 }
1284
1285 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1286 { \
1287         dev_priv->uncore.fw_domains_table = \
1288                         (struct intel_forcewake_range *)(d); \
1289         dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1290 }
1291
1292 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1293                                          unsigned long action, void *data)
1294 {
1295         struct drm_i915_private *dev_priv = container_of(nb,
1296                         struct drm_i915_private, uncore.pmic_bus_access_nb);
1297
1298         switch (action) {
1299         case MBI_PMIC_BUS_ACCESS_BEGIN:
1300                 /*
1301                  * forcewake all now to make sure that we don't need to do a
1302                  * forcewake later which on systems where this notifier gets
1303                  * called requires the punit to access to the shared pmic i2c
1304                  * bus, which will be busy after this notification, leading to:
1305                  * "render: timed out waiting for forcewake ack request."
1306                  * errors.
1307                  */
1308                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1309                 break;
1310         case MBI_PMIC_BUS_ACCESS_END:
1311                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1312                 break;
1313         }
1314
1315         return NOTIFY_OK;
1316 }
1317
1318 void intel_uncore_init(struct drm_i915_private *dev_priv)
1319 {
1320         i915_check_vgpu(dev_priv);
1321
1322         intel_uncore_edram_detect(dev_priv);
1323         intel_uncore_fw_domains_init(dev_priv);
1324         __intel_uncore_early_sanitize(dev_priv, false);
1325
1326         dev_priv->uncore.unclaimed_mmio_check = 1;
1327         dev_priv->uncore.pmic_bus_access_nb.notifier_call =
1328                 i915_pmic_bus_access_notifier;
1329
1330         switch (INTEL_INFO(dev_priv)->gen) {
1331         default:
1332         case 9:
1333                 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1334                 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1335                 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1336                 if (HAS_DECOUPLED_MMIO(dev_priv)) {
1337                         dev_priv->uncore.funcs.mmio_readl =
1338                                                 gen9_decoupled_read32;
1339                         dev_priv->uncore.funcs.mmio_readq =
1340                                                 gen9_decoupled_read64;
1341                         dev_priv->uncore.funcs.mmio_writel =
1342                                                 gen9_decoupled_write32;
1343                 }
1344                 break;
1345         case 8:
1346                 if (IS_CHERRYVIEW(dev_priv)) {
1347                         ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1348                         ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1349                         ASSIGN_READ_MMIO_VFUNCS(fwtable);
1350
1351                 } else {
1352                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1353                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1354                 }
1355                 break;
1356         case 7:
1357         case 6:
1358                 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1359
1360                 if (IS_VALLEYVIEW(dev_priv)) {
1361                         ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1362                         ASSIGN_READ_MMIO_VFUNCS(fwtable);
1363                 } else {
1364                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1365                 }
1366                 break;
1367         case 5:
1368                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1369                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1370                 break;
1371         case 4:
1372         case 3:
1373         case 2:
1374                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1375                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1376                 break;
1377         }
1378
1379         iosf_mbi_register_pmic_bus_access_notifier(
1380                 &dev_priv->uncore.pmic_bus_access_nb);
1381
1382         i915_check_and_clear_faults(dev_priv);
1383 }
1384 #undef ASSIGN_WRITE_MMIO_VFUNCS
1385 #undef ASSIGN_READ_MMIO_VFUNCS
1386
1387 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1388 {
1389         iosf_mbi_unregister_pmic_bus_access_notifier(
1390                 &dev_priv->uncore.pmic_bus_access_nb);
1391
1392         /* Paranoia: make sure we have disabled everything before we exit. */
1393         intel_uncore_sanitize(dev_priv);
1394         intel_uncore_forcewake_reset(dev_priv, false);
1395 }
1396
1397 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1398
1399 static const struct register_whitelist {
1400         i915_reg_t offset_ldw, offset_udw;
1401         uint32_t size;
1402         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1403         uint32_t gen_bitmask;
1404 } whitelist[] = {
1405         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1406           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1407           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1408 };
1409
1410 int i915_reg_read_ioctl(struct drm_device *dev,
1411                         void *data, struct drm_file *file)
1412 {
1413         struct drm_i915_private *dev_priv = to_i915(dev);
1414         struct drm_i915_reg_read *reg = data;
1415         struct register_whitelist const *entry = whitelist;
1416         unsigned size;
1417         i915_reg_t offset_ldw, offset_udw;
1418         int i, ret = 0;
1419
1420         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1421                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1422                     (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
1423                         break;
1424         }
1425
1426         if (i == ARRAY_SIZE(whitelist))
1427                 return -EINVAL;
1428
1429         /* We use the low bits to encode extra flags as the register should
1430          * be naturally aligned (and those that are not so aligned merely
1431          * limit the available flags for that register).
1432          */
1433         offset_ldw = entry->offset_ldw;
1434         offset_udw = entry->offset_udw;
1435         size = entry->size;
1436         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1437
1438         intel_runtime_pm_get(dev_priv);
1439
1440         switch (size) {
1441         case 8 | 1:
1442                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1443                 break;
1444         case 8:
1445                 reg->val = I915_READ64(offset_ldw);
1446                 break;
1447         case 4:
1448                 reg->val = I915_READ(offset_ldw);
1449                 break;
1450         case 2:
1451                 reg->val = I915_READ16(offset_ldw);
1452                 break;
1453         case 1:
1454                 reg->val = I915_READ8(offset_ldw);
1455                 break;
1456         default:
1457                 ret = -EINVAL;
1458                 goto out;
1459         }
1460
1461 out:
1462         intel_runtime_pm_put(dev_priv);
1463         return ret;
1464 }
1465
1466 static int i915_reset_complete(struct pci_dev *pdev)
1467 {
1468         u8 gdrst;
1469         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1470         return (gdrst & GRDOM_RESET_STATUS) == 0;
1471 }
1472
1473 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1474 {
1475         struct pci_dev *pdev = dev_priv->drm.pdev;
1476
1477         /* assert reset for at least 20 usec */
1478         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1479         udelay(20);
1480         pci_write_config_byte(pdev, I915_GDRST, 0);
1481
1482         return wait_for(i915_reset_complete(pdev), 500);
1483 }
1484
1485 static int g4x_reset_complete(struct pci_dev *pdev)
1486 {
1487         u8 gdrst;
1488         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1489         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1490 }
1491
1492 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1493 {
1494         struct pci_dev *pdev = dev_priv->drm.pdev;
1495         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1496         return wait_for(g4x_reset_complete(pdev), 500);
1497 }
1498
1499 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1500 {
1501         struct pci_dev *pdev = dev_priv->drm.pdev;
1502         int ret;
1503
1504         pci_write_config_byte(pdev, I915_GDRST,
1505                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1506         ret =  wait_for(g4x_reset_complete(pdev), 500);
1507         if (ret)
1508                 return ret;
1509
1510         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1511         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1512         POSTING_READ(VDECCLK_GATE_D);
1513
1514         pci_write_config_byte(pdev, I915_GDRST,
1515                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1516         ret =  wait_for(g4x_reset_complete(pdev), 500);
1517         if (ret)
1518                 return ret;
1519
1520         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1521         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1522         POSTING_READ(VDECCLK_GATE_D);
1523
1524         pci_write_config_byte(pdev, I915_GDRST, 0);
1525
1526         return 0;
1527 }
1528
1529 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1530                              unsigned engine_mask)
1531 {
1532         int ret;
1533
1534         I915_WRITE(ILK_GDSR,
1535                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1536         ret = intel_wait_for_register(dev_priv,
1537                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1538                                       500);
1539         if (ret)
1540                 return ret;
1541
1542         I915_WRITE(ILK_GDSR,
1543                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1544         ret = intel_wait_for_register(dev_priv,
1545                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1546                                       500);
1547         if (ret)
1548                 return ret;
1549
1550         I915_WRITE(ILK_GDSR, 0);
1551
1552         return 0;
1553 }
1554
1555 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1556 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1557                                 u32 hw_domain_mask)
1558 {
1559         /* GEN6_GDRST is not in the gt power well, no need to check
1560          * for fifo space for the write or forcewake the chip for
1561          * the read
1562          */
1563         __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1564
1565         /* Spin waiting for the device to ack the reset requests */
1566         return intel_wait_for_register_fw(dev_priv,
1567                                           GEN6_GDRST, hw_domain_mask, 0,
1568                                           500);
1569 }
1570
1571 /**
1572  * gen6_reset_engines - reset individual engines
1573  * @dev_priv: i915 device
1574  * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1575  *
1576  * This function will reset the individual engines that are set in engine_mask.
1577  * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1578  *
1579  * Note: It is responsibility of the caller to handle the difference between
1580  * asking full domain reset versus reset for all available individual engines.
1581  *
1582  * Returns 0 on success, nonzero on error.
1583  */
1584 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1585                               unsigned engine_mask)
1586 {
1587         struct intel_engine_cs *engine;
1588         const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1589                 [RCS] = GEN6_GRDOM_RENDER,
1590                 [BCS] = GEN6_GRDOM_BLT,
1591                 [VCS] = GEN6_GRDOM_MEDIA,
1592                 [VCS2] = GEN8_GRDOM_MEDIA2,
1593                 [VECS] = GEN6_GRDOM_VECS,
1594         };
1595         u32 hw_mask;
1596         int ret;
1597
1598         if (engine_mask == ALL_ENGINES) {
1599                 hw_mask = GEN6_GRDOM_FULL;
1600         } else {
1601                 unsigned int tmp;
1602
1603                 hw_mask = 0;
1604                 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1605                         hw_mask |= hw_engine_mask[engine->id];
1606         }
1607
1608         ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1609
1610         intel_uncore_forcewake_reset(dev_priv, true);
1611
1612         return ret;
1613 }
1614
1615 /**
1616  * intel_wait_for_register_fw - wait until register matches expected state
1617  * @dev_priv: the i915 device
1618  * @reg: the register to read
1619  * @mask: mask to apply to register value
1620  * @value: expected value
1621  * @timeout_ms: timeout in millisecond
1622  *
1623  * This routine waits until the target register @reg contains the expected
1624  * @value after applying the @mask, i.e. it waits until ::
1625  *
1626  *     (I915_READ_FW(reg) & mask) == value
1627  *
1628  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1629  *
1630  * Note that this routine assumes the caller holds forcewake asserted, it is
1631  * not suitable for very long waits. See intel_wait_for_register() if you
1632  * wish to wait without holding forcewake for the duration (i.e. you expect
1633  * the wait to be slow).
1634  *
1635  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1636  */
1637 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1638                                i915_reg_t reg,
1639                                const u32 mask,
1640                                const u32 value,
1641                                const unsigned long timeout_ms)
1642 {
1643 #define done ((I915_READ_FW(reg) & mask) == value)
1644         int ret = wait_for_us(done, 2);
1645         if (ret)
1646                 ret = wait_for(done, timeout_ms);
1647         return ret;
1648 #undef done
1649 }
1650
1651 /**
1652  * intel_wait_for_register - wait until register matches expected state
1653  * @dev_priv: the i915 device
1654  * @reg: the register to read
1655  * @mask: mask to apply to register value
1656  * @value: expected value
1657  * @timeout_ms: timeout in millisecond
1658  *
1659  * This routine waits until the target register @reg contains the expected
1660  * @value after applying the @mask, i.e. it waits until ::
1661  *
1662  *     (I915_READ(reg) & mask) == value
1663  *
1664  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1665  *
1666  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1667  */
1668 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1669                             i915_reg_t reg,
1670                             const u32 mask,
1671                             const u32 value,
1672                             const unsigned long timeout_ms)
1673 {
1674
1675         unsigned fw =
1676                 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1677         int ret;
1678
1679         intel_uncore_forcewake_get(dev_priv, fw);
1680         ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1681         intel_uncore_forcewake_put(dev_priv, fw);
1682         if (ret)
1683                 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1684                                timeout_ms);
1685
1686         return ret;
1687 }
1688
1689 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1690 {
1691         struct drm_i915_private *dev_priv = engine->i915;
1692         int ret;
1693
1694         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1695                       _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1696
1697         ret = intel_wait_for_register_fw(dev_priv,
1698                                          RING_RESET_CTL(engine->mmio_base),
1699                                          RESET_CTL_READY_TO_RESET,
1700                                          RESET_CTL_READY_TO_RESET,
1701                                          700);
1702         if (ret)
1703                 DRM_ERROR("%s: reset request timeout\n", engine->name);
1704
1705         return ret;
1706 }
1707
1708 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1709 {
1710         struct drm_i915_private *dev_priv = engine->i915;
1711
1712         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1713                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1714 }
1715
1716 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1717                               unsigned engine_mask)
1718 {
1719         struct intel_engine_cs *engine;
1720         unsigned int tmp;
1721
1722         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1723                 if (gen8_request_engine_reset(engine))
1724                         goto not_ready;
1725
1726         return gen6_reset_engines(dev_priv, engine_mask);
1727
1728 not_ready:
1729         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1730                 gen8_unrequest_engine_reset(engine);
1731
1732         return -EIO;
1733 }
1734
1735 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1736
1737 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1738 {
1739         if (!i915.reset)
1740                 return NULL;
1741
1742         if (INTEL_INFO(dev_priv)->gen >= 8)
1743                 return gen8_reset_engines;
1744         else if (INTEL_INFO(dev_priv)->gen >= 6)
1745                 return gen6_reset_engines;
1746         else if (IS_GEN5(dev_priv))
1747                 return ironlake_do_reset;
1748         else if (IS_G4X(dev_priv))
1749                 return g4x_do_reset;
1750         else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
1751                 return g33_do_reset;
1752         else if (INTEL_INFO(dev_priv)->gen >= 3)
1753                 return i915_do_reset;
1754         else
1755                 return NULL;
1756 }
1757
1758 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1759 {
1760         reset_func reset;
1761         int ret;
1762
1763         reset = intel_get_gpu_reset(dev_priv);
1764         if (reset == NULL)
1765                 return -ENODEV;
1766
1767         /* If the power well sleeps during the reset, the reset
1768          * request may be dropped and never completes (causing -EIO).
1769          */
1770         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1771         ret = reset(dev_priv, engine_mask);
1772         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1773
1774         return ret;
1775 }
1776
1777 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1778 {
1779         return intel_get_gpu_reset(dev_priv) != NULL;
1780 }
1781
1782 int intel_guc_reset(struct drm_i915_private *dev_priv)
1783 {
1784         int ret;
1785         unsigned long irqflags;
1786
1787         if (!HAS_GUC(dev_priv))
1788                 return -EINVAL;
1789
1790         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1791         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1792
1793         ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1794
1795         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1796         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1797
1798         return ret;
1799 }
1800
1801 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1802 {
1803         return check_for_unclaimed_mmio(dev_priv);
1804 }
1805
1806 bool
1807 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1808 {
1809         if (unlikely(i915.mmio_debug ||
1810                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1811                 return false;
1812
1813         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1814                 DRM_DEBUG("Unclaimed register detected, "
1815                           "enabling oneshot unclaimed register reporting. "
1816                           "Please use i915.mmio_debug=N for more information.\n");
1817                 i915.mmio_debug++;
1818                 dev_priv->uncore.unclaimed_mmio_check--;
1819                 return true;
1820         }
1821
1822         return false;
1823 }
1824
1825 static enum forcewake_domains
1826 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1827                                 i915_reg_t reg)
1828 {
1829         u32 offset = i915_mmio_reg_offset(reg);
1830         enum forcewake_domains fw_domains;
1831
1832         if (HAS_FWTABLE(dev_priv)) {
1833                 fw_domains = __fwtable_reg_read_fw_domains(offset);
1834         } else if (INTEL_GEN(dev_priv) >= 6) {
1835                 fw_domains = __gen6_reg_read_fw_domains(offset);
1836         } else {
1837                 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1838                 fw_domains = 0;
1839         }
1840
1841         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1842
1843         return fw_domains;
1844 }
1845
1846 static enum forcewake_domains
1847 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1848                                  i915_reg_t reg)
1849 {
1850         u32 offset = i915_mmio_reg_offset(reg);
1851         enum forcewake_domains fw_domains;
1852
1853         if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1854                 fw_domains = __fwtable_reg_write_fw_domains(offset);
1855         } else if (IS_GEN8(dev_priv)) {
1856                 fw_domains = __gen8_reg_write_fw_domains(offset);
1857         } else if (IS_GEN(dev_priv, 6, 7)) {
1858                 fw_domains = FORCEWAKE_RENDER;
1859         } else {
1860                 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1861                 fw_domains = 0;
1862         }
1863
1864         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1865
1866         return fw_domains;
1867 }
1868
1869 /**
1870  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1871  *                                  a register
1872  * @dev_priv: pointer to struct drm_i915_private
1873  * @reg: register in question
1874  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1875  *
1876  * Returns a set of forcewake domains required to be taken with for example
1877  * intel_uncore_forcewake_get for the specified register to be accessible in the
1878  * specified mode (read, write or read/write) with raw mmio accessors.
1879  *
1880  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1881  * callers to do FIFO management on their own or risk losing writes.
1882  */
1883 enum forcewake_domains
1884 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1885                                i915_reg_t reg, unsigned int op)
1886 {
1887         enum forcewake_domains fw_domains = 0;
1888
1889         WARN_ON(!op);
1890
1891         if (intel_vgpu_active(dev_priv))
1892                 return 0;
1893
1894         if (op & FW_REG_READ)
1895                 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1896
1897         if (op & FW_REG_WRITE)
1898                 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1899
1900         return fw_domains;
1901 }
1902
1903 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1904 #include "selftests/intel_uncore.c"
1905 #endif