2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_rect.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_plane_helper.h>
39 #include "intel_drv.h"
40 #include "intel_frontbuffer.h"
41 #include <drm/i915_drm.h>
44 bool intel_format_is_yuv(u32 format)
58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
62 if (!adjusted_mode->crtc_htotal)
65 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
66 1000 * adjusted_mode->crtc_htotal);
69 /* FIXME: We should instead only take spinlocks once for the entire update
70 * instead of once per mmio. */
71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
72 #define VBLANK_EVASION_TIME_US 250
74 #define VBLANK_EVASION_TIME_US 100
78 * intel_pipe_update_start() - start update of a set of display registers
79 * @new_crtc_state: the new crtc state
81 * Mark the start of an update to pipe registers that should be updated
82 * atomically regarding vblank. If the next vblank will happens within
83 * the next 100 us, this function waits until the vblank passes.
85 * After a successful call to this function, interrupts will be disabled
86 * until a subsequent call to intel_pipe_update_end(). That is done to
87 * avoid random delays.
89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
91 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
92 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
93 const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
94 long timeout = msecs_to_jiffies_timeout(1);
95 int scanline, min, max, vblank_start;
96 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
97 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
98 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
101 vblank_start = adjusted_mode->crtc_vblank_start;
102 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
103 vblank_start = DIV_ROUND_UP(vblank_start, 2);
105 /* FIXME needs to be calibrated sensibly */
106 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
107 VBLANK_EVASION_TIME_US);
108 max = vblank_start - 1;
112 if (min <= 0 || max <= 0)
115 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
118 crtc->debug.min_vbl = min;
119 crtc->debug.max_vbl = max;
120 trace_i915_pipe_update_start(crtc);
124 * prepare_to_wait() has a memory barrier, which guarantees
125 * other CPUs can see the task state update by the time we
128 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
130 scanline = intel_get_crtc_scanline(crtc);
131 if (scanline < min || scanline > max)
135 DRM_ERROR("Potential atomic update failure on pipe %c\n",
136 pipe_name(crtc->pipe));
142 timeout = schedule_timeout(timeout);
147 finish_wait(wq, &wait);
149 drm_crtc_vblank_put(&crtc->base);
152 * On VLV/CHV DSI the scanline counter would appear to
153 * increment approx. 1/3 of a scanline before start of vblank.
154 * The registers still get latched at start of vblank however.
155 * This means we must not write any registers on the first
156 * line of vblank (since not the whole line is actually in
157 * vblank). And unfortunately we can't use the interrupt to
158 * wait here since it will fire too soon. We could use the
159 * frame start interrupt instead since it will fire after the
160 * critical scanline, but that would require more changes
161 * in the interrupt code. So for now we'll just do the nasty
162 * thing and poll for the bad scanline to pass us by.
164 * FIXME figure out if BXT+ DSI suffers from this as well
166 while (need_vlv_dsi_wa && scanline == vblank_start)
167 scanline = intel_get_crtc_scanline(crtc);
169 crtc->debug.scanline_start = scanline;
170 crtc->debug.start_vbl_time = ktime_get();
171 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
173 trace_i915_pipe_update_vblank_evaded(crtc);
177 * intel_pipe_update_end() - end update of a set of display registers
178 * @new_crtc_state: the new crtc state
180 * Mark the end of an update started with intel_pipe_update_start(). This
181 * re-enables interrupts and verifies the update was actually completed
184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
186 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
187 enum pipe pipe = crtc->pipe;
188 int scanline_end = intel_get_crtc_scanline(crtc);
189 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
190 ktime_t end_vbl_time = ktime_get();
191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
193 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
195 /* We're still in the vblank-evade critical section, this can't race.
196 * Would be slightly nice to just grab the vblank count and arm the
197 * event outside of the critical section - the spinlock might spin for a
199 if (new_crtc_state->base.event) {
200 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
202 spin_lock(&crtc->base.dev->event_lock);
203 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
204 spin_unlock(&crtc->base.dev->event_lock);
206 new_crtc_state->base.event = NULL;
211 if (intel_vgpu_active(dev_priv))
214 if (crtc->debug.start_vbl_count &&
215 crtc->debug.start_vbl_count != end_vbl_count) {
216 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
217 pipe_name(pipe), crtc->debug.start_vbl_count,
219 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
220 crtc->debug.min_vbl, crtc->debug.max_vbl,
221 crtc->debug.scanline_start, scanline_end);
223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
224 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
225 VBLANK_EVASION_TIME_US)
226 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
228 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
229 VBLANK_EVASION_TIME_US);
234 skl_update_plane(struct intel_plane *plane,
235 const struct intel_crtc_state *crtc_state,
236 const struct intel_plane_state *plane_state)
238 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
239 const struct drm_framebuffer *fb = plane_state->base.fb;
240 enum plane_id plane_id = plane->id;
241 enum pipe pipe = plane->pipe;
242 u32 plane_ctl = plane_state->ctl;
243 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
244 u32 surf_addr = plane_state->main.offset;
245 unsigned int rotation = plane_state->base.rotation;
246 u32 stride = skl_plane_stride(fb, 0, rotation);
247 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
248 int crtc_x = plane_state->base.dst.x1;
249 int crtc_y = plane_state->base.dst.y1;
250 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
251 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
252 uint32_t x = plane_state->main.x;
253 uint32_t y = plane_state->main.y;
254 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
255 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
256 unsigned long irqflags;
258 /* Sizes are 0 based */
264 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
266 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
267 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
268 plane_state->color_ctl);
271 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
272 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
273 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
276 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
277 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
278 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
279 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
280 (plane_state->aux.offset - surf_addr) | aux_stride);
281 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
282 (plane_state->aux.y << 16) | plane_state->aux.x);
284 /* program plane scaler */
285 if (plane_state->scaler_id >= 0) {
286 int scaler_id = plane_state->scaler_id;
287 const struct intel_scaler *scaler;
289 scaler = &crtc_state->scaler_state.scalers[scaler_id];
291 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
292 PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
293 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
294 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
295 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
296 ((crtc_w + 1) << 16)|(crtc_h + 1));
298 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
300 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
303 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
304 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
305 intel_plane_ggtt_offset(plane_state) + surf_addr);
306 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
308 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
312 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
314 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
315 enum plane_id plane_id = plane->id;
316 enum pipe pipe = plane->pipe;
317 unsigned long irqflags;
319 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
321 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
323 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
324 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
326 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
330 skl_plane_get_hw_state(struct intel_plane *plane)
332 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
333 enum intel_display_power_domain power_domain;
334 enum plane_id plane_id = plane->id;
335 enum pipe pipe = plane->pipe;
338 power_domain = POWER_DOMAIN_PIPE(pipe);
339 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
342 ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
344 intel_display_power_put(dev_priv, power_domain);
350 chv_update_csc(const struct intel_plane_state *plane_state)
352 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
353 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
354 const struct drm_framebuffer *fb = plane_state->base.fb;
355 enum plane_id plane_id = plane->id;
357 * |r| | c0 c1 c2 | |cr|
358 * |g| = | c3 c4 c5 | x |y |
359 * |b| | c6 c7 c8 | |cb|
361 * Coefficients are s3.12.
363 * Cb and Cr apparently come in as signed already, and
364 * we always get full range data in on account of CLRC0/1.
366 static const s16 csc_matrix[][9] = {
367 /* BT.601 full range YCbCr -> full range RGB */
368 [DRM_COLOR_YCBCR_BT601] = {
373 /* BT.709 full range YCbCr -> full range RGB */
374 [DRM_COLOR_YCBCR_BT709] = {
380 const s16 *csc = csc_matrix[plane_state->base.color_encoding];
382 /* Seems RGB data bypasses the CSC always */
383 if (!intel_format_is_yuv(fb->format->format))
386 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
387 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
388 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
390 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
391 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
392 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
393 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
394 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
396 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
397 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
398 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
400 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
401 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
402 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
409 vlv_update_clrc(const struct intel_plane_state *plane_state)
411 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
412 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
413 const struct drm_framebuffer *fb = plane_state->base.fb;
414 enum pipe pipe = plane->pipe;
415 enum plane_id plane_id = plane->id;
416 int contrast, brightness, sh_scale, sh_sin, sh_cos;
418 if (intel_format_is_yuv(fb->format->format) &&
419 plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
421 * Expand limited range to full range:
422 * Contrast is applied first and is used to expand Y range.
423 * Brightness is applied second and is used to remove the
424 * offset from Y. Saturation/hue is used to expand CbCr range.
426 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
427 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
428 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
429 sh_sin = SIN_0 * sh_scale;
430 sh_cos = COS_0 * sh_scale;
432 /* Pass-through everything. */
436 sh_sin = SIN_0 * sh_scale;
437 sh_cos = COS_0 * sh_scale;
440 /* FIXME these register are single buffered :( */
441 I915_WRITE_FW(SPCLRC0(pipe, plane_id),
442 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
443 I915_WRITE_FW(SPCLRC1(pipe, plane_id),
444 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
447 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
448 const struct intel_plane_state *plane_state)
450 const struct drm_framebuffer *fb = plane_state->base.fb;
451 unsigned int rotation = plane_state->base.rotation;
452 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
455 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
457 switch (fb->format->format) {
458 case DRM_FORMAT_YUYV:
459 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
461 case DRM_FORMAT_YVYU:
462 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
464 case DRM_FORMAT_UYVY:
465 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
467 case DRM_FORMAT_VYUY:
468 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
470 case DRM_FORMAT_RGB565:
471 sprctl |= SP_FORMAT_BGR565;
473 case DRM_FORMAT_XRGB8888:
474 sprctl |= SP_FORMAT_BGRX8888;
476 case DRM_FORMAT_ARGB8888:
477 sprctl |= SP_FORMAT_BGRA8888;
479 case DRM_FORMAT_XBGR2101010:
480 sprctl |= SP_FORMAT_RGBX1010102;
482 case DRM_FORMAT_ABGR2101010:
483 sprctl |= SP_FORMAT_RGBA1010102;
485 case DRM_FORMAT_XBGR8888:
486 sprctl |= SP_FORMAT_RGBX8888;
488 case DRM_FORMAT_ABGR8888:
489 sprctl |= SP_FORMAT_RGBA8888;
492 MISSING_CASE(fb->format->format);
496 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
497 sprctl |= SP_YUV_FORMAT_BT709;
499 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
502 if (rotation & DRM_MODE_ROTATE_180)
503 sprctl |= SP_ROTATE_180;
505 if (rotation & DRM_MODE_REFLECT_X)
508 if (key->flags & I915_SET_COLORKEY_SOURCE)
509 sprctl |= SP_SOURCE_KEY;
515 vlv_update_plane(struct intel_plane *plane,
516 const struct intel_crtc_state *crtc_state,
517 const struct intel_plane_state *plane_state)
519 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
520 const struct drm_framebuffer *fb = plane_state->base.fb;
521 enum pipe pipe = plane->pipe;
522 enum plane_id plane_id = plane->id;
523 u32 sprctl = plane_state->ctl;
524 u32 sprsurf_offset = plane_state->main.offset;
526 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
527 int crtc_x = plane_state->base.dst.x1;
528 int crtc_y = plane_state->base.dst.y1;
529 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
530 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
531 uint32_t x = plane_state->main.x;
532 uint32_t y = plane_state->main.y;
533 unsigned long irqflags;
535 /* Sizes are 0 based */
539 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
541 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
543 vlv_update_clrc(plane_state);
545 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
546 chv_update_csc(plane_state);
549 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
550 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
551 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
553 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
554 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
556 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
557 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
559 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
561 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
563 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
564 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
565 I915_WRITE_FW(SPSURF(pipe, plane_id),
566 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
567 POSTING_READ_FW(SPSURF(pipe, plane_id));
569 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
573 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
575 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
576 enum pipe pipe = plane->pipe;
577 enum plane_id plane_id = plane->id;
578 unsigned long irqflags;
580 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
582 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
584 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
585 POSTING_READ_FW(SPSURF(pipe, plane_id));
587 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
591 vlv_plane_get_hw_state(struct intel_plane *plane)
593 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
594 enum intel_display_power_domain power_domain;
595 enum plane_id plane_id = plane->id;
596 enum pipe pipe = plane->pipe;
599 power_domain = POWER_DOMAIN_PIPE(pipe);
600 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
603 ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
605 intel_display_power_put(dev_priv, power_domain);
610 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
611 const struct intel_plane_state *plane_state)
613 struct drm_i915_private *dev_priv =
614 to_i915(plane_state->base.plane->dev);
615 const struct drm_framebuffer *fb = plane_state->base.fb;
616 unsigned int rotation = plane_state->base.rotation;
617 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
620 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
622 if (IS_IVYBRIDGE(dev_priv))
623 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
625 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
626 sprctl |= SPRITE_PIPE_CSC_ENABLE;
628 switch (fb->format->format) {
629 case DRM_FORMAT_XBGR8888:
630 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
632 case DRM_FORMAT_XRGB8888:
633 sprctl |= SPRITE_FORMAT_RGBX888;
635 case DRM_FORMAT_YUYV:
636 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
638 case DRM_FORMAT_YVYU:
639 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
641 case DRM_FORMAT_UYVY:
642 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
644 case DRM_FORMAT_VYUY:
645 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
648 MISSING_CASE(fb->format->format);
652 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
653 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
655 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
656 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
658 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
659 sprctl |= SPRITE_TILED;
661 if (rotation & DRM_MODE_ROTATE_180)
662 sprctl |= SPRITE_ROTATE_180;
664 if (key->flags & I915_SET_COLORKEY_DESTINATION)
665 sprctl |= SPRITE_DEST_KEY;
666 else if (key->flags & I915_SET_COLORKEY_SOURCE)
667 sprctl |= SPRITE_SOURCE_KEY;
673 ivb_update_plane(struct intel_plane *plane,
674 const struct intel_crtc_state *crtc_state,
675 const struct intel_plane_state *plane_state)
677 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
678 const struct drm_framebuffer *fb = plane_state->base.fb;
679 enum pipe pipe = plane->pipe;
680 u32 sprctl = plane_state->ctl, sprscale = 0;
681 u32 sprsurf_offset = plane_state->main.offset;
683 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
684 int crtc_x = plane_state->base.dst.x1;
685 int crtc_y = plane_state->base.dst.y1;
686 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
687 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
688 uint32_t x = plane_state->main.x;
689 uint32_t y = plane_state->main.y;
690 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
691 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
692 unsigned long irqflags;
694 /* Sizes are 0 based */
700 if (crtc_w != src_w || crtc_h != src_h)
701 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
703 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
705 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
708 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
709 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
710 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
713 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
714 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
716 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
718 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
719 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
720 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
721 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
723 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
725 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
726 if (plane->can_scale)
727 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
728 I915_WRITE_FW(SPRCTL(pipe), sprctl);
729 I915_WRITE_FW(SPRSURF(pipe),
730 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
731 POSTING_READ_FW(SPRSURF(pipe));
733 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
737 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
739 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
740 enum pipe pipe = plane->pipe;
741 unsigned long irqflags;
743 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
745 I915_WRITE_FW(SPRCTL(pipe), 0);
746 /* Can't leave the scaler enabled... */
747 if (plane->can_scale)
748 I915_WRITE_FW(SPRSCALE(pipe), 0);
750 I915_WRITE_FW(SPRSURF(pipe), 0);
751 POSTING_READ_FW(SPRSURF(pipe));
753 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
757 ivb_plane_get_hw_state(struct intel_plane *plane)
759 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
760 enum intel_display_power_domain power_domain;
761 enum pipe pipe = plane->pipe;
764 power_domain = POWER_DOMAIN_PIPE(pipe);
765 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
768 ret = I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
770 intel_display_power_put(dev_priv, power_domain);
775 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
776 const struct intel_plane_state *plane_state)
778 struct drm_i915_private *dev_priv =
779 to_i915(plane_state->base.plane->dev);
780 const struct drm_framebuffer *fb = plane_state->base.fb;
781 unsigned int rotation = plane_state->base.rotation;
782 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
785 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
787 if (IS_GEN6(dev_priv))
788 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
790 switch (fb->format->format) {
791 case DRM_FORMAT_XBGR8888:
792 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
794 case DRM_FORMAT_XRGB8888:
795 dvscntr |= DVS_FORMAT_RGBX888;
797 case DRM_FORMAT_YUYV:
798 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
800 case DRM_FORMAT_YVYU:
801 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
803 case DRM_FORMAT_UYVY:
804 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
806 case DRM_FORMAT_VYUY:
807 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
810 MISSING_CASE(fb->format->format);
814 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
815 dvscntr |= DVS_YUV_FORMAT_BT709;
817 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
818 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
820 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
821 dvscntr |= DVS_TILED;
823 if (rotation & DRM_MODE_ROTATE_180)
824 dvscntr |= DVS_ROTATE_180;
826 if (key->flags & I915_SET_COLORKEY_DESTINATION)
827 dvscntr |= DVS_DEST_KEY;
828 else if (key->flags & I915_SET_COLORKEY_SOURCE)
829 dvscntr |= DVS_SOURCE_KEY;
835 g4x_update_plane(struct intel_plane *plane,
836 const struct intel_crtc_state *crtc_state,
837 const struct intel_plane_state *plane_state)
839 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
840 const struct drm_framebuffer *fb = plane_state->base.fb;
841 enum pipe pipe = plane->pipe;
842 u32 dvscntr = plane_state->ctl, dvsscale = 0;
843 u32 dvssurf_offset = plane_state->main.offset;
845 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
846 int crtc_x = plane_state->base.dst.x1;
847 int crtc_y = plane_state->base.dst.y1;
848 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
849 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
850 uint32_t x = plane_state->main.x;
851 uint32_t y = plane_state->main.y;
852 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
853 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
854 unsigned long irqflags;
856 /* Sizes are 0 based */
862 if (crtc_w != src_w || crtc_h != src_h)
863 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
865 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
867 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
870 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
871 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
872 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
875 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
876 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
878 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
879 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
881 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
883 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
884 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
885 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
886 I915_WRITE_FW(DVSSURF(pipe),
887 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
888 POSTING_READ_FW(DVSSURF(pipe));
890 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
894 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
896 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
897 enum pipe pipe = plane->pipe;
898 unsigned long irqflags;
900 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
902 I915_WRITE_FW(DVSCNTR(pipe), 0);
903 /* Disable the scaler */
904 I915_WRITE_FW(DVSSCALE(pipe), 0);
906 I915_WRITE_FW(DVSSURF(pipe), 0);
907 POSTING_READ_FW(DVSSURF(pipe));
909 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
913 g4x_plane_get_hw_state(struct intel_plane *plane)
915 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
916 enum intel_display_power_domain power_domain;
917 enum pipe pipe = plane->pipe;
920 power_domain = POWER_DOMAIN_PIPE(pipe);
921 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
924 ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
926 intel_display_power_put(dev_priv, power_domain);
932 intel_check_sprite_plane(struct intel_plane *plane,
933 struct intel_crtc_state *crtc_state,
934 struct intel_plane_state *state)
936 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
937 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
938 struct drm_framebuffer *fb = state->base.fb;
939 int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
940 int max_scale, min_scale;
943 uint32_t pixel_format = 0;
946 state->base.visible = false;
950 /* Don't modify another pipe's plane */
951 if (plane->pipe != crtc->pipe) {
952 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
956 /* FIXME check all gen limits */
957 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > max_stride) {
958 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
962 /* setup can_scale, min_scale, max_scale */
963 if (INTEL_GEN(dev_priv) >= 9) {
965 pixel_format = state->base.fb->format->format;
966 /* use scaler when colorkey is not required */
967 if (!state->ckey.flags) {
971 skl_max_scale(crtc, crtc_state, pixel_format);
974 min_scale = DRM_PLANE_HELPER_NO_SCALING;
975 max_scale = DRM_PLANE_HELPER_NO_SCALING;
978 can_scale = plane->can_scale;
979 max_scale = plane->max_downscale << 16;
980 min_scale = plane->can_scale ? 1 : (1 << 16);
983 ret = drm_atomic_helper_check_plane_state(&state->base,
985 min_scale, max_scale,
990 if (state->base.visible) {
991 struct drm_rect *src = &state->base.src;
992 struct drm_rect *dst = &state->base.dst;
993 unsigned int crtc_w = drm_rect_width(dst);
994 unsigned int crtc_h = drm_rect_height(dst);
995 uint32_t src_x, src_y, src_w, src_h;
998 * Hardware doesn't handle subpixel coordinates.
999 * Adjust to (macro)pixel boundary, but be careful not to
1000 * increase the source viewport size, because that could
1001 * push the downscaling factor out of bounds.
1003 src_x = src->x1 >> 16;
1004 src_w = drm_rect_width(src) >> 16;
1005 src_y = src->y1 >> 16;
1006 src_h = drm_rect_height(src) >> 16;
1008 src->x1 = src_x << 16;
1009 src->x2 = (src_x + src_w) << 16;
1010 src->y1 = src_y << 16;
1011 src->y2 = (src_y + src_h) << 16;
1013 if (intel_format_is_yuv(fb->format->format) &&
1014 fb->format->format != DRM_FORMAT_NV12 &&
1015 (src_x % 2 || src_w % 2)) {
1016 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
1021 /* Check size restrictions when scaling */
1022 if (src_w != crtc_w || src_h != crtc_h) {
1023 unsigned int width_bytes;
1024 int cpp = fb->format->cpp[0];
1026 WARN_ON(!can_scale);
1028 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1030 /* FIXME interlacing min height is 6 */
1031 if (INTEL_GEN(dev_priv) < 9 && (
1032 src_w < 3 || src_h < 3 ||
1033 src_w > 2048 || src_h > 2048 ||
1034 crtc_w < 3 || crtc_h < 3 ||
1035 width_bytes > 4096 || fb->pitches[0] > 4096)) {
1036 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1042 if (INTEL_GEN(dev_priv) >= 9) {
1043 ret = skl_check_plane_surface(crtc_state, state);
1047 state->ctl = skl_plane_ctl(crtc_state, state);
1048 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1049 ret = i9xx_check_plane_surface(state);
1053 state->ctl = vlv_sprite_ctl(crtc_state, state);
1054 } else if (INTEL_GEN(dev_priv) >= 7) {
1055 ret = i9xx_check_plane_surface(state);
1059 state->ctl = ivb_sprite_ctl(crtc_state, state);
1061 ret = i9xx_check_plane_surface(state);
1065 state->ctl = g4x_sprite_ctl(crtc_state, state);
1068 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1069 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
1074 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv)
1077 struct drm_i915_private *dev_priv = to_i915(dev);
1078 struct drm_intel_sprite_colorkey *set = data;
1079 struct drm_plane *plane;
1080 struct drm_plane_state *plane_state;
1081 struct drm_atomic_state *state;
1082 struct drm_modeset_acquire_ctx ctx;
1085 /* ignore the pointless "none" flag */
1086 set->flags &= ~I915_SET_COLORKEY_NONE;
1088 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1091 /* Make sure we don't try to enable both src & dest simultaneously */
1092 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1095 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1096 set->flags & I915_SET_COLORKEY_DESTINATION)
1099 plane = drm_plane_find(dev, file_priv, set->plane_id);
1100 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1103 drm_modeset_acquire_init(&ctx, 0);
1105 state = drm_atomic_state_alloc(plane->dev);
1110 state->acquire_ctx = &ctx;
1113 plane_state = drm_atomic_get_plane_state(state, plane);
1114 ret = PTR_ERR_OR_ZERO(plane_state);
1116 to_intel_plane_state(plane_state)->ckey = *set;
1117 ret = drm_atomic_commit(state);
1120 if (ret != -EDEADLK)
1123 drm_atomic_state_clear(state);
1124 drm_modeset_backoff(&ctx);
1127 drm_atomic_state_put(state);
1129 drm_modeset_drop_locks(&ctx);
1130 drm_modeset_acquire_fini(&ctx);
1134 static const uint32_t g4x_plane_formats[] = {
1135 DRM_FORMAT_XRGB8888,
1142 static const uint64_t i9xx_plane_format_modifiers[] = {
1143 I915_FORMAT_MOD_X_TILED,
1144 DRM_FORMAT_MOD_LINEAR,
1145 DRM_FORMAT_MOD_INVALID
1148 static const uint32_t snb_plane_formats[] = {
1149 DRM_FORMAT_XBGR8888,
1150 DRM_FORMAT_XRGB8888,
1157 static const uint32_t vlv_plane_formats[] = {
1159 DRM_FORMAT_ABGR8888,
1160 DRM_FORMAT_ARGB8888,
1161 DRM_FORMAT_XBGR8888,
1162 DRM_FORMAT_XRGB8888,
1163 DRM_FORMAT_XBGR2101010,
1164 DRM_FORMAT_ABGR2101010,
1171 static uint32_t skl_plane_formats[] = {
1173 DRM_FORMAT_ABGR8888,
1174 DRM_FORMAT_ARGB8888,
1175 DRM_FORMAT_XBGR8888,
1176 DRM_FORMAT_XRGB8888,
1183 static uint32_t skl_planar_formats[] = {
1185 DRM_FORMAT_ABGR8888,
1186 DRM_FORMAT_ARGB8888,
1187 DRM_FORMAT_XBGR8888,
1188 DRM_FORMAT_XRGB8888,
1196 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1197 I915_FORMAT_MOD_Yf_TILED,
1198 I915_FORMAT_MOD_Y_TILED,
1199 I915_FORMAT_MOD_X_TILED,
1200 DRM_FORMAT_MOD_LINEAR,
1201 DRM_FORMAT_MOD_INVALID
1204 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1205 I915_FORMAT_MOD_Yf_TILED_CCS,
1206 I915_FORMAT_MOD_Y_TILED_CCS,
1207 I915_FORMAT_MOD_Yf_TILED,
1208 I915_FORMAT_MOD_Y_TILED,
1209 I915_FORMAT_MOD_X_TILED,
1210 DRM_FORMAT_MOD_LINEAR,
1211 DRM_FORMAT_MOD_INVALID
1214 static bool g4x_mod_supported(uint32_t format, uint64_t modifier)
1217 case DRM_FORMAT_XRGB8888:
1218 case DRM_FORMAT_YUYV:
1219 case DRM_FORMAT_YVYU:
1220 case DRM_FORMAT_UYVY:
1221 case DRM_FORMAT_VYUY:
1222 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1223 modifier == I915_FORMAT_MOD_X_TILED)
1231 static bool snb_mod_supported(uint32_t format, uint64_t modifier)
1234 case DRM_FORMAT_XRGB8888:
1235 case DRM_FORMAT_XBGR8888:
1236 case DRM_FORMAT_YUYV:
1237 case DRM_FORMAT_YVYU:
1238 case DRM_FORMAT_UYVY:
1239 case DRM_FORMAT_VYUY:
1240 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1241 modifier == I915_FORMAT_MOD_X_TILED)
1249 static bool vlv_mod_supported(uint32_t format, uint64_t modifier)
1252 case DRM_FORMAT_RGB565:
1253 case DRM_FORMAT_ABGR8888:
1254 case DRM_FORMAT_ARGB8888:
1255 case DRM_FORMAT_XBGR8888:
1256 case DRM_FORMAT_XRGB8888:
1257 case DRM_FORMAT_XBGR2101010:
1258 case DRM_FORMAT_ABGR2101010:
1259 case DRM_FORMAT_YUYV:
1260 case DRM_FORMAT_YVYU:
1261 case DRM_FORMAT_UYVY:
1262 case DRM_FORMAT_VYUY:
1263 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1264 modifier == I915_FORMAT_MOD_X_TILED)
1272 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
1275 case DRM_FORMAT_XRGB8888:
1276 case DRM_FORMAT_XBGR8888:
1277 case DRM_FORMAT_ARGB8888:
1278 case DRM_FORMAT_ABGR8888:
1279 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
1280 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
1283 case DRM_FORMAT_RGB565:
1284 case DRM_FORMAT_XRGB2101010:
1285 case DRM_FORMAT_XBGR2101010:
1286 case DRM_FORMAT_YUYV:
1287 case DRM_FORMAT_YVYU:
1288 case DRM_FORMAT_UYVY:
1289 case DRM_FORMAT_VYUY:
1290 case DRM_FORMAT_NV12:
1291 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1295 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1296 modifier == I915_FORMAT_MOD_X_TILED ||
1297 modifier == I915_FORMAT_MOD_Y_TILED)
1305 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1309 struct drm_i915_private *dev_priv = to_i915(plane->dev);
1311 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1314 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1315 modifier != DRM_FORMAT_MOD_LINEAR)
1318 if (INTEL_GEN(dev_priv) >= 9)
1319 return skl_mod_supported(format, modifier);
1320 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1321 return vlv_mod_supported(format, modifier);
1322 else if (INTEL_GEN(dev_priv) >= 6)
1323 return snb_mod_supported(format, modifier);
1325 return g4x_mod_supported(format, modifier);
1328 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1329 .update_plane = drm_atomic_helper_update_plane,
1330 .disable_plane = drm_atomic_helper_disable_plane,
1331 .destroy = intel_plane_destroy,
1332 .atomic_get_property = intel_plane_atomic_get_property,
1333 .atomic_set_property = intel_plane_atomic_set_property,
1334 .atomic_duplicate_state = intel_plane_duplicate_state,
1335 .atomic_destroy_state = intel_plane_destroy_state,
1336 .format_mod_supported = intel_sprite_plane_format_mod_supported,
1339 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1340 enum pipe pipe, enum plane_id plane_id)
1342 if (plane_id == PLANE_CURSOR)
1345 if (INTEL_GEN(dev_priv) >= 10)
1348 if (IS_GEMINILAKE(dev_priv))
1349 return pipe != PIPE_C;
1351 return pipe != PIPE_C &&
1352 (plane_id == PLANE_PRIMARY ||
1353 plane_id == PLANE_SPRITE0);
1356 struct intel_plane *
1357 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, int plane)
1360 struct intel_plane *intel_plane = NULL;
1361 struct intel_plane_state *state = NULL;
1362 unsigned long possible_crtcs;
1363 const uint32_t *plane_formats;
1364 const uint64_t *modifiers;
1365 unsigned int supported_rotations;
1366 int num_plane_formats;
1369 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1375 state = intel_create_plane_state(&intel_plane->base);
1380 intel_plane->base.state = &state->base;
1382 if (INTEL_GEN(dev_priv) >= 9) {
1383 intel_plane->can_scale = true;
1384 state->scaler_id = -1;
1386 intel_plane->update_plane = skl_update_plane;
1387 intel_plane->disable_plane = skl_disable_plane;
1388 intel_plane->get_hw_state = skl_plane_get_hw_state;
1390 if (skl_plane_has_planar(dev_priv, pipe,
1391 PLANE_SPRITE0 + plane)) {
1392 plane_formats = skl_planar_formats;
1393 num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1395 plane_formats = skl_plane_formats;
1396 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1399 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
1400 modifiers = skl_plane_format_modifiers_ccs;
1402 modifiers = skl_plane_format_modifiers_noccs;
1403 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1404 intel_plane->can_scale = false;
1405 intel_plane->max_downscale = 1;
1407 intel_plane->update_plane = vlv_update_plane;
1408 intel_plane->disable_plane = vlv_disable_plane;
1409 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1411 plane_formats = vlv_plane_formats;
1412 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1413 modifiers = i9xx_plane_format_modifiers;
1414 } else if (INTEL_GEN(dev_priv) >= 7) {
1415 if (IS_IVYBRIDGE(dev_priv)) {
1416 intel_plane->can_scale = true;
1417 intel_plane->max_downscale = 2;
1419 intel_plane->can_scale = false;
1420 intel_plane->max_downscale = 1;
1423 intel_plane->update_plane = ivb_update_plane;
1424 intel_plane->disable_plane = ivb_disable_plane;
1425 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1427 plane_formats = snb_plane_formats;
1428 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1429 modifiers = i9xx_plane_format_modifiers;
1431 intel_plane->can_scale = true;
1432 intel_plane->max_downscale = 16;
1434 intel_plane->update_plane = g4x_update_plane;
1435 intel_plane->disable_plane = g4x_disable_plane;
1436 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1438 modifiers = i9xx_plane_format_modifiers;
1439 if (IS_GEN6(dev_priv)) {
1440 plane_formats = snb_plane_formats;
1441 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1443 plane_formats = g4x_plane_formats;
1444 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1448 if (INTEL_GEN(dev_priv) >= 9) {
1449 supported_rotations =
1450 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1451 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1452 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1453 supported_rotations =
1454 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1457 supported_rotations =
1458 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1461 intel_plane->pipe = pipe;
1462 intel_plane->i9xx_plane = plane;
1463 intel_plane->id = PLANE_SPRITE0 + plane;
1464 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1465 intel_plane->check_plane = intel_check_sprite_plane;
1467 possible_crtcs = (1 << pipe);
1469 if (INTEL_GEN(dev_priv) >= 9)
1470 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1471 possible_crtcs, &intel_sprite_plane_funcs,
1472 plane_formats, num_plane_formats,
1474 DRM_PLANE_TYPE_OVERLAY,
1475 "plane %d%c", plane + 2, pipe_name(pipe));
1477 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1478 possible_crtcs, &intel_sprite_plane_funcs,
1479 plane_formats, num_plane_formats,
1481 DRM_PLANE_TYPE_OVERLAY,
1482 "sprite %c", sprite_name(pipe, plane));
1486 drm_plane_create_rotation_property(&intel_plane->base,
1488 supported_rotations);
1490 drm_plane_create_color_properties(&intel_plane->base,
1491 BIT(DRM_COLOR_YCBCR_BT601) |
1492 BIT(DRM_COLOR_YCBCR_BT709),
1493 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1494 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1495 DRM_COLOR_YCBCR_BT709,
1496 DRM_COLOR_YCBCR_LIMITED_RANGE);
1498 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1506 return ERR_PTR(ret);