2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
41 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
42 struct drm_framebuffer *fb,
43 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
44 unsigned int crtc_w, unsigned int crtc_h,
45 uint32_t x, uint32_t y,
46 uint32_t src_w, uint32_t src_h)
48 struct drm_device *dev = dplane->dev;
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 struct intel_plane *intel_plane = to_intel_plane(dplane);
51 int pipe = intel_plane->pipe;
52 int plane = intel_plane->plane;
54 unsigned long sprsurf_offset, linear_offset;
55 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
57 sprctl = I915_READ(SPCNTR(pipe, plane));
59 /* Mask out pixel format bits in case we change it */
60 sprctl &= ~SP_PIXFORMAT_MASK;
61 sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
64 switch (fb->pixel_format) {
66 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
69 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
72 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
75 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
77 case DRM_FORMAT_RGB565:
78 sprctl |= SP_FORMAT_BGR565;
80 case DRM_FORMAT_XRGB8888:
81 sprctl |= SP_FORMAT_BGRX8888;
83 case DRM_FORMAT_ARGB8888:
84 sprctl |= SP_FORMAT_BGRA8888;
86 case DRM_FORMAT_XBGR2101010:
87 sprctl |= SP_FORMAT_RGBX1010102;
89 case DRM_FORMAT_ABGR2101010:
90 sprctl |= SP_FORMAT_RGBA1010102;
92 case DRM_FORMAT_XBGR8888:
93 sprctl |= SP_FORMAT_RGBX8888;
95 case DRM_FORMAT_ABGR8888:
96 sprctl |= SP_FORMAT_RGBA8888;
100 * If we get here one of the upper layers failed to filter
101 * out the unsupported plane formats
108 * Enable gamma to match primary/cursor plane behaviour.
109 * FIXME should be user controllable via propertiesa.
111 sprctl |= SP_GAMMA_ENABLE;
113 if (obj->tiling_mode != I915_TILING_NONE)
118 intel_update_sprite_watermarks(dplane, crtc, src_w, pixel_size, true,
119 src_w != crtc_w || src_h != crtc_h);
121 /* Sizes are 0 based */
127 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
128 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
130 linear_offset = y * fb->pitches[0] + x * pixel_size;
131 sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
135 linear_offset -= sprsurf_offset;
137 if (obj->tiling_mode != I915_TILING_NONE)
138 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
140 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
142 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
143 I915_WRITE(SPCNTR(pipe, plane), sprctl);
144 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
146 POSTING_READ(SPSURF(pipe, plane));
150 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
152 struct drm_device *dev = dplane->dev;
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 struct intel_plane *intel_plane = to_intel_plane(dplane);
155 int pipe = intel_plane->pipe;
156 int plane = intel_plane->plane;
158 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
160 /* Activate double buffered register update */
161 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
162 POSTING_READ(SPSURF(pipe, plane));
164 intel_update_sprite_watermarks(dplane, crtc, 0, 0, false, false);
168 vlv_update_colorkey(struct drm_plane *dplane,
169 struct drm_intel_sprite_colorkey *key)
171 struct drm_device *dev = dplane->dev;
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct intel_plane *intel_plane = to_intel_plane(dplane);
174 int pipe = intel_plane->pipe;
175 int plane = intel_plane->plane;
178 if (key->flags & I915_SET_COLORKEY_DESTINATION)
181 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
182 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
183 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
185 sprctl = I915_READ(SPCNTR(pipe, plane));
186 sprctl &= ~SP_SOURCE_KEY;
187 if (key->flags & I915_SET_COLORKEY_SOURCE)
188 sprctl |= SP_SOURCE_KEY;
189 I915_WRITE(SPCNTR(pipe, plane), sprctl);
191 POSTING_READ(SPKEYMSK(pipe, plane));
197 vlv_get_colorkey(struct drm_plane *dplane,
198 struct drm_intel_sprite_colorkey *key)
200 struct drm_device *dev = dplane->dev;
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_plane *intel_plane = to_intel_plane(dplane);
203 int pipe = intel_plane->pipe;
204 int plane = intel_plane->plane;
207 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
208 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
209 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
211 sprctl = I915_READ(SPCNTR(pipe, plane));
212 if (sprctl & SP_SOURCE_KEY)
213 key->flags = I915_SET_COLORKEY_SOURCE;
215 key->flags = I915_SET_COLORKEY_NONE;
219 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
220 struct drm_framebuffer *fb,
221 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
222 unsigned int crtc_w, unsigned int crtc_h,
223 uint32_t x, uint32_t y,
224 uint32_t src_w, uint32_t src_h)
226 struct drm_device *dev = plane->dev;
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 struct intel_plane *intel_plane = to_intel_plane(plane);
229 int pipe = intel_plane->pipe;
230 u32 sprctl, sprscale = 0;
231 unsigned long sprsurf_offset, linear_offset;
232 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
234 sprctl = I915_READ(SPRCTL(pipe));
236 /* Mask out pixel format bits in case we change it */
237 sprctl &= ~SPRITE_PIXFORMAT_MASK;
238 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
239 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
240 sprctl &= ~SPRITE_TILED;
242 switch (fb->pixel_format) {
243 case DRM_FORMAT_XBGR8888:
244 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
246 case DRM_FORMAT_XRGB8888:
247 sprctl |= SPRITE_FORMAT_RGBX888;
249 case DRM_FORMAT_YUYV:
250 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
252 case DRM_FORMAT_YVYU:
253 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
255 case DRM_FORMAT_UYVY:
256 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
258 case DRM_FORMAT_VYUY:
259 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
266 * Enable gamma to match primary/cursor plane behaviour.
267 * FIXME should be user controllable via propertiesa.
269 sprctl |= SPRITE_GAMMA_ENABLE;
271 if (obj->tiling_mode != I915_TILING_NONE)
272 sprctl |= SPRITE_TILED;
274 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
275 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
277 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
279 sprctl |= SPRITE_ENABLE;
281 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
282 sprctl |= SPRITE_PIPE_CSC_ENABLE;
284 intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true,
285 src_w != crtc_w || src_h != crtc_h);
287 /* Sizes are 0 based */
293 if (crtc_w != src_w || crtc_h != src_h)
294 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
296 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
297 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
299 linear_offset = y * fb->pitches[0] + x * pixel_size;
301 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
302 pixel_size, fb->pitches[0]);
303 linear_offset -= sprsurf_offset;
305 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
307 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
308 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
309 else if (obj->tiling_mode != I915_TILING_NONE)
310 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
312 I915_WRITE(SPRLINOFF(pipe), linear_offset);
314 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
315 if (intel_plane->can_scale)
316 I915_WRITE(SPRSCALE(pipe), sprscale);
317 I915_WRITE(SPRCTL(pipe), sprctl);
318 I915_MODIFY_DISPBASE(SPRSURF(pipe),
319 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
320 POSTING_READ(SPRSURF(pipe));
324 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
326 struct drm_device *dev = plane->dev;
327 struct drm_i915_private *dev_priv = dev->dev_private;
328 struct intel_plane *intel_plane = to_intel_plane(plane);
329 int pipe = intel_plane->pipe;
331 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
332 /* Can't leave the scaler enabled... */
333 if (intel_plane->can_scale)
334 I915_WRITE(SPRSCALE(pipe), 0);
335 /* Activate double buffered register update */
336 I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
337 POSTING_READ(SPRSURF(pipe));
339 intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false);
343 ivb_update_colorkey(struct drm_plane *plane,
344 struct drm_intel_sprite_colorkey *key)
346 struct drm_device *dev = plane->dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 struct intel_plane *intel_plane;
352 intel_plane = to_intel_plane(plane);
354 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
355 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
356 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
358 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
359 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
360 if (key->flags & I915_SET_COLORKEY_DESTINATION)
361 sprctl |= SPRITE_DEST_KEY;
362 else if (key->flags & I915_SET_COLORKEY_SOURCE)
363 sprctl |= SPRITE_SOURCE_KEY;
364 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
366 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
372 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
374 struct drm_device *dev = plane->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 struct intel_plane *intel_plane;
379 intel_plane = to_intel_plane(plane);
381 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
382 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
383 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
386 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
388 if (sprctl & SPRITE_DEST_KEY)
389 key->flags = I915_SET_COLORKEY_DESTINATION;
390 else if (sprctl & SPRITE_SOURCE_KEY)
391 key->flags = I915_SET_COLORKEY_SOURCE;
393 key->flags = I915_SET_COLORKEY_NONE;
397 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
398 struct drm_framebuffer *fb,
399 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
400 unsigned int crtc_w, unsigned int crtc_h,
401 uint32_t x, uint32_t y,
402 uint32_t src_w, uint32_t src_h)
404 struct drm_device *dev = plane->dev;
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 struct intel_plane *intel_plane = to_intel_plane(plane);
407 int pipe = intel_plane->pipe;
408 unsigned long dvssurf_offset, linear_offset;
409 u32 dvscntr, dvsscale;
410 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
412 dvscntr = I915_READ(DVSCNTR(pipe));
414 /* Mask out pixel format bits in case we change it */
415 dvscntr &= ~DVS_PIXFORMAT_MASK;
416 dvscntr &= ~DVS_RGB_ORDER_XBGR;
417 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
418 dvscntr &= ~DVS_TILED;
420 switch (fb->pixel_format) {
421 case DRM_FORMAT_XBGR8888:
422 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
424 case DRM_FORMAT_XRGB8888:
425 dvscntr |= DVS_FORMAT_RGBX888;
427 case DRM_FORMAT_YUYV:
428 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
430 case DRM_FORMAT_YVYU:
431 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
433 case DRM_FORMAT_UYVY:
434 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
436 case DRM_FORMAT_VYUY:
437 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
444 * Enable gamma to match primary/cursor plane behaviour.
445 * FIXME should be user controllable via propertiesa.
447 dvscntr |= DVS_GAMMA_ENABLE;
449 if (obj->tiling_mode != I915_TILING_NONE)
450 dvscntr |= DVS_TILED;
453 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
454 dvscntr |= DVS_ENABLE;
456 intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true,
457 src_w != crtc_w || src_h != crtc_h);
459 /* Sizes are 0 based */
466 if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
467 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
469 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
470 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
472 linear_offset = y * fb->pitches[0] + x * pixel_size;
474 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
475 pixel_size, fb->pitches[0]);
476 linear_offset -= dvssurf_offset;
478 if (obj->tiling_mode != I915_TILING_NONE)
479 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
481 I915_WRITE(DVSLINOFF(pipe), linear_offset);
483 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
484 I915_WRITE(DVSSCALE(pipe), dvsscale);
485 I915_WRITE(DVSCNTR(pipe), dvscntr);
486 I915_MODIFY_DISPBASE(DVSSURF(pipe),
487 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
488 POSTING_READ(DVSSURF(pipe));
492 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
494 struct drm_device *dev = plane->dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 struct intel_plane *intel_plane = to_intel_plane(plane);
497 int pipe = intel_plane->pipe;
499 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
500 /* Disable the scaler */
501 I915_WRITE(DVSSCALE(pipe), 0);
502 /* Flush double buffered register updates */
503 I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
504 POSTING_READ(DVSSURF(pipe));
506 intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false);
510 intel_enable_primary(struct drm_crtc *crtc)
512 struct drm_device *dev = crtc->dev;
513 struct drm_i915_private *dev_priv = dev->dev_private;
514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
515 int reg = DSPCNTR(intel_crtc->plane);
517 if (intel_crtc->primary_enabled)
520 intel_crtc->primary_enabled = true;
522 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
523 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
526 * FIXME IPS should be fine as long as one plane is
527 * enabled, but in practice it seems to have problems
528 * when going from primary only to sprite only and vice
531 if (intel_crtc->config.ips_enabled) {
532 intel_wait_for_vblank(dev, intel_crtc->pipe);
533 hsw_enable_ips(intel_crtc);
536 mutex_lock(&dev->struct_mutex);
537 intel_update_fbc(dev);
538 mutex_unlock(&dev->struct_mutex);
542 intel_disable_primary(struct drm_crtc *crtc)
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
547 int reg = DSPCNTR(intel_crtc->plane);
549 if (!intel_crtc->primary_enabled)
552 intel_crtc->primary_enabled = false;
554 mutex_lock(&dev->struct_mutex);
555 if (dev_priv->fbc.plane == intel_crtc->plane)
556 intel_disable_fbc(dev);
557 mutex_unlock(&dev->struct_mutex);
560 * FIXME IPS should be fine as long as one plane is
561 * enabled, but in practice it seems to have problems
562 * when going from primary only to sprite only and vice
565 hsw_disable_ips(intel_crtc);
567 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
568 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
572 ilk_update_colorkey(struct drm_plane *plane,
573 struct drm_intel_sprite_colorkey *key)
575 struct drm_device *dev = plane->dev;
576 struct drm_i915_private *dev_priv = dev->dev_private;
577 struct intel_plane *intel_plane;
581 intel_plane = to_intel_plane(plane);
583 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
584 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
585 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
587 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
588 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
589 if (key->flags & I915_SET_COLORKEY_DESTINATION)
590 dvscntr |= DVS_DEST_KEY;
591 else if (key->flags & I915_SET_COLORKEY_SOURCE)
592 dvscntr |= DVS_SOURCE_KEY;
593 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
595 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
601 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
603 struct drm_device *dev = plane->dev;
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 struct intel_plane *intel_plane;
608 intel_plane = to_intel_plane(plane);
610 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
611 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
612 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
615 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
617 if (dvscntr & DVS_DEST_KEY)
618 key->flags = I915_SET_COLORKEY_DESTINATION;
619 else if (dvscntr & DVS_SOURCE_KEY)
620 key->flags = I915_SET_COLORKEY_SOURCE;
622 key->flags = I915_SET_COLORKEY_NONE;
626 format_is_yuv(uint32_t format)
629 case DRM_FORMAT_YUYV:
630 case DRM_FORMAT_UYVY:
631 case DRM_FORMAT_VYUY:
632 case DRM_FORMAT_YVYU:
640 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
641 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
642 unsigned int crtc_w, unsigned int crtc_h,
643 uint32_t src_x, uint32_t src_y,
644 uint32_t src_w, uint32_t src_h)
646 struct drm_device *dev = plane->dev;
647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
648 struct intel_plane *intel_plane = to_intel_plane(plane);
649 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
650 struct drm_i915_gem_object *obj = intel_fb->obj;
651 struct drm_i915_gem_object *old_obj = intel_plane->obj;
653 bool disable_primary = false;
656 int max_scale, min_scale;
657 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
658 struct drm_rect src = {
659 /* sample coordinates in 16.16 fixed point */
665 struct drm_rect dst = {
668 .x2 = crtc_x + crtc_w,
670 .y2 = crtc_y + crtc_h,
672 const struct drm_rect clip = {
673 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
674 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
678 unsigned int crtc_w, crtc_h;
679 uint32_t src_x, src_y, src_w, src_h;
691 /* Don't modify another pipe's plane */
692 if (intel_plane->pipe != intel_crtc->pipe) {
693 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
697 /* FIXME check all gen limits */
698 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
699 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
703 /* Sprite planes can be linear or x-tiled surfaces */
704 switch (obj->tiling_mode) {
705 case I915_TILING_NONE:
709 DRM_DEBUG_KMS("Unsupported tiling mode\n");
714 * FIXME the following code does a bunch of fuzzy adjustments to the
715 * coordinates and sizes. We probably need some way to decide whether
716 * more strict checking should be done instead.
718 max_scale = intel_plane->max_downscale << 16;
719 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
721 hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
724 vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale);
727 visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale);
731 crtc_w = drm_rect_width(&dst);
732 crtc_h = drm_rect_height(&dst);
735 /* check again in case clipping clamped the results */
736 hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
738 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
739 drm_rect_debug_print(&src, true);
740 drm_rect_debug_print(&dst, false);
745 vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale);
747 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
748 drm_rect_debug_print(&src, true);
749 drm_rect_debug_print(&dst, false);
754 /* Make the source viewport size an exact multiple of the scaling factors. */
755 drm_rect_adjust_size(&src,
756 drm_rect_width(&dst) * hscale - drm_rect_width(&src),
757 drm_rect_height(&dst) * vscale - drm_rect_height(&src));
759 /* sanity check to make sure the src viewport wasn't enlarged */
760 WARN_ON(src.x1 < (int) src_x ||
761 src.y1 < (int) src_y ||
762 src.x2 > (int) (src_x + src_w) ||
763 src.y2 > (int) (src_y + src_h));
766 * Hardware doesn't handle subpixel coordinates.
767 * Adjust to (macro)pixel boundary, but be careful not to
768 * increase the source viewport size, because that could
769 * push the downscaling factor out of bounds.
771 src_x = src.x1 >> 16;
772 src_w = drm_rect_width(&src) >> 16;
773 src_y = src.y1 >> 16;
774 src_h = drm_rect_height(&src) >> 16;
776 if (format_is_yuv(fb->pixel_format)) {
781 * Must keep src and dst the
782 * same if we can't scale.
784 if (!intel_plane->can_scale)
792 /* Check size restrictions when scaling */
793 if (visible && (src_w != crtc_w || src_h != crtc_h)) {
794 unsigned int width_bytes;
796 WARN_ON(!intel_plane->can_scale);
798 /* FIXME interlacing min height is 6 */
800 if (crtc_w < 3 || crtc_h < 3)
803 if (src_w < 3 || src_h < 3)
806 width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size;
808 if (src_w > 2048 || src_h > 2048 ||
809 width_bytes > 4096 || fb->pitches[0] > 4096) {
810 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
816 dst.x2 = crtc_x + crtc_w;
818 dst.y2 = crtc_y + crtc_h;
821 * If the sprite is completely covering the primary plane,
822 * we can disable the primary and save power.
824 disable_primary = drm_rect_equals(&dst, &clip);
825 WARN_ON(disable_primary && !visible && intel_crtc->active);
827 mutex_lock(&dev->struct_mutex);
829 /* Note that this will apply the VT-d workaround for scanouts,
830 * which is more restrictive than required for sprites. (The
831 * primary plane requires 256KiB alignment with 64 PTE padding,
832 * the sprite planes only require 128KiB alignment and 32 PTE padding.
834 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
836 mutex_unlock(&dev->struct_mutex);
841 intel_plane->crtc_x = orig.crtc_x;
842 intel_plane->crtc_y = orig.crtc_y;
843 intel_plane->crtc_w = orig.crtc_w;
844 intel_plane->crtc_h = orig.crtc_h;
845 intel_plane->src_x = orig.src_x;
846 intel_plane->src_y = orig.src_y;
847 intel_plane->src_w = orig.src_w;
848 intel_plane->src_h = orig.src_h;
849 intel_plane->obj = obj;
851 if (intel_crtc->active) {
853 * Be sure to re-enable the primary before the sprite is no longer
856 if (!disable_primary)
857 intel_enable_primary(crtc);
860 intel_plane->update_plane(plane, crtc, fb, obj,
861 crtc_x, crtc_y, crtc_w, crtc_h,
862 src_x, src_y, src_w, src_h);
864 intel_plane->disable_plane(plane, crtc);
867 intel_disable_primary(crtc);
870 /* Unpin old obj after new one is active to avoid ugliness */
873 * It's fairly common to simply update the position of
874 * an existing object. In that case, we don't need to
875 * wait for vblank to avoid ugliness, we only need to
876 * do the pin & ref bookkeeping.
878 if (old_obj != obj && intel_crtc->active)
879 intel_wait_for_vblank(dev, intel_crtc->pipe);
881 mutex_lock(&dev->struct_mutex);
882 intel_unpin_fb_obj(old_obj);
883 mutex_unlock(&dev->struct_mutex);
890 intel_disable_plane(struct drm_plane *plane)
892 struct drm_device *dev = plane->dev;
893 struct intel_plane *intel_plane = to_intel_plane(plane);
894 struct intel_crtc *intel_crtc;
899 if (WARN_ON(!plane->crtc))
902 intel_crtc = to_intel_crtc(plane->crtc);
904 if (intel_crtc->active) {
905 intel_enable_primary(plane->crtc);
906 intel_plane->disable_plane(plane, plane->crtc);
909 if (intel_plane->obj) {
910 if (intel_crtc->active)
911 intel_wait_for_vblank(dev, intel_plane->pipe);
913 mutex_lock(&dev->struct_mutex);
914 intel_unpin_fb_obj(intel_plane->obj);
915 mutex_unlock(&dev->struct_mutex);
917 intel_plane->obj = NULL;
923 static void intel_destroy_plane(struct drm_plane *plane)
925 struct intel_plane *intel_plane = to_intel_plane(plane);
926 intel_disable_plane(plane);
927 drm_plane_cleanup(plane);
931 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
932 struct drm_file *file_priv)
934 struct drm_intel_sprite_colorkey *set = data;
935 struct drm_mode_object *obj;
936 struct drm_plane *plane;
937 struct intel_plane *intel_plane;
940 if (!drm_core_check_feature(dev, DRIVER_MODESET))
943 /* Make sure we don't try to enable both src & dest simultaneously */
944 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
947 drm_modeset_lock_all(dev);
949 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
955 plane = obj_to_plane(obj);
956 intel_plane = to_intel_plane(plane);
957 ret = intel_plane->update_colorkey(plane, set);
960 drm_modeset_unlock_all(dev);
964 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
965 struct drm_file *file_priv)
967 struct drm_intel_sprite_colorkey *get = data;
968 struct drm_mode_object *obj;
969 struct drm_plane *plane;
970 struct intel_plane *intel_plane;
973 if (!drm_core_check_feature(dev, DRIVER_MODESET))
976 drm_modeset_lock_all(dev);
978 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
984 plane = obj_to_plane(obj);
985 intel_plane = to_intel_plane(plane);
986 intel_plane->get_colorkey(plane, get);
989 drm_modeset_unlock_all(dev);
993 void intel_plane_restore(struct drm_plane *plane)
995 struct intel_plane *intel_plane = to_intel_plane(plane);
997 if (!plane->crtc || !plane->fb)
1000 intel_update_plane(plane, plane->crtc, plane->fb,
1001 intel_plane->crtc_x, intel_plane->crtc_y,
1002 intel_plane->crtc_w, intel_plane->crtc_h,
1003 intel_plane->src_x, intel_plane->src_y,
1004 intel_plane->src_w, intel_plane->src_h);
1007 void intel_plane_disable(struct drm_plane *plane)
1009 if (!plane->crtc || !plane->fb)
1012 intel_disable_plane(plane);
1015 static const struct drm_plane_funcs intel_plane_funcs = {
1016 .update_plane = intel_update_plane,
1017 .disable_plane = intel_disable_plane,
1018 .destroy = intel_destroy_plane,
1021 static uint32_t ilk_plane_formats[] = {
1022 DRM_FORMAT_XRGB8888,
1029 static uint32_t snb_plane_formats[] = {
1030 DRM_FORMAT_XBGR8888,
1031 DRM_FORMAT_XRGB8888,
1038 static uint32_t vlv_plane_formats[] = {
1040 DRM_FORMAT_ABGR8888,
1041 DRM_FORMAT_ARGB8888,
1042 DRM_FORMAT_XBGR8888,
1043 DRM_FORMAT_XRGB8888,
1044 DRM_FORMAT_XBGR2101010,
1045 DRM_FORMAT_ABGR2101010,
1053 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1055 struct intel_plane *intel_plane;
1056 unsigned long possible_crtcs;
1057 const uint32_t *plane_formats;
1058 int num_plane_formats;
1061 if (INTEL_INFO(dev)->gen < 5)
1064 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1068 switch (INTEL_INFO(dev)->gen) {
1071 intel_plane->can_scale = true;
1072 intel_plane->max_downscale = 16;
1073 intel_plane->update_plane = ilk_update_plane;
1074 intel_plane->disable_plane = ilk_disable_plane;
1075 intel_plane->update_colorkey = ilk_update_colorkey;
1076 intel_plane->get_colorkey = ilk_get_colorkey;
1079 plane_formats = snb_plane_formats;
1080 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1082 plane_formats = ilk_plane_formats;
1083 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1089 if (IS_IVYBRIDGE(dev)) {
1090 intel_plane->can_scale = true;
1091 intel_plane->max_downscale = 2;
1093 intel_plane->can_scale = false;
1094 intel_plane->max_downscale = 1;
1097 if (IS_VALLEYVIEW(dev)) {
1098 intel_plane->update_plane = vlv_update_plane;
1099 intel_plane->disable_plane = vlv_disable_plane;
1100 intel_plane->update_colorkey = vlv_update_colorkey;
1101 intel_plane->get_colorkey = vlv_get_colorkey;
1103 plane_formats = vlv_plane_formats;
1104 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1106 intel_plane->update_plane = ivb_update_plane;
1107 intel_plane->disable_plane = ivb_disable_plane;
1108 intel_plane->update_colorkey = ivb_update_colorkey;
1109 intel_plane->get_colorkey = ivb_get_colorkey;
1111 plane_formats = snb_plane_formats;
1112 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1121 intel_plane->pipe = pipe;
1122 intel_plane->plane = plane;
1123 possible_crtcs = (1 << pipe);
1124 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
1126 plane_formats, num_plane_formats,