Merge tag 'drm-intel-next-2018-09-06-2' of git://anongit.freedesktop.org/drm/drm...
[platform/kernel/linux-rpi.git] / drivers / gpu / drm / i915 / intel_sprite.c
1 /*
2  * Copyright © 2011 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
25  *
26  * New plane/sprite handling.
27  *
28  * The older chips had a separate interface for programming plane related
29  * registers; newer ones are much simpler and we can use the new DRM plane
30  * support.
31  */
32 #include <drm/drmP.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_rect.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_plane_helper.h>
39 #include "intel_drv.h"
40 #include "intel_frontbuffer.h"
41 #include <drm/i915_drm.h>
42 #include "i915_drv.h"
43
44 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
45                              int usecs)
46 {
47         /* paranoia */
48         if (!adjusted_mode->crtc_htotal)
49                 return 1;
50
51         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
52                             1000 * adjusted_mode->crtc_htotal);
53 }
54
55 /* FIXME: We should instead only take spinlocks once for the entire update
56  * instead of once per mmio. */
57 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
58 #define VBLANK_EVASION_TIME_US 250
59 #else
60 #define VBLANK_EVASION_TIME_US 100
61 #endif
62
63 /**
64  * intel_pipe_update_start() - start update of a set of display registers
65  * @new_crtc_state: the new crtc state
66  *
67  * Mark the start of an update to pipe registers that should be updated
68  * atomically regarding vblank. If the next vblank will happens within
69  * the next 100 us, this function waits until the vblank passes.
70  *
71  * After a successful call to this function, interrupts will be disabled
72  * until a subsequent call to intel_pipe_update_end(). That is done to
73  * avoid random delays.
74  */
75 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
76 {
77         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
78         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
79         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
80         long timeout = msecs_to_jiffies_timeout(1);
81         int scanline, min, max, vblank_start;
82         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
83         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
84                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
85         DEFINE_WAIT(wait);
86         u32 psr_status;
87
88         vblank_start = adjusted_mode->crtc_vblank_start;
89         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
90                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
91
92         /* FIXME needs to be calibrated sensibly */
93         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
94                                                       VBLANK_EVASION_TIME_US);
95         max = vblank_start - 1;
96
97         if (min <= 0 || max <= 0)
98                 goto irq_disable;
99
100         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
101                 goto irq_disable;
102
103         /*
104          * Wait for psr to idle out after enabling the VBL interrupts
105          * VBL interrupts will start the PSR exit and prevent a PSR
106          * re-entry as well.
107          */
108         if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
109                 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
110                           psr_status);
111
112         local_irq_disable();
113
114         crtc->debug.min_vbl = min;
115         crtc->debug.max_vbl = max;
116         trace_i915_pipe_update_start(crtc);
117
118         for (;;) {
119                 /*
120                  * prepare_to_wait() has a memory barrier, which guarantees
121                  * other CPUs can see the task state update by the time we
122                  * read the scanline.
123                  */
124                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
125
126                 scanline = intel_get_crtc_scanline(crtc);
127                 if (scanline < min || scanline > max)
128                         break;
129
130                 if (!timeout) {
131                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
132                                   pipe_name(crtc->pipe));
133                         break;
134                 }
135
136                 local_irq_enable();
137
138                 timeout = schedule_timeout(timeout);
139
140                 local_irq_disable();
141         }
142
143         finish_wait(wq, &wait);
144
145         drm_crtc_vblank_put(&crtc->base);
146
147         /*
148          * On VLV/CHV DSI the scanline counter would appear to
149          * increment approx. 1/3 of a scanline before start of vblank.
150          * The registers still get latched at start of vblank however.
151          * This means we must not write any registers on the first
152          * line of vblank (since not the whole line is actually in
153          * vblank). And unfortunately we can't use the interrupt to
154          * wait here since it will fire too soon. We could use the
155          * frame start interrupt instead since it will fire after the
156          * critical scanline, but that would require more changes
157          * in the interrupt code. So for now we'll just do the nasty
158          * thing and poll for the bad scanline to pass us by.
159          *
160          * FIXME figure out if BXT+ DSI suffers from this as well
161          */
162         while (need_vlv_dsi_wa && scanline == vblank_start)
163                 scanline = intel_get_crtc_scanline(crtc);
164
165         crtc->debug.scanline_start = scanline;
166         crtc->debug.start_vbl_time = ktime_get();
167         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
168
169         trace_i915_pipe_update_vblank_evaded(crtc);
170         return;
171
172 irq_disable:
173         local_irq_disable();
174 }
175
176 /**
177  * intel_pipe_update_end() - end update of a set of display registers
178  * @new_crtc_state: the new crtc state
179  *
180  * Mark the end of an update started with intel_pipe_update_start(). This
181  * re-enables interrupts and verifies the update was actually completed
182  * before a vblank.
183  */
184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
185 {
186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
187         enum pipe pipe = crtc->pipe;
188         int scanline_end = intel_get_crtc_scanline(crtc);
189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
190         ktime_t end_vbl_time = ktime_get();
191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
192
193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
194
195         /* We're still in the vblank-evade critical section, this can't race.
196          * Would be slightly nice to just grab the vblank count and arm the
197          * event outside of the critical section - the spinlock might spin for a
198          * while ... */
199         if (new_crtc_state->base.event) {
200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
201
202                 spin_lock(&crtc->base.dev->event_lock);
203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
204                 spin_unlock(&crtc->base.dev->event_lock);
205
206                 new_crtc_state->base.event = NULL;
207         }
208
209         local_irq_enable();
210
211         if (intel_vgpu_active(dev_priv))
212                 return;
213
214         if (crtc->debug.start_vbl_count &&
215             crtc->debug.start_vbl_count != end_vbl_count) {
216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
217                           pipe_name(pipe), crtc->debug.start_vbl_count,
218                           end_vbl_count,
219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
221                           crtc->debug.scanline_start, scanline_end);
222         }
223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
225                  VBLANK_EVASION_TIME_US)
226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
227                          pipe_name(pipe),
228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
229                          VBLANK_EVASION_TIME_US);
230 #endif
231 }
232
233 void
234 skl_update_plane(struct intel_plane *plane,
235                  const struct intel_crtc_state *crtc_state,
236                  const struct intel_plane_state *plane_state)
237 {
238         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
239         const struct drm_framebuffer *fb = plane_state->base.fb;
240         enum plane_id plane_id = plane->id;
241         enum pipe pipe = plane->pipe;
242         u32 plane_ctl = plane_state->ctl;
243         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
244         u32 surf_addr = plane_state->main.offset;
245         unsigned int rotation = plane_state->base.rotation;
246         u32 stride = skl_plane_stride(fb, 0, rotation);
247         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
248         int crtc_x = plane_state->base.dst.x1;
249         int crtc_y = plane_state->base.dst.y1;
250         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
251         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
252         uint32_t x = plane_state->main.x;
253         uint32_t y = plane_state->main.y;
254         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
255         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
256         unsigned long irqflags;
257
258         /* Sizes are 0 based */
259         src_w--;
260         src_h--;
261         crtc_w--;
262         crtc_h--;
263
264         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
265
266         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
267                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
268                               plane_state->color_ctl);
269
270         if (key->flags) {
271                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
272                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
273                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
274         }
275
276         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
277         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
278         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
279         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
280                       (plane_state->aux.offset - surf_addr) | aux_stride);
281         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
282                       (plane_state->aux.y << 16) | plane_state->aux.x);
283
284         /* program plane scaler */
285         if (plane_state->scaler_id >= 0) {
286                 int scaler_id = plane_state->scaler_id;
287                 const struct intel_scaler *scaler =
288                         &crtc_state->scaler_state.scalers[scaler_id];
289                 u16 y_hphase, uv_rgb_hphase;
290                 u16 y_vphase, uv_rgb_vphase;
291
292                 /* TODO: handle sub-pixel coordinates */
293                 if (fb->format->format == DRM_FORMAT_NV12) {
294                         y_hphase = skl_scaler_calc_phase(1, false);
295                         y_vphase = skl_scaler_calc_phase(1, false);
296
297                         /* MPEG2 chroma siting convention */
298                         uv_rgb_hphase = skl_scaler_calc_phase(2, true);
299                         uv_rgb_vphase = skl_scaler_calc_phase(2, false);
300                 } else {
301                         /* not used */
302                         y_hphase = 0;
303                         y_vphase = 0;
304
305                         uv_rgb_hphase = skl_scaler_calc_phase(1, false);
306                         uv_rgb_vphase = skl_scaler_calc_phase(1, false);
307                 }
308
309                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
310                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
311                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
312                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
313                               PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
314                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
315                               PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
316                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
317                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
318                               ((crtc_w + 1) << 16)|(crtc_h + 1));
319
320                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
321         } else {
322                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
323         }
324
325         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
326         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
327                       intel_plane_ggtt_offset(plane_state) + surf_addr);
328         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
329
330         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
331 }
332
333 void
334 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
335 {
336         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
337         enum plane_id plane_id = plane->id;
338         enum pipe pipe = plane->pipe;
339         unsigned long irqflags;
340
341         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
342
343         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
344
345         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
346         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
347
348         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
349 }
350
351 bool
352 skl_plane_get_hw_state(struct intel_plane *plane,
353                        enum pipe *pipe)
354 {
355         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
356         enum intel_display_power_domain power_domain;
357         enum plane_id plane_id = plane->id;
358         bool ret;
359
360         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
361         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
362                 return false;
363
364         ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
365
366         *pipe = plane->pipe;
367
368         intel_display_power_put(dev_priv, power_domain);
369
370         return ret;
371 }
372
373 static void
374 chv_update_csc(const struct intel_plane_state *plane_state)
375 {
376         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
377         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
378         const struct drm_framebuffer *fb = plane_state->base.fb;
379         enum plane_id plane_id = plane->id;
380         /*
381          * |r|   | c0 c1 c2 |   |cr|
382          * |g| = | c3 c4 c5 | x |y |
383          * |b|   | c6 c7 c8 |   |cb|
384          *
385          * Coefficients are s3.12.
386          *
387          * Cb and Cr apparently come in as signed already, and
388          * we always get full range data in on account of CLRC0/1.
389          */
390         static const s16 csc_matrix[][9] = {
391                 /* BT.601 full range YCbCr -> full range RGB */
392                 [DRM_COLOR_YCBCR_BT601] = {
393                          5743, 4096,     0,
394                         -2925, 4096, -1410,
395                             0, 4096,  7258,
396                 },
397                 /* BT.709 full range YCbCr -> full range RGB */
398                 [DRM_COLOR_YCBCR_BT709] = {
399                          6450, 4096,     0,
400                         -1917, 4096,  -767,
401                             0, 4096,  7601,
402                 },
403         };
404         const s16 *csc = csc_matrix[plane_state->base.color_encoding];
405
406         /* Seems RGB data bypasses the CSC always */
407         if (!fb->format->is_yuv)
408                 return;
409
410         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
411         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
412         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
413
414         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
415         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
416         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
417         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
418         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
419
420         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
421         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
422         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
423
424         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
425         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
426         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
427 }
428
429 #define SIN_0 0
430 #define COS_0 1
431
432 static void
433 vlv_update_clrc(const struct intel_plane_state *plane_state)
434 {
435         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
436         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
437         const struct drm_framebuffer *fb = plane_state->base.fb;
438         enum pipe pipe = plane->pipe;
439         enum plane_id plane_id = plane->id;
440         int contrast, brightness, sh_scale, sh_sin, sh_cos;
441
442         if (fb->format->is_yuv &&
443             plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
444                 /*
445                  * Expand limited range to full range:
446                  * Contrast is applied first and is used to expand Y range.
447                  * Brightness is applied second and is used to remove the
448                  * offset from Y. Saturation/hue is used to expand CbCr range.
449                  */
450                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
451                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
452                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
453                 sh_sin = SIN_0 * sh_scale;
454                 sh_cos = COS_0 * sh_scale;
455         } else {
456                 /* Pass-through everything. */
457                 contrast = 1 << 6;
458                 brightness = 0;
459                 sh_scale = 1 << 7;
460                 sh_sin = SIN_0 * sh_scale;
461                 sh_cos = COS_0 * sh_scale;
462         }
463
464         /* FIXME these register are single buffered :( */
465         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
466                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
467         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
468                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
469 }
470
471 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
472                           const struct intel_plane_state *plane_state)
473 {
474         const struct drm_framebuffer *fb = plane_state->base.fb;
475         unsigned int rotation = plane_state->base.rotation;
476         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
477         u32 sprctl;
478
479         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
480
481         switch (fb->format->format) {
482         case DRM_FORMAT_YUYV:
483                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
484                 break;
485         case DRM_FORMAT_YVYU:
486                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
487                 break;
488         case DRM_FORMAT_UYVY:
489                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
490                 break;
491         case DRM_FORMAT_VYUY:
492                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
493                 break;
494         case DRM_FORMAT_RGB565:
495                 sprctl |= SP_FORMAT_BGR565;
496                 break;
497         case DRM_FORMAT_XRGB8888:
498                 sprctl |= SP_FORMAT_BGRX8888;
499                 break;
500         case DRM_FORMAT_ARGB8888:
501                 sprctl |= SP_FORMAT_BGRA8888;
502                 break;
503         case DRM_FORMAT_XBGR2101010:
504                 sprctl |= SP_FORMAT_RGBX1010102;
505                 break;
506         case DRM_FORMAT_ABGR2101010:
507                 sprctl |= SP_FORMAT_RGBA1010102;
508                 break;
509         case DRM_FORMAT_XBGR8888:
510                 sprctl |= SP_FORMAT_RGBX8888;
511                 break;
512         case DRM_FORMAT_ABGR8888:
513                 sprctl |= SP_FORMAT_RGBA8888;
514                 break;
515         default:
516                 MISSING_CASE(fb->format->format);
517                 return 0;
518         }
519
520         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
521                 sprctl |= SP_YUV_FORMAT_BT709;
522
523         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
524                 sprctl |= SP_TILED;
525
526         if (rotation & DRM_MODE_ROTATE_180)
527                 sprctl |= SP_ROTATE_180;
528
529         if (rotation & DRM_MODE_REFLECT_X)
530                 sprctl |= SP_MIRROR;
531
532         if (key->flags & I915_SET_COLORKEY_SOURCE)
533                 sprctl |= SP_SOURCE_KEY;
534
535         return sprctl;
536 }
537
538 static void
539 vlv_update_plane(struct intel_plane *plane,
540                  const struct intel_crtc_state *crtc_state,
541                  const struct intel_plane_state *plane_state)
542 {
543         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
544         const struct drm_framebuffer *fb = plane_state->base.fb;
545         enum pipe pipe = plane->pipe;
546         enum plane_id plane_id = plane->id;
547         u32 sprctl = plane_state->ctl;
548         u32 sprsurf_offset = plane_state->main.offset;
549         u32 linear_offset;
550         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
551         int crtc_x = plane_state->base.dst.x1;
552         int crtc_y = plane_state->base.dst.y1;
553         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
554         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
555         uint32_t x = plane_state->main.x;
556         uint32_t y = plane_state->main.y;
557         unsigned long irqflags;
558
559         /* Sizes are 0 based */
560         crtc_w--;
561         crtc_h--;
562
563         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
564
565         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
566
567         vlv_update_clrc(plane_state);
568
569         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
570                 chv_update_csc(plane_state);
571
572         if (key->flags) {
573                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
574                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
575                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
576         }
577         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
578         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
579
580         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
581                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
582         else
583                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
584
585         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
586
587         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
588         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
589         I915_WRITE_FW(SPSURF(pipe, plane_id),
590                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
591         POSTING_READ_FW(SPSURF(pipe, plane_id));
592
593         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
594 }
595
596 static void
597 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
598 {
599         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
600         enum pipe pipe = plane->pipe;
601         enum plane_id plane_id = plane->id;
602         unsigned long irqflags;
603
604         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
605
606         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
607
608         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
609         POSTING_READ_FW(SPSURF(pipe, plane_id));
610
611         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
612 }
613
614 static bool
615 vlv_plane_get_hw_state(struct intel_plane *plane,
616                        enum pipe *pipe)
617 {
618         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
619         enum intel_display_power_domain power_domain;
620         enum plane_id plane_id = plane->id;
621         bool ret;
622
623         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
624         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
625                 return false;
626
627         ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
628
629         *pipe = plane->pipe;
630
631         intel_display_power_put(dev_priv, power_domain);
632
633         return ret;
634 }
635
636 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
637                           const struct intel_plane_state *plane_state)
638 {
639         struct drm_i915_private *dev_priv =
640                 to_i915(plane_state->base.plane->dev);
641         const struct drm_framebuffer *fb = plane_state->base.fb;
642         unsigned int rotation = plane_state->base.rotation;
643         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
644         u32 sprctl;
645
646         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
647
648         if (IS_IVYBRIDGE(dev_priv))
649                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
650
651         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
652                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
653
654         switch (fb->format->format) {
655         case DRM_FORMAT_XBGR8888:
656                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
657                 break;
658         case DRM_FORMAT_XRGB8888:
659                 sprctl |= SPRITE_FORMAT_RGBX888;
660                 break;
661         case DRM_FORMAT_YUYV:
662                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
663                 break;
664         case DRM_FORMAT_YVYU:
665                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
666                 break;
667         case DRM_FORMAT_UYVY:
668                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
669                 break;
670         case DRM_FORMAT_VYUY:
671                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
672                 break;
673         default:
674                 MISSING_CASE(fb->format->format);
675                 return 0;
676         }
677
678         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
679                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
680
681         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
682                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
683
684         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
685                 sprctl |= SPRITE_TILED;
686
687         if (rotation & DRM_MODE_ROTATE_180)
688                 sprctl |= SPRITE_ROTATE_180;
689
690         if (key->flags & I915_SET_COLORKEY_DESTINATION)
691                 sprctl |= SPRITE_DEST_KEY;
692         else if (key->flags & I915_SET_COLORKEY_SOURCE)
693                 sprctl |= SPRITE_SOURCE_KEY;
694
695         return sprctl;
696 }
697
698 static void
699 ivb_update_plane(struct intel_plane *plane,
700                  const struct intel_crtc_state *crtc_state,
701                  const struct intel_plane_state *plane_state)
702 {
703         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
704         const struct drm_framebuffer *fb = plane_state->base.fb;
705         enum pipe pipe = plane->pipe;
706         u32 sprctl = plane_state->ctl, sprscale = 0;
707         u32 sprsurf_offset = plane_state->main.offset;
708         u32 linear_offset;
709         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
710         int crtc_x = plane_state->base.dst.x1;
711         int crtc_y = plane_state->base.dst.y1;
712         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
713         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
714         uint32_t x = plane_state->main.x;
715         uint32_t y = plane_state->main.y;
716         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
717         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
718         unsigned long irqflags;
719
720         /* Sizes are 0 based */
721         src_w--;
722         src_h--;
723         crtc_w--;
724         crtc_h--;
725
726         if (crtc_w != src_w || crtc_h != src_h)
727                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
728
729         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
730
731         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
732
733         if (key->flags) {
734                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
735                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
736                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
737         }
738
739         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
740         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
741
742         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
743          * register */
744         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
745                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
746         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
747                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
748         else
749                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
750
751         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
752         if (plane->can_scale)
753                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
754         I915_WRITE_FW(SPRCTL(pipe), sprctl);
755         I915_WRITE_FW(SPRSURF(pipe),
756                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
757         POSTING_READ_FW(SPRSURF(pipe));
758
759         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
760 }
761
762 static void
763 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
764 {
765         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
766         enum pipe pipe = plane->pipe;
767         unsigned long irqflags;
768
769         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
770
771         I915_WRITE_FW(SPRCTL(pipe), 0);
772         /* Can't leave the scaler enabled... */
773         if (plane->can_scale)
774                 I915_WRITE_FW(SPRSCALE(pipe), 0);
775
776         I915_WRITE_FW(SPRSURF(pipe), 0);
777         POSTING_READ_FW(SPRSURF(pipe));
778
779         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
780 }
781
782 static bool
783 ivb_plane_get_hw_state(struct intel_plane *plane,
784                        enum pipe *pipe)
785 {
786         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
787         enum intel_display_power_domain power_domain;
788         bool ret;
789
790         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
791         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
792                 return false;
793
794         ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
795
796         *pipe = plane->pipe;
797
798         intel_display_power_put(dev_priv, power_domain);
799
800         return ret;
801 }
802
803 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
804                           const struct intel_plane_state *plane_state)
805 {
806         struct drm_i915_private *dev_priv =
807                 to_i915(plane_state->base.plane->dev);
808         const struct drm_framebuffer *fb = plane_state->base.fb;
809         unsigned int rotation = plane_state->base.rotation;
810         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
811         u32 dvscntr;
812
813         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
814
815         if (IS_GEN6(dev_priv))
816                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
817
818         switch (fb->format->format) {
819         case DRM_FORMAT_XBGR8888:
820                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
821                 break;
822         case DRM_FORMAT_XRGB8888:
823                 dvscntr |= DVS_FORMAT_RGBX888;
824                 break;
825         case DRM_FORMAT_YUYV:
826                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
827                 break;
828         case DRM_FORMAT_YVYU:
829                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
830                 break;
831         case DRM_FORMAT_UYVY:
832                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
833                 break;
834         case DRM_FORMAT_VYUY:
835                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
836                 break;
837         default:
838                 MISSING_CASE(fb->format->format);
839                 return 0;
840         }
841
842         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
843                 dvscntr |= DVS_YUV_FORMAT_BT709;
844
845         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
846                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
847
848         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
849                 dvscntr |= DVS_TILED;
850
851         if (rotation & DRM_MODE_ROTATE_180)
852                 dvscntr |= DVS_ROTATE_180;
853
854         if (key->flags & I915_SET_COLORKEY_DESTINATION)
855                 dvscntr |= DVS_DEST_KEY;
856         else if (key->flags & I915_SET_COLORKEY_SOURCE)
857                 dvscntr |= DVS_SOURCE_KEY;
858
859         return dvscntr;
860 }
861
862 static void
863 g4x_update_plane(struct intel_plane *plane,
864                  const struct intel_crtc_state *crtc_state,
865                  const struct intel_plane_state *plane_state)
866 {
867         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
868         const struct drm_framebuffer *fb = plane_state->base.fb;
869         enum pipe pipe = plane->pipe;
870         u32 dvscntr = plane_state->ctl, dvsscale = 0;
871         u32 dvssurf_offset = plane_state->main.offset;
872         u32 linear_offset;
873         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
874         int crtc_x = plane_state->base.dst.x1;
875         int crtc_y = plane_state->base.dst.y1;
876         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
877         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
878         uint32_t x = plane_state->main.x;
879         uint32_t y = plane_state->main.y;
880         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
881         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
882         unsigned long irqflags;
883
884         /* Sizes are 0 based */
885         src_w--;
886         src_h--;
887         crtc_w--;
888         crtc_h--;
889
890         if (crtc_w != src_w || crtc_h != src_h)
891                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
892
893         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
894
895         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
896
897         if (key->flags) {
898                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
899                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
900                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
901         }
902
903         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
904         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
905
906         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
907                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
908         else
909                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
910
911         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
912         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
913         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
914         I915_WRITE_FW(DVSSURF(pipe),
915                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
916         POSTING_READ_FW(DVSSURF(pipe));
917
918         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
919 }
920
921 static void
922 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
923 {
924         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
925         enum pipe pipe = plane->pipe;
926         unsigned long irqflags;
927
928         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
929
930         I915_WRITE_FW(DVSCNTR(pipe), 0);
931         /* Disable the scaler */
932         I915_WRITE_FW(DVSSCALE(pipe), 0);
933
934         I915_WRITE_FW(DVSSURF(pipe), 0);
935         POSTING_READ_FW(DVSSURF(pipe));
936
937         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
938 }
939
940 static bool
941 g4x_plane_get_hw_state(struct intel_plane *plane,
942                        enum pipe *pipe)
943 {
944         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
945         enum intel_display_power_domain power_domain;
946         bool ret;
947
948         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
949         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
950                 return false;
951
952         ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
953
954         *pipe = plane->pipe;
955
956         intel_display_power_put(dev_priv, power_domain);
957
958         return ret;
959 }
960
961 static int
962 intel_check_sprite_plane(struct intel_crtc_state *crtc_state,
963                          struct intel_plane_state *state)
964 {
965         struct intel_plane *plane = to_intel_plane(state->base.plane);
966         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
967         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
968         struct drm_framebuffer *fb = state->base.fb;
969         int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
970         int max_scale, min_scale;
971         bool can_scale;
972         int ret;
973         uint32_t pixel_format = 0;
974
975         if (!fb) {
976                 state->base.visible = false;
977                 return 0;
978         }
979
980         /* Don't modify another pipe's plane */
981         if (plane->pipe != crtc->pipe) {
982                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
983                 return -EINVAL;
984         }
985
986         /* FIXME check all gen limits */
987         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > max_stride) {
988                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
989                 return -EINVAL;
990         }
991
992         /* setup can_scale, min_scale, max_scale */
993         if (INTEL_GEN(dev_priv) >= 9) {
994                 if (state->base.fb)
995                         pixel_format = state->base.fb->format->format;
996                 /* use scaler when colorkey is not required */
997                 if (!state->ckey.flags) {
998                         can_scale = 1;
999                         min_scale = 1;
1000                         max_scale =
1001                                 skl_max_scale(crtc, crtc_state, pixel_format);
1002                 } else {
1003                         can_scale = 0;
1004                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
1005                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
1006                 }
1007         } else {
1008                 can_scale = plane->can_scale;
1009                 max_scale = plane->max_downscale << 16;
1010                 min_scale = plane->can_scale ? 1 : (1 << 16);
1011         }
1012
1013         ret = drm_atomic_helper_check_plane_state(&state->base,
1014                                                   &crtc_state->base,
1015                                                   min_scale, max_scale,
1016                                                   true, true);
1017         if (ret)
1018                 return ret;
1019
1020         if (state->base.visible) {
1021                 struct drm_rect *src = &state->base.src;
1022                 struct drm_rect *dst = &state->base.dst;
1023                 unsigned int crtc_w = drm_rect_width(dst);
1024                 unsigned int crtc_h = drm_rect_height(dst);
1025                 uint32_t src_x, src_y, src_w, src_h;
1026
1027                 /*
1028                  * Hardware doesn't handle subpixel coordinates.
1029                  * Adjust to (macro)pixel boundary, but be careful not to
1030                  * increase the source viewport size, because that could
1031                  * push the downscaling factor out of bounds.
1032                  */
1033                 src_x = src->x1 >> 16;
1034                 src_w = drm_rect_width(src) >> 16;
1035                 src_y = src->y1 >> 16;
1036                 src_h = drm_rect_height(src) >> 16;
1037
1038                 src->x1 = src_x << 16;
1039                 src->x2 = (src_x + src_w) << 16;
1040                 src->y1 = src_y << 16;
1041                 src->y2 = (src_y + src_h) << 16;
1042
1043                 if (fb->format->is_yuv &&
1044                     fb->format->format != DRM_FORMAT_NV12 &&
1045                     (src_x % 2 || src_w % 2)) {
1046                         DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
1047                                       src_x, src_w);
1048                         return -EINVAL;
1049                 }
1050
1051                 /* Check size restrictions when scaling */
1052                 if (src_w != crtc_w || src_h != crtc_h) {
1053                         unsigned int width_bytes;
1054                         int cpp = fb->format->cpp[0];
1055
1056                         WARN_ON(!can_scale);
1057
1058                         width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1059
1060                         /* FIXME interlacing min height is 6 */
1061                         if (INTEL_GEN(dev_priv) < 9 && (
1062                              src_w < 3 || src_h < 3 ||
1063                              src_w > 2048 || src_h > 2048 ||
1064                              crtc_w < 3 || crtc_h < 3 ||
1065                              width_bytes > 4096 || fb->pitches[0] > 4096)) {
1066                                 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1067                                 return -EINVAL;
1068                         }
1069                 }
1070         }
1071
1072         if (INTEL_GEN(dev_priv) >= 9) {
1073                 ret = skl_check_plane_surface(crtc_state, state);
1074                 if (ret)
1075                         return ret;
1076
1077                 state->ctl = skl_plane_ctl(crtc_state, state);
1078         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1079                 ret = i9xx_check_plane_surface(state);
1080                 if (ret)
1081                         return ret;
1082
1083                 state->ctl = vlv_sprite_ctl(crtc_state, state);
1084         } else if (INTEL_GEN(dev_priv) >= 7) {
1085                 ret = i9xx_check_plane_surface(state);
1086                 if (ret)
1087                         return ret;
1088
1089                 state->ctl = ivb_sprite_ctl(crtc_state, state);
1090         } else {
1091                 ret = i9xx_check_plane_surface(state);
1092                 if (ret)
1093                         return ret;
1094
1095                 state->ctl = g4x_sprite_ctl(crtc_state, state);
1096         }
1097
1098         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1099                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
1100
1101         return 0;
1102 }
1103
1104 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1105 {
1106         return INTEL_GEN(dev_priv) >= 9;
1107 }
1108
1109 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1110                                  const struct drm_intel_sprite_colorkey *set)
1111 {
1112         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1113         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1114         struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1115
1116         *key = *set;
1117
1118         /*
1119          * We want src key enabled on the
1120          * sprite and not on the primary.
1121          */
1122         if (plane->id == PLANE_PRIMARY &&
1123             set->flags & I915_SET_COLORKEY_SOURCE)
1124                 key->flags = 0;
1125
1126         /*
1127          * On SKL+ we want dst key enabled on
1128          * the primary and not on the sprite.
1129          */
1130         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1131             set->flags & I915_SET_COLORKEY_DESTINATION)
1132                 key->flags = 0;
1133 }
1134
1135 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1136                                     struct drm_file *file_priv)
1137 {
1138         struct drm_i915_private *dev_priv = to_i915(dev);
1139         struct drm_intel_sprite_colorkey *set = data;
1140         struct drm_plane *plane;
1141         struct drm_plane_state *plane_state;
1142         struct drm_atomic_state *state;
1143         struct drm_modeset_acquire_ctx ctx;
1144         int ret = 0;
1145
1146         /* ignore the pointless "none" flag */
1147         set->flags &= ~I915_SET_COLORKEY_NONE;
1148
1149         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1150                 return -EINVAL;
1151
1152         /* Make sure we don't try to enable both src & dest simultaneously */
1153         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1154                 return -EINVAL;
1155
1156         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1157             set->flags & I915_SET_COLORKEY_DESTINATION)
1158                 return -EINVAL;
1159
1160         plane = drm_plane_find(dev, file_priv, set->plane_id);
1161         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1162                 return -ENOENT;
1163
1164         /*
1165          * SKL+ only plane 2 can do destination keying against plane 1.
1166          * Also multiple planes can't do destination keying on the same
1167          * pipe simultaneously.
1168          */
1169         if (INTEL_GEN(dev_priv) >= 9 &&
1170             to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1171             set->flags & I915_SET_COLORKEY_DESTINATION)
1172                 return -EINVAL;
1173
1174         drm_modeset_acquire_init(&ctx, 0);
1175
1176         state = drm_atomic_state_alloc(plane->dev);
1177         if (!state) {
1178                 ret = -ENOMEM;
1179                 goto out;
1180         }
1181         state->acquire_ctx = &ctx;
1182
1183         while (1) {
1184                 plane_state = drm_atomic_get_plane_state(state, plane);
1185                 ret = PTR_ERR_OR_ZERO(plane_state);
1186                 if (!ret)
1187                         intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1188
1189                 /*
1190                  * On some platforms we have to configure
1191                  * the dst colorkey on the primary plane.
1192                  */
1193                 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1194                         struct intel_crtc *crtc =
1195                                 intel_get_crtc_for_pipe(dev_priv,
1196                                                         to_intel_plane(plane)->pipe);
1197
1198                         plane_state = drm_atomic_get_plane_state(state,
1199                                                                  crtc->base.primary);
1200                         ret = PTR_ERR_OR_ZERO(plane_state);
1201                         if (!ret)
1202                                 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1203                 }
1204
1205                 if (!ret)
1206                         ret = drm_atomic_commit(state);
1207
1208                 if (ret != -EDEADLK)
1209                         break;
1210
1211                 drm_atomic_state_clear(state);
1212                 drm_modeset_backoff(&ctx);
1213         }
1214
1215         drm_atomic_state_put(state);
1216 out:
1217         drm_modeset_drop_locks(&ctx);
1218         drm_modeset_acquire_fini(&ctx);
1219         return ret;
1220 }
1221
1222 static const uint32_t g4x_plane_formats[] = {
1223         DRM_FORMAT_XRGB8888,
1224         DRM_FORMAT_YUYV,
1225         DRM_FORMAT_YVYU,
1226         DRM_FORMAT_UYVY,
1227         DRM_FORMAT_VYUY,
1228 };
1229
1230 static const uint64_t i9xx_plane_format_modifiers[] = {
1231         I915_FORMAT_MOD_X_TILED,
1232         DRM_FORMAT_MOD_LINEAR,
1233         DRM_FORMAT_MOD_INVALID
1234 };
1235
1236 static const uint32_t snb_plane_formats[] = {
1237         DRM_FORMAT_XBGR8888,
1238         DRM_FORMAT_XRGB8888,
1239         DRM_FORMAT_YUYV,
1240         DRM_FORMAT_YVYU,
1241         DRM_FORMAT_UYVY,
1242         DRM_FORMAT_VYUY,
1243 };
1244
1245 static const uint32_t vlv_plane_formats[] = {
1246         DRM_FORMAT_RGB565,
1247         DRM_FORMAT_ABGR8888,
1248         DRM_FORMAT_ARGB8888,
1249         DRM_FORMAT_XBGR8888,
1250         DRM_FORMAT_XRGB8888,
1251         DRM_FORMAT_XBGR2101010,
1252         DRM_FORMAT_ABGR2101010,
1253         DRM_FORMAT_YUYV,
1254         DRM_FORMAT_YVYU,
1255         DRM_FORMAT_UYVY,
1256         DRM_FORMAT_VYUY,
1257 };
1258
1259 static uint32_t skl_plane_formats[] = {
1260         DRM_FORMAT_RGB565,
1261         DRM_FORMAT_ABGR8888,
1262         DRM_FORMAT_ARGB8888,
1263         DRM_FORMAT_XBGR8888,
1264         DRM_FORMAT_XRGB8888,
1265         DRM_FORMAT_YUYV,
1266         DRM_FORMAT_YVYU,
1267         DRM_FORMAT_UYVY,
1268         DRM_FORMAT_VYUY,
1269 };
1270
1271 static uint32_t skl_planar_formats[] = {
1272         DRM_FORMAT_RGB565,
1273         DRM_FORMAT_ABGR8888,
1274         DRM_FORMAT_ARGB8888,
1275         DRM_FORMAT_XBGR8888,
1276         DRM_FORMAT_XRGB8888,
1277         DRM_FORMAT_YUYV,
1278         DRM_FORMAT_YVYU,
1279         DRM_FORMAT_UYVY,
1280         DRM_FORMAT_VYUY,
1281         DRM_FORMAT_NV12,
1282 };
1283
1284 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1285         I915_FORMAT_MOD_Yf_TILED,
1286         I915_FORMAT_MOD_Y_TILED,
1287         I915_FORMAT_MOD_X_TILED,
1288         DRM_FORMAT_MOD_LINEAR,
1289         DRM_FORMAT_MOD_INVALID
1290 };
1291
1292 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1293         I915_FORMAT_MOD_Yf_TILED_CCS,
1294         I915_FORMAT_MOD_Y_TILED_CCS,
1295         I915_FORMAT_MOD_Yf_TILED,
1296         I915_FORMAT_MOD_Y_TILED,
1297         I915_FORMAT_MOD_X_TILED,
1298         DRM_FORMAT_MOD_LINEAR,
1299         DRM_FORMAT_MOD_INVALID
1300 };
1301
1302 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1303                                             u32 format, u64 modifier)
1304 {
1305         switch (modifier) {
1306         case DRM_FORMAT_MOD_LINEAR:
1307         case I915_FORMAT_MOD_X_TILED:
1308                 break;
1309         default:
1310                 return false;
1311         }
1312
1313         switch (format) {
1314         case DRM_FORMAT_XRGB8888:
1315         case DRM_FORMAT_YUYV:
1316         case DRM_FORMAT_YVYU:
1317         case DRM_FORMAT_UYVY:
1318         case DRM_FORMAT_VYUY:
1319                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1320                     modifier == I915_FORMAT_MOD_X_TILED)
1321                         return true;
1322                 /* fall through */
1323         default:
1324                 return false;
1325         }
1326 }
1327
1328 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1329                                             u32 format, u64 modifier)
1330 {
1331         switch (modifier) {
1332         case DRM_FORMAT_MOD_LINEAR:
1333         case I915_FORMAT_MOD_X_TILED:
1334                 break;
1335         default:
1336                 return false;
1337         }
1338
1339         switch (format) {
1340         case DRM_FORMAT_XRGB8888:
1341         case DRM_FORMAT_XBGR8888:
1342         case DRM_FORMAT_YUYV:
1343         case DRM_FORMAT_YVYU:
1344         case DRM_FORMAT_UYVY:
1345         case DRM_FORMAT_VYUY:
1346                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1347                     modifier == I915_FORMAT_MOD_X_TILED)
1348                         return true;
1349                 /* fall through */
1350         default:
1351                 return false;
1352         }
1353 }
1354
1355 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1356                                             u32 format, u64 modifier)
1357 {
1358         switch (modifier) {
1359         case DRM_FORMAT_MOD_LINEAR:
1360         case I915_FORMAT_MOD_X_TILED:
1361                 break;
1362         default:
1363                 return false;
1364         }
1365
1366         switch (format) {
1367         case DRM_FORMAT_RGB565:
1368         case DRM_FORMAT_ABGR8888:
1369         case DRM_FORMAT_ARGB8888:
1370         case DRM_FORMAT_XBGR8888:
1371         case DRM_FORMAT_XRGB8888:
1372         case DRM_FORMAT_XBGR2101010:
1373         case DRM_FORMAT_ABGR2101010:
1374         case DRM_FORMAT_YUYV:
1375         case DRM_FORMAT_YVYU:
1376         case DRM_FORMAT_UYVY:
1377         case DRM_FORMAT_VYUY:
1378                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1379                     modifier == I915_FORMAT_MOD_X_TILED)
1380                         return true;
1381                 /* fall through */
1382         default:
1383                 return false;
1384         }
1385 }
1386
1387 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1388                                            u32 format, u64 modifier)
1389 {
1390         struct intel_plane *plane = to_intel_plane(_plane);
1391
1392         switch (modifier) {
1393         case DRM_FORMAT_MOD_LINEAR:
1394         case I915_FORMAT_MOD_X_TILED:
1395         case I915_FORMAT_MOD_Y_TILED:
1396         case I915_FORMAT_MOD_Yf_TILED:
1397                 break;
1398         case I915_FORMAT_MOD_Y_TILED_CCS:
1399         case I915_FORMAT_MOD_Yf_TILED_CCS:
1400                 if (!plane->has_ccs)
1401                         return false;
1402                 break;
1403         default:
1404                 return false;
1405         }
1406
1407         switch (format) {
1408         case DRM_FORMAT_XRGB8888:
1409         case DRM_FORMAT_XBGR8888:
1410         case DRM_FORMAT_ARGB8888:
1411         case DRM_FORMAT_ABGR8888:
1412                 if (is_ccs_modifier(modifier))
1413                         return true;
1414                 /* fall through */
1415         case DRM_FORMAT_RGB565:
1416         case DRM_FORMAT_XRGB2101010:
1417         case DRM_FORMAT_XBGR2101010:
1418         case DRM_FORMAT_YUYV:
1419         case DRM_FORMAT_YVYU:
1420         case DRM_FORMAT_UYVY:
1421         case DRM_FORMAT_VYUY:
1422         case DRM_FORMAT_NV12:
1423                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1424                         return true;
1425                 /* fall through */
1426         case DRM_FORMAT_C8:
1427                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1428                     modifier == I915_FORMAT_MOD_X_TILED ||
1429                     modifier == I915_FORMAT_MOD_Y_TILED)
1430                         return true;
1431                 /* fall through */
1432         default:
1433                 return false;
1434         }
1435 }
1436
1437 static const struct drm_plane_funcs g4x_sprite_funcs = {
1438         .update_plane = drm_atomic_helper_update_plane,
1439         .disable_plane = drm_atomic_helper_disable_plane,
1440         .destroy = intel_plane_destroy,
1441         .atomic_get_property = intel_plane_atomic_get_property,
1442         .atomic_set_property = intel_plane_atomic_set_property,
1443         .atomic_duplicate_state = intel_plane_duplicate_state,
1444         .atomic_destroy_state = intel_plane_destroy_state,
1445         .format_mod_supported = g4x_sprite_format_mod_supported,
1446 };
1447
1448 static const struct drm_plane_funcs snb_sprite_funcs = {
1449         .update_plane = drm_atomic_helper_update_plane,
1450         .disable_plane = drm_atomic_helper_disable_plane,
1451         .destroy = intel_plane_destroy,
1452         .atomic_get_property = intel_plane_atomic_get_property,
1453         .atomic_set_property = intel_plane_atomic_set_property,
1454         .atomic_duplicate_state = intel_plane_duplicate_state,
1455         .atomic_destroy_state = intel_plane_destroy_state,
1456         .format_mod_supported = snb_sprite_format_mod_supported,
1457 };
1458
1459 static const struct drm_plane_funcs vlv_sprite_funcs = {
1460         .update_plane = drm_atomic_helper_update_plane,
1461         .disable_plane = drm_atomic_helper_disable_plane,
1462         .destroy = intel_plane_destroy,
1463         .atomic_get_property = intel_plane_atomic_get_property,
1464         .atomic_set_property = intel_plane_atomic_set_property,
1465         .atomic_duplicate_state = intel_plane_duplicate_state,
1466         .atomic_destroy_state = intel_plane_destroy_state,
1467         .format_mod_supported = vlv_sprite_format_mod_supported,
1468 };
1469
1470 static const struct drm_plane_funcs skl_plane_funcs = {
1471         .update_plane = drm_atomic_helper_update_plane,
1472         .disable_plane = drm_atomic_helper_disable_plane,
1473         .destroy = intel_plane_destroy,
1474         .atomic_get_property = intel_plane_atomic_get_property,
1475         .atomic_set_property = intel_plane_atomic_set_property,
1476         .atomic_duplicate_state = intel_plane_duplicate_state,
1477         .atomic_destroy_state = intel_plane_destroy_state,
1478         .format_mod_supported = skl_plane_format_mod_supported,
1479 };
1480
1481 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1482                        enum pipe pipe, enum plane_id plane_id)
1483 {
1484         if (plane_id == PLANE_CURSOR)
1485                 return false;
1486
1487         if (INTEL_GEN(dev_priv) >= 10)
1488                 return true;
1489
1490         if (IS_GEMINILAKE(dev_priv))
1491                 return pipe != PIPE_C;
1492
1493         return pipe != PIPE_C &&
1494                 (plane_id == PLANE_PRIMARY ||
1495                  plane_id == PLANE_SPRITE0);
1496 }
1497
1498 struct intel_plane *
1499 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1500                           enum pipe pipe, int plane)
1501 {
1502         struct intel_plane *intel_plane = NULL;
1503         struct intel_plane_state *state = NULL;
1504         const struct drm_plane_funcs *plane_funcs;
1505         unsigned long possible_crtcs;
1506         const uint32_t *plane_formats;
1507         const uint64_t *modifiers;
1508         unsigned int supported_rotations;
1509         int num_plane_formats;
1510         int ret;
1511
1512         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1513         if (!intel_plane) {
1514                 ret = -ENOMEM;
1515                 goto fail;
1516         }
1517
1518         state = intel_create_plane_state(&intel_plane->base);
1519         if (!state) {
1520                 ret = -ENOMEM;
1521                 goto fail;
1522         }
1523         intel_plane->base.state = &state->base;
1524
1525         if (INTEL_GEN(dev_priv) >= 9) {
1526                 intel_plane->can_scale = true;
1527                 state->scaler_id = -1;
1528
1529                 intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
1530                                                          PLANE_SPRITE0 + plane);
1531
1532                 intel_plane->update_plane = skl_update_plane;
1533                 intel_plane->disable_plane = skl_disable_plane;
1534                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1535
1536                 if (skl_plane_has_planar(dev_priv, pipe,
1537                                          PLANE_SPRITE0 + plane)) {
1538                         plane_formats = skl_planar_formats;
1539                         num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1540                 } else {
1541                         plane_formats = skl_plane_formats;
1542                         num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1543                 }
1544
1545                 if (intel_plane->has_ccs)
1546                         modifiers = skl_plane_format_modifiers_ccs;
1547                 else
1548                         modifiers = skl_plane_format_modifiers_noccs;
1549
1550                 plane_funcs = &skl_plane_funcs;
1551         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1552                 intel_plane->can_scale = false;
1553                 intel_plane->max_downscale = 1;
1554
1555                 intel_plane->update_plane = vlv_update_plane;
1556                 intel_plane->disable_plane = vlv_disable_plane;
1557                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1558
1559                 plane_formats = vlv_plane_formats;
1560                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1561                 modifiers = i9xx_plane_format_modifiers;
1562
1563                 plane_funcs = &vlv_sprite_funcs;
1564         } else if (INTEL_GEN(dev_priv) >= 7) {
1565                 if (IS_IVYBRIDGE(dev_priv)) {
1566                         intel_plane->can_scale = true;
1567                         intel_plane->max_downscale = 2;
1568                 } else {
1569                         intel_plane->can_scale = false;
1570                         intel_plane->max_downscale = 1;
1571                 }
1572
1573                 intel_plane->update_plane = ivb_update_plane;
1574                 intel_plane->disable_plane = ivb_disable_plane;
1575                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1576
1577                 plane_formats = snb_plane_formats;
1578                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1579                 modifiers = i9xx_plane_format_modifiers;
1580
1581                 plane_funcs = &snb_sprite_funcs;
1582         } else {
1583                 intel_plane->can_scale = true;
1584                 intel_plane->max_downscale = 16;
1585
1586                 intel_plane->update_plane = g4x_update_plane;
1587                 intel_plane->disable_plane = g4x_disable_plane;
1588                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1589
1590                 modifiers = i9xx_plane_format_modifiers;
1591                 if (IS_GEN6(dev_priv)) {
1592                         plane_formats = snb_plane_formats;
1593                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1594
1595                         plane_funcs = &snb_sprite_funcs;
1596                 } else {
1597                         plane_formats = g4x_plane_formats;
1598                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1599
1600                         plane_funcs = &g4x_sprite_funcs;
1601                 }
1602         }
1603
1604         if (INTEL_GEN(dev_priv) >= 9) {
1605                 supported_rotations =
1606                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1607                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1608         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1609                 supported_rotations =
1610                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1611                         DRM_MODE_REFLECT_X;
1612         } else {
1613                 supported_rotations =
1614                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1615         }
1616
1617         intel_plane->pipe = pipe;
1618         intel_plane->i9xx_plane = plane;
1619         intel_plane->id = PLANE_SPRITE0 + plane;
1620         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1621         intel_plane->check_plane = intel_check_sprite_plane;
1622
1623         possible_crtcs = (1 << pipe);
1624
1625         if (INTEL_GEN(dev_priv) >= 9)
1626                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1627                                                possible_crtcs, plane_funcs,
1628                                                plane_formats, num_plane_formats,
1629                                                modifiers,
1630                                                DRM_PLANE_TYPE_OVERLAY,
1631                                                "plane %d%c", plane + 2, pipe_name(pipe));
1632         else
1633                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1634                                                possible_crtcs, plane_funcs,
1635                                                plane_formats, num_plane_formats,
1636                                                modifiers,
1637                                                DRM_PLANE_TYPE_OVERLAY,
1638                                                "sprite %c", sprite_name(pipe, plane));
1639         if (ret)
1640                 goto fail;
1641
1642         drm_plane_create_rotation_property(&intel_plane->base,
1643                                            DRM_MODE_ROTATE_0,
1644                                            supported_rotations);
1645
1646         drm_plane_create_color_properties(&intel_plane->base,
1647                                           BIT(DRM_COLOR_YCBCR_BT601) |
1648                                           BIT(DRM_COLOR_YCBCR_BT709),
1649                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1650                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1651                                           DRM_COLOR_YCBCR_BT709,
1652                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1653
1654         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1655
1656         return intel_plane;
1657
1658 fail:
1659         kfree(state);
1660         kfree(intel_plane);
1661
1662         return ERR_PTR(ret);
1663 }