drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 static bool
  45 format_is_yuv(uint32_t format)
  46 {
  47         switch (format) {
  48         case DRM_FORMAT_YUYV:
  49         case DRM_FORMAT_UYVY:
  50         case DRM_FORMAT_VYUY:
  51         case DRM_FORMAT_YVYU:
  52                 return true;
  53         default:
  54                 return false;
  55         }
  56 }
  57
  58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  59                              int usecs)
  60 {
  61         /* paranoia */
  62         if (!adjusted_mode->crtc_htotal)
  63                 return 1;
  64
  65         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  66                             1000 * adjusted_mode->crtc_htotal);
  67 }
  68
  69 /* FIXME: We should instead only take spinlocks once for the entire update
  70  * instead of once per mmio. */
  71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  72 #define VBLANK_EVASION_TIME_US 250
  73 #else
  74 #define VBLANK_EVASION_TIME_US 100
  75 #endif
  76
  77 /**
  78  * intel_pipe_update_start() - start update of a set of display registers
  79  * @new_crtc_state: the new crtc state
  80  *
  81  * Mark the start of an update to pipe registers that should be updated
  82  * atomically regarding vblank. If the next vblank will happens within
  83  * the next 100 us, this function waits until the vblank passes.
  84  *
  85  * After a successful call to this function, interrupts will be disabled
  86  * until a subsequent call to intel_pipe_update_end(). That is done to
  87  * avoid random delays.
  88  */
  89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  90 {
  91         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  92         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  93         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  94         long timeout = msecs_to_jiffies_timeout(1);
  95         int scanline, min, max, vblank_start;
  96         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  97         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  98                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  99         DEFINE_WAIT(wait);
 100
 101         vblank_start = adjusted_mode->crtc_vblank_start;
 102         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 103                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
 104
 105         /* FIXME needs to be calibrated sensibly */
 106         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 107                                                       VBLANK_EVASION_TIME_US);
 108         max = vblank_start - 1;
 109
 110         local_irq_disable();
 111
 112         if (min <= 0 || max <= 0)
 113                 return;
 114
 115         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 116                 return;
 117
 118         crtc->debug.min_vbl = min;
 119         crtc->debug.max_vbl = max;
 120         trace_i915_pipe_update_start(crtc);
 121
 122         for (;;) {
 123                 /*
 124                  * prepare_to_wait() has a memory barrier, which guarantees
 125                  * other CPUs can see the task state update by the time we
 126                  * read the scanline.
 127                  */
 128                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 129
 130                 scanline = intel_get_crtc_scanline(crtc);
 131                 if (scanline < min || scanline > max)
 132                         break;
 133
 134                 if (timeout <= 0) {
 135                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 136                                   pipe_name(crtc->pipe));
 137                         break;
 138                 }
 139
 140                 local_irq_enable();
 141
 142                 timeout = schedule_timeout(timeout);
 143
 144                 local_irq_disable();
 145         }
 146
 147         finish_wait(wq, &wait);
 148
 149         drm_crtc_vblank_put(&crtc->base);
 150
 151         /*
 152          * On VLV/CHV DSI the scanline counter would appear to
 153          * increment approx. 1/3 of a scanline before start of vblank.
 154          * The registers still get latched at start of vblank however.
 155          * This means we must not write any registers on the first
 156          * line of vblank (since not the whole line is actually in
 157          * vblank). And unfortunately we can't use the interrupt to
 158          * wait here since it will fire too soon. We could use the
 159          * frame start interrupt instead since it will fire after the
 160          * critical scanline, but that would require more changes
 161          * in the interrupt code. So for now we'll just do the nasty
 162          * thing and poll for the bad scanline to pass us by.
 163          *
 164          * FIXME figure out if BXT+ DSI suffers from this as well
 165          */
 166         while (need_vlv_dsi_wa && scanline == vblank_start)
 167                 scanline = intel_get_crtc_scanline(crtc);
 168
 169         crtc->debug.scanline_start = scanline;
 170         crtc->debug.start_vbl_time = ktime_get();
 171         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 172
 173         trace_i915_pipe_update_vblank_evaded(crtc);
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 void
 234 skl_update_plane(struct intel_plane *plane,
 235                  const struct intel_crtc_state *crtc_state,
 236                  const struct intel_plane_state *plane_state)
 237 {
 238         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 239         const struct drm_framebuffer *fb = plane_state->base.fb;
 240         enum plane_id plane_id = plane->id;
 241         enum pipe pipe = plane->pipe;
 242         u32 plane_ctl = plane_state->ctl;
 243         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 244         u32 surf_addr = plane_state->main.offset;
 245         unsigned int rotation = plane_state->base.rotation;
 246         u32 stride = skl_plane_stride(fb, 0, rotation);
 247         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
 248         int crtc_x = plane_state->base.dst.x1;
 249         int crtc_y = plane_state->base.dst.y1;
 250         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 251         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 252         uint32_t x = plane_state->main.x;
 253         uint32_t y = plane_state->main.y;
 254         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 255         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 256         unsigned long irqflags;
 257
 258         /* Sizes are 0 based */
 259         src_w--;
 260         src_h--;
 261         crtc_w--;
 262         crtc_h--;
 263
 264         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 265
 266         if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 267                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 268                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
 269                               PLANE_COLOR_PIPE_CSC_ENABLE |
 270                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
 271         }
 272
 273         if (key->flags) {
 274                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 275                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 276                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 277         }
 278
 279         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 280         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 281         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 282         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 283                       (plane_state->aux.offset - surf_addr) | aux_stride);
 284         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 285                       (plane_state->aux.y << 16) | plane_state->aux.x);
 286
 287         /* program plane scaler */
 288         if (plane_state->scaler_id >= 0) {
 289                 int scaler_id = plane_state->scaler_id;
 290                 const struct intel_scaler *scaler;
 291
 292                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 293
 294                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 295                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 296                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 297                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 298                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 299                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 300
 301                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 302         } else {
 303                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 304         }
 305
 306         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 307         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 308                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 309         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 310
 311         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 312 }
 313
 314 void
 315 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 316 {
 317         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 318         enum plane_id plane_id = plane->id;
 319         enum pipe pipe = plane->pipe;
 320         unsigned long irqflags;
 321
 322         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 323
 324         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 325
 326         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 327         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 328
 329         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 330 }
 331
 332 static void
 333 chv_update_csc(struct intel_plane *plane, uint32_t format)
 334 {
 335         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 336         enum plane_id plane_id = plane->id;
 337
 338         /* Seems RGB data bypasses the CSC always */
 339         if (!format_is_yuv(format))
 340                 return;
 341
 342         /*
 343          * BT.601 limited range YCbCr -> full range RGB
 344          *
 345          * |r|   | 6537 4769     0|   |cr  |
 346          * |g| = |-3330 4769 -1605| x |y-64|
 347          * |b|   |    0 4769  8263|   |cb  |
 348          *
 349          * Cb and Cr apparently come in as signed already, so no
 350          * need for any offset. For Y we need to remove the offset.
 351          */
 352         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 353         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 354         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 355
 356         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 357         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 358         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 359         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 360         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
 361
 362         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 363         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 364         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 365
 366         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 367         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 368         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 369 }
 370
 371 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 372                           const struct intel_plane_state *plane_state)
 373 {
 374         const struct drm_framebuffer *fb = plane_state->base.fb;
 375         unsigned int rotation = plane_state->base.rotation;
 376         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 377         u32 sprctl;
 378
 379         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 380
 381         switch (fb->format->format) {
 382         case DRM_FORMAT_YUYV:
 383                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 384                 break;
 385         case DRM_FORMAT_YVYU:
 386                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 387                 break;
 388         case DRM_FORMAT_UYVY:
 389                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 390                 break;
 391         case DRM_FORMAT_VYUY:
 392                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 393                 break;
 394         case DRM_FORMAT_RGB565:
 395                 sprctl |= SP_FORMAT_BGR565;
 396                 break;
 397         case DRM_FORMAT_XRGB8888:
 398                 sprctl |= SP_FORMAT_BGRX8888;
 399                 break;
 400         case DRM_FORMAT_ARGB8888:
 401                 sprctl |= SP_FORMAT_BGRA8888;
 402                 break;
 403         case DRM_FORMAT_XBGR2101010:
 404                 sprctl |= SP_FORMAT_RGBX1010102;
 405                 break;
 406         case DRM_FORMAT_ABGR2101010:
 407                 sprctl |= SP_FORMAT_RGBA1010102;
 408                 break;
 409         case DRM_FORMAT_XBGR8888:
 410                 sprctl |= SP_FORMAT_RGBX8888;
 411                 break;
 412         case DRM_FORMAT_ABGR8888:
 413                 sprctl |= SP_FORMAT_RGBA8888;
 414                 break;
 415         default:
 416                 MISSING_CASE(fb->format->format);
 417                 return 0;
 418         }
 419
 420         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 421                 sprctl |= SP_TILED;
 422
 423         if (rotation & DRM_MODE_ROTATE_180)
 424                 sprctl |= SP_ROTATE_180;
 425
 426         if (rotation & DRM_MODE_REFLECT_X)
 427                 sprctl |= SP_MIRROR;
 428
 429         if (key->flags & I915_SET_COLORKEY_SOURCE)
 430                 sprctl |= SP_SOURCE_KEY;
 431
 432         return sprctl;
 433 }
 434
 435 static void
 436 vlv_update_plane(struct intel_plane *plane,
 437                  const struct intel_crtc_state *crtc_state,
 438                  const struct intel_plane_state *plane_state)
 439 {
 440         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 441         const struct drm_framebuffer *fb = plane_state->base.fb;
 442         enum pipe pipe = plane->pipe;
 443         enum plane_id plane_id = plane->id;
 444         u32 sprctl = plane_state->ctl;
 445         u32 sprsurf_offset = plane_state->main.offset;
 446         u32 linear_offset;
 447         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 448         int crtc_x = plane_state->base.dst.x1;
 449         int crtc_y = plane_state->base.dst.y1;
 450         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 451         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 452         uint32_t x = plane_state->main.x;
 453         uint32_t y = plane_state->main.y;
 454         unsigned long irqflags;
 455
 456         /* Sizes are 0 based */
 457         crtc_w--;
 458         crtc_h--;
 459
 460         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 461
 462         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 463
 464         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 465                 chv_update_csc(plane, fb->format->format);
 466
 467         if (key->flags) {
 468                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 469                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 470                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 471         }
 472         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 473         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 474
 475         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 476                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 477         else
 478                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 479
 480         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 481
 482         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 483         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 484         I915_WRITE_FW(SPSURF(pipe, plane_id),
 485                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 486         POSTING_READ_FW(SPSURF(pipe, plane_id));
 487
 488         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 489 }
 490
 491 static void
 492 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 493 {
 494         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 495         enum pipe pipe = plane->pipe;
 496         enum plane_id plane_id = plane->id;
 497         unsigned long irqflags;
 498
 499         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 500
 501         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 502
 503         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 504         POSTING_READ_FW(SPSURF(pipe, plane_id));
 505
 506         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 507 }
 508
 509 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 510                           const struct intel_plane_state *plane_state)
 511 {
 512         struct drm_i915_private *dev_priv =
 513                 to_i915(plane_state->base.plane->dev);
 514         const struct drm_framebuffer *fb = plane_state->base.fb;
 515         unsigned int rotation = plane_state->base.rotation;
 516         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 517         u32 sprctl;
 518
 519         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 520
 521         if (IS_IVYBRIDGE(dev_priv))
 522                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 523
 524         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 525                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 526
 527         switch (fb->format->format) {
 528         case DRM_FORMAT_XBGR8888:
 529                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 530                 break;
 531         case DRM_FORMAT_XRGB8888:
 532                 sprctl |= SPRITE_FORMAT_RGBX888;
 533                 break;
 534         case DRM_FORMAT_YUYV:
 535                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 536                 break;
 537         case DRM_FORMAT_YVYU:
 538                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 539                 break;
 540         case DRM_FORMAT_UYVY:
 541                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 542                 break;
 543         case DRM_FORMAT_VYUY:
 544                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 545                 break;
 546         default:
 547                 MISSING_CASE(fb->format->format);
 548                 return 0;
 549         }
 550
 551         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 552                 sprctl |= SPRITE_TILED;
 553
 554         if (rotation & DRM_MODE_ROTATE_180)
 555                 sprctl |= SPRITE_ROTATE_180;
 556
 557         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 558                 sprctl |= SPRITE_DEST_KEY;
 559         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 560                 sprctl |= SPRITE_SOURCE_KEY;
 561
 562         return sprctl;
 563 }
 564
 565 static void
 566 ivb_update_plane(struct intel_plane *plane,
 567                  const struct intel_crtc_state *crtc_state,
 568                  const struct intel_plane_state *plane_state)
 569 {
 570         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 571         const struct drm_framebuffer *fb = plane_state->base.fb;
 572         enum pipe pipe = plane->pipe;
 573         u32 sprctl = plane_state->ctl, sprscale = 0;
 574         u32 sprsurf_offset = plane_state->main.offset;
 575         u32 linear_offset;
 576         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 577         int crtc_x = plane_state->base.dst.x1;
 578         int crtc_y = plane_state->base.dst.y1;
 579         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 580         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 581         uint32_t x = plane_state->main.x;
 582         uint32_t y = plane_state->main.y;
 583         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 584         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 585         unsigned long irqflags;
 586
 587         /* Sizes are 0 based */
 588         src_w--;
 589         src_h--;
 590         crtc_w--;
 591         crtc_h--;
 592
 593         if (crtc_w != src_w || crtc_h != src_h)
 594                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 595
 596         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 597
 598         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 599
 600         if (key->flags) {
 601                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 602                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 603                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 604         }
 605
 606         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 607         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 608
 609         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 610          * register */
 611         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 612                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 613         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 614                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 615         else
 616                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 617
 618         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 619         if (plane->can_scale)
 620                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 621         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 622         I915_WRITE_FW(SPRSURF(pipe),
 623                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 624         POSTING_READ_FW(SPRSURF(pipe));
 625
 626         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 627 }
 628
 629 static void
 630 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 631 {
 632         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 633         enum pipe pipe = plane->pipe;
 634         unsigned long irqflags;
 635
 636         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 637
 638         I915_WRITE_FW(SPRCTL(pipe), 0);
 639         /* Can't leave the scaler enabled... */
 640         if (plane->can_scale)
 641                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 642
 643         I915_WRITE_FW(SPRSURF(pipe), 0);
 644         POSTING_READ_FW(SPRSURF(pipe));
 645
 646         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 647 }
 648
 649 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 650                           const struct intel_plane_state *plane_state)
 651 {
 652         struct drm_i915_private *dev_priv =
 653                 to_i915(plane_state->base.plane->dev);
 654         const struct drm_framebuffer *fb = plane_state->base.fb;
 655         unsigned int rotation = plane_state->base.rotation;
 656         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 657         u32 dvscntr;
 658
 659         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 660
 661         if (IS_GEN6(dev_priv))
 662                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 663
 664         switch (fb->format->format) {
 665         case DRM_FORMAT_XBGR8888:
 666                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 667                 break;
 668         case DRM_FORMAT_XRGB8888:
 669                 dvscntr |= DVS_FORMAT_RGBX888;
 670                 break;
 671         case DRM_FORMAT_YUYV:
 672                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 673                 break;
 674         case DRM_FORMAT_YVYU:
 675                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 676                 break;
 677         case DRM_FORMAT_UYVY:
 678                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 679                 break;
 680         case DRM_FORMAT_VYUY:
 681                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 682                 break;
 683         default:
 684                 MISSING_CASE(fb->format->format);
 685                 return 0;
 686         }
 687
 688         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 689                 dvscntr |= DVS_TILED;
 690
 691         if (rotation & DRM_MODE_ROTATE_180)
 692                 dvscntr |= DVS_ROTATE_180;
 693
 694         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 695                 dvscntr |= DVS_DEST_KEY;
 696         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 697                 dvscntr |= DVS_SOURCE_KEY;
 698
 699         return dvscntr;
 700 }
 701
 702 static void
 703 g4x_update_plane(struct intel_plane *plane,
 704                  const struct intel_crtc_state *crtc_state,
 705                  const struct intel_plane_state *plane_state)
 706 {
 707         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 708         const struct drm_framebuffer *fb = plane_state->base.fb;
 709         enum pipe pipe = plane->pipe;
 710         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 711         u32 dvssurf_offset = plane_state->main.offset;
 712         u32 linear_offset;
 713         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 714         int crtc_x = plane_state->base.dst.x1;
 715         int crtc_y = plane_state->base.dst.y1;
 716         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 717         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 718         uint32_t x = plane_state->main.x;
 719         uint32_t y = plane_state->main.y;
 720         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 721         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 722         unsigned long irqflags;
 723
 724         /* Sizes are 0 based */
 725         src_w--;
 726         src_h--;
 727         crtc_w--;
 728         crtc_h--;
 729
 730         if (crtc_w != src_w || crtc_h != src_h)
 731                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 732
 733         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 734
 735         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 736
 737         if (key->flags) {
 738                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 739                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 740                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 741         }
 742
 743         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 744         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 745
 746         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 747                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 748         else
 749                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 750
 751         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 752         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 753         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 754         I915_WRITE_FW(DVSSURF(pipe),
 755                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 756         POSTING_READ_FW(DVSSURF(pipe));
 757
 758         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 759 }
 760
 761 static void
 762 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 763 {
 764         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 765         enum pipe pipe = plane->pipe;
 766         unsigned long irqflags;
 767
 768         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 769
 770         I915_WRITE_FW(DVSCNTR(pipe), 0);
 771         /* Disable the scaler */
 772         I915_WRITE_FW(DVSSCALE(pipe), 0);
 773
 774         I915_WRITE_FW(DVSSURF(pipe), 0);
 775         POSTING_READ_FW(DVSSURF(pipe));
 776
 777         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 778 }
 779
 780 static int
 781 intel_check_sprite_plane(struct intel_plane *plane,
 782                          struct intel_crtc_state *crtc_state,
 783                          struct intel_plane_state *state)
 784 {
 785         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 786         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 787         struct drm_framebuffer *fb = state->base.fb;
 788         int crtc_x, crtc_y;
 789         unsigned int crtc_w, crtc_h;
 790         uint32_t src_x, src_y, src_w, src_h;
 791         struct drm_rect *src = &state->base.src;
 792         struct drm_rect *dst = &state->base.dst;
 793         const struct drm_rect *clip = &state->clip;
 794         int hscale, vscale;
 795         int max_scale, min_scale;
 796         bool can_scale;
 797         int ret;
 798
 799         *src = drm_plane_state_src(&state->base);
 800         *dst = drm_plane_state_dest(&state->base);
 801
 802         if (!fb) {
 803                 state->base.visible = false;
 804                 return 0;
 805         }
 806
 807         /* Don't modify another pipe's plane */
 808         if (plane->pipe != crtc->pipe) {
 809                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 810                 return -EINVAL;
 811         }
 812
 813         /* FIXME check all gen limits */
 814         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 815                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 816                 return -EINVAL;
 817         }
 818
 819         /* setup can_scale, min_scale, max_scale */
 820         if (INTEL_GEN(dev_priv) >= 9) {
 821                 /* use scaler when colorkey is not required */
 822                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 823                         can_scale = 1;
 824                         min_scale = 1;
 825                         max_scale = skl_max_scale(crtc, crtc_state);
 826                 } else {
 827                         can_scale = 0;
 828                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 829                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 830                 }
 831         } else {
 832                 can_scale = plane->can_scale;
 833                 max_scale = plane->max_downscale << 16;
 834                 min_scale = plane->can_scale ? 1 : (1 << 16);
 835         }
 836
 837         /*
 838          * FIXME the following code does a bunch of fuzzy adjustments to the
 839          * coordinates and sizes. We probably need some way to decide whether
 840          * more strict checking should be done instead.
 841          */
 842         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 843                         state->base.rotation);
 844
 845         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 846         BUG_ON(hscale < 0);
 847
 848         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 849         BUG_ON(vscale < 0);
 850
 851         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 852
 853         crtc_x = dst->x1;
 854         crtc_y = dst->y1;
 855         crtc_w = drm_rect_width(dst);
 856         crtc_h = drm_rect_height(dst);
 857
 858         if (state->base.visible) {
 859                 /* check again in case clipping clamped the results */
 860                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 861                 if (hscale < 0) {
 862                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 863                         drm_rect_debug_print("src: ", src, true);
 864                         drm_rect_debug_print("dst: ", dst, false);
 865
 866                         return hscale;
 867                 }
 868
 869                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 870                 if (vscale < 0) {
 871                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 872                         drm_rect_debug_print("src: ", src, true);
 873                         drm_rect_debug_print("dst: ", dst, false);
 874
 875                         return vscale;
 876                 }
 877
 878                 /* Make the source viewport size an exact multiple of the scaling factors. */
 879                 drm_rect_adjust_size(src,
 880                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 881                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 882
 883                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 884                                     state->base.rotation);
 885
 886                 /* sanity check to make sure the src viewport wasn't enlarged */
 887                 WARN_ON(src->x1 < (int) state->base.src_x ||
 888                         src->y1 < (int) state->base.src_y ||
 889                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 890                         src->y2 > (int) state->base.src_y + state->base.src_h);
 891
 892                 /*
 893                  * Hardware doesn't handle subpixel coordinates.
 894                  * Adjust to (macro)pixel boundary, but be careful not to
 895                  * increase the source viewport size, because that could
 896                  * push the downscaling factor out of bounds.
 897                  */
 898                 src_x = src->x1 >> 16;
 899                 src_w = drm_rect_width(src) >> 16;
 900                 src_y = src->y1 >> 16;
 901                 src_h = drm_rect_height(src) >> 16;
 902
 903                 if (format_is_yuv(fb->format->format)) {
 904                         src_x &= ~1;
 905                         src_w &= ~1;
 906
 907                         /*
 908                          * Must keep src and dst the
 909                          * same if we can't scale.
 910                          */
 911                         if (!can_scale)
 912                                 crtc_w &= ~1;
 913
 914                         if (crtc_w == 0)
 915                                 state->base.visible = false;
 916                 }
 917         }
 918
 919         /* Check size restrictions when scaling */
 920         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 921                 unsigned int width_bytes;
 922                 int cpp = fb->format->cpp[0];
 923
 924                 WARN_ON(!can_scale);
 925
 926                 /* FIXME interlacing min height is 6 */
 927
 928                 if (crtc_w < 3 || crtc_h < 3)
 929                         state->base.visible = false;
 930
 931                 if (src_w < 3 || src_h < 3)
 932                         state->base.visible = false;
 933
 934                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 935
 936                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
 937                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 938                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 939                         return -EINVAL;
 940                 }
 941         }
 942
 943         if (state->base.visible) {
 944                 src->x1 = src_x << 16;
 945                 src->x2 = (src_x + src_w) << 16;
 946                 src->y1 = src_y << 16;
 947                 src->y2 = (src_y + src_h) << 16;
 948         }
 949
 950         dst->x1 = crtc_x;
 951         dst->x2 = crtc_x + crtc_w;
 952         dst->y1 = crtc_y;
 953         dst->y2 = crtc_y + crtc_h;
 954
 955         if (INTEL_GEN(dev_priv) >= 9) {
 956                 ret = skl_check_plane_surface(state);
 957                 if (ret)
 958                         return ret;
 959
 960                 state->ctl = skl_plane_ctl(crtc_state, state);
 961         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 962                 ret = i9xx_check_plane_surface(state);
 963                 if (ret)
 964                         return ret;
 965
 966                 state->ctl = vlv_sprite_ctl(crtc_state, state);
 967         } else if (INTEL_GEN(dev_priv) >= 7) {
 968                 ret = i9xx_check_plane_surface(state);
 969                 if (ret)
 970                         return ret;
 971
 972                 state->ctl = ivb_sprite_ctl(crtc_state, state);
 973         } else {
 974                 ret = i9xx_check_plane_surface(state);
 975                 if (ret)
 976                         return ret;
 977
 978                 state->ctl = g4x_sprite_ctl(crtc_state, state);
 979         }
 980
 981         return 0;
 982 }
 983
 984 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 985                               struct drm_file *file_priv)
 986 {
 987         struct drm_i915_private *dev_priv = to_i915(dev);
 988         struct drm_intel_sprite_colorkey *set = data;
 989         struct drm_plane *plane;
 990         struct drm_plane_state *plane_state;
 991         struct drm_atomic_state *state;
 992         struct drm_modeset_acquire_ctx ctx;
 993         int ret = 0;
 994
 995         /* Make sure we don't try to enable both src & dest simultaneously */
 996         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 997                 return -EINVAL;
 998
 999         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1000             set->flags & I915_SET_COLORKEY_DESTINATION)
1001                 return -EINVAL;
1002
1003         plane = drm_plane_find(dev, file_priv, set->plane_id);
1004         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1005                 return -ENOENT;
1006
1007         drm_modeset_acquire_init(&ctx, 0);
1008
1009         state = drm_atomic_state_alloc(plane->dev);
1010         if (!state) {
1011                 ret = -ENOMEM;
1012                 goto out;
1013         }
1014         state->acquire_ctx = &ctx;
1015
1016         while (1) {
1017                 plane_state = drm_atomic_get_plane_state(state, plane);
1018                 ret = PTR_ERR_OR_ZERO(plane_state);
1019                 if (!ret) {
1020                         to_intel_plane_state(plane_state)->ckey = *set;
1021                         ret = drm_atomic_commit(state);
1022                 }
1023
1024                 if (ret != -EDEADLK)
1025                         break;
1026
1027                 drm_atomic_state_clear(state);
1028                 drm_modeset_backoff(&ctx);
1029         }
1030
1031         drm_atomic_state_put(state);
1032 out:
1033         drm_modeset_drop_locks(&ctx);
1034         drm_modeset_acquire_fini(&ctx);
1035         return ret;
1036 }
1037
1038 static const uint32_t g4x_plane_formats[] = {
1039         DRM_FORMAT_XRGB8888,
1040         DRM_FORMAT_YUYV,
1041         DRM_FORMAT_YVYU,
1042         DRM_FORMAT_UYVY,
1043         DRM_FORMAT_VYUY,
1044 };
1045
1046 static const uint64_t i9xx_plane_format_modifiers[] = {
1047         I915_FORMAT_MOD_X_TILED,
1048         DRM_FORMAT_MOD_LINEAR,
1049         DRM_FORMAT_MOD_INVALID
1050 };
1051
1052 static const uint32_t snb_plane_formats[] = {
1053         DRM_FORMAT_XBGR8888,
1054         DRM_FORMAT_XRGB8888,
1055         DRM_FORMAT_YUYV,
1056         DRM_FORMAT_YVYU,
1057         DRM_FORMAT_UYVY,
1058         DRM_FORMAT_VYUY,
1059 };
1060
1061 static const uint32_t vlv_plane_formats[] = {
1062         DRM_FORMAT_RGB565,
1063         DRM_FORMAT_ABGR8888,
1064         DRM_FORMAT_ARGB8888,
1065         DRM_FORMAT_XBGR8888,
1066         DRM_FORMAT_XRGB8888,
1067         DRM_FORMAT_XBGR2101010,
1068         DRM_FORMAT_ABGR2101010,
1069         DRM_FORMAT_YUYV,
1070         DRM_FORMAT_YVYU,
1071         DRM_FORMAT_UYVY,
1072         DRM_FORMAT_VYUY,
1073 };
1074
1075 static uint32_t skl_plane_formats[] = {
1076         DRM_FORMAT_RGB565,
1077         DRM_FORMAT_ABGR8888,
1078         DRM_FORMAT_ARGB8888,
1079         DRM_FORMAT_XBGR8888,
1080         DRM_FORMAT_XRGB8888,
1081         DRM_FORMAT_YUYV,
1082         DRM_FORMAT_YVYU,
1083         DRM_FORMAT_UYVY,
1084         DRM_FORMAT_VYUY,
1085 };
1086
1087 static const uint64_t skl_plane_format_modifiers[] = {
1088         I915_FORMAT_MOD_X_TILED,
1089         DRM_FORMAT_MOD_LINEAR,
1090         DRM_FORMAT_MOD_INVALID
1091 };
1092
1093 static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane,
1094                                                   uint32_t format,
1095                                                   uint64_t modifier)
1096 {
1097         switch (format) {
1098         case DRM_FORMAT_XBGR8888:
1099         case DRM_FORMAT_XRGB8888:
1100         case DRM_FORMAT_YUYV:
1101         case DRM_FORMAT_YVYU:
1102         case DRM_FORMAT_UYVY:
1103         case DRM_FORMAT_VYUY:
1104                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1105                     modifier == I915_FORMAT_MOD_X_TILED)
1106                         return true;
1107                 /* fall through */
1108         default:
1109                 return false;
1110         }
1111 }
1112
1113 static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane,
1114                                                   uint32_t format,
1115                                                   uint64_t modifier)
1116 {
1117         switch (format) {
1118         case DRM_FORMAT_YUYV:
1119         case DRM_FORMAT_YVYU:
1120         case DRM_FORMAT_UYVY:
1121         case DRM_FORMAT_VYUY:
1122         case DRM_FORMAT_RGB565:
1123         case DRM_FORMAT_XRGB8888:
1124         case DRM_FORMAT_ARGB8888:
1125         case DRM_FORMAT_XBGR2101010:
1126         case DRM_FORMAT_ABGR2101010:
1127         case DRM_FORMAT_XBGR8888:
1128         case DRM_FORMAT_ABGR8888:
1129                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1130                     modifier == I915_FORMAT_MOD_X_TILED)
1131                         return true;
1132                 /* fall through */
1133         default:
1134                 return false;
1135         }
1136 }
1137
1138 static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane,
1139                                                   uint32_t format,
1140                                                   uint64_t modifier)
1141 {
1142         /* This is the same as primary plane since SKL has universal planes */
1143         switch (format) {
1144         case DRM_FORMAT_XRGB8888:
1145         case DRM_FORMAT_XBGR8888:
1146         case DRM_FORMAT_ARGB8888:
1147         case DRM_FORMAT_ABGR8888:
1148         case DRM_FORMAT_RGB565:
1149         case DRM_FORMAT_XRGB2101010:
1150         case DRM_FORMAT_XBGR2101010:
1151         case DRM_FORMAT_YUYV:
1152         case DRM_FORMAT_YVYU:
1153         case DRM_FORMAT_UYVY:
1154         case DRM_FORMAT_VYUY:
1155                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1156                         return true;
1157                 /* fall through */
1158         case DRM_FORMAT_C8:
1159                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1160                     modifier == I915_FORMAT_MOD_X_TILED ||
1161                     modifier == I915_FORMAT_MOD_Y_TILED)
1162                         return true;
1163                 /* fall through */
1164         default:
1165                 return false;
1166         }
1167 }
1168
1169 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1170                                                     uint32_t format,
1171                                                     uint64_t modifier)
1172 {
1173         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1174
1175         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1176                 return false;
1177
1178         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1179             modifier != DRM_FORMAT_MOD_LINEAR)
1180                 return false;
1181
1182         if (INTEL_GEN(dev_priv) >= 9)
1183                 return skl_sprite_plane_format_mod_supported(plane, format, modifier);
1184         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1185                 return vlv_sprite_plane_format_mod_supported(plane, format, modifier);
1186         else
1187                 return g4x_sprite_plane_format_mod_supported(plane, format, modifier);
1188
1189         unreachable();
1190 }
1191
1192 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1193         .update_plane = drm_atomic_helper_update_plane,
1194         .disable_plane = drm_atomic_helper_disable_plane,
1195         .destroy = intel_plane_destroy,
1196         .atomic_get_property = intel_plane_atomic_get_property,
1197         .atomic_set_property = intel_plane_atomic_set_property,
1198         .atomic_duplicate_state = intel_plane_duplicate_state,
1199         .atomic_destroy_state = intel_plane_destroy_state,
1200         .format_mod_supported = intel_sprite_plane_format_mod_supported,
1201 };
1202
1203 struct intel_plane *
1204 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1205                           enum pipe pipe, int plane)
1206 {
1207         struct intel_plane *intel_plane = NULL;
1208         struct intel_plane_state *state = NULL;
1209         unsigned long possible_crtcs;
1210         const uint32_t *plane_formats;
1211         const uint64_t *modifiers;
1212         unsigned int supported_rotations;
1213         int num_plane_formats;
1214         int ret;
1215
1216         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1217         if (!intel_plane) {
1218                 ret = -ENOMEM;
1219                 goto fail;
1220         }
1221
1222         state = intel_create_plane_state(&intel_plane->base);
1223         if (!state) {
1224                 ret = -ENOMEM;
1225                 goto fail;
1226         }
1227         intel_plane->base.state = &state->base;
1228
1229         if (INTEL_GEN(dev_priv) >= 10) {
1230                 intel_plane->can_scale = true;
1231                 state->scaler_id = -1;
1232
1233                 intel_plane->update_plane = skl_update_plane;
1234                 intel_plane->disable_plane = skl_disable_plane;
1235
1236                 plane_formats = skl_plane_formats;
1237                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1238                 modifiers = skl_plane_format_modifiers;
1239         } else if (INTEL_GEN(dev_priv) >= 9) {
1240                 intel_plane->can_scale = true;
1241                 state->scaler_id = -1;
1242
1243                 intel_plane->update_plane = skl_update_plane;
1244                 intel_plane->disable_plane = skl_disable_plane;
1245
1246                 plane_formats = skl_plane_formats;
1247                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1248                 modifiers = skl_plane_format_modifiers;
1249         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1250                 intel_plane->can_scale = false;
1251                 intel_plane->max_downscale = 1;
1252
1253                 intel_plane->update_plane = vlv_update_plane;
1254                 intel_plane->disable_plane = vlv_disable_plane;
1255
1256                 plane_formats = vlv_plane_formats;
1257                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1258                 modifiers = i9xx_plane_format_modifiers;
1259         } else if (INTEL_GEN(dev_priv) >= 7) {
1260                 if (IS_IVYBRIDGE(dev_priv)) {
1261                         intel_plane->can_scale = true;
1262                         intel_plane->max_downscale = 2;
1263                 } else {
1264                         intel_plane->can_scale = false;
1265                         intel_plane->max_downscale = 1;
1266                 }
1267
1268                 intel_plane->update_plane = ivb_update_plane;
1269                 intel_plane->disable_plane = ivb_disable_plane;
1270
1271                 plane_formats = snb_plane_formats;
1272                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1273                 modifiers = i9xx_plane_format_modifiers;
1274         } else {
1275                 intel_plane->can_scale = true;
1276                 intel_plane->max_downscale = 16;
1277
1278                 intel_plane->update_plane = g4x_update_plane;
1279                 intel_plane->disable_plane = g4x_disable_plane;
1280
1281                 modifiers = i9xx_plane_format_modifiers;
1282                 if (IS_GEN6(dev_priv)) {
1283                         plane_formats = snb_plane_formats;
1284                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1285                 } else {
1286                         plane_formats = g4x_plane_formats;
1287                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1288                 }
1289         }
1290
1291         if (INTEL_GEN(dev_priv) >= 9) {
1292                 supported_rotations =
1293                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1294                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1295         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1296                 supported_rotations =
1297                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1298                         DRM_MODE_REFLECT_X;
1299         } else {
1300                 supported_rotations =
1301                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1302         }
1303
1304         intel_plane->pipe = pipe;
1305         intel_plane->plane = plane;
1306         intel_plane->id = PLANE_SPRITE0 + plane;
1307         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1308         intel_plane->check_plane = intel_check_sprite_plane;
1309
1310         possible_crtcs = (1 << pipe);
1311
1312         if (INTEL_GEN(dev_priv) >= 9)
1313                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1314                                                possible_crtcs, &intel_sprite_plane_funcs,
1315                                                plane_formats, num_plane_formats,
1316                                                modifiers,
1317                                                DRM_PLANE_TYPE_OVERLAY,
1318                                                "plane %d%c", plane + 2, pipe_name(pipe));
1319         else
1320                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1321                                                possible_crtcs, &intel_sprite_plane_funcs,
1322                                                plane_formats, num_plane_formats,
1323                                                modifiers,
1324                                                DRM_PLANE_TYPE_OVERLAY,
1325                                                "sprite %c", sprite_name(pipe, plane));
1326         if (ret)
1327                 goto fail;
1328
1329         drm_plane_create_rotation_property(&intel_plane->base,
1330                                            DRM_MODE_ROTATE_0,
1331                                            supported_rotations);
1332
1333         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1334
1335         return intel_plane;
1336
1337 fail:
1338         kfree(state);
1339         kfree(intel_plane);
1340
1341         return ERR_PTR(ret);
1342 }