1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _INTEL_RINGBUFFER_H_
3 #define _INTEL_RINGBUFFER_H_
5 #include <linux/hashtable.h>
6 #include <linux/seqlock.h>
8 #include "i915_gem_batch_pool.h"
12 #include "i915_request.h"
13 #include "i915_selftest.h"
14 #include "i915_timeline.h"
15 #include "intel_gpu_commands.h"
18 struct i915_sched_attr;
20 #define I915_CMD_HASH_ORDER 9
22 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
23 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
24 * to give some inclination as to some of the magic values used in the various
27 #define CACHELINE_BYTES 64
28 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
30 struct intel_hw_status_page {
36 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
37 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
39 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
40 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
42 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
43 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
45 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
46 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
48 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
49 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
51 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
52 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
54 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
55 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
57 enum intel_engine_hangcheck_action {
62 ENGINE_ACTIVE_SUBUNITS,
67 static inline const char *
68 hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
75 case ENGINE_ACTIVE_SEQNO:
76 return "active seqno";
77 case ENGINE_ACTIVE_HEAD:
79 case ENGINE_ACTIVE_SUBUNITS:
80 return "active subunits";
81 case ENGINE_WAIT_KICK:
90 #define I915_MAX_SLICES 3
91 #define I915_MAX_SUBSLICES 8
93 #define instdone_slice_mask(dev_priv__) \
94 (INTEL_GEN(dev_priv__) == 7 ? \
95 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
97 #define instdone_subslice_mask(dev_priv__) \
98 (INTEL_GEN(dev_priv__) == 7 ? \
99 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
101 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
102 for ((slice__) = 0, (subslice__) = 0; \
103 (slice__) < I915_MAX_SLICES; \
104 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
105 (slice__) += ((subslice__) == 0)) \
106 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
107 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
109 struct intel_instdone {
111 /* The following exist only in the RCS engine */
113 u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
114 u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
117 struct intel_engine_hangcheck {
120 enum intel_engine_hangcheck_action action;
121 unsigned long action_timestamp;
123 struct intel_instdone instdone;
124 struct i915_request *active_request;
130 struct i915_vma *vma;
133 struct i915_timeline *timeline;
134 struct list_head request_list;
135 struct list_head active_link;
146 struct i915_gem_context;
147 struct drm_i915_reg_table;
150 * we use a single page to load ctx workarounds so all of these
151 * values are referred in terms of dwords
153 * struct i915_wa_ctx_bb:
154 * offset: specifies batch starting position, also helpful in case
155 * if we want to have multiple batches at different offsets based on
156 * some criteria. It is not a requirement at the moment but provides
157 * an option for future use.
158 * size: size of the batch in DWORDS
160 struct i915_ctx_workarounds {
161 struct i915_wa_ctx_bb {
164 } indirect_ctx, per_ctx;
165 struct i915_vma *vma;
170 #define I915_MAX_VCS 4
171 #define I915_MAX_VECS 2
174 * Engine IDs definitions.
175 * Keep instances of the same type engine together.
177 enum intel_engine_id {
184 #define _VCS(n) (VCS + (n))
187 #define _VECS(n) (VECS + (n))
190 struct i915_priolist {
192 struct list_head requests;
196 struct st_preempt_hang {
197 struct completion completion;
202 * struct intel_engine_execlists - execlist submission queue and port state
204 * The struct intel_engine_execlists represents the combined logical state of
205 * driver and the hardware state for execlist mode of submission.
207 struct intel_engine_execlists {
209 * @tasklet: softirq tasklet for bottom handler
211 struct tasklet_struct tasklet;
214 * @default_priolist: priority list for I915_PRIORITY_NORMAL
216 struct i915_priolist default_priolist;
219 * @no_priolist: priority lists disabled
224 * @submit_reg: gen-specific execlist submission register
225 * set to the ExecList Submission Port (elsp) register pre-Gen11 and to
226 * the ExecList Submission Queue Contents register array for Gen11+
228 u32 __iomem *submit_reg;
231 * @ctrl_reg: the enhanced execlists control register, used to load the
232 * submit queue on the HW and to request preemptions to idle
234 u32 __iomem *ctrl_reg;
237 * @port: execlist port states
239 * For each hardware ELSP (ExecList Submission Port) we keep
240 * track of the last request and the number of times we submitted
241 * that port to hw. We then count the number of times the hw reports
242 * a context completion or preemption. As only one context can
243 * be active on hw, we limit resubmission of context to port[0]. This
244 * is called Lite Restore, of the context.
246 struct execlist_port {
248 * @request_count: combined request and submission count
250 struct i915_request *request_count;
251 #define EXECLIST_COUNT_BITS 2
252 #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
253 #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
254 #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
255 #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
256 #define port_set(p, packed) ((p)->request_count = (packed))
257 #define port_isset(p) ((p)->request_count)
258 #define port_index(p, execlists) ((p) - (execlists)->port)
261 * @context_id: context ID for port
263 GEM_DEBUG_DECL(u32 context_id);
265 #define EXECLIST_MAX_PORTS 2
266 } port[EXECLIST_MAX_PORTS];
269 * @active: is the HW active? We consider the HW as active after
270 * submitting any context for execution and until we have seen the
271 * last context completion event. After that, we do not expect any
272 * more events until we submit, and so can park the HW.
274 * As we have a small number of different sources from which we feed
275 * the HW, we track the state of each inside a single bitfield.
278 #define EXECLISTS_ACTIVE_USER 0
279 #define EXECLISTS_ACTIVE_PREEMPT 1
280 #define EXECLISTS_ACTIVE_HWACK 2
283 * @port_mask: number of execlist ports - 1
285 unsigned int port_mask;
288 * @queue_priority: Highest pending priority.
290 * When we add requests into the queue, or adjust the priority of
291 * executing requests, we compute the maximum priority of those
292 * pending requests. We can then use this value to determine if
293 * we need to preempt the executing requests to service the queue.
298 * @queue: queue of requests, in priority lists
300 struct rb_root_cached queue;
303 * @csb_read: control register for Context Switch buffer
305 * Note this register is always in mmio.
307 u32 __iomem *csb_read;
310 * @csb_write: control register for Context Switch buffer
312 * Note this register may be either mmio or HWSP shadow.
317 * @csb_status: status array for Context Switch buffer
319 * Note these register may be either mmio or HWSP shadow.
324 * @preempt_complete_status: expected CSB upon completing preemption
326 u32 preempt_complete_status;
329 * @csb_write_reset: reset value for CSB write pointer
331 * As the CSB write pointer maybe either in HWSP or as a field
332 * inside an mmio register, we want to reprogram it slightly
333 * differently to avoid later confusion.
338 * @csb_head: context status buffer head
342 I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
345 #define INTEL_ENGINE_CS_MAX_NAME 8
347 struct intel_engine_cs {
348 struct drm_i915_private *i915;
349 char name[INTEL_ENGINE_CS_MAX_NAME];
351 enum intel_engine_id id;
363 struct intel_ring *buffer;
365 struct i915_timeline timeline;
367 struct drm_i915_gem_object *default_state;
368 void *pinned_default_state;
370 unsigned long irq_posted;
371 #define ENGINE_IRQ_BREADCRUMB 0
373 /* Rather than have every client wait upon all user interrupts,
374 * with the herd waking after every interrupt and each doing the
375 * heavyweight seqno dance, we delegate the task (of being the
376 * bottom-half of the user interrupt) to the first client. After
377 * every interrupt, we wake up one client, who does the heavyweight
378 * coherent seqno read and either goes back to sleep (if incomplete),
379 * or wakes up all the completed clients in parallel, before then
380 * transferring the bottom-half status to the next client in the queue.
382 * Compared to walking the entire list of waiters in a single dedicated
383 * bottom-half, we reduce the latency of the first waiter by avoiding
384 * a context switch, but incur additional coherent seqno reads when
385 * following the chain of request breadcrumbs. Since it is most likely
386 * that we have a single client waiting on each seqno, then reducing
387 * the overhead of waking that client is much preferred.
389 struct intel_breadcrumbs {
390 spinlock_t irq_lock; /* protects irq_*; irqsafe */
391 struct intel_wait *irq_wait; /* oldest waiter by retirement */
393 spinlock_t rb_lock; /* protects the rb and wraps irq_lock */
394 struct rb_root waiters; /* sorted by retirement, priority */
395 struct list_head signals; /* sorted by retirement */
396 struct task_struct *signaler; /* used for fence signalling */
398 struct timer_list fake_irq; /* used after a missed interrupt */
399 struct timer_list hangcheck; /* detect missed interrupts */
401 unsigned int hangcheck_interrupts;
402 unsigned int irq_enabled;
403 unsigned int irq_count;
406 I915_SELFTEST_DECLARE(bool mock : 1);
411 * @enable: Bitmask of enable sample events on this engine.
413 * Bits correspond to sample event types, for instance
414 * I915_SAMPLE_QUEUED is bit 0 etc.
418 * @enable_count: Reference count for the enabled samplers.
420 * Index number corresponds to the bit number from @enable.
422 unsigned int enable_count[I915_PMU_SAMPLE_BITS];
424 * @sample: Counter values for sampling events.
426 * Our internal timer stores the current counters in this field.
428 #define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1)
429 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
433 * A pool of objects to use as shadow copies of client batch buffers
434 * when the command parser is enabled. Prevents the client from
435 * modifying the batch contents after software parsing.
437 struct i915_gem_batch_pool batch_pool;
439 struct intel_hw_status_page status_page;
440 struct i915_ctx_workarounds wa_ctx;
441 struct i915_vma *scratch;
443 u32 irq_keep_mask; /* always keep these interrupts */
444 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
445 void (*irq_enable)(struct intel_engine_cs *engine);
446 void (*irq_disable)(struct intel_engine_cs *engine);
448 int (*init_hw)(struct intel_engine_cs *engine);
451 struct i915_request *(*prepare)(struct intel_engine_cs *engine);
452 void (*reset)(struct intel_engine_cs *engine,
453 struct i915_request *rq);
454 void (*finish)(struct intel_engine_cs *engine);
457 void (*park)(struct intel_engine_cs *engine);
458 void (*unpark)(struct intel_engine_cs *engine);
460 void (*set_default_submission)(struct intel_engine_cs *engine);
462 struct intel_context *(*context_pin)(struct intel_engine_cs *engine,
463 struct i915_gem_context *ctx);
465 int (*request_alloc)(struct i915_request *rq);
466 int (*init_context)(struct i915_request *rq);
468 int (*emit_flush)(struct i915_request *request, u32 mode);
469 #define EMIT_INVALIDATE BIT(0)
470 #define EMIT_FLUSH BIT(1)
471 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
472 int (*emit_bb_start)(struct i915_request *rq,
473 u64 offset, u32 length,
474 unsigned int dispatch_flags);
475 #define I915_DISPATCH_SECURE BIT(0)
476 #define I915_DISPATCH_PINNED BIT(1)
477 void (*emit_breadcrumb)(struct i915_request *rq, u32 *cs);
478 int emit_breadcrumb_sz;
480 /* Pass the request to the hardware queue (e.g. directly into
481 * the legacy ringbuffer or to the end of an execlist).
483 * This is called from an atomic context with irqs disabled; must
486 void (*submit_request)(struct i915_request *rq);
488 /* Call when the priority on a request has changed and it and its
489 * dependencies may need rescheduling. Note the request itself may
490 * not be ready to run!
492 * Called under the struct_mutex.
494 void (*schedule)(struct i915_request *request,
495 const struct i915_sched_attr *attr);
498 * Cancel all requests on the hardware, or queued for execution.
499 * This should only cancel the ready requests that have been
500 * submitted to the engine (via the engine->submit_request callback).
501 * This is called when marking the device as wedged.
503 void (*cancel_requests)(struct intel_engine_cs *engine);
505 /* Some chipsets are not quite as coherent as advertised and need
506 * an expensive kick to force a true read of the up-to-date seqno.
507 * However, the up-to-date seqno is not always required and the last
508 * seen value is good enough. Note that the seqno will always be
509 * monotonic, even if not coherent.
511 void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
512 void (*cleanup)(struct intel_engine_cs *engine);
514 /* GEN8 signal/wait table - never trust comments!
515 * signal to signal to signal to signal to signal to
516 * RCS VCS BCS VECS VCS2
517 * --------------------------------------------------------------------
518 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
519 * |-------------------------------------------------------------------
520 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
521 * |-------------------------------------------------------------------
522 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
523 * |-------------------------------------------------------------------
524 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
525 * |-------------------------------------------------------------------
526 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
527 * |-------------------------------------------------------------------
530 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
531 * ie. transpose of g(x, y)
533 * sync from sync from sync from sync from sync from
534 * RCS VCS BCS VECS VCS2
535 * --------------------------------------------------------------------
536 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
537 * |-------------------------------------------------------------------
538 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
539 * |-------------------------------------------------------------------
540 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
541 * |-------------------------------------------------------------------
542 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
543 * |-------------------------------------------------------------------
544 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
545 * |-------------------------------------------------------------------
548 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
549 * ie. transpose of f(x, y)
552 #define GEN6_SEMAPHORE_LAST VECS_HW
553 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
554 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
556 /* our mbox written by others */
557 u32 wait[GEN6_NUM_SEMAPHORES];
558 /* mboxes this ring signals to */
559 i915_reg_t signal[GEN6_NUM_SEMAPHORES];
563 int (*sync_to)(struct i915_request *rq,
564 struct i915_request *signal);
565 u32 *(*signal)(struct i915_request *rq, u32 *cs);
568 struct intel_engine_execlists execlists;
570 /* Contexts are pinned whilst they are active on the GPU. The last
571 * context executed remains active whilst the GPU is idle - the
572 * switch away and write to the context object only occurs on the
573 * next execution. Contexts are only unpinned on retirement of the
574 * following request ensuring that we can always write to the object
575 * on the context switch even after idling. Across suspend, we switch
576 * to the kernel context and trash it as the save may not happen
577 * before the hardware is powered down.
579 struct intel_context *last_retired_context;
581 /* status_notifier: list of callbacks for context-switch changes */
582 struct atomic_notifier_head context_status_notifier;
584 struct intel_engine_hangcheck hangcheck;
586 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
587 #define I915_ENGINE_SUPPORTS_STATS BIT(1)
588 #define I915_ENGINE_HAS_PREEMPTION BIT(2)
592 * Table of commands the command parser needs to know about
595 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
598 * Table of registers allowed in commands that read/write registers.
600 const struct drm_i915_reg_table *reg_tables;
604 * Returns the bitmask for the length field of the specified command.
605 * Return 0 for an unrecognized/invalid command.
607 * If the command parser finds an entry for a command in the engine's
608 * cmd_tables, it gets the command's length based on the table entry.
609 * If not, it calls this function to determine the per-engine length
610 * field encoding for the command (i.e. different opcode ranges use
611 * certain bits to encode the command length in the header).
613 u32 (*get_cmd_length_mask)(u32 cmd_header);
617 * @lock: Lock protecting the below fields.
621 * @enabled: Reference count indicating number of listeners.
623 unsigned int enabled;
625 * @active: Number of contexts currently scheduled in.
629 * @enabled_at: Timestamp when busy stats were enabled.
633 * @start: Timestamp of the last idle to active transition.
635 * Idle is defined as active == 0, active is active > 0.
639 * @total: Total time this engine was busy.
641 * Accumulated time not counting the most recent block in cases
642 * where engine is currently busy (active > 0).
649 intel_engine_needs_cmd_parser(const struct intel_engine_cs *engine)
651 return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER;
655 intel_engine_supports_stats(const struct intel_engine_cs *engine)
657 return engine->flags & I915_ENGINE_SUPPORTS_STATS;
661 intel_engine_has_preemption(const struct intel_engine_cs *engine)
663 return engine->flags & I915_ENGINE_HAS_PREEMPTION;
666 static inline bool __execlists_need_preempt(int prio, int last)
668 return prio > max(0, last);
672 execlists_set_active(struct intel_engine_execlists *execlists,
675 __set_bit(bit, (unsigned long *)&execlists->active);
679 execlists_set_active_once(struct intel_engine_execlists *execlists,
682 return !__test_and_set_bit(bit, (unsigned long *)&execlists->active);
686 execlists_clear_active(struct intel_engine_execlists *execlists,
689 __clear_bit(bit, (unsigned long *)&execlists->active);
693 execlists_clear_all_active(struct intel_engine_execlists *execlists)
695 execlists->active = 0;
699 execlists_is_active(const struct intel_engine_execlists *execlists,
702 return test_bit(bit, (unsigned long *)&execlists->active);
705 void execlists_user_begin(struct intel_engine_execlists *execlists,
706 const struct execlist_port *port);
707 void execlists_user_end(struct intel_engine_execlists *execlists);
710 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists);
713 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
715 static inline unsigned int
716 execlists_num_ports(const struct intel_engine_execlists * const execlists)
718 return execlists->port_mask + 1;
721 static inline struct execlist_port *
722 execlists_port_complete(struct intel_engine_execlists * const execlists,
723 struct execlist_port * const port)
725 const unsigned int m = execlists->port_mask;
727 GEM_BUG_ON(port_index(port, execlists) != 0);
728 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
730 memmove(port, port + 1, m * sizeof(struct execlist_port));
731 memset(port + m, 0, sizeof(struct execlist_port));
736 static inline unsigned int
737 intel_engine_flag(const struct intel_engine_cs *engine)
739 return BIT(engine->id);
743 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
745 /* Ensure that the compiler doesn't optimize away the load. */
746 return READ_ONCE(engine->status_page.page_addr[reg]);
750 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
752 /* Writing into the status page should be done sparingly. Since
753 * we do when we are uncertain of the device state, we take a bit
754 * of extra paranoia to try and ensure that the HWS takes the value
755 * we give and that it doesn't end up trapped inside the CPU!
757 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
759 clflush(&engine->status_page.page_addr[reg]);
760 engine->status_page.page_addr[reg] = value;
761 clflush(&engine->status_page.page_addr[reg]);
764 WRITE_ONCE(engine->status_page.page_addr[reg], value);
769 * Reads a dword out of the status page, which is written to from the command
770 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
773 * The following dwords have a reserved meaning:
774 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
775 * 0x04: ring 0 head pointer
776 * 0x05: ring 1 head pointer (915-class)
777 * 0x06: ring 2 head pointer (915-class)
778 * 0x10-0x1b: Context status DWords (GM45)
779 * 0x1f: Last written status offset. (GM45)
780 * 0x20-0x2f: Reserved (Gen6+)
782 * The area from dword 0x30 to 0x3ff is available for driver usage.
784 #define I915_GEM_HWS_INDEX 0x30
785 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
786 #define I915_GEM_HWS_PREEMPT_INDEX 0x32
787 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
788 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
789 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
791 #define I915_HWS_CSB_BUF0_INDEX 0x10
792 #define I915_HWS_CSB_WRITE_INDEX 0x1f
793 #define CNL_HWS_CSB_WRITE_INDEX 0x2f
796 intel_engine_create_ring(struct intel_engine_cs *engine,
797 struct i915_timeline *timeline,
799 int intel_ring_pin(struct intel_ring *ring);
800 void intel_ring_reset(struct intel_ring *ring, u32 tail);
801 unsigned int intel_ring_update_space(struct intel_ring *ring);
802 void intel_ring_unpin(struct intel_ring *ring);
803 void intel_ring_free(struct intel_ring *ring);
805 void intel_engine_stop(struct intel_engine_cs *engine);
806 void intel_engine_cleanup(struct intel_engine_cs *engine);
808 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
810 int __must_check intel_ring_cacheline_align(struct i915_request *rq);
812 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes);
813 u32 __must_check *intel_ring_begin(struct i915_request *rq, unsigned int n);
815 static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)
819 * This serves as a placeholder in the code so that the reader
820 * can compare against the preceding intel_ring_begin() and
821 * check that the number of dwords emitted matches the space
822 * reserved for the command packet (i.e. the value passed to
823 * intel_ring_begin()).
825 GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);
828 static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
830 return pos & (ring->size - 1);
834 intel_ring_offset_valid(const struct intel_ring *ring,
837 if (pos & -ring->size) /* must be strictly within the ring */
840 if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
846 static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
848 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
849 u32 offset = addr - rq->ring->vaddr;
850 GEM_BUG_ON(offset > rq->ring->size);
851 return intel_ring_wrap(rq->ring, offset);
855 assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
857 GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
861 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6
862 * Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
863 * Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
864 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
865 * same cacheline, the Head Pointer must not be greater than the Tail
868 * We use ring->head as the last known location of the actual RING_HEAD,
869 * it may have advanced but in the worst case it is equally the same
870 * as ring->head and so we should never program RING_TAIL to advance
871 * into the same cacheline as ring->head.
873 #define cacheline(a) round_down(a, CACHELINE_BYTES)
874 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
879 static inline unsigned int
880 intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
882 /* Whilst writes to the tail are strictly order, there is no
883 * serialisation between readers and the writers. The tail may be
884 * read by i915_request_retire() just as it is being updated
885 * by execlists, as although the breadcrumb is complete, the context
886 * switch hasn't been seen.
888 assert_ring_tail_valid(ring, tail);
893 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
895 void intel_engine_setup_common(struct intel_engine_cs *engine);
896 int intel_engine_init_common(struct intel_engine_cs *engine);
897 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
899 int intel_engine_create_scratch(struct intel_engine_cs *engine,
901 void intel_engine_cleanup_scratch(struct intel_engine_cs *engine);
903 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
904 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
905 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
906 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
908 int intel_engine_stop_cs(struct intel_engine_cs *engine);
909 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
911 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
912 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
914 static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
917 * We are only peeking at the tail of the submit queue (and not the
918 * queue itself) in order to gain a hint as to the current active
919 * state of the engine. Callers are not expected to be taking
920 * engine->timeline->lock, nor are they expected to be concerned
921 * wtih serialising this hint with anything, so document it as
922 * a hint and nothing more.
924 return READ_ONCE(engine->timeline.seqno);
927 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
929 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
932 static inline bool intel_engine_signaled(struct intel_engine_cs *engine,
935 return i915_seqno_passed(intel_engine_get_seqno(engine), seqno);
938 static inline bool intel_engine_has_completed(struct intel_engine_cs *engine,
942 return intel_engine_signaled(engine, seqno);
945 static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
949 return intel_engine_signaled(engine, seqno - 1);
952 void intel_engine_get_instdone(struct intel_engine_cs *engine,
953 struct intel_instdone *instdone);
956 * Arbitrary size for largest possible 'add request' sequence. The code paths
957 * are complex and variable. Empirical measurement shows that the worst case
958 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
959 * we need to allocate double the largest single packet within that emission
960 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
962 #define MIN_SPACE_FOR_ADD_REQUEST 336
964 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
966 return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
969 static inline u32 intel_hws_preempt_done_address(struct intel_engine_cs *engine)
971 return engine->status_page.ggtt_offset + I915_GEM_HWS_PREEMPT_ADDR;
974 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
975 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
977 static inline void intel_wait_init(struct intel_wait *wait)
980 wait->request = NULL;
983 static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno)
989 static inline bool intel_wait_has_seqno(const struct intel_wait *wait)
995 intel_wait_update_seqno(struct intel_wait *wait, u32 seqno)
998 return intel_wait_has_seqno(wait);
1002 intel_wait_update_request(struct intel_wait *wait,
1003 const struct i915_request *rq)
1005 return intel_wait_update_seqno(wait, i915_request_global_seqno(rq));
1009 intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno)
1011 return wait->seqno == seqno;
1015 intel_wait_check_request(const struct intel_wait *wait,
1016 const struct i915_request *rq)
1018 return intel_wait_check_seqno(wait, i915_request_global_seqno(rq));
1021 static inline bool intel_wait_complete(const struct intel_wait *wait)
1023 return RB_EMPTY_NODE(&wait->node);
1026 bool intel_engine_add_wait(struct intel_engine_cs *engine,
1027 struct intel_wait *wait);
1028 void intel_engine_remove_wait(struct intel_engine_cs *engine,
1029 struct intel_wait *wait);
1030 bool intel_engine_enable_signaling(struct i915_request *request, bool wakeup);
1031 void intel_engine_cancel_signaling(struct i915_request *request);
1033 static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
1035 return READ_ONCE(engine->breadcrumbs.irq_wait);
1038 unsigned int intel_engine_wakeup(struct intel_engine_cs *engine);
1039 #define ENGINE_WAKEUP_WAITER BIT(0)
1040 #define ENGINE_WAKEUP_ASLEEP BIT(1)
1042 void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
1043 void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
1045 void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
1046 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
1048 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
1049 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
1051 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
1053 memset(batch, 0, 6 * sizeof(u32));
1055 batch[0] = GFX_OP_PIPE_CONTROL(6);
1063 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset)
1065 /* We're using qword write, offset should be aligned to 8 bytes. */
1066 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
1068 /* w/a for post sync ops following a GPGPU operation we
1069 * need a prior CS_STALL, which is emitted by the flush
1070 * following the batch.
1072 *cs++ = GFX_OP_PIPE_CONTROL(6);
1073 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
1074 PIPE_CONTROL_QW_WRITE;
1078 /* We're thrashing one dword of HWS. */
1085 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset)
1087 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1088 GEM_BUG_ON(gtt_offset & (1 << 5));
1089 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
1090 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
1092 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1093 *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
1100 void intel_engines_sanitize(struct drm_i915_private *i915);
1102 bool intel_engine_is_idle(struct intel_engine_cs *engine);
1103 bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
1105 bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine);
1106 void intel_engine_lost_context(struct intel_engine_cs *engine);
1108 void intel_engines_park(struct drm_i915_private *i915);
1109 void intel_engines_unpark(struct drm_i915_private *i915);
1111 void intel_engines_reset_default_submission(struct drm_i915_private *i915);
1112 unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915);
1114 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
1117 void intel_engine_dump(struct intel_engine_cs *engine,
1118 struct drm_printer *m,
1119 const char *header, ...);
1121 struct intel_engine_cs *
1122 intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);
1124 static inline void intel_engine_context_in(struct intel_engine_cs *engine)
1126 unsigned long flags;
1128 if (READ_ONCE(engine->stats.enabled) == 0)
1131 write_seqlock_irqsave(&engine->stats.lock, flags);
1133 if (engine->stats.enabled > 0) {
1134 if (engine->stats.active++ == 0)
1135 engine->stats.start = ktime_get();
1136 GEM_BUG_ON(engine->stats.active == 0);
1139 write_sequnlock_irqrestore(&engine->stats.lock, flags);
1142 static inline void intel_engine_context_out(struct intel_engine_cs *engine)
1144 unsigned long flags;
1146 if (READ_ONCE(engine->stats.enabled) == 0)
1149 write_seqlock_irqsave(&engine->stats.lock, flags);
1151 if (engine->stats.enabled > 0) {
1154 if (engine->stats.active && --engine->stats.active == 0) {
1156 * Decrement the active context count and in case GPU
1157 * is now idle add up to the running total.
1159 last = ktime_sub(ktime_get(), engine->stats.start);
1161 engine->stats.total = ktime_add(engine->stats.total,
1163 } else if (engine->stats.active == 0) {
1165 * After turning on engine stats, context out might be
1166 * the first event in which case we account from the
1167 * time stats gathering was turned on.
1169 last = ktime_sub(ktime_get(), engine->stats.enabled_at);
1171 engine->stats.total = ktime_add(engine->stats.total,
1176 write_sequnlock_irqrestore(&engine->stats.lock, flags);
1179 int intel_enable_engine_stats(struct intel_engine_cs *engine);
1180 void intel_disable_engine_stats(struct intel_engine_cs *engine);
1182 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
1184 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1186 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
1188 if (!execlists->preempt_hang.inject_hang)
1191 complete(&execlists->preempt_hang.completion);
1197 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
1204 #endif /* _INTEL_RINGBUFFER_H_ */