drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34
  35 #include "i915_drv.h"
  36 #include "i915_gem_render_state.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39 #include "intel_workarounds.h"
  40
  41 /* Rough estimate of the typical request size, performing a flush,
  42  * set-context and then emitting the batch.
  43  */
  44 #define LEGACY_REQUEST_SIZE 200
  45
  46 static unsigned int __intel_ring_space(unsigned int head,
  47                                        unsigned int tail,
  48                                        unsigned int size)
  49 {
  50         /*
  51          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
  52          * same cacheline, the Head Pointer must not be greater than the Tail
  53          * Pointer."
  54          */
  55         GEM_BUG_ON(!is_power_of_2(size));
  56         return (head - tail - CACHELINE_BYTES) & (size - 1);
  57 }
  58
  59 unsigned int intel_ring_update_space(struct intel_ring *ring)
  60 {
  61         unsigned int space;
  62
  63         space = __intel_ring_space(ring->head, ring->emit, ring->size);
  64
  65         ring->space = space;
  66         return space;
  67 }
  68
  69 static int
  70 gen2_render_ring_flush(struct i915_request *rq, u32 mode)
  71 {
  72         u32 cmd, *cs;
  73
  74         cmd = MI_FLUSH;
  75
  76         if (mode & EMIT_INVALIDATE)
  77                 cmd |= MI_READ_FLUSH;
  78
  79         cs = intel_ring_begin(rq, 2);
  80         if (IS_ERR(cs))
  81                 return PTR_ERR(cs);
  82
  83         *cs++ = cmd;
  84         *cs++ = MI_NOOP;
  85         intel_ring_advance(rq, cs);
  86
  87         return 0;
  88 }
  89
  90 static int
  91 gen4_render_ring_flush(struct i915_request *rq, u32 mode)
  92 {
  93         u32 cmd, *cs;
  94
  95         /*
  96          * read/write caches:
  97          *
  98          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  99          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 100          * also flushed at 2d versus 3d pipeline switches.
 101          *
 102          * read-only caches:
 103          *
 104          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 105          * MI_READ_FLUSH is set, and is always flushed on 965.
 106          *
 107          * I915_GEM_DOMAIN_COMMAND may not exist?
 108          *
 109          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 110          * invalidated when MI_EXE_FLUSH is set.
 111          *
 112          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 113          * invalidated with every MI_FLUSH.
 114          *
 115          * TLBs:
 116          *
 117          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 118          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 119          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 120          * are flushed at any MI_FLUSH.
 121          */
 122
 123         cmd = MI_FLUSH;
 124         if (mode & EMIT_INVALIDATE) {
 125                 cmd |= MI_EXE_FLUSH;
 126                 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915))
 127                         cmd |= MI_INVALIDATE_ISP;
 128         }
 129
 130         cs = intel_ring_begin(rq, 2);
 131         if (IS_ERR(cs))
 132                 return PTR_ERR(cs);
 133
 134         *cs++ = cmd;
 135         *cs++ = MI_NOOP;
 136         intel_ring_advance(rq, cs);
 137
 138         return 0;
 139 }
 140
 141 /*
 142  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 143  * implementing two workarounds on gen6.  From section 1.4.7.1
 144  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 145  *
 146  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 147  * produced by non-pipelined state commands), software needs to first
 148  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 149  * 0.
 150  *
 151  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 152  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 153  *
 154  * And the workaround for these two requires this workaround first:
 155  *
 156  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 157  * BEFORE the pipe-control with a post-sync op and no write-cache
 158  * flushes.
 159  *
 160  * And this last workaround is tricky because of the requirements on
 161  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 162  * volume 2 part 1:
 163  *
 164  *     "1 of the following must also be set:
 165  *      - Render Target Cache Flush Enable ([12] of DW1)
 166  *      - Depth Cache Flush Enable ([0] of DW1)
 167  *      - Stall at Pixel Scoreboard ([1] of DW1)
 168  *      - Depth Stall ([13] of DW1)
 169  *      - Post-Sync Operation ([13] of DW1)
 170  *      - Notify Enable ([8] of DW1)"
 171  *
 172  * The cache flushes require the workaround flush that triggered this
 173  * one, so we can't use it.  Depth stall would trigger the same.
 174  * Post-sync nonzero is what triggered this second workaround, so we
 175  * can't use that one either.  Notify enable is IRQs, which aren't
 176  * really our business.  That leaves only stall at scoreboard.
 177  */
 178 static int
 179 intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
 180 {
 181         u32 scratch_addr =
 182                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 183         u32 *cs;
 184
 185         cs = intel_ring_begin(rq, 6);
 186         if (IS_ERR(cs))
 187                 return PTR_ERR(cs);
 188
 189         *cs++ = GFX_OP_PIPE_CONTROL(5);
 190         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 191         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 192         *cs++ = 0; /* low dword */
 193         *cs++ = 0; /* high dword */
 194         *cs++ = MI_NOOP;
 195         intel_ring_advance(rq, cs);
 196
 197         cs = intel_ring_begin(rq, 6);
 198         if (IS_ERR(cs))
 199                 return PTR_ERR(cs);
 200
 201         *cs++ = GFX_OP_PIPE_CONTROL(5);
 202         *cs++ = PIPE_CONTROL_QW_WRITE;
 203         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 204         *cs++ = 0;
 205         *cs++ = 0;
 206         *cs++ = MI_NOOP;
 207         intel_ring_advance(rq, cs);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 214 {
 215         u32 scratch_addr =
 216                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 217         u32 *cs, flags = 0;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(rq);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (mode & EMIT_FLUSH) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (mode & EMIT_INVALIDATE) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         cs = intel_ring_begin(rq, 4);
 252         if (IS_ERR(cs))
 253                 return PTR_ERR(cs);
 254
 255         *cs++ = GFX_OP_PIPE_CONTROL(4);
 256         *cs++ = flags;
 257         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 258         *cs++ = 0;
 259         intel_ring_advance(rq, cs);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct i915_request *rq)
 266 {
 267         u32 *cs;
 268
 269         cs = intel_ring_begin(rq, 4);
 270         if (IS_ERR(cs))
 271                 return PTR_ERR(cs);
 272
 273         *cs++ = GFX_OP_PIPE_CONTROL(4);
 274         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 275         *cs++ = 0;
 276         *cs++ = 0;
 277         intel_ring_advance(rq, cs);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 284 {
 285         u32 scratch_addr =
 286                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 287         u32 *cs, flags = 0;
 288
 289         /*
 290          * Ensure that any following seqno writes only happen when the render
 291          * cache is indeed flushed.
 292          *
 293          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 294          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 295          * don't try to be clever and just set it unconditionally.
 296          */
 297         flags |= PIPE_CONTROL_CS_STALL;
 298
 299         /* Just flush everything.  Experiments have shown that reducing the
 300          * number of bits based on the write domains has little performance
 301          * impact.
 302          */
 303         if (mode & EMIT_FLUSH) {
 304                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 305                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 306                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 307                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 308         }
 309         if (mode & EMIT_INVALIDATE) {
 310                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 311                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 312                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 324
 325                 /* Workaround: we must issue a pipe_control with CS-stall bit
 326                  * set before a pipe_control command that has the state cache
 327                  * invalidate bit set. */
 328                 gen7_render_ring_cs_stall_wa(rq);
 329         }
 330
 331         cs = intel_ring_begin(rq, 4);
 332         if (IS_ERR(cs))
 333                 return PTR_ERR(cs);
 334
 335         *cs++ = GFX_OP_PIPE_CONTROL(4);
 336         *cs++ = flags;
 337         *cs++ = scratch_addr;
 338         *cs++ = 0;
 339         intel_ring_advance(rq, cs);
 340
 341         return 0;
 342 }
 343
 344 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 345 {
 346         struct drm_i915_private *dev_priv = engine->i915;
 347         u32 addr;
 348
 349         addr = dev_priv->status_page_dmah->busaddr;
 350         if (INTEL_GEN(dev_priv) >= 4)
 351                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 352         I915_WRITE(HWS_PGA, addr);
 353 }
 354
 355 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 356 {
 357         struct drm_i915_private *dev_priv = engine->i915;
 358         i915_reg_t mmio;
 359
 360         /* The ring status page addresses are no longer next to the rest of
 361          * the ring registers as of gen7.
 362          */
 363         if (IS_GEN7(dev_priv)) {
 364                 switch (engine->id) {
 365                 /*
 366                  * No more rings exist on Gen7. Default case is only to shut up
 367                  * gcc switch check warning.
 368                  */
 369                 default:
 370                         GEM_BUG_ON(engine->id);
 371                 case RCS:
 372                         mmio = RENDER_HWS_PGA_GEN7;
 373                         break;
 374                 case BCS:
 375                         mmio = BLT_HWS_PGA_GEN7;
 376                         break;
 377                 case VCS:
 378                         mmio = BSD_HWS_PGA_GEN7;
 379                         break;
 380                 case VECS:
 381                         mmio = VEBOX_HWS_PGA_GEN7;
 382                         break;
 383                 }
 384         } else if (IS_GEN6(dev_priv)) {
 385                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 386         } else {
 387                 mmio = RING_HWS_PGA(engine->mmio_base);
 388         }
 389
 390         if (INTEL_GEN(dev_priv) >= 6)
 391                 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
 392
 393         I915_WRITE(mmio, engine->status_page.ggtt_offset);
 394         POSTING_READ(mmio);
 395
 396         /* Flush the TLB for this page */
 397         if (IS_GEN(dev_priv, 6, 7)) {
 398                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 399
 400                 /* ring should be idle before issuing a sync flush*/
 401                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 402
 403                 I915_WRITE(reg,
 404                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 405                                               INSTPM_SYNC_FLUSH));
 406                 if (intel_wait_for_register(dev_priv,
 407                                             reg, INSTPM_SYNC_FLUSH, 0,
 408                                             1000))
 409                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 410                                   engine->name);
 411         }
 412 }
 413
 414 static bool stop_ring(struct intel_engine_cs *engine)
 415 {
 416         struct drm_i915_private *dev_priv = engine->i915;
 417
 418         if (INTEL_GEN(dev_priv) > 2) {
 419                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 420                 if (intel_wait_for_register(dev_priv,
 421                                             RING_MI_MODE(engine->mmio_base),
 422                                             MODE_IDLE,
 423                                             MODE_IDLE,
 424                                             1000)) {
 425                         DRM_ERROR("%s : timed out trying to stop ring\n",
 426                                   engine->name);
 427                         /* Sometimes we observe that the idle flag is not
 428                          * set even though the ring is empty. So double
 429                          * check before giving up.
 430                          */
 431                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 432                                 return false;
 433                 }
 434         }
 435
 436         I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
 437
 438         I915_WRITE_HEAD(engine, 0);
 439         I915_WRITE_TAIL(engine, 0);
 440
 441         /* The ring must be empty before it is disabled */
 442         I915_WRITE_CTL(engine, 0);
 443
 444         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 445 }
 446
 447 static int init_ring_common(struct intel_engine_cs *engine)
 448 {
 449         struct drm_i915_private *dev_priv = engine->i915;
 450         struct intel_ring *ring = engine->buffer;
 451         int ret = 0;
 452
 453         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 454
 455         if (!stop_ring(engine)) {
 456                 /* G45 ring initialization often fails to reset head to zero */
 457                 DRM_DEBUG_DRIVER("%s head not reset to zero "
 458                                 "ctl %08x head %08x tail %08x start %08x\n",
 459                                 engine->name,
 460                                 I915_READ_CTL(engine),
 461                                 I915_READ_HEAD(engine),
 462                                 I915_READ_TAIL(engine),
 463                                 I915_READ_START(engine));
 464
 465                 if (!stop_ring(engine)) {
 466                         DRM_ERROR("failed to set %s head to zero "
 467                                   "ctl %08x head %08x tail %08x start %08x\n",
 468                                   engine->name,
 469                                   I915_READ_CTL(engine),
 470                                   I915_READ_HEAD(engine),
 471                                   I915_READ_TAIL(engine),
 472                                   I915_READ_START(engine));
 473                         ret = -EIO;
 474                         goto out;
 475                 }
 476         }
 477
 478         if (HWS_NEEDS_PHYSICAL(dev_priv))
 479                 ring_setup_phys_status_page(engine);
 480         else
 481                 intel_ring_setup_status_page(engine);
 482
 483         intel_engine_reset_breadcrumbs(engine);
 484
 485         /* Enforce ordering by reading HEAD register back */
 486         I915_READ_HEAD(engine);
 487
 488         /* Initialize the ring. This must happen _after_ we've cleared the ring
 489          * registers with the above sequence (the readback of the HEAD registers
 490          * also enforces ordering), otherwise the hw might lose the new ring
 491          * register values. */
 492         I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
 493
 494         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 495         if (I915_READ_HEAD(engine))
 496                 DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
 497                                  engine->name, I915_READ_HEAD(engine));
 498
 499         intel_ring_update_space(ring);
 500         I915_WRITE_HEAD(engine, ring->head);
 501         I915_WRITE_TAIL(engine, ring->tail);
 502         (void)I915_READ_TAIL(engine);
 503
 504         I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 505
 506         /* If the head is still not zero, the ring is dead */
 507         if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
 508                                     RING_VALID, RING_VALID,
 509                                     50)) {
 510                 DRM_ERROR("%s initialization failed "
 511                           "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
 512                           engine->name,
 513                           I915_READ_CTL(engine),
 514                           I915_READ_CTL(engine) & RING_VALID,
 515                           I915_READ_HEAD(engine), ring->head,
 516                           I915_READ_TAIL(engine), ring->tail,
 517                           I915_READ_START(engine),
 518                           i915_ggtt_offset(ring->vma));
 519                 ret = -EIO;
 520                 goto out;
 521         }
 522
 523         intel_engine_init_hangcheck(engine);
 524
 525         if (INTEL_GEN(dev_priv) > 2)
 526                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 527
 528 out:
 529         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 530
 531         return ret;
 532 }
 533
 534 static struct i915_request *reset_prepare(struct intel_engine_cs *engine)
 535 {
 536         intel_engine_stop_cs(engine);
 537
 538         if (engine->irq_seqno_barrier)
 539                 engine->irq_seqno_barrier(engine);
 540
 541         return i915_gem_find_active_request(engine);
 542 }
 543
 544 static void skip_request(struct i915_request *rq)
 545 {
 546         void *vaddr = rq->ring->vaddr;
 547         u32 head;
 548
 549         head = rq->infix;
 550         if (rq->postfix < head) {
 551                 memset32(vaddr + head, MI_NOOP,
 552                          (rq->ring->size - head) / sizeof(u32));
 553                 head = 0;
 554         }
 555         memset32(vaddr + head, MI_NOOP, (rq->postfix - head) / sizeof(u32));
 556 }
 557
 558 static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq)
 559 {
 560         GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0);
 561
 562         /*
 563          * RC6 must be prevented until the reset is complete and the engine
 564          * reinitialised. If it occurs in the middle of this sequence, the
 565          * state written to/loaded from the power context is ill-defined (e.g.
 566          * the PP_BASE_DIR may be lost).
 567          */
 568         assert_forcewakes_active(engine->i915, FORCEWAKE_ALL);
 569
 570         /*
 571          * Try to restore the logical GPU state to match the continuation
 572          * of the request queue. If we skip the context/PD restore, then
 573          * the next request may try to execute assuming that its context
 574          * is valid and loaded on the GPU and so may try to access invalid
 575          * memory, prompting repeated GPU hangs.
 576          *
 577          * If the request was guilty, we still restore the logical state
 578          * in case the next request requires it (e.g. the aliasing ppgtt),
 579          * but skip over the hung batch.
 580          *
 581          * If the request was innocent, we try to replay the request with
 582          * the restored context.
 583          */
 584         if (rq) {
 585                 /* If the rq hung, jump to its breadcrumb and skip the batch */
 586                 rq->ring->head = intel_ring_wrap(rq->ring, rq->head);
 587                 if (rq->fence.error == -EIO)
 588                         skip_request(rq);
 589         }
 590 }
 591
 592 static void reset_finish(struct intel_engine_cs *engine)
 593 {
 594 }
 595
 596 static int intel_rcs_ctx_init(struct i915_request *rq)
 597 {
 598         int ret;
 599
 600         ret = intel_ctx_workarounds_emit(rq);
 601         if (ret != 0)
 602                 return ret;
 603
 604         ret = i915_gem_render_state_emit(rq);
 605         if (ret)
 606                 return ret;
 607
 608         return 0;
 609 }
 610
 611 static int init_render_ring(struct intel_engine_cs *engine)
 612 {
 613         struct drm_i915_private *dev_priv = engine->i915;
 614         int ret = init_ring_common(engine);
 615         if (ret)
 616                 return ret;
 617
 618         intel_whitelist_workarounds_apply(engine);
 619
 620         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 621         if (IS_GEN(dev_priv, 4, 6))
 622                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 623
 624         /* We need to disable the AsyncFlip performance optimisations in order
 625          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 626          * programmed to '1' on all products.
 627          *
 628          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 629          */
 630         if (IS_GEN(dev_priv, 6, 7))
 631                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 632
 633         /* Required for the hardware to program scanline values for waiting */
 634         /* WaEnableFlushTlbInvalidationMode:snb */
 635         if (IS_GEN6(dev_priv))
 636                 I915_WRITE(GFX_MODE,
 637                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 638
 639         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 640         if (IS_GEN7(dev_priv))
 641                 I915_WRITE(GFX_MODE_GEN7,
 642                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 643                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 644
 645         if (IS_GEN6(dev_priv)) {
 646                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 647                  * "If this bit is set, STCunit will have LRA as replacement
 648                  *  policy. [...] This bit must be reset.  LRA replacement
 649                  *  policy is not supported."
 650                  */
 651                 I915_WRITE(CACHE_MODE_0,
 652                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 653         }
 654
 655         if (IS_GEN(dev_priv, 6, 7))
 656                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 657
 658         if (INTEL_GEN(dev_priv) >= 6)
 659                 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 660
 661         return 0;
 662 }
 663
 664 static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
 665 {
 666         struct drm_i915_private *dev_priv = rq->i915;
 667         struct intel_engine_cs *engine;
 668         enum intel_engine_id id;
 669         int num_rings = 0;
 670
 671         for_each_engine(engine, dev_priv, id) {
 672                 i915_reg_t mbox_reg;
 673
 674                 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
 675                         continue;
 676
 677                 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
 678                 if (i915_mmio_reg_valid(mbox_reg)) {
 679                         *cs++ = MI_LOAD_REGISTER_IMM(1);
 680                         *cs++ = i915_mmio_reg_offset(mbox_reg);
 681                         *cs++ = rq->global_seqno;
 682                         num_rings++;
 683                 }
 684         }
 685         if (num_rings & 1)
 686                 *cs++ = MI_NOOP;
 687
 688         return cs;
 689 }
 690
 691 static void cancel_requests(struct intel_engine_cs *engine)
 692 {
 693         struct i915_request *request;
 694         unsigned long flags;
 695
 696         spin_lock_irqsave(&engine->timeline.lock, flags);
 697
 698         /* Mark all submitted requests as skipped. */
 699         list_for_each_entry(request, &engine->timeline.requests, link) {
 700                 GEM_BUG_ON(!request->global_seqno);
 701                 if (!i915_request_completed(request))
 702                         dma_fence_set_error(&request->fence, -EIO);
 703         }
 704         /* Remaining _unready_ requests will be nop'ed when submitted */
 705
 706         spin_unlock_irqrestore(&engine->timeline.lock, flags);
 707 }
 708
 709 static void i9xx_submit_request(struct i915_request *request)
 710 {
 711         struct drm_i915_private *dev_priv = request->i915;
 712
 713         i915_request_submit(request);
 714
 715         I915_WRITE_TAIL(request->engine,
 716                         intel_ring_set_tail(request->ring, request->tail));
 717 }
 718
 719 static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 720 {
 721         *cs++ = MI_STORE_DWORD_INDEX;
 722         *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
 723         *cs++ = rq->global_seqno;
 724         *cs++ = MI_USER_INTERRUPT;
 725
 726         rq->tail = intel_ring_offset(rq, cs);
 727         assert_ring_tail_valid(rq->ring, rq->tail);
 728 }
 729
 730 static const int i9xx_emit_breadcrumb_sz = 4;
 731
 732 static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 733 {
 734         return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
 735 }
 736
 737 static int
 738 gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal)
 739 {
 740         u32 dw1 = MI_SEMAPHORE_MBOX |
 741                   MI_SEMAPHORE_COMPARE |
 742                   MI_SEMAPHORE_REGISTER;
 743         u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
 744         u32 *cs;
 745
 746         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 747
 748         cs = intel_ring_begin(rq, 4);
 749         if (IS_ERR(cs))
 750                 return PTR_ERR(cs);
 751
 752         *cs++ = dw1 | wait_mbox;
 753         /* Throughout all of the GEM code, seqno passed implies our current
 754          * seqno is >= the last seqno executed. However for hardware the
 755          * comparison is strictly greater than.
 756          */
 757         *cs++ = signal->global_seqno - 1;
 758         *cs++ = 0;
 759         *cs++ = MI_NOOP;
 760         intel_ring_advance(rq, cs);
 761
 762         return 0;
 763 }
 764
 765 static void
 766 gen5_seqno_barrier(struct intel_engine_cs *engine)
 767 {
 768         /* MI_STORE are internally buffered by the GPU and not flushed
 769          * either by MI_FLUSH or SyncFlush or any other combination of
 770          * MI commands.
 771          *
 772          * "Only the submission of the store operation is guaranteed.
 773          * The write result will be complete (coherent) some time later
 774          * (this is practically a finite period but there is no guaranteed
 775          * latency)."
 776          *
 777          * Empirically, we observe that we need a delay of at least 75us to
 778          * be sure that the seqno write is visible by the CPU.
 779          */
 780         usleep_range(125, 250);
 781 }
 782
 783 static void
 784 gen6_seqno_barrier(struct intel_engine_cs *engine)
 785 {
 786         struct drm_i915_private *dev_priv = engine->i915;
 787
 788         /* Workaround to force correct ordering between irq and seqno writes on
 789          * ivb (and maybe also on snb) by reading from a CS register (like
 790          * ACTHD) before reading the status page.
 791          *
 792          * Note that this effectively stalls the read by the time it takes to
 793          * do a memory transaction, which more or less ensures that the write
 794          * from the GPU has sufficient time to invalidate the CPU cacheline.
 795          * Alternatively we could delay the interrupt from the CS ring to give
 796          * the write time to land, but that would incur a delay after every
 797          * batch i.e. much more frequent than a delay when waiting for the
 798          * interrupt (with the same net latency).
 799          *
 800          * Also note that to prevent whole machine hangs on gen7, we have to
 801          * take the spinlock to guard against concurrent cacheline access.
 802          */
 803         spin_lock_irq(&dev_priv->uncore.lock);
 804         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
 805         spin_unlock_irq(&dev_priv->uncore.lock);
 806 }
 807
 808 static void
 809 gen5_irq_enable(struct intel_engine_cs *engine)
 810 {
 811         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
 812 }
 813
 814 static void
 815 gen5_irq_disable(struct intel_engine_cs *engine)
 816 {
 817         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
 818 }
 819
 820 static void
 821 i9xx_irq_enable(struct intel_engine_cs *engine)
 822 {
 823         struct drm_i915_private *dev_priv = engine->i915;
 824
 825         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 826         I915_WRITE(IMR, dev_priv->irq_mask);
 827         POSTING_READ_FW(RING_IMR(engine->mmio_base));
 828 }
 829
 830 static void
 831 i9xx_irq_disable(struct intel_engine_cs *engine)
 832 {
 833         struct drm_i915_private *dev_priv = engine->i915;
 834
 835         dev_priv->irq_mask |= engine->irq_enable_mask;
 836         I915_WRITE(IMR, dev_priv->irq_mask);
 837 }
 838
 839 static void
 840 i8xx_irq_enable(struct intel_engine_cs *engine)
 841 {
 842         struct drm_i915_private *dev_priv = engine->i915;
 843
 844         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 845         I915_WRITE16(IMR, dev_priv->irq_mask);
 846         POSTING_READ16(RING_IMR(engine->mmio_base));
 847 }
 848
 849 static void
 850 i8xx_irq_disable(struct intel_engine_cs *engine)
 851 {
 852         struct drm_i915_private *dev_priv = engine->i915;
 853
 854         dev_priv->irq_mask |= engine->irq_enable_mask;
 855         I915_WRITE16(IMR, dev_priv->irq_mask);
 856 }
 857
 858 static int
 859 bsd_ring_flush(struct i915_request *rq, u32 mode)
 860 {
 861         u32 *cs;
 862
 863         cs = intel_ring_begin(rq, 2);
 864         if (IS_ERR(cs))
 865                 return PTR_ERR(cs);
 866
 867         *cs++ = MI_FLUSH;
 868         *cs++ = MI_NOOP;
 869         intel_ring_advance(rq, cs);
 870         return 0;
 871 }
 872
 873 static void
 874 gen6_irq_enable(struct intel_engine_cs *engine)
 875 {
 876         struct drm_i915_private *dev_priv = engine->i915;
 877
 878         I915_WRITE_IMR(engine,
 879                        ~(engine->irq_enable_mask |
 880                          engine->irq_keep_mask));
 881         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 882 }
 883
 884 static void
 885 gen6_irq_disable(struct intel_engine_cs *engine)
 886 {
 887         struct drm_i915_private *dev_priv = engine->i915;
 888
 889         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 890         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
 891 }
 892
 893 static void
 894 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
 895 {
 896         struct drm_i915_private *dev_priv = engine->i915;
 897
 898         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
 899         gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
 900 }
 901
 902 static void
 903 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
 904 {
 905         struct drm_i915_private *dev_priv = engine->i915;
 906
 907         I915_WRITE_IMR(engine, ~0);
 908         gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 909 }
 910
 911 static int
 912 i965_emit_bb_start(struct i915_request *rq,
 913                    u64 offset, u32 length,
 914                    unsigned int dispatch_flags)
 915 {
 916         u32 *cs;
 917
 918         cs = intel_ring_begin(rq, 2);
 919         if (IS_ERR(cs))
 920                 return PTR_ERR(cs);
 921
 922         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
 923                 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
 924         *cs++ = offset;
 925         intel_ring_advance(rq, cs);
 926
 927         return 0;
 928 }
 929
 930 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 931 #define I830_BATCH_LIMIT (256*1024)
 932 #define I830_TLB_ENTRIES (2)
 933 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 934 static int
 935 i830_emit_bb_start(struct i915_request *rq,
 936                    u64 offset, u32 len,
 937                    unsigned int dispatch_flags)
 938 {
 939         u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
 940
 941         cs = intel_ring_begin(rq, 6);
 942         if (IS_ERR(cs))
 943                 return PTR_ERR(cs);
 944
 945         /* Evict the invalid PTE TLBs */
 946         *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
 947         *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
 948         *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
 949         *cs++ = cs_offset;
 950         *cs++ = 0xdeadbeef;
 951         *cs++ = MI_NOOP;
 952         intel_ring_advance(rq, cs);
 953
 954         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
 955                 if (len > I830_BATCH_LIMIT)
 956                         return -ENOSPC;
 957
 958                 cs = intel_ring_begin(rq, 6 + 2);
 959                 if (IS_ERR(cs))
 960                         return PTR_ERR(cs);
 961
 962                 /* Blit the batch (which has now all relocs applied) to the
 963                  * stable batch scratch bo area (so that the CS never
 964                  * stumbles over its tlb invalidation bug) ...
 965                  */
 966                 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
 967                 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
 968                 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
 969                 *cs++ = cs_offset;
 970                 *cs++ = 4096;
 971                 *cs++ = offset;
 972
 973                 *cs++ = MI_FLUSH;
 974                 *cs++ = MI_NOOP;
 975                 intel_ring_advance(rq, cs);
 976
 977                 /* ... and execute it. */
 978                 offset = cs_offset;
 979         }
 980
 981         cs = intel_ring_begin(rq, 2);
 982         if (IS_ERR(cs))
 983                 return PTR_ERR(cs);
 984
 985         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
 986         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
 987                 MI_BATCH_NON_SECURE);
 988         intel_ring_advance(rq, cs);
 989
 990         return 0;
 991 }
 992
 993 static int
 994 i915_emit_bb_start(struct i915_request *rq,
 995                    u64 offset, u32 len,
 996                    unsigned int dispatch_flags)
 997 {
 998         u32 *cs;
 999
1000         cs = intel_ring_begin(rq, 2);
1001         if (IS_ERR(cs))
1002                 return PTR_ERR(cs);
1003
1004         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1005         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1006                 MI_BATCH_NON_SECURE);
1007         intel_ring_advance(rq, cs);
1008
1009         return 0;
1010 }
1011
1012
1013
1014 int intel_ring_pin(struct intel_ring *ring,
1015                    struct drm_i915_private *i915,
1016                    unsigned int offset_bias)
1017 {
1018         enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1019         struct i915_vma *vma = ring->vma;
1020         unsigned int flags;
1021         void *addr;
1022         int ret;
1023
1024         GEM_BUG_ON(ring->vaddr);
1025
1026
1027         flags = PIN_GLOBAL;
1028         if (offset_bias)
1029                 flags |= PIN_OFFSET_BIAS | offset_bias;
1030         if (vma->obj->stolen)
1031                 flags |= PIN_MAPPABLE;
1032
1033         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1034                 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1035                         ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1036                 else
1037                         ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1038                 if (unlikely(ret))
1039                         return ret;
1040         }
1041
1042         ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1043         if (unlikely(ret))
1044                 return ret;
1045
1046         if (i915_vma_is_map_and_fenceable(vma))
1047                 addr = (void __force *)i915_vma_pin_iomap(vma);
1048         else
1049                 addr = i915_gem_object_pin_map(vma->obj, map);
1050         if (IS_ERR(addr))
1051                 goto err;
1052
1053         vma->obj->pin_global++;
1054
1055         ring->vaddr = addr;
1056         return 0;
1057
1058 err:
1059         i915_vma_unpin(vma);
1060         return PTR_ERR(addr);
1061 }
1062
1063 void intel_ring_reset(struct intel_ring *ring, u32 tail)
1064 {
1065         ring->tail = tail;
1066         ring->head = tail;
1067         ring->emit = tail;
1068         intel_ring_update_space(ring);
1069 }
1070
1071 void intel_ring_unpin(struct intel_ring *ring)
1072 {
1073         GEM_BUG_ON(!ring->vma);
1074         GEM_BUG_ON(!ring->vaddr);
1075
1076         /* Discard any unused bytes beyond that submitted to hw. */
1077         intel_ring_reset(ring, ring->tail);
1078
1079         if (i915_vma_is_map_and_fenceable(ring->vma))
1080                 i915_vma_unpin_iomap(ring->vma);
1081         else
1082                 i915_gem_object_unpin_map(ring->vma->obj);
1083         ring->vaddr = NULL;
1084
1085         ring->vma->obj->pin_global--;
1086         i915_vma_unpin(ring->vma);
1087 }
1088
1089 static struct i915_vma *
1090 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1091 {
1092         struct drm_i915_gem_object *obj;
1093         struct i915_vma *vma;
1094
1095         obj = i915_gem_object_create_stolen(dev_priv, size);
1096         if (!obj)
1097                 obj = i915_gem_object_create_internal(dev_priv, size);
1098         if (IS_ERR(obj))
1099                 return ERR_CAST(obj);
1100
1101         /* mark ring buffers as read-only from GPU side by default */
1102         obj->gt_ro = 1;
1103
1104         vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
1105         if (IS_ERR(vma))
1106                 goto err;
1107
1108         return vma;
1109
1110 err:
1111         i915_gem_object_put(obj);
1112         return vma;
1113 }
1114
1115 struct intel_ring *
1116 intel_engine_create_ring(struct intel_engine_cs *engine,
1117                          struct i915_timeline *timeline,
1118                          int size)
1119 {
1120         struct intel_ring *ring;
1121         struct i915_vma *vma;
1122
1123         GEM_BUG_ON(!is_power_of_2(size));
1124         GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1125         GEM_BUG_ON(timeline == &engine->timeline);
1126         lockdep_assert_held(&engine->i915->drm.struct_mutex);
1127
1128         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1129         if (!ring)
1130                 return ERR_PTR(-ENOMEM);
1131
1132         INIT_LIST_HEAD(&ring->request_list);
1133         ring->timeline = i915_timeline_get(timeline);
1134
1135         ring->size = size;
1136         /* Workaround an erratum on the i830 which causes a hang if
1137          * the TAIL pointer points to within the last 2 cachelines
1138          * of the buffer.
1139          */
1140         ring->effective_size = size;
1141         if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1142                 ring->effective_size -= 2 * CACHELINE_BYTES;
1143
1144         intel_ring_update_space(ring);
1145
1146         vma = intel_ring_create_vma(engine->i915, size);
1147         if (IS_ERR(vma)) {
1148                 kfree(ring);
1149                 return ERR_CAST(vma);
1150         }
1151         ring->vma = vma;
1152
1153         return ring;
1154 }
1155
1156 void
1157 intel_ring_free(struct intel_ring *ring)
1158 {
1159         struct drm_i915_gem_object *obj = ring->vma->obj;
1160
1161         i915_vma_close(ring->vma);
1162         __i915_gem_object_release_unless_active(obj);
1163
1164         i915_timeline_put(ring->timeline);
1165         kfree(ring);
1166 }
1167
1168 static void intel_ring_context_destroy(struct intel_context *ce)
1169 {
1170         GEM_BUG_ON(ce->pin_count);
1171
1172         if (ce->state)
1173                 __i915_gem_object_release_unless_active(ce->state->obj);
1174 }
1175
1176 static int __context_pin(struct intel_context *ce)
1177 {
1178         struct i915_vma *vma;
1179         int err;
1180
1181         vma = ce->state;
1182         if (!vma)
1183                 return 0;
1184
1185         /*
1186          * Clear this page out of any CPU caches for coherent swap-in/out.
1187          * We only want to do this on the first bind so that we do not stall
1188          * on an active context (which by nature is already on the GPU).
1189          */
1190         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1191                 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1192                 if (err)
1193                         return err;
1194         }
1195
1196         err = i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
1197                            PIN_GLOBAL | PIN_HIGH);
1198         if (err)
1199                 return err;
1200
1201         /*
1202          * And mark is as a globally pinned object to let the shrinker know
1203          * it cannot reclaim the object until we release it.
1204          */
1205         vma->obj->pin_global++;
1206
1207         return 0;
1208 }
1209
1210 static void __context_unpin(struct intel_context *ce)
1211 {
1212         struct i915_vma *vma;
1213
1214         vma = ce->state;
1215         if (!vma)
1216                 return;
1217
1218         vma->obj->pin_global--;
1219         i915_vma_unpin(vma);
1220 }
1221
1222 static void intel_ring_context_unpin(struct intel_context *ce)
1223 {
1224         __context_unpin(ce);
1225
1226         i915_gem_context_put(ce->gem_context);
1227 }
1228
1229 static struct i915_vma *
1230 alloc_context_vma(struct intel_engine_cs *engine)
1231 {
1232         struct drm_i915_private *i915 = engine->i915;
1233         struct drm_i915_gem_object *obj;
1234         struct i915_vma *vma;
1235         int err;
1236
1237         obj = i915_gem_object_create(i915, engine->context_size);
1238         if (IS_ERR(obj))
1239                 return ERR_CAST(obj);
1240
1241         if (engine->default_state) {
1242                 void *defaults, *vaddr;
1243
1244                 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1245                 if (IS_ERR(vaddr)) {
1246                         err = PTR_ERR(vaddr);
1247                         goto err_obj;
1248                 }
1249
1250                 defaults = i915_gem_object_pin_map(engine->default_state,
1251                                                    I915_MAP_WB);
1252                 if (IS_ERR(defaults)) {
1253                         err = PTR_ERR(defaults);
1254                         goto err_map;
1255                 }
1256
1257                 memcpy(vaddr, defaults, engine->context_size);
1258
1259                 i915_gem_object_unpin_map(engine->default_state);
1260                 i915_gem_object_unpin_map(obj);
1261         }
1262
1263         /*
1264          * Try to make the context utilize L3 as well as LLC.
1265          *
1266          * On VLV we don't have L3 controls in the PTEs so we
1267          * shouldn't touch the cache level, especially as that
1268          * would make the object snooped which might have a
1269          * negative performance impact.
1270          *
1271          * Snooping is required on non-llc platforms in execlist
1272          * mode, but since all GGTT accesses use PAT entry 0 we
1273          * get snooping anyway regardless of cache_level.
1274          *
1275          * This is only applicable for Ivy Bridge devices since
1276          * later platforms don't have L3 control bits in the PTE.
1277          */
1278         if (IS_IVYBRIDGE(i915)) {
1279                 /* Ignore any error, regard it as a simple optimisation */
1280                 i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
1281         }
1282
1283         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1284         if (IS_ERR(vma)) {
1285                 err = PTR_ERR(vma);
1286                 goto err_obj;
1287         }
1288
1289         return vma;
1290
1291 err_map:
1292         i915_gem_object_unpin_map(obj);
1293 err_obj:
1294         i915_gem_object_put(obj);
1295         return ERR_PTR(err);
1296 }
1297
1298 static struct intel_context *
1299 __ring_context_pin(struct intel_engine_cs *engine,
1300                    struct i915_gem_context *ctx,
1301                    struct intel_context *ce)
1302 {
1303         int err;
1304
1305         if (!ce->state && engine->context_size) {
1306                 struct i915_vma *vma;
1307
1308                 vma = alloc_context_vma(engine);
1309                 if (IS_ERR(vma)) {
1310                         err = PTR_ERR(vma);
1311                         goto err;
1312                 }
1313
1314                 ce->state = vma;
1315         }
1316
1317         err = __context_pin(ce);
1318         if (err)
1319                 goto err;
1320
1321         i915_gem_context_get(ctx);
1322
1323         /* One ringbuffer to rule them all */
1324         GEM_BUG_ON(!engine->buffer);
1325         ce->ring = engine->buffer;
1326
1327         return ce;
1328
1329 err:
1330         ce->pin_count = 0;
1331         return ERR_PTR(err);
1332 }
1333
1334 static const struct intel_context_ops ring_context_ops = {
1335         .unpin = intel_ring_context_unpin,
1336         .destroy = intel_ring_context_destroy,
1337 };
1338
1339 static struct intel_context *
1340 intel_ring_context_pin(struct intel_engine_cs *engine,
1341                        struct i915_gem_context *ctx)
1342 {
1343         struct intel_context *ce = to_intel_context(ctx, engine);
1344
1345         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1346
1347         if (likely(ce->pin_count++))
1348                 return ce;
1349         GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1350
1351         ce->ops = &ring_context_ops;
1352
1353         return __ring_context_pin(engine, ctx, ce);
1354 }
1355
1356 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1357 {
1358         struct intel_ring *ring;
1359         struct i915_timeline *timeline;
1360         int err;
1361
1362         intel_engine_setup_common(engine);
1363
1364         timeline = i915_timeline_create(engine->i915, engine->name);
1365         if (IS_ERR(timeline)) {
1366                 err = PTR_ERR(timeline);
1367                 goto err;
1368         }
1369
1370         ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
1371         i915_timeline_put(timeline);
1372         if (IS_ERR(ring)) {
1373                 err = PTR_ERR(ring);
1374                 goto err;
1375         }
1376
1377         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1378         err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
1379         if (err)
1380                 goto err_ring;
1381
1382         GEM_BUG_ON(engine->buffer);
1383         engine->buffer = ring;
1384
1385         err = intel_engine_init_common(engine);
1386         if (err)
1387                 goto err_unpin;
1388
1389         return 0;
1390
1391 err_unpin:
1392         intel_ring_unpin(ring);
1393 err_ring:
1394         intel_ring_free(ring);
1395 err:
1396         intel_engine_cleanup_common(engine);
1397         return err;
1398 }
1399
1400 void intel_engine_cleanup(struct intel_engine_cs *engine)
1401 {
1402         struct drm_i915_private *dev_priv = engine->i915;
1403
1404         WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1405                 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
1406
1407         intel_ring_unpin(engine->buffer);
1408         intel_ring_free(engine->buffer);
1409
1410         if (engine->cleanup)
1411                 engine->cleanup(engine);
1412
1413         intel_engine_cleanup_common(engine);
1414
1415         dev_priv->engine[engine->id] = NULL;
1416         kfree(engine);
1417 }
1418
1419 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1420 {
1421         struct intel_engine_cs *engine;
1422         enum intel_engine_id id;
1423
1424         /* Restart from the beginning of the rings for convenience */
1425         for_each_engine(engine, dev_priv, id)
1426                 intel_ring_reset(engine->buffer, 0);
1427 }
1428
1429 static int load_pd_dir(struct i915_request *rq,
1430                        const struct i915_hw_ppgtt *ppgtt)
1431 {
1432         const struct intel_engine_cs * const engine = rq->engine;
1433         u32 *cs;
1434
1435         cs = intel_ring_begin(rq, 6);
1436         if (IS_ERR(cs))
1437                 return PTR_ERR(cs);
1438
1439         *cs++ = MI_LOAD_REGISTER_IMM(1);
1440         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1441         *cs++ = PP_DIR_DCLV_2G;
1442
1443         *cs++ = MI_LOAD_REGISTER_IMM(1);
1444         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1445         *cs++ = ppgtt->pd.base.ggtt_offset << 10;
1446
1447         intel_ring_advance(rq, cs);
1448
1449         return 0;
1450 }
1451
1452 static inline int mi_set_context(struct i915_request *rq, u32 flags)
1453 {
1454         struct drm_i915_private *i915 = rq->i915;
1455         struct intel_engine_cs *engine = rq->engine;
1456         enum intel_engine_id id;
1457         const int num_rings =
1458                 /* Use an extended w/a on gen7 if signalling from other rings */
1459                 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
1460                 INTEL_INFO(i915)->num_rings - 1 :
1461                 0;
1462         bool force_restore = false;
1463         int len;
1464         u32 *cs;
1465
1466         flags |= MI_MM_SPACE_GTT;
1467         if (IS_HASWELL(i915))
1468                 /* These flags are for resource streamer on HSW+ */
1469                 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1470         else
1471                 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1472
1473         len = 4;
1474         if (IS_GEN7(i915))
1475                 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1476         if (flags & MI_FORCE_RESTORE) {
1477                 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
1478                 flags &= ~MI_FORCE_RESTORE;
1479                 force_restore = true;
1480                 len += 2;
1481         }
1482
1483         cs = intel_ring_begin(rq, len);
1484         if (IS_ERR(cs))
1485                 return PTR_ERR(cs);
1486
1487         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1488         if (IS_GEN7(i915)) {
1489                 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1490                 if (num_rings) {
1491                         struct intel_engine_cs *signaller;
1492
1493                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1494                         for_each_engine(signaller, i915, id) {
1495                                 if (signaller == engine)
1496                                         continue;
1497
1498                                 *cs++ = i915_mmio_reg_offset(
1499                                            RING_PSMI_CTL(signaller->mmio_base));
1500                                 *cs++ = _MASKED_BIT_ENABLE(
1501                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1502                         }
1503                 }
1504         }
1505
1506         if (force_restore) {
1507                 /*
1508                  * The HW doesn't handle being told to restore the current
1509                  * context very well. Quite often it likes goes to go off and
1510                  * sulk, especially when it is meant to be reloading PP_DIR.
1511                  * A very simple fix to force the reload is to simply switch
1512                  * away from the current context and back again.
1513                  *
1514                  * Note that the kernel_context will contain random state
1515                  * following the INHIBIT_RESTORE. We accept this since we
1516                  * never use the kernel_context state; it is merely a
1517                  * placeholder we use to flush other contexts.
1518                  */
1519                 *cs++ = MI_SET_CONTEXT;
1520                 *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
1521                                                           engine)->state) |
1522                         MI_MM_SPACE_GTT |
1523                         MI_RESTORE_INHIBIT;
1524         }
1525
1526         *cs++ = MI_NOOP;
1527         *cs++ = MI_SET_CONTEXT;
1528         *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
1529         /*
1530          * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1531          * WaMiSetContext_Hang:snb,ivb,vlv
1532          */
1533         *cs++ = MI_NOOP;
1534
1535         if (IS_GEN7(i915)) {
1536                 if (num_rings) {
1537                         struct intel_engine_cs *signaller;
1538                         i915_reg_t last_reg = {}; /* keep gcc quiet */
1539
1540                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1541                         for_each_engine(signaller, i915, id) {
1542                                 if (signaller == engine)
1543                                         continue;
1544
1545                                 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1546                                 *cs++ = i915_mmio_reg_offset(last_reg);
1547                                 *cs++ = _MASKED_BIT_DISABLE(
1548                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1549                         }
1550
1551                         /* Insert a delay before the next switch! */
1552                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1553                         *cs++ = i915_mmio_reg_offset(last_reg);
1554                         *cs++ = i915_ggtt_offset(engine->scratch);
1555                         *cs++ = MI_NOOP;
1556                 }
1557                 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1558         }
1559
1560         intel_ring_advance(rq, cs);
1561
1562         return 0;
1563 }
1564
1565 static int remap_l3(struct i915_request *rq, int slice)
1566 {
1567         u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1568         int i;
1569
1570         if (!remap_info)
1571                 return 0;
1572
1573         cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1574         if (IS_ERR(cs))
1575                 return PTR_ERR(cs);
1576
1577         /*
1578          * Note: We do not worry about the concurrent register cacheline hang
1579          * here because no other code should access these registers other than
1580          * at initialization time.
1581          */
1582         *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1583         for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1584                 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1585                 *cs++ = remap_info[i];
1586         }
1587         *cs++ = MI_NOOP;
1588         intel_ring_advance(rq, cs);
1589
1590         return 0;
1591 }
1592
1593 static int switch_context(struct i915_request *rq)
1594 {
1595         struct intel_engine_cs *engine = rq->engine;
1596         struct i915_gem_context *ctx = rq->gem_context;
1597         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1598         unsigned int unwind_mm = 0;
1599         u32 hw_flags = 0;
1600         int ret, i;
1601
1602         lockdep_assert_held(&rq->i915->drm.struct_mutex);
1603         GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1604
1605         if (ppgtt) {
1606                 ret = load_pd_dir(rq, ppgtt);
1607                 if (ret)
1608                         goto err;
1609
1610                 if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) {
1611                         unwind_mm = intel_engine_flag(engine);
1612                         ppgtt->pd_dirty_rings &= ~unwind_mm;
1613                         hw_flags = MI_FORCE_RESTORE;
1614                 }
1615         }
1616
1617         if (rq->hw_context->state) {
1618                 GEM_BUG_ON(engine->id != RCS);
1619
1620                 /*
1621                  * The kernel context(s) is treated as pure scratch and is not
1622                  * expected to retain any state (as we sacrifice it during
1623                  * suspend and on resume it may be corrupted). This is ok,
1624                  * as nothing actually executes using the kernel context; it
1625                  * is purely used for flushing user contexts.
1626                  */
1627                 if (i915_gem_context_is_kernel(ctx))
1628                         hw_flags = MI_RESTORE_INHIBIT;
1629
1630                 ret = mi_set_context(rq, hw_flags);
1631                 if (ret)
1632                         goto err_mm;
1633         }
1634
1635         if (ctx->remap_slice) {
1636                 for (i = 0; i < MAX_L3_SLICES; i++) {
1637                         if (!(ctx->remap_slice & BIT(i)))
1638                                 continue;
1639
1640                         ret = remap_l3(rq, i);
1641                         if (ret)
1642                                 goto err_mm;
1643                 }
1644
1645                 ctx->remap_slice = 0;
1646         }
1647
1648         return 0;
1649
1650 err_mm:
1651         if (unwind_mm)
1652                 ppgtt->pd_dirty_rings |= unwind_mm;
1653 err:
1654         return ret;
1655 }
1656
1657 static int ring_request_alloc(struct i915_request *request)
1658 {
1659         int ret;
1660
1661         GEM_BUG_ON(!request->hw_context->pin_count);
1662
1663         /* Flush enough space to reduce the likelihood of waiting after
1664          * we start building the request - in which case we will just
1665          * have to repeat work.
1666          */
1667         request->reserved_space += LEGACY_REQUEST_SIZE;
1668
1669         ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1670         if (ret)
1671                 return ret;
1672
1673         ret = switch_context(request);
1674         if (ret)
1675                 return ret;
1676
1677         request->reserved_space -= LEGACY_REQUEST_SIZE;
1678         return 0;
1679 }
1680
1681 static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1682 {
1683         struct i915_request *target;
1684         long timeout;
1685
1686         lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1687
1688         if (intel_ring_update_space(ring) >= bytes)
1689                 return 0;
1690
1691         GEM_BUG_ON(list_empty(&ring->request_list));
1692         list_for_each_entry(target, &ring->request_list, ring_link) {
1693                 /* Would completion of this request free enough space? */
1694                 if (bytes <= __intel_ring_space(target->postfix,
1695                                                 ring->emit, ring->size))
1696                         break;
1697         }
1698
1699         if (WARN_ON(&target->ring_link == &ring->request_list))
1700                 return -ENOSPC;
1701
1702         timeout = i915_request_wait(target,
1703                                     I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1704                                     MAX_SCHEDULE_TIMEOUT);
1705         if (timeout < 0)
1706                 return timeout;
1707
1708         i915_request_retire_upto(target);
1709
1710         intel_ring_update_space(ring);
1711         GEM_BUG_ON(ring->space < bytes);
1712         return 0;
1713 }
1714
1715 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes)
1716 {
1717         GEM_BUG_ON(bytes > ring->effective_size);
1718         if (unlikely(bytes > ring->effective_size - ring->emit))
1719                 bytes += ring->size - ring->emit;
1720
1721         if (unlikely(bytes > ring->space)) {
1722                 int ret = wait_for_space(ring, bytes);
1723                 if (unlikely(ret))
1724                         return ret;
1725         }
1726
1727         GEM_BUG_ON(ring->space < bytes);
1728         return 0;
1729 }
1730
1731 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1732 {
1733         struct intel_ring *ring = rq->ring;
1734         const unsigned int remain_usable = ring->effective_size - ring->emit;
1735         const unsigned int bytes = num_dwords * sizeof(u32);
1736         unsigned int need_wrap = 0;
1737         unsigned int total_bytes;
1738         u32 *cs;
1739
1740         /* Packets must be qword aligned. */
1741         GEM_BUG_ON(num_dwords & 1);
1742
1743         total_bytes = bytes + rq->reserved_space;
1744         GEM_BUG_ON(total_bytes > ring->effective_size);
1745
1746         if (unlikely(total_bytes > remain_usable)) {
1747                 const int remain_actual = ring->size - ring->emit;
1748
1749                 if (bytes > remain_usable) {
1750                         /*
1751                          * Not enough space for the basic request. So need to
1752                          * flush out the remainder and then wait for
1753                          * base + reserved.
1754                          */
1755                         total_bytes += remain_actual;
1756                         need_wrap = remain_actual | 1;
1757                 } else  {
1758                         /*
1759                          * The base request will fit but the reserved space
1760                          * falls off the end. So we don't need an immediate
1761                          * wrap and only need to effectively wait for the
1762                          * reserved size from the start of ringbuffer.
1763                          */
1764                         total_bytes = rq->reserved_space + remain_actual;
1765                 }
1766         }
1767
1768         if (unlikely(total_bytes > ring->space)) {
1769                 int ret;
1770
1771                 /*
1772                  * Space is reserved in the ringbuffer for finalising the
1773                  * request, as that cannot be allowed to fail. During request
1774                  * finalisation, reserved_space is set to 0 to stop the
1775                  * overallocation and the assumption is that then we never need
1776                  * to wait (which has the risk of failing with EINTR).
1777                  *
1778                  * See also i915_request_alloc() and i915_request_add().
1779                  */
1780                 GEM_BUG_ON(!rq->reserved_space);
1781
1782                 ret = wait_for_space(ring, total_bytes);
1783                 if (unlikely(ret))
1784                         return ERR_PTR(ret);
1785         }
1786
1787         if (unlikely(need_wrap)) {
1788                 need_wrap &= ~1;
1789                 GEM_BUG_ON(need_wrap > ring->space);
1790                 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1791                 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
1792
1793                 /* Fill the tail with MI_NOOP */
1794                 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
1795                 ring->space -= need_wrap;
1796                 ring->emit = 0;
1797         }
1798
1799         GEM_BUG_ON(ring->emit > ring->size - bytes);
1800         GEM_BUG_ON(ring->space < bytes);
1801         cs = ring->vaddr + ring->emit;
1802         GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
1803         ring->emit += bytes;
1804         ring->space -= bytes;
1805
1806         return cs;
1807 }
1808
1809 /* Align the ring tail to a cacheline boundary */
1810 int intel_ring_cacheline_align(struct i915_request *rq)
1811 {
1812         int num_dwords;
1813         void *cs;
1814
1815         num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
1816         if (num_dwords == 0)
1817                 return 0;
1818
1819         num_dwords = CACHELINE_DWORDS - num_dwords;
1820         GEM_BUG_ON(num_dwords & 1);
1821
1822         cs = intel_ring_begin(rq, num_dwords);
1823         if (IS_ERR(cs))
1824                 return PTR_ERR(cs);
1825
1826         memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);
1827         intel_ring_advance(rq, cs);
1828
1829         GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));
1830         return 0;
1831 }
1832
1833 static void gen6_bsd_submit_request(struct i915_request *request)
1834 {
1835         struct drm_i915_private *dev_priv = request->i915;
1836
1837         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1838
1839        /* Every tail move must follow the sequence below */
1840
1841         /* Disable notification that the ring is IDLE. The GT
1842          * will then assume that it is busy and bring it out of rc6.
1843          */
1844         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1845                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1846
1847         /* Clear the context id. Here be magic! */
1848         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
1849
1850         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1851         if (__intel_wait_for_register_fw(dev_priv,
1852                                          GEN6_BSD_SLEEP_PSMI_CONTROL,
1853                                          GEN6_BSD_SLEEP_INDICATOR,
1854                                          0,
1855                                          1000, 0, NULL))
1856                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1857
1858         /* Now that the ring is fully powered up, update the tail */
1859         i9xx_submit_request(request);
1860
1861         /* Let the ring send IDLE messages to the GT again,
1862          * and so let it sleep to conserve power when idle.
1863          */
1864         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1865                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1866
1867         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1868 }
1869
1870 static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
1871 {
1872         u32 cmd, *cs;
1873
1874         cs = intel_ring_begin(rq, 4);
1875         if (IS_ERR(cs))
1876                 return PTR_ERR(cs);
1877
1878         cmd = MI_FLUSH_DW;
1879
1880         /* We always require a command barrier so that subsequent
1881          * commands, such as breadcrumb interrupts, are strictly ordered
1882          * wrt the contents of the write cache being flushed to memory
1883          * (and thus being coherent from the CPU).
1884          */
1885         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1886
1887         /*
1888          * Bspec vol 1c.5 - video engine command streamer:
1889          * "If ENABLED, all TLBs will be invalidated once the flush
1890          * operation is complete. This bit is only valid when the
1891          * Post-Sync Operation field is a value of 1h or 3h."
1892          */
1893         if (mode & EMIT_INVALIDATE)
1894                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1895
1896         *cs++ = cmd;
1897         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1898         *cs++ = 0;
1899         *cs++ = MI_NOOP;
1900         intel_ring_advance(rq, cs);
1901         return 0;
1902 }
1903
1904 static int
1905 hsw_emit_bb_start(struct i915_request *rq,
1906                   u64 offset, u32 len,
1907                   unsigned int dispatch_flags)
1908 {
1909         u32 *cs;
1910
1911         cs = intel_ring_begin(rq, 2);
1912         if (IS_ERR(cs))
1913                 return PTR_ERR(cs);
1914
1915         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1916                 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
1917                 (dispatch_flags & I915_DISPATCH_RS ?
1918                 MI_BATCH_RESOURCE_STREAMER : 0);
1919         /* bit0-7 is the length on GEN6+ */
1920         *cs++ = offset;
1921         intel_ring_advance(rq, cs);
1922
1923         return 0;
1924 }
1925
1926 static int
1927 gen6_emit_bb_start(struct i915_request *rq,
1928                    u64 offset, u32 len,
1929                    unsigned int dispatch_flags)
1930 {
1931         u32 *cs;
1932
1933         cs = intel_ring_begin(rq, 2);
1934         if (IS_ERR(cs))
1935                 return PTR_ERR(cs);
1936
1937         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1938                 0 : MI_BATCH_NON_SECURE_I965);
1939         /* bit0-7 is the length on GEN6+ */
1940         *cs++ = offset;
1941         intel_ring_advance(rq, cs);
1942
1943         return 0;
1944 }
1945
1946 /* Blitter support (SandyBridge+) */
1947
1948 static int gen6_ring_flush(struct i915_request *rq, u32 mode)
1949 {
1950         u32 cmd, *cs;
1951
1952         cs = intel_ring_begin(rq, 4);
1953         if (IS_ERR(cs))
1954                 return PTR_ERR(cs);
1955
1956         cmd = MI_FLUSH_DW;
1957
1958         /* We always require a command barrier so that subsequent
1959          * commands, such as breadcrumb interrupts, are strictly ordered
1960          * wrt the contents of the write cache being flushed to memory
1961          * (and thus being coherent from the CPU).
1962          */
1963         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1964
1965         /*
1966          * Bspec vol 1c.3 - blitter engine command streamer:
1967          * "If ENABLED, all TLBs will be invalidated once the flush
1968          * operation is complete. This bit is only valid when the
1969          * Post-Sync Operation field is a value of 1h or 3h."
1970          */
1971         if (mode & EMIT_INVALIDATE)
1972                 cmd |= MI_INVALIDATE_TLB;
1973         *cs++ = cmd;
1974         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1975         *cs++ = 0;
1976         *cs++ = MI_NOOP;
1977         intel_ring_advance(rq, cs);
1978
1979         return 0;
1980 }
1981
1982 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
1983                                        struct intel_engine_cs *engine)
1984 {
1985         int i;
1986
1987         if (!HAS_LEGACY_SEMAPHORES(dev_priv))
1988                 return;
1989
1990         GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
1991         engine->semaphore.sync_to = gen6_ring_sync_to;
1992         engine->semaphore.signal = gen6_signal;
1993
1994         /*
1995          * The current semaphore is only applied on pre-gen8
1996          * platform.  And there is no VCS2 ring on the pre-gen8
1997          * platform. So the semaphore between RCS and VCS2 is
1998          * initialized as INVALID.
1999          */
2000         for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
2001                 static const struct {
2002                         u32 wait_mbox;
2003                         i915_reg_t mbox_reg;
2004                 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
2005                         [RCS_HW] = {
2006                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
2007                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
2008                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2009                         },
2010                         [VCS_HW] = {
2011                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
2012                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
2013                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2014                         },
2015                         [BCS_HW] = {
2016                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
2017                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
2018                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2019                         },
2020                         [VECS_HW] = {
2021                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2022                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2023                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2024                         },
2025                 };
2026                 u32 wait_mbox;
2027                 i915_reg_t mbox_reg;
2028
2029                 if (i == engine->hw_id) {
2030                         wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2031                         mbox_reg = GEN6_NOSYNC;
2032                 } else {
2033                         wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
2034                         mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
2035                 }
2036
2037                 engine->semaphore.mbox.wait[i] = wait_mbox;
2038                 engine->semaphore.mbox.signal[i] = mbox_reg;
2039         }
2040 }
2041
2042 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2043                                 struct intel_engine_cs *engine)
2044 {
2045         if (INTEL_GEN(dev_priv) >= 6) {
2046                 engine->irq_enable = gen6_irq_enable;
2047                 engine->irq_disable = gen6_irq_disable;
2048                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2049         } else if (INTEL_GEN(dev_priv) >= 5) {
2050                 engine->irq_enable = gen5_irq_enable;
2051                 engine->irq_disable = gen5_irq_disable;
2052                 engine->irq_seqno_barrier = gen5_seqno_barrier;
2053         } else if (INTEL_GEN(dev_priv) >= 3) {
2054                 engine->irq_enable = i9xx_irq_enable;
2055                 engine->irq_disable = i9xx_irq_disable;
2056         } else {
2057                 engine->irq_enable = i8xx_irq_enable;
2058                 engine->irq_disable = i8xx_irq_disable;
2059         }
2060 }
2061
2062 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
2063 {
2064         engine->submit_request = i9xx_submit_request;
2065         engine->cancel_requests = cancel_requests;
2066
2067         engine->park = NULL;
2068         engine->unpark = NULL;
2069 }
2070
2071 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
2072 {
2073         i9xx_set_default_submission(engine);
2074         engine->submit_request = gen6_bsd_submit_request;
2075 }
2076
2077 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2078                                       struct intel_engine_cs *engine)
2079 {
2080         /* gen8+ are only supported with execlists */
2081         GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
2082
2083         intel_ring_init_irq(dev_priv, engine);
2084         intel_ring_init_semaphores(dev_priv, engine);
2085
2086         engine->init_hw = init_ring_common;
2087         engine->reset.prepare = reset_prepare;
2088         engine->reset.reset = reset_ring;
2089         engine->reset.finish = reset_finish;
2090
2091         engine->context_pin = intel_ring_context_pin;
2092         engine->request_alloc = ring_request_alloc;
2093
2094         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
2095         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
2096         if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
2097                 int num_rings;
2098
2099                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2100
2101                 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
2102                 engine->emit_breadcrumb_sz += num_rings * 3;
2103                 if (num_rings & 1)
2104                         engine->emit_breadcrumb_sz++;
2105         }
2106
2107         engine->set_default_submission = i9xx_set_default_submission;
2108
2109         if (INTEL_GEN(dev_priv) >= 6)
2110                 engine->emit_bb_start = gen6_emit_bb_start;
2111         else if (INTEL_GEN(dev_priv) >= 4)
2112                 engine->emit_bb_start = i965_emit_bb_start;
2113         else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2114                 engine->emit_bb_start = i830_emit_bb_start;
2115         else
2116                 engine->emit_bb_start = i915_emit_bb_start;
2117 }
2118
2119 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2120 {
2121         struct drm_i915_private *dev_priv = engine->i915;
2122         int ret;
2123
2124         intel_ring_default_vfuncs(dev_priv, engine);
2125
2126         if (HAS_L3_DPF(dev_priv))
2127                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2128
2129         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2130
2131         if (INTEL_GEN(dev_priv) >= 6) {
2132                 engine->init_context = intel_rcs_ctx_init;
2133                 engine->emit_flush = gen7_render_ring_flush;
2134                 if (IS_GEN6(dev_priv))
2135                         engine->emit_flush = gen6_render_ring_flush;
2136         } else if (IS_GEN5(dev_priv)) {
2137                 engine->emit_flush = gen4_render_ring_flush;
2138         } else {
2139                 if (INTEL_GEN(dev_priv) < 4)
2140                         engine->emit_flush = gen2_render_ring_flush;
2141                 else
2142                         engine->emit_flush = gen4_render_ring_flush;
2143                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2144         }
2145
2146         if (IS_HASWELL(dev_priv))
2147                 engine->emit_bb_start = hsw_emit_bb_start;
2148
2149         engine->init_hw = init_render_ring;
2150
2151         ret = intel_init_ring_buffer(engine);
2152         if (ret)
2153                 return ret;
2154
2155         if (INTEL_GEN(dev_priv) >= 6) {
2156                 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2157                 if (ret)
2158                         return ret;
2159         } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2160                 ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
2161                 if (ret)
2162                         return ret;
2163         }
2164
2165         return 0;
2166 }
2167
2168 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2169 {
2170         struct drm_i915_private *dev_priv = engine->i915;
2171
2172         intel_ring_default_vfuncs(dev_priv, engine);
2173
2174         if (INTEL_GEN(dev_priv) >= 6) {
2175                 /* gen6 bsd needs a special wa for tail updates */
2176                 if (IS_GEN6(dev_priv))
2177                         engine->set_default_submission = gen6_bsd_set_default_submission;
2178                 engine->emit_flush = gen6_bsd_ring_flush;
2179                 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2180         } else {
2181                 engine->emit_flush = bsd_ring_flush;
2182                 if (IS_GEN5(dev_priv))
2183                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2184                 else
2185                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2186         }
2187
2188         return intel_init_ring_buffer(engine);
2189 }
2190
2191 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2192 {
2193         struct drm_i915_private *dev_priv = engine->i915;
2194
2195         intel_ring_default_vfuncs(dev_priv, engine);
2196
2197         engine->emit_flush = gen6_ring_flush;
2198         engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2199
2200         return intel_init_ring_buffer(engine);
2201 }
2202
2203 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2204 {
2205         struct drm_i915_private *dev_priv = engine->i915;
2206
2207         intel_ring_default_vfuncs(dev_priv, engine);
2208
2209         engine->emit_flush = gen6_ring_flush;
2210         engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2211         engine->irq_enable = hsw_vebox_irq_enable;
2212         engine->irq_disable = hsw_vebox_irq_disable;
2213
2214         return intel_init_ring_buffer(engine);
2215 }