drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34
  35 #include "i915_drv.h"
  36 #include "i915_gem_render_state.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39 #include "intel_workarounds.h"
  40
  41 /* Rough estimate of the typical request size, performing a flush,
  42  * set-context and then emitting the batch.
  43  */
  44 #define LEGACY_REQUEST_SIZE 200
  45
  46 static unsigned int __intel_ring_space(unsigned int head,
  47                                        unsigned int tail,
  48                                        unsigned int size)
  49 {
  50         /*
  51          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
  52          * same cacheline, the Head Pointer must not be greater than the Tail
  53          * Pointer."
  54          */
  55         GEM_BUG_ON(!is_power_of_2(size));
  56         return (head - tail - CACHELINE_BYTES) & (size - 1);
  57 }
  58
  59 unsigned int intel_ring_update_space(struct intel_ring *ring)
  60 {
  61         unsigned int space;
  62
  63         space = __intel_ring_space(ring->head, ring->emit, ring->size);
  64
  65         ring->space = space;
  66         return space;
  67 }
  68
  69 static int
  70 gen2_render_ring_flush(struct i915_request *rq, u32 mode)
  71 {
  72         u32 cmd, *cs;
  73
  74         cmd = MI_FLUSH;
  75
  76         if (mode & EMIT_INVALIDATE)
  77                 cmd |= MI_READ_FLUSH;
  78
  79         cs = intel_ring_begin(rq, 2);
  80         if (IS_ERR(cs))
  81                 return PTR_ERR(cs);
  82
  83         *cs++ = cmd;
  84         *cs++ = MI_NOOP;
  85         intel_ring_advance(rq, cs);
  86
  87         return 0;
  88 }
  89
  90 static int
  91 gen4_render_ring_flush(struct i915_request *rq, u32 mode)
  92 {
  93         u32 cmd, *cs;
  94
  95         /*
  96          * read/write caches:
  97          *
  98          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  99          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 100          * also flushed at 2d versus 3d pipeline switches.
 101          *
 102          * read-only caches:
 103          *
 104          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 105          * MI_READ_FLUSH is set, and is always flushed on 965.
 106          *
 107          * I915_GEM_DOMAIN_COMMAND may not exist?
 108          *
 109          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 110          * invalidated when MI_EXE_FLUSH is set.
 111          *
 112          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 113          * invalidated with every MI_FLUSH.
 114          *
 115          * TLBs:
 116          *
 117          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 118          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 119          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 120          * are flushed at any MI_FLUSH.
 121          */
 122
 123         cmd = MI_FLUSH;
 124         if (mode & EMIT_INVALIDATE) {
 125                 cmd |= MI_EXE_FLUSH;
 126                 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915))
 127                         cmd |= MI_INVALIDATE_ISP;
 128         }
 129
 130         cs = intel_ring_begin(rq, 2);
 131         if (IS_ERR(cs))
 132                 return PTR_ERR(cs);
 133
 134         *cs++ = cmd;
 135         *cs++ = MI_NOOP;
 136         intel_ring_advance(rq, cs);
 137
 138         return 0;
 139 }
 140
 141 /*
 142  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 143  * implementing two workarounds on gen6.  From section 1.4.7.1
 144  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 145  *
 146  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 147  * produced by non-pipelined state commands), software needs to first
 148  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 149  * 0.
 150  *
 151  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 152  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 153  *
 154  * And the workaround for these two requires this workaround first:
 155  *
 156  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 157  * BEFORE the pipe-control with a post-sync op and no write-cache
 158  * flushes.
 159  *
 160  * And this last workaround is tricky because of the requirements on
 161  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 162  * volume 2 part 1:
 163  *
 164  *     "1 of the following must also be set:
 165  *      - Render Target Cache Flush Enable ([12] of DW1)
 166  *      - Depth Cache Flush Enable ([0] of DW1)
 167  *      - Stall at Pixel Scoreboard ([1] of DW1)
 168  *      - Depth Stall ([13] of DW1)
 169  *      - Post-Sync Operation ([13] of DW1)
 170  *      - Notify Enable ([8] of DW1)"
 171  *
 172  * The cache flushes require the workaround flush that triggered this
 173  * one, so we can't use it.  Depth stall would trigger the same.
 174  * Post-sync nonzero is what triggered this second workaround, so we
 175  * can't use that one either.  Notify enable is IRQs, which aren't
 176  * really our business.  That leaves only stall at scoreboard.
 177  */
 178 static int
 179 intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
 180 {
 181         u32 scratch_addr =
 182                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 183         u32 *cs;
 184
 185         cs = intel_ring_begin(rq, 6);
 186         if (IS_ERR(cs))
 187                 return PTR_ERR(cs);
 188
 189         *cs++ = GFX_OP_PIPE_CONTROL(5);
 190         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 191         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 192         *cs++ = 0; /* low dword */
 193         *cs++ = 0; /* high dword */
 194         *cs++ = MI_NOOP;
 195         intel_ring_advance(rq, cs);
 196
 197         cs = intel_ring_begin(rq, 6);
 198         if (IS_ERR(cs))
 199                 return PTR_ERR(cs);
 200
 201         *cs++ = GFX_OP_PIPE_CONTROL(5);
 202         *cs++ = PIPE_CONTROL_QW_WRITE;
 203         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 204         *cs++ = 0;
 205         *cs++ = 0;
 206         *cs++ = MI_NOOP;
 207         intel_ring_advance(rq, cs);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 214 {
 215         u32 scratch_addr =
 216                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 217         u32 *cs, flags = 0;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(rq);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (mode & EMIT_FLUSH) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (mode & EMIT_INVALIDATE) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         cs = intel_ring_begin(rq, 4);
 252         if (IS_ERR(cs))
 253                 return PTR_ERR(cs);
 254
 255         *cs++ = GFX_OP_PIPE_CONTROL(4);
 256         *cs++ = flags;
 257         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 258         *cs++ = 0;
 259         intel_ring_advance(rq, cs);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct i915_request *rq)
 266 {
 267         u32 *cs;
 268
 269         cs = intel_ring_begin(rq, 4);
 270         if (IS_ERR(cs))
 271                 return PTR_ERR(cs);
 272
 273         *cs++ = GFX_OP_PIPE_CONTROL(4);
 274         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 275         *cs++ = 0;
 276         *cs++ = 0;
 277         intel_ring_advance(rq, cs);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 284 {
 285         u32 scratch_addr =
 286                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 287         u32 *cs, flags = 0;
 288
 289         /*
 290          * Ensure that any following seqno writes only happen when the render
 291          * cache is indeed flushed.
 292          *
 293          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 294          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 295          * don't try to be clever and just set it unconditionally.
 296          */
 297         flags |= PIPE_CONTROL_CS_STALL;
 298
 299         /* Just flush everything.  Experiments have shown that reducing the
 300          * number of bits based on the write domains has little performance
 301          * impact.
 302          */
 303         if (mode & EMIT_FLUSH) {
 304                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 305                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 306                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 307                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 308         }
 309         if (mode & EMIT_INVALIDATE) {
 310                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 311                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 312                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 324
 325                 /* Workaround: we must issue a pipe_control with CS-stall bit
 326                  * set before a pipe_control command that has the state cache
 327                  * invalidate bit set. */
 328                 gen7_render_ring_cs_stall_wa(rq);
 329         }
 330
 331         cs = intel_ring_begin(rq, 4);
 332         if (IS_ERR(cs))
 333                 return PTR_ERR(cs);
 334
 335         *cs++ = GFX_OP_PIPE_CONTROL(4);
 336         *cs++ = flags;
 337         *cs++ = scratch_addr;
 338         *cs++ = 0;
 339         intel_ring_advance(rq, cs);
 340
 341         return 0;
 342 }
 343
 344 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 345 {
 346         struct drm_i915_private *dev_priv = engine->i915;
 347         u32 addr;
 348
 349         addr = dev_priv->status_page_dmah->busaddr;
 350         if (INTEL_GEN(dev_priv) >= 4)
 351                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 352         I915_WRITE(HWS_PGA, addr);
 353 }
 354
 355 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 356 {
 357         struct drm_i915_private *dev_priv = engine->i915;
 358         i915_reg_t mmio;
 359
 360         /* The ring status page addresses are no longer next to the rest of
 361          * the ring registers as of gen7.
 362          */
 363         if (IS_GEN7(dev_priv)) {
 364                 switch (engine->id) {
 365                 /*
 366                  * No more rings exist on Gen7. Default case is only to shut up
 367                  * gcc switch check warning.
 368                  */
 369                 default:
 370                         GEM_BUG_ON(engine->id);
 371                 case RCS:
 372                         mmio = RENDER_HWS_PGA_GEN7;
 373                         break;
 374                 case BCS:
 375                         mmio = BLT_HWS_PGA_GEN7;
 376                         break;
 377                 case VCS:
 378                         mmio = BSD_HWS_PGA_GEN7;
 379                         break;
 380                 case VECS:
 381                         mmio = VEBOX_HWS_PGA_GEN7;
 382                         break;
 383                 }
 384         } else if (IS_GEN6(dev_priv)) {
 385                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 386         } else {
 387                 mmio = RING_HWS_PGA(engine->mmio_base);
 388         }
 389
 390         if (INTEL_GEN(dev_priv) >= 6)
 391                 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
 392
 393         I915_WRITE(mmio, engine->status_page.ggtt_offset);
 394         POSTING_READ(mmio);
 395
 396         /* Flush the TLB for this page */
 397         if (IS_GEN(dev_priv, 6, 7)) {
 398                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 399
 400                 /* ring should be idle before issuing a sync flush*/
 401                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 402
 403                 I915_WRITE(reg,
 404                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 405                                               INSTPM_SYNC_FLUSH));
 406                 if (intel_wait_for_register(dev_priv,
 407                                             reg, INSTPM_SYNC_FLUSH, 0,
 408                                             1000))
 409                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 410                                   engine->name);
 411         }
 412 }
 413
 414 static bool stop_ring(struct intel_engine_cs *engine)
 415 {
 416         struct drm_i915_private *dev_priv = engine->i915;
 417
 418         if (INTEL_GEN(dev_priv) > 2) {
 419                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 420                 if (intel_wait_for_register(dev_priv,
 421                                             RING_MI_MODE(engine->mmio_base),
 422                                             MODE_IDLE,
 423                                             MODE_IDLE,
 424                                             1000)) {
 425                         DRM_ERROR("%s : timed out trying to stop ring\n",
 426                                   engine->name);
 427                         /* Sometimes we observe that the idle flag is not
 428                          * set even though the ring is empty. So double
 429                          * check before giving up.
 430                          */
 431                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 432                                 return false;
 433                 }
 434         }
 435
 436         I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
 437
 438         I915_WRITE_HEAD(engine, 0);
 439         I915_WRITE_TAIL(engine, 0);
 440
 441         /* The ring must be empty before it is disabled */
 442         I915_WRITE_CTL(engine, 0);
 443
 444         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 445 }
 446
 447 static int init_ring_common(struct intel_engine_cs *engine)
 448 {
 449         struct drm_i915_private *dev_priv = engine->i915;
 450         struct intel_ring *ring = engine->buffer;
 451         int ret = 0;
 452
 453         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 454
 455         if (!stop_ring(engine)) {
 456                 /* G45 ring initialization often fails to reset head to zero */
 457                 DRM_DEBUG_DRIVER("%s head not reset to zero "
 458                                 "ctl %08x head %08x tail %08x start %08x\n",
 459                                 engine->name,
 460                                 I915_READ_CTL(engine),
 461                                 I915_READ_HEAD(engine),
 462                                 I915_READ_TAIL(engine),
 463                                 I915_READ_START(engine));
 464
 465                 if (!stop_ring(engine)) {
 466                         DRM_ERROR("failed to set %s head to zero "
 467                                   "ctl %08x head %08x tail %08x start %08x\n",
 468                                   engine->name,
 469                                   I915_READ_CTL(engine),
 470                                   I915_READ_HEAD(engine),
 471                                   I915_READ_TAIL(engine),
 472                                   I915_READ_START(engine));
 473                         ret = -EIO;
 474                         goto out;
 475                 }
 476         }
 477
 478         if (HWS_NEEDS_PHYSICAL(dev_priv))
 479                 ring_setup_phys_status_page(engine);
 480         else
 481                 intel_ring_setup_status_page(engine);
 482
 483         intel_engine_reset_breadcrumbs(engine);
 484
 485         /* Enforce ordering by reading HEAD register back */
 486         I915_READ_HEAD(engine);
 487
 488         /* Initialize the ring. This must happen _after_ we've cleared the ring
 489          * registers with the above sequence (the readback of the HEAD registers
 490          * also enforces ordering), otherwise the hw might lose the new ring
 491          * register values. */
 492         I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
 493
 494         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 495         if (I915_READ_HEAD(engine))
 496                 DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
 497                                  engine->name, I915_READ_HEAD(engine));
 498
 499         intel_ring_update_space(ring);
 500         I915_WRITE_HEAD(engine, ring->head);
 501         I915_WRITE_TAIL(engine, ring->tail);
 502         (void)I915_READ_TAIL(engine);
 503
 504         I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 505
 506         /* If the head is still not zero, the ring is dead */
 507         if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
 508                                     RING_VALID, RING_VALID,
 509                                     50)) {
 510                 DRM_ERROR("%s initialization failed "
 511                           "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
 512                           engine->name,
 513                           I915_READ_CTL(engine),
 514                           I915_READ_CTL(engine) & RING_VALID,
 515                           I915_READ_HEAD(engine), ring->head,
 516                           I915_READ_TAIL(engine), ring->tail,
 517                           I915_READ_START(engine),
 518                           i915_ggtt_offset(ring->vma));
 519                 ret = -EIO;
 520                 goto out;
 521         }
 522
 523         intel_engine_init_hangcheck(engine);
 524
 525         if (INTEL_GEN(dev_priv) > 2)
 526                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 527
 528 out:
 529         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 530
 531         return ret;
 532 }
 533
 534 static struct i915_request *reset_prepare(struct intel_engine_cs *engine)
 535 {
 536         intel_engine_stop_cs(engine);
 537
 538         if (engine->irq_seqno_barrier)
 539                 engine->irq_seqno_barrier(engine);
 540
 541         return i915_gem_find_active_request(engine);
 542 }
 543
 544 static void reset_ring(struct intel_engine_cs *engine,
 545                        struct i915_request *request)
 546 {
 547         GEM_TRACE("%s seqno=%x\n",
 548                   engine->name, request ? request->global_seqno : 0);
 549
 550         /*
 551          * RC6 must be prevented until the reset is complete and the engine
 552          * reinitialised. If it occurs in the middle of this sequence, the
 553          * state written to/loaded from the power context is ill-defined (e.g.
 554          * the PP_BASE_DIR may be lost).
 555          */
 556         assert_forcewakes_active(engine->i915, FORCEWAKE_ALL);
 557
 558         /*
 559          * Try to restore the logical GPU state to match the continuation
 560          * of the request queue. If we skip the context/PD restore, then
 561          * the next request may try to execute assuming that its context
 562          * is valid and loaded on the GPU and so may try to access invalid
 563          * memory, prompting repeated GPU hangs.
 564          *
 565          * If the request was guilty, we still restore the logical state
 566          * in case the next request requires it (e.g. the aliasing ppgtt),
 567          * but skip over the hung batch.
 568          *
 569          * If the request was innocent, we try to replay the request with
 570          * the restored context.
 571          */
 572         if (request) {
 573                 struct drm_i915_private *dev_priv = request->i915;
 574                 struct intel_context *ce = request->hw_context;
 575                 struct i915_hw_ppgtt *ppgtt;
 576
 577                 if (ce->state) {
 578                         I915_WRITE(CCID,
 579                                    i915_ggtt_offset(ce->state) |
 580                                    BIT(8) /* must be set! */ |
 581                                    CCID_EXTENDED_STATE_SAVE |
 582                                    CCID_EXTENDED_STATE_RESTORE |
 583                                    CCID_EN);
 584                 }
 585
 586                 ppgtt = request->gem_context->ppgtt ?: engine->i915->mm.aliasing_ppgtt;
 587                 if (ppgtt) {
 588                         u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
 589
 590                         I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
 591                         I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset);
 592
 593                         /* Wait for the PD reload to complete */
 594                         if (intel_wait_for_register(dev_priv,
 595                                                     RING_PP_DIR_BASE(engine),
 596                                                     BIT(0), 0,
 597                                                     10))
 598                                 DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n");
 599
 600                         ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
 601                 }
 602
 603                 /* If the rq hung, jump to its breadcrumb and skip the batch */
 604                 if (request->fence.error == -EIO)
 605                         request->ring->head = request->postfix;
 606         } else {
 607                 engine->legacy_active_context = NULL;
 608                 engine->legacy_active_ppgtt = NULL;
 609         }
 610 }
 611
 612 static void reset_finish(struct intel_engine_cs *engine)
 613 {
 614 }
 615
 616 static int intel_rcs_ctx_init(struct i915_request *rq)
 617 {
 618         int ret;
 619
 620         ret = intel_ctx_workarounds_emit(rq);
 621         if (ret != 0)
 622                 return ret;
 623
 624         ret = i915_gem_render_state_emit(rq);
 625         if (ret)
 626                 return ret;
 627
 628         return 0;
 629 }
 630
 631 static int init_render_ring(struct intel_engine_cs *engine)
 632 {
 633         struct drm_i915_private *dev_priv = engine->i915;
 634         int ret = init_ring_common(engine);
 635         if (ret)
 636                 return ret;
 637
 638         intel_whitelist_workarounds_apply(engine);
 639
 640         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 641         if (IS_GEN(dev_priv, 4, 6))
 642                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 643
 644         /* We need to disable the AsyncFlip performance optimisations in order
 645          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 646          * programmed to '1' on all products.
 647          *
 648          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 649          */
 650         if (IS_GEN(dev_priv, 6, 7))
 651                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 652
 653         /* Required for the hardware to program scanline values for waiting */
 654         /* WaEnableFlushTlbInvalidationMode:snb */
 655         if (IS_GEN6(dev_priv))
 656                 I915_WRITE(GFX_MODE,
 657                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 658
 659         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 660         if (IS_GEN7(dev_priv))
 661                 I915_WRITE(GFX_MODE_GEN7,
 662                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 663                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 664
 665         if (IS_GEN6(dev_priv)) {
 666                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 667                  * "If this bit is set, STCunit will have LRA as replacement
 668                  *  policy. [...] This bit must be reset.  LRA replacement
 669                  *  policy is not supported."
 670                  */
 671                 I915_WRITE(CACHE_MODE_0,
 672                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 673         }
 674
 675         if (IS_GEN(dev_priv, 6, 7))
 676                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 677
 678         if (INTEL_GEN(dev_priv) >= 6)
 679                 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 680
 681         return 0;
 682 }
 683
 684 static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
 685 {
 686         struct drm_i915_private *dev_priv = rq->i915;
 687         struct intel_engine_cs *engine;
 688         enum intel_engine_id id;
 689         int num_rings = 0;
 690
 691         for_each_engine(engine, dev_priv, id) {
 692                 i915_reg_t mbox_reg;
 693
 694                 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
 695                         continue;
 696
 697                 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
 698                 if (i915_mmio_reg_valid(mbox_reg)) {
 699                         *cs++ = MI_LOAD_REGISTER_IMM(1);
 700                         *cs++ = i915_mmio_reg_offset(mbox_reg);
 701                         *cs++ = rq->global_seqno;
 702                         num_rings++;
 703                 }
 704         }
 705         if (num_rings & 1)
 706                 *cs++ = MI_NOOP;
 707
 708         return cs;
 709 }
 710
 711 static void cancel_requests(struct intel_engine_cs *engine)
 712 {
 713         struct i915_request *request;
 714         unsigned long flags;
 715
 716         spin_lock_irqsave(&engine->timeline.lock, flags);
 717
 718         /* Mark all submitted requests as skipped. */
 719         list_for_each_entry(request, &engine->timeline.requests, link) {
 720                 GEM_BUG_ON(!request->global_seqno);
 721                 if (!i915_request_completed(request))
 722                         dma_fence_set_error(&request->fence, -EIO);
 723         }
 724         /* Remaining _unready_ requests will be nop'ed when submitted */
 725
 726         spin_unlock_irqrestore(&engine->timeline.lock, flags);
 727 }
 728
 729 static void i9xx_submit_request(struct i915_request *request)
 730 {
 731         struct drm_i915_private *dev_priv = request->i915;
 732
 733         i915_request_submit(request);
 734
 735         I915_WRITE_TAIL(request->engine,
 736                         intel_ring_set_tail(request->ring, request->tail));
 737 }
 738
 739 static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 740 {
 741         *cs++ = MI_STORE_DWORD_INDEX;
 742         *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
 743         *cs++ = rq->global_seqno;
 744         *cs++ = MI_USER_INTERRUPT;
 745
 746         rq->tail = intel_ring_offset(rq, cs);
 747         assert_ring_tail_valid(rq->ring, rq->tail);
 748 }
 749
 750 static const int i9xx_emit_breadcrumb_sz = 4;
 751
 752 static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 753 {
 754         return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
 755 }
 756
 757 static int
 758 gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal)
 759 {
 760         u32 dw1 = MI_SEMAPHORE_MBOX |
 761                   MI_SEMAPHORE_COMPARE |
 762                   MI_SEMAPHORE_REGISTER;
 763         u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
 764         u32 *cs;
 765
 766         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 767
 768         cs = intel_ring_begin(rq, 4);
 769         if (IS_ERR(cs))
 770                 return PTR_ERR(cs);
 771
 772         *cs++ = dw1 | wait_mbox;
 773         /* Throughout all of the GEM code, seqno passed implies our current
 774          * seqno is >= the last seqno executed. However for hardware the
 775          * comparison is strictly greater than.
 776          */
 777         *cs++ = signal->global_seqno - 1;
 778         *cs++ = 0;
 779         *cs++ = MI_NOOP;
 780         intel_ring_advance(rq, cs);
 781
 782         return 0;
 783 }
 784
 785 static void
 786 gen5_seqno_barrier(struct intel_engine_cs *engine)
 787 {
 788         /* MI_STORE are internally buffered by the GPU and not flushed
 789          * either by MI_FLUSH or SyncFlush or any other combination of
 790          * MI commands.
 791          *
 792          * "Only the submission of the store operation is guaranteed.
 793          * The write result will be complete (coherent) some time later
 794          * (this is practically a finite period but there is no guaranteed
 795          * latency)."
 796          *
 797          * Empirically, we observe that we need a delay of at least 75us to
 798          * be sure that the seqno write is visible by the CPU.
 799          */
 800         usleep_range(125, 250);
 801 }
 802
 803 static void
 804 gen6_seqno_barrier(struct intel_engine_cs *engine)
 805 {
 806         struct drm_i915_private *dev_priv = engine->i915;
 807
 808         /* Workaround to force correct ordering between irq and seqno writes on
 809          * ivb (and maybe also on snb) by reading from a CS register (like
 810          * ACTHD) before reading the status page.
 811          *
 812          * Note that this effectively stalls the read by the time it takes to
 813          * do a memory transaction, which more or less ensures that the write
 814          * from the GPU has sufficient time to invalidate the CPU cacheline.
 815          * Alternatively we could delay the interrupt from the CS ring to give
 816          * the write time to land, but that would incur a delay after every
 817          * batch i.e. much more frequent than a delay when waiting for the
 818          * interrupt (with the same net latency).
 819          *
 820          * Also note that to prevent whole machine hangs on gen7, we have to
 821          * take the spinlock to guard against concurrent cacheline access.
 822          */
 823         spin_lock_irq(&dev_priv->uncore.lock);
 824         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
 825         spin_unlock_irq(&dev_priv->uncore.lock);
 826 }
 827
 828 static void
 829 gen5_irq_enable(struct intel_engine_cs *engine)
 830 {
 831         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
 832 }
 833
 834 static void
 835 gen5_irq_disable(struct intel_engine_cs *engine)
 836 {
 837         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
 838 }
 839
 840 static void
 841 i9xx_irq_enable(struct intel_engine_cs *engine)
 842 {
 843         struct drm_i915_private *dev_priv = engine->i915;
 844
 845         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 846         I915_WRITE(IMR, dev_priv->irq_mask);
 847         POSTING_READ_FW(RING_IMR(engine->mmio_base));
 848 }
 849
 850 static void
 851 i9xx_irq_disable(struct intel_engine_cs *engine)
 852 {
 853         struct drm_i915_private *dev_priv = engine->i915;
 854
 855         dev_priv->irq_mask |= engine->irq_enable_mask;
 856         I915_WRITE(IMR, dev_priv->irq_mask);
 857 }
 858
 859 static void
 860 i8xx_irq_enable(struct intel_engine_cs *engine)
 861 {
 862         struct drm_i915_private *dev_priv = engine->i915;
 863
 864         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 865         I915_WRITE16(IMR, dev_priv->irq_mask);
 866         POSTING_READ16(RING_IMR(engine->mmio_base));
 867 }
 868
 869 static void
 870 i8xx_irq_disable(struct intel_engine_cs *engine)
 871 {
 872         struct drm_i915_private *dev_priv = engine->i915;
 873
 874         dev_priv->irq_mask |= engine->irq_enable_mask;
 875         I915_WRITE16(IMR, dev_priv->irq_mask);
 876 }
 877
 878 static int
 879 bsd_ring_flush(struct i915_request *rq, u32 mode)
 880 {
 881         u32 *cs;
 882
 883         cs = intel_ring_begin(rq, 2);
 884         if (IS_ERR(cs))
 885                 return PTR_ERR(cs);
 886
 887         *cs++ = MI_FLUSH;
 888         *cs++ = MI_NOOP;
 889         intel_ring_advance(rq, cs);
 890         return 0;
 891 }
 892
 893 static void
 894 gen6_irq_enable(struct intel_engine_cs *engine)
 895 {
 896         struct drm_i915_private *dev_priv = engine->i915;
 897
 898         I915_WRITE_IMR(engine,
 899                        ~(engine->irq_enable_mask |
 900                          engine->irq_keep_mask));
 901         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 902 }
 903
 904 static void
 905 gen6_irq_disable(struct intel_engine_cs *engine)
 906 {
 907         struct drm_i915_private *dev_priv = engine->i915;
 908
 909         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 910         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
 911 }
 912
 913 static void
 914 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
 915 {
 916         struct drm_i915_private *dev_priv = engine->i915;
 917
 918         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
 919         gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
 920 }
 921
 922 static void
 923 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
 924 {
 925         struct drm_i915_private *dev_priv = engine->i915;
 926
 927         I915_WRITE_IMR(engine, ~0);
 928         gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 929 }
 930
 931 static int
 932 i965_emit_bb_start(struct i915_request *rq,
 933                    u64 offset, u32 length,
 934                    unsigned int dispatch_flags)
 935 {
 936         u32 *cs;
 937
 938         cs = intel_ring_begin(rq, 2);
 939         if (IS_ERR(cs))
 940                 return PTR_ERR(cs);
 941
 942         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
 943                 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
 944         *cs++ = offset;
 945         intel_ring_advance(rq, cs);
 946
 947         return 0;
 948 }
 949
 950 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 951 #define I830_BATCH_LIMIT (256*1024)
 952 #define I830_TLB_ENTRIES (2)
 953 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 954 static int
 955 i830_emit_bb_start(struct i915_request *rq,
 956                    u64 offset, u32 len,
 957                    unsigned int dispatch_flags)
 958 {
 959         u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
 960
 961         cs = intel_ring_begin(rq, 6);
 962         if (IS_ERR(cs))
 963                 return PTR_ERR(cs);
 964
 965         /* Evict the invalid PTE TLBs */
 966         *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
 967         *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
 968         *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
 969         *cs++ = cs_offset;
 970         *cs++ = 0xdeadbeef;
 971         *cs++ = MI_NOOP;
 972         intel_ring_advance(rq, cs);
 973
 974         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
 975                 if (len > I830_BATCH_LIMIT)
 976                         return -ENOSPC;
 977
 978                 cs = intel_ring_begin(rq, 6 + 2);
 979                 if (IS_ERR(cs))
 980                         return PTR_ERR(cs);
 981
 982                 /* Blit the batch (which has now all relocs applied) to the
 983                  * stable batch scratch bo area (so that the CS never
 984                  * stumbles over its tlb invalidation bug) ...
 985                  */
 986                 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
 987                 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
 988                 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
 989                 *cs++ = cs_offset;
 990                 *cs++ = 4096;
 991                 *cs++ = offset;
 992
 993                 *cs++ = MI_FLUSH;
 994                 *cs++ = MI_NOOP;
 995                 intel_ring_advance(rq, cs);
 996
 997                 /* ... and execute it. */
 998                 offset = cs_offset;
 999         }
1000
1001         cs = intel_ring_begin(rq, 2);
1002         if (IS_ERR(cs))
1003                 return PTR_ERR(cs);
1004
1005         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1006         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1007                 MI_BATCH_NON_SECURE);
1008         intel_ring_advance(rq, cs);
1009
1010         return 0;
1011 }
1012
1013 static int
1014 i915_emit_bb_start(struct i915_request *rq,
1015                    u64 offset, u32 len,
1016                    unsigned int dispatch_flags)
1017 {
1018         u32 *cs;
1019
1020         cs = intel_ring_begin(rq, 2);
1021         if (IS_ERR(cs))
1022                 return PTR_ERR(cs);
1023
1024         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1025         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1026                 MI_BATCH_NON_SECURE);
1027         intel_ring_advance(rq, cs);
1028
1029         return 0;
1030 }
1031
1032
1033
1034 int intel_ring_pin(struct intel_ring *ring,
1035                    struct drm_i915_private *i915,
1036                    unsigned int offset_bias)
1037 {
1038         enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1039         struct i915_vma *vma = ring->vma;
1040         unsigned int flags;
1041         void *addr;
1042         int ret;
1043
1044         GEM_BUG_ON(ring->vaddr);
1045
1046
1047         flags = PIN_GLOBAL;
1048         if (offset_bias)
1049                 flags |= PIN_OFFSET_BIAS | offset_bias;
1050         if (vma->obj->stolen)
1051                 flags |= PIN_MAPPABLE;
1052
1053         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1054                 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1055                         ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1056                 else
1057                         ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1058                 if (unlikely(ret))
1059                         return ret;
1060         }
1061
1062         ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1063         if (unlikely(ret))
1064                 return ret;
1065
1066         if (i915_vma_is_map_and_fenceable(vma))
1067                 addr = (void __force *)i915_vma_pin_iomap(vma);
1068         else
1069                 addr = i915_gem_object_pin_map(vma->obj, map);
1070         if (IS_ERR(addr))
1071                 goto err;
1072
1073         vma->obj->pin_global++;
1074
1075         ring->vaddr = addr;
1076         return 0;
1077
1078 err:
1079         i915_vma_unpin(vma);
1080         return PTR_ERR(addr);
1081 }
1082
1083 void intel_ring_reset(struct intel_ring *ring, u32 tail)
1084 {
1085         ring->tail = tail;
1086         ring->head = tail;
1087         ring->emit = tail;
1088         intel_ring_update_space(ring);
1089 }
1090
1091 void intel_ring_unpin(struct intel_ring *ring)
1092 {
1093         GEM_BUG_ON(!ring->vma);
1094         GEM_BUG_ON(!ring->vaddr);
1095
1096         /* Discard any unused bytes beyond that submitted to hw. */
1097         intel_ring_reset(ring, ring->tail);
1098
1099         if (i915_vma_is_map_and_fenceable(ring->vma))
1100                 i915_vma_unpin_iomap(ring->vma);
1101         else
1102                 i915_gem_object_unpin_map(ring->vma->obj);
1103         ring->vaddr = NULL;
1104
1105         ring->vma->obj->pin_global--;
1106         i915_vma_unpin(ring->vma);
1107 }
1108
1109 static struct i915_vma *
1110 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1111 {
1112         struct drm_i915_gem_object *obj;
1113         struct i915_vma *vma;
1114
1115         obj = i915_gem_object_create_stolen(dev_priv, size);
1116         if (!obj)
1117                 obj = i915_gem_object_create_internal(dev_priv, size);
1118         if (IS_ERR(obj))
1119                 return ERR_CAST(obj);
1120
1121         /* mark ring buffers as read-only from GPU side by default */
1122         obj->gt_ro = 1;
1123
1124         vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
1125         if (IS_ERR(vma))
1126                 goto err;
1127
1128         return vma;
1129
1130 err:
1131         i915_gem_object_put(obj);
1132         return vma;
1133 }
1134
1135 struct intel_ring *
1136 intel_engine_create_ring(struct intel_engine_cs *engine,
1137                          struct i915_timeline *timeline,
1138                          int size)
1139 {
1140         struct intel_ring *ring;
1141         struct i915_vma *vma;
1142
1143         GEM_BUG_ON(!is_power_of_2(size));
1144         GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1145         GEM_BUG_ON(timeline == &engine->timeline);
1146         lockdep_assert_held(&engine->i915->drm.struct_mutex);
1147
1148         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1149         if (!ring)
1150                 return ERR_PTR(-ENOMEM);
1151
1152         INIT_LIST_HEAD(&ring->request_list);
1153         ring->timeline = i915_timeline_get(timeline);
1154
1155         ring->size = size;
1156         /* Workaround an erratum on the i830 which causes a hang if
1157          * the TAIL pointer points to within the last 2 cachelines
1158          * of the buffer.
1159          */
1160         ring->effective_size = size;
1161         if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1162                 ring->effective_size -= 2 * CACHELINE_BYTES;
1163
1164         intel_ring_update_space(ring);
1165
1166         vma = intel_ring_create_vma(engine->i915, size);
1167         if (IS_ERR(vma)) {
1168                 kfree(ring);
1169                 return ERR_CAST(vma);
1170         }
1171         ring->vma = vma;
1172
1173         return ring;
1174 }
1175
1176 void
1177 intel_ring_free(struct intel_ring *ring)
1178 {
1179         struct drm_i915_gem_object *obj = ring->vma->obj;
1180
1181         i915_vma_close(ring->vma);
1182         __i915_gem_object_release_unless_active(obj);
1183
1184         i915_timeline_put(ring->timeline);
1185         kfree(ring);
1186 }
1187
1188 static void intel_ring_context_destroy(struct intel_context *ce)
1189 {
1190         GEM_BUG_ON(ce->pin_count);
1191
1192         if (ce->state)
1193                 __i915_gem_object_release_unless_active(ce->state->obj);
1194 }
1195
1196 static int __context_pin(struct intel_context *ce)
1197 {
1198         struct i915_vma *vma;
1199         int err;
1200
1201         vma = ce->state;
1202         if (!vma)
1203                 return 0;
1204
1205         /*
1206          * Clear this page out of any CPU caches for coherent swap-in/out.
1207          * We only want to do this on the first bind so that we do not stall
1208          * on an active context (which by nature is already on the GPU).
1209          */
1210         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1211                 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1212                 if (err)
1213                         return err;
1214         }
1215
1216         err = i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
1217                            PIN_GLOBAL | PIN_HIGH);
1218         if (err)
1219                 return err;
1220
1221         /*
1222          * And mark is as a globally pinned object to let the shrinker know
1223          * it cannot reclaim the object until we release it.
1224          */
1225         vma->obj->pin_global++;
1226
1227         return 0;
1228 }
1229
1230 static void __context_unpin(struct intel_context *ce)
1231 {
1232         struct i915_vma *vma;
1233
1234         vma = ce->state;
1235         if (!vma)
1236                 return;
1237
1238         vma->obj->pin_global--;
1239         i915_vma_unpin(vma);
1240 }
1241
1242 static void intel_ring_context_unpin(struct intel_context *ce)
1243 {
1244         __context_unpin(ce);
1245
1246         i915_gem_context_put(ce->gem_context);
1247 }
1248
1249 static struct i915_vma *
1250 alloc_context_vma(struct intel_engine_cs *engine)
1251 {
1252         struct drm_i915_private *i915 = engine->i915;
1253         struct drm_i915_gem_object *obj;
1254         struct i915_vma *vma;
1255         int err;
1256
1257         obj = i915_gem_object_create(i915, engine->context_size);
1258         if (IS_ERR(obj))
1259                 return ERR_CAST(obj);
1260
1261         if (engine->default_state) {
1262                 void *defaults, *vaddr;
1263
1264                 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1265                 if (IS_ERR(vaddr)) {
1266                         err = PTR_ERR(vaddr);
1267                         goto err_obj;
1268                 }
1269
1270                 defaults = i915_gem_object_pin_map(engine->default_state,
1271                                                    I915_MAP_WB);
1272                 if (IS_ERR(defaults)) {
1273                         err = PTR_ERR(defaults);
1274                         goto err_map;
1275                 }
1276
1277                 memcpy(vaddr, defaults, engine->context_size);
1278
1279                 i915_gem_object_unpin_map(engine->default_state);
1280                 i915_gem_object_unpin_map(obj);
1281         }
1282
1283         /*
1284          * Try to make the context utilize L3 as well as LLC.
1285          *
1286          * On VLV we don't have L3 controls in the PTEs so we
1287          * shouldn't touch the cache level, especially as that
1288          * would make the object snooped which might have a
1289          * negative performance impact.
1290          *
1291          * Snooping is required on non-llc platforms in execlist
1292          * mode, but since all GGTT accesses use PAT entry 0 we
1293          * get snooping anyway regardless of cache_level.
1294          *
1295          * This is only applicable for Ivy Bridge devices since
1296          * later platforms don't have L3 control bits in the PTE.
1297          */
1298         if (IS_IVYBRIDGE(i915)) {
1299                 /* Ignore any error, regard it as a simple optimisation */
1300                 i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
1301         }
1302
1303         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1304         if (IS_ERR(vma)) {
1305                 err = PTR_ERR(vma);
1306                 goto err_obj;
1307         }
1308
1309         return vma;
1310
1311 err_map:
1312         i915_gem_object_unpin_map(obj);
1313 err_obj:
1314         i915_gem_object_put(obj);
1315         return ERR_PTR(err);
1316 }
1317
1318 static struct intel_context *
1319 __ring_context_pin(struct intel_engine_cs *engine,
1320                    struct i915_gem_context *ctx,
1321                    struct intel_context *ce)
1322 {
1323         int err;
1324
1325         if (!ce->state && engine->context_size) {
1326                 struct i915_vma *vma;
1327
1328                 vma = alloc_context_vma(engine);
1329                 if (IS_ERR(vma)) {
1330                         err = PTR_ERR(vma);
1331                         goto err;
1332                 }
1333
1334                 ce->state = vma;
1335         }
1336
1337         err = __context_pin(ce);
1338         if (err)
1339                 goto err;
1340
1341         i915_gem_context_get(ctx);
1342
1343         /* One ringbuffer to rule them all */
1344         GEM_BUG_ON(!engine->buffer);
1345         ce->ring = engine->buffer;
1346
1347         return ce;
1348
1349 err:
1350         ce->pin_count = 0;
1351         return ERR_PTR(err);
1352 }
1353
1354 static const struct intel_context_ops ring_context_ops = {
1355         .unpin = intel_ring_context_unpin,
1356         .destroy = intel_ring_context_destroy,
1357 };
1358
1359 static struct intel_context *
1360 intel_ring_context_pin(struct intel_engine_cs *engine,
1361                        struct i915_gem_context *ctx)
1362 {
1363         struct intel_context *ce = to_intel_context(ctx, engine);
1364
1365         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1366
1367         if (likely(ce->pin_count++))
1368                 return ce;
1369         GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1370
1371         ce->ops = &ring_context_ops;
1372
1373         return __ring_context_pin(engine, ctx, ce);
1374 }
1375
1376 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1377 {
1378         struct intel_ring *ring;
1379         struct i915_timeline *timeline;
1380         int err;
1381
1382         intel_engine_setup_common(engine);
1383
1384         timeline = i915_timeline_create(engine->i915, engine->name);
1385         if (IS_ERR(timeline)) {
1386                 err = PTR_ERR(timeline);
1387                 goto err;
1388         }
1389
1390         ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
1391         i915_timeline_put(timeline);
1392         if (IS_ERR(ring)) {
1393                 err = PTR_ERR(ring);
1394                 goto err;
1395         }
1396
1397         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1398         err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
1399         if (err)
1400                 goto err_ring;
1401
1402         GEM_BUG_ON(engine->buffer);
1403         engine->buffer = ring;
1404
1405         err = intel_engine_init_common(engine);
1406         if (err)
1407                 goto err_unpin;
1408
1409         return 0;
1410
1411 err_unpin:
1412         intel_ring_unpin(ring);
1413 err_ring:
1414         intel_ring_free(ring);
1415 err:
1416         intel_engine_cleanup_common(engine);
1417         return err;
1418 }
1419
1420 void intel_engine_cleanup(struct intel_engine_cs *engine)
1421 {
1422         struct drm_i915_private *dev_priv = engine->i915;
1423
1424         WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1425                 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
1426
1427         intel_ring_unpin(engine->buffer);
1428         intel_ring_free(engine->buffer);
1429
1430         if (engine->cleanup)
1431                 engine->cleanup(engine);
1432
1433         intel_engine_cleanup_common(engine);
1434
1435         dev_priv->engine[engine->id] = NULL;
1436         kfree(engine);
1437 }
1438
1439 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1440 {
1441         struct intel_engine_cs *engine;
1442         enum intel_engine_id id;
1443
1444         /* Restart from the beginning of the rings for convenience */
1445         for_each_engine(engine, dev_priv, id)
1446                 intel_ring_reset(engine->buffer, 0);
1447 }
1448
1449 static inline int mi_set_context(struct i915_request *rq, u32 flags)
1450 {
1451         struct drm_i915_private *i915 = rq->i915;
1452         struct intel_engine_cs *engine = rq->engine;
1453         enum intel_engine_id id;
1454         const int num_rings =
1455                 /* Use an extended w/a on gen7 if signalling from other rings */
1456                 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
1457                 INTEL_INFO(i915)->num_rings - 1 :
1458                 0;
1459         bool force_restore = false;
1460         int len;
1461         u32 *cs;
1462
1463         flags |= MI_MM_SPACE_GTT;
1464         if (IS_HASWELL(i915))
1465                 /* These flags are for resource streamer on HSW+ */
1466                 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1467         else
1468                 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1469
1470         len = 4;
1471         if (IS_GEN7(i915))
1472                 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1473         if (flags & MI_FORCE_RESTORE) {
1474                 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
1475                 flags &= ~MI_FORCE_RESTORE;
1476                 force_restore = true;
1477                 len += 2;
1478         }
1479
1480         cs = intel_ring_begin(rq, len);
1481         if (IS_ERR(cs))
1482                 return PTR_ERR(cs);
1483
1484         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1485         if (IS_GEN7(i915)) {
1486                 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1487                 if (num_rings) {
1488                         struct intel_engine_cs *signaller;
1489
1490                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1491                         for_each_engine(signaller, i915, id) {
1492                                 if (signaller == engine)
1493                                         continue;
1494
1495                                 *cs++ = i915_mmio_reg_offset(
1496                                            RING_PSMI_CTL(signaller->mmio_base));
1497                                 *cs++ = _MASKED_BIT_ENABLE(
1498                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1499                         }
1500                 }
1501         }
1502
1503         if (force_restore) {
1504                 /*
1505                  * The HW doesn't handle being told to restore the current
1506                  * context very well. Quite often it likes goes to go off and
1507                  * sulk, especially when it is meant to be reloading PP_DIR.
1508                  * A very simple fix to force the reload is to simply switch
1509                  * away from the current context and back again.
1510                  *
1511                  * Note that the kernel_context will contain random state
1512                  * following the INHIBIT_RESTORE. We accept this since we
1513                  * never use the kernel_context state; it is merely a
1514                  * placeholder we use to flush other contexts.
1515                  */
1516                 *cs++ = MI_SET_CONTEXT;
1517                 *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
1518                                                           engine)->state) |
1519                         MI_MM_SPACE_GTT |
1520                         MI_RESTORE_INHIBIT;
1521         }
1522
1523         *cs++ = MI_NOOP;
1524         *cs++ = MI_SET_CONTEXT;
1525         *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
1526         /*
1527          * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1528          * WaMiSetContext_Hang:snb,ivb,vlv
1529          */
1530         *cs++ = MI_NOOP;
1531
1532         if (IS_GEN7(i915)) {
1533                 if (num_rings) {
1534                         struct intel_engine_cs *signaller;
1535                         i915_reg_t last_reg = {}; /* keep gcc quiet */
1536
1537                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1538                         for_each_engine(signaller, i915, id) {
1539                                 if (signaller == engine)
1540                                         continue;
1541
1542                                 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1543                                 *cs++ = i915_mmio_reg_offset(last_reg);
1544                                 *cs++ = _MASKED_BIT_DISABLE(
1545                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1546                         }
1547
1548                         /* Insert a delay before the next switch! */
1549                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1550                         *cs++ = i915_mmio_reg_offset(last_reg);
1551                         *cs++ = i915_ggtt_offset(engine->scratch);
1552                         *cs++ = MI_NOOP;
1553                 }
1554                 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1555         }
1556
1557         intel_ring_advance(rq, cs);
1558
1559         return 0;
1560 }
1561
1562 static int remap_l3(struct i915_request *rq, int slice)
1563 {
1564         u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1565         int i;
1566
1567         if (!remap_info)
1568                 return 0;
1569
1570         cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1571         if (IS_ERR(cs))
1572                 return PTR_ERR(cs);
1573
1574         /*
1575          * Note: We do not worry about the concurrent register cacheline hang
1576          * here because no other code should access these registers other than
1577          * at initialization time.
1578          */
1579         *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1580         for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1581                 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1582                 *cs++ = remap_info[i];
1583         }
1584         *cs++ = MI_NOOP;
1585         intel_ring_advance(rq, cs);
1586
1587         return 0;
1588 }
1589
1590 static int switch_context(struct i915_request *rq)
1591 {
1592         struct intel_engine_cs *engine = rq->engine;
1593         struct i915_gem_context *to_ctx = rq->gem_context;
1594         struct i915_hw_ppgtt *to_mm =
1595                 to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1596         struct i915_gem_context *from_ctx = engine->legacy_active_context;
1597         struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt;
1598         u32 hw_flags = 0;
1599         int ret, i;
1600
1601         lockdep_assert_held(&rq->i915->drm.struct_mutex);
1602         GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1603
1604         if (to_mm != from_mm ||
1605             (to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) {
1606                 trace_switch_mm(engine, to_ctx);
1607                 ret = to_mm->switch_mm(to_mm, rq);
1608                 if (ret)
1609                         goto err;
1610
1611                 to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
1612                 engine->legacy_active_ppgtt = to_mm;
1613                 hw_flags = MI_FORCE_RESTORE;
1614         }
1615
1616         if (rq->hw_context->state &&
1617             (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
1618                 GEM_BUG_ON(engine->id != RCS);
1619
1620                 /*
1621                  * The kernel context(s) is treated as pure scratch and is not
1622                  * expected to retain any state (as we sacrifice it during
1623                  * suspend and on resume it may be corrupted). This is ok,
1624                  * as nothing actually executes using the kernel context; it
1625                  * is purely used for flushing user contexts.
1626                  */
1627                 if (i915_gem_context_is_kernel(to_ctx))
1628                         hw_flags = MI_RESTORE_INHIBIT;
1629
1630                 ret = mi_set_context(rq, hw_flags);
1631                 if (ret)
1632                         goto err_mm;
1633
1634                 engine->legacy_active_context = to_ctx;
1635         }
1636
1637         if (to_ctx->remap_slice) {
1638                 for (i = 0; i < MAX_L3_SLICES; i++) {
1639                         if (!(to_ctx->remap_slice & BIT(i)))
1640                                 continue;
1641
1642                         ret = remap_l3(rq, i);
1643                         if (ret)
1644                                 goto err_ctx;
1645                 }
1646
1647                 to_ctx->remap_slice = 0;
1648         }
1649
1650         return 0;
1651
1652 err_ctx:
1653         engine->legacy_active_context = from_ctx;
1654 err_mm:
1655         engine->legacy_active_ppgtt = from_mm;
1656 err:
1657         return ret;
1658 }
1659
1660 static int ring_request_alloc(struct i915_request *request)
1661 {
1662         int ret;
1663
1664         GEM_BUG_ON(!request->hw_context->pin_count);
1665
1666         /* Flush enough space to reduce the likelihood of waiting after
1667          * we start building the request - in which case we will just
1668          * have to repeat work.
1669          */
1670         request->reserved_space += LEGACY_REQUEST_SIZE;
1671
1672         ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1673         if (ret)
1674                 return ret;
1675
1676         ret = switch_context(request);
1677         if (ret)
1678                 return ret;
1679
1680         request->reserved_space -= LEGACY_REQUEST_SIZE;
1681         return 0;
1682 }
1683
1684 static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1685 {
1686         struct i915_request *target;
1687         long timeout;
1688
1689         lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1690
1691         if (intel_ring_update_space(ring) >= bytes)
1692                 return 0;
1693
1694         GEM_BUG_ON(list_empty(&ring->request_list));
1695         list_for_each_entry(target, &ring->request_list, ring_link) {
1696                 /* Would completion of this request free enough space? */
1697                 if (bytes <= __intel_ring_space(target->postfix,
1698                                                 ring->emit, ring->size))
1699                         break;
1700         }
1701
1702         if (WARN_ON(&target->ring_link == &ring->request_list))
1703                 return -ENOSPC;
1704
1705         timeout = i915_request_wait(target,
1706                                     I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1707                                     MAX_SCHEDULE_TIMEOUT);
1708         if (timeout < 0)
1709                 return timeout;
1710
1711         i915_request_retire_upto(target);
1712
1713         intel_ring_update_space(ring);
1714         GEM_BUG_ON(ring->space < bytes);
1715         return 0;
1716 }
1717
1718 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes)
1719 {
1720         GEM_BUG_ON(bytes > ring->effective_size);
1721         if (unlikely(bytes > ring->effective_size - ring->emit))
1722                 bytes += ring->size - ring->emit;
1723
1724         if (unlikely(bytes > ring->space)) {
1725                 int ret = wait_for_space(ring, bytes);
1726                 if (unlikely(ret))
1727                         return ret;
1728         }
1729
1730         GEM_BUG_ON(ring->space < bytes);
1731         return 0;
1732 }
1733
1734 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1735 {
1736         struct intel_ring *ring = rq->ring;
1737         const unsigned int remain_usable = ring->effective_size - ring->emit;
1738         const unsigned int bytes = num_dwords * sizeof(u32);
1739         unsigned int need_wrap = 0;
1740         unsigned int total_bytes;
1741         u32 *cs;
1742
1743         /* Packets must be qword aligned. */
1744         GEM_BUG_ON(num_dwords & 1);
1745
1746         total_bytes = bytes + rq->reserved_space;
1747         GEM_BUG_ON(total_bytes > ring->effective_size);
1748
1749         if (unlikely(total_bytes > remain_usable)) {
1750                 const int remain_actual = ring->size - ring->emit;
1751
1752                 if (bytes > remain_usable) {
1753                         /*
1754                          * Not enough space for the basic request. So need to
1755                          * flush out the remainder and then wait for
1756                          * base + reserved.
1757                          */
1758                         total_bytes += remain_actual;
1759                         need_wrap = remain_actual | 1;
1760                 } else  {
1761                         /*
1762                          * The base request will fit but the reserved space
1763                          * falls off the end. So we don't need an immediate
1764                          * wrap and only need to effectively wait for the
1765                          * reserved size from the start of ringbuffer.
1766                          */
1767                         total_bytes = rq->reserved_space + remain_actual;
1768                 }
1769         }
1770
1771         if (unlikely(total_bytes > ring->space)) {
1772                 int ret;
1773
1774                 /*
1775                  * Space is reserved in the ringbuffer for finalising the
1776                  * request, as that cannot be allowed to fail. During request
1777                  * finalisation, reserved_space is set to 0 to stop the
1778                  * overallocation and the assumption is that then we never need
1779                  * to wait (which has the risk of failing with EINTR).
1780                  *
1781                  * See also i915_request_alloc() and i915_request_add().
1782                  */
1783                 GEM_BUG_ON(!rq->reserved_space);
1784
1785                 ret = wait_for_space(ring, total_bytes);
1786                 if (unlikely(ret))
1787                         return ERR_PTR(ret);
1788         }
1789
1790         if (unlikely(need_wrap)) {
1791                 need_wrap &= ~1;
1792                 GEM_BUG_ON(need_wrap > ring->space);
1793                 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1794                 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
1795
1796                 /* Fill the tail with MI_NOOP */
1797                 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
1798                 ring->space -= need_wrap;
1799                 ring->emit = 0;
1800         }
1801
1802         GEM_BUG_ON(ring->emit > ring->size - bytes);
1803         GEM_BUG_ON(ring->space < bytes);
1804         cs = ring->vaddr + ring->emit;
1805         GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
1806         ring->emit += bytes;
1807         ring->space -= bytes;
1808
1809         return cs;
1810 }
1811
1812 /* Align the ring tail to a cacheline boundary */
1813 int intel_ring_cacheline_align(struct i915_request *rq)
1814 {
1815         int num_dwords;
1816         void *cs;
1817
1818         num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
1819         if (num_dwords == 0)
1820                 return 0;
1821
1822         num_dwords = CACHELINE_DWORDS - num_dwords;
1823         GEM_BUG_ON(num_dwords & 1);
1824
1825         cs = intel_ring_begin(rq, num_dwords);
1826         if (IS_ERR(cs))
1827                 return PTR_ERR(cs);
1828
1829         memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);
1830         intel_ring_advance(rq, cs);
1831
1832         GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));
1833         return 0;
1834 }
1835
1836 static void gen6_bsd_submit_request(struct i915_request *request)
1837 {
1838         struct drm_i915_private *dev_priv = request->i915;
1839
1840         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1841
1842        /* Every tail move must follow the sequence below */
1843
1844         /* Disable notification that the ring is IDLE. The GT
1845          * will then assume that it is busy and bring it out of rc6.
1846          */
1847         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1848                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1849
1850         /* Clear the context id. Here be magic! */
1851         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
1852
1853         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1854         if (__intel_wait_for_register_fw(dev_priv,
1855                                          GEN6_BSD_SLEEP_PSMI_CONTROL,
1856                                          GEN6_BSD_SLEEP_INDICATOR,
1857                                          0,
1858                                          1000, 0, NULL))
1859                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1860
1861         /* Now that the ring is fully powered up, update the tail */
1862         i9xx_submit_request(request);
1863
1864         /* Let the ring send IDLE messages to the GT again,
1865          * and so let it sleep to conserve power when idle.
1866          */
1867         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1868                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1869
1870         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1871 }
1872
1873 static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
1874 {
1875         u32 cmd, *cs;
1876
1877         cs = intel_ring_begin(rq, 4);
1878         if (IS_ERR(cs))
1879                 return PTR_ERR(cs);
1880
1881         cmd = MI_FLUSH_DW;
1882
1883         /* We always require a command barrier so that subsequent
1884          * commands, such as breadcrumb interrupts, are strictly ordered
1885          * wrt the contents of the write cache being flushed to memory
1886          * (and thus being coherent from the CPU).
1887          */
1888         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1889
1890         /*
1891          * Bspec vol 1c.5 - video engine command streamer:
1892          * "If ENABLED, all TLBs will be invalidated once the flush
1893          * operation is complete. This bit is only valid when the
1894          * Post-Sync Operation field is a value of 1h or 3h."
1895          */
1896         if (mode & EMIT_INVALIDATE)
1897                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1898
1899         *cs++ = cmd;
1900         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1901         *cs++ = 0;
1902         *cs++ = MI_NOOP;
1903         intel_ring_advance(rq, cs);
1904         return 0;
1905 }
1906
1907 static int
1908 hsw_emit_bb_start(struct i915_request *rq,
1909                   u64 offset, u32 len,
1910                   unsigned int dispatch_flags)
1911 {
1912         u32 *cs;
1913
1914         cs = intel_ring_begin(rq, 2);
1915         if (IS_ERR(cs))
1916                 return PTR_ERR(cs);
1917
1918         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1919                 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
1920                 (dispatch_flags & I915_DISPATCH_RS ?
1921                 MI_BATCH_RESOURCE_STREAMER : 0);
1922         /* bit0-7 is the length on GEN6+ */
1923         *cs++ = offset;
1924         intel_ring_advance(rq, cs);
1925
1926         return 0;
1927 }
1928
1929 static int
1930 gen6_emit_bb_start(struct i915_request *rq,
1931                    u64 offset, u32 len,
1932                    unsigned int dispatch_flags)
1933 {
1934         u32 *cs;
1935
1936         cs = intel_ring_begin(rq, 2);
1937         if (IS_ERR(cs))
1938                 return PTR_ERR(cs);
1939
1940         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1941                 0 : MI_BATCH_NON_SECURE_I965);
1942         /* bit0-7 is the length on GEN6+ */
1943         *cs++ = offset;
1944         intel_ring_advance(rq, cs);
1945
1946         return 0;
1947 }
1948
1949 /* Blitter support (SandyBridge+) */
1950
1951 static int gen6_ring_flush(struct i915_request *rq, u32 mode)
1952 {
1953         u32 cmd, *cs;
1954
1955         cs = intel_ring_begin(rq, 4);
1956         if (IS_ERR(cs))
1957                 return PTR_ERR(cs);
1958
1959         cmd = MI_FLUSH_DW;
1960
1961         /* We always require a command barrier so that subsequent
1962          * commands, such as breadcrumb interrupts, are strictly ordered
1963          * wrt the contents of the write cache being flushed to memory
1964          * (and thus being coherent from the CPU).
1965          */
1966         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1967
1968         /*
1969          * Bspec vol 1c.3 - blitter engine command streamer:
1970          * "If ENABLED, all TLBs will be invalidated once the flush
1971          * operation is complete. This bit is only valid when the
1972          * Post-Sync Operation field is a value of 1h or 3h."
1973          */
1974         if (mode & EMIT_INVALIDATE)
1975                 cmd |= MI_INVALIDATE_TLB;
1976         *cs++ = cmd;
1977         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1978         *cs++ = 0;
1979         *cs++ = MI_NOOP;
1980         intel_ring_advance(rq, cs);
1981
1982         return 0;
1983 }
1984
1985 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
1986                                        struct intel_engine_cs *engine)
1987 {
1988         int i;
1989
1990         if (!HAS_LEGACY_SEMAPHORES(dev_priv))
1991                 return;
1992
1993         GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
1994         engine->semaphore.sync_to = gen6_ring_sync_to;
1995         engine->semaphore.signal = gen6_signal;
1996
1997         /*
1998          * The current semaphore is only applied on pre-gen8
1999          * platform.  And there is no VCS2 ring on the pre-gen8
2000          * platform. So the semaphore between RCS and VCS2 is
2001          * initialized as INVALID.
2002          */
2003         for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
2004                 static const struct {
2005                         u32 wait_mbox;
2006                         i915_reg_t mbox_reg;
2007                 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
2008                         [RCS_HW] = {
2009                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
2010                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
2011                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2012                         },
2013                         [VCS_HW] = {
2014                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
2015                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
2016                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2017                         },
2018                         [BCS_HW] = {
2019                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
2020                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
2021                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2022                         },
2023                         [VECS_HW] = {
2024                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2025                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2026                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2027                         },
2028                 };
2029                 u32 wait_mbox;
2030                 i915_reg_t mbox_reg;
2031
2032                 if (i == engine->hw_id) {
2033                         wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2034                         mbox_reg = GEN6_NOSYNC;
2035                 } else {
2036                         wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
2037                         mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
2038                 }
2039
2040                 engine->semaphore.mbox.wait[i] = wait_mbox;
2041                 engine->semaphore.mbox.signal[i] = mbox_reg;
2042         }
2043 }
2044
2045 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2046                                 struct intel_engine_cs *engine)
2047 {
2048         if (INTEL_GEN(dev_priv) >= 6) {
2049                 engine->irq_enable = gen6_irq_enable;
2050                 engine->irq_disable = gen6_irq_disable;
2051                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2052         } else if (INTEL_GEN(dev_priv) >= 5) {
2053                 engine->irq_enable = gen5_irq_enable;
2054                 engine->irq_disable = gen5_irq_disable;
2055                 engine->irq_seqno_barrier = gen5_seqno_barrier;
2056         } else if (INTEL_GEN(dev_priv) >= 3) {
2057                 engine->irq_enable = i9xx_irq_enable;
2058                 engine->irq_disable = i9xx_irq_disable;
2059         } else {
2060                 engine->irq_enable = i8xx_irq_enable;
2061                 engine->irq_disable = i8xx_irq_disable;
2062         }
2063 }
2064
2065 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
2066 {
2067         engine->submit_request = i9xx_submit_request;
2068         engine->cancel_requests = cancel_requests;
2069
2070         engine->park = NULL;
2071         engine->unpark = NULL;
2072 }
2073
2074 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
2075 {
2076         i9xx_set_default_submission(engine);
2077         engine->submit_request = gen6_bsd_submit_request;
2078 }
2079
2080 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2081                                       struct intel_engine_cs *engine)
2082 {
2083         /* gen8+ are only supported with execlists */
2084         GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
2085
2086         intel_ring_init_irq(dev_priv, engine);
2087         intel_ring_init_semaphores(dev_priv, engine);
2088
2089         engine->init_hw = init_ring_common;
2090         engine->reset.prepare = reset_prepare;
2091         engine->reset.reset = reset_ring;
2092         engine->reset.finish = reset_finish;
2093
2094         engine->context_pin = intel_ring_context_pin;
2095         engine->request_alloc = ring_request_alloc;
2096
2097         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
2098         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
2099         if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
2100                 int num_rings;
2101
2102                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2103
2104                 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
2105                 engine->emit_breadcrumb_sz += num_rings * 3;
2106                 if (num_rings & 1)
2107                         engine->emit_breadcrumb_sz++;
2108         }
2109
2110         engine->set_default_submission = i9xx_set_default_submission;
2111
2112         if (INTEL_GEN(dev_priv) >= 6)
2113                 engine->emit_bb_start = gen6_emit_bb_start;
2114         else if (INTEL_GEN(dev_priv) >= 4)
2115                 engine->emit_bb_start = i965_emit_bb_start;
2116         else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2117                 engine->emit_bb_start = i830_emit_bb_start;
2118         else
2119                 engine->emit_bb_start = i915_emit_bb_start;
2120 }
2121
2122 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2123 {
2124         struct drm_i915_private *dev_priv = engine->i915;
2125         int ret;
2126
2127         intel_ring_default_vfuncs(dev_priv, engine);
2128
2129         if (HAS_L3_DPF(dev_priv))
2130                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2131
2132         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2133
2134         if (INTEL_GEN(dev_priv) >= 6) {
2135                 engine->init_context = intel_rcs_ctx_init;
2136                 engine->emit_flush = gen7_render_ring_flush;
2137                 if (IS_GEN6(dev_priv))
2138                         engine->emit_flush = gen6_render_ring_flush;
2139         } else if (IS_GEN5(dev_priv)) {
2140                 engine->emit_flush = gen4_render_ring_flush;
2141         } else {
2142                 if (INTEL_GEN(dev_priv) < 4)
2143                         engine->emit_flush = gen2_render_ring_flush;
2144                 else
2145                         engine->emit_flush = gen4_render_ring_flush;
2146                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2147         }
2148
2149         if (IS_HASWELL(dev_priv))
2150                 engine->emit_bb_start = hsw_emit_bb_start;
2151
2152         engine->init_hw = init_render_ring;
2153
2154         ret = intel_init_ring_buffer(engine);
2155         if (ret)
2156                 return ret;
2157
2158         if (INTEL_GEN(dev_priv) >= 6) {
2159                 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2160                 if (ret)
2161                         return ret;
2162         } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2163                 ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
2164                 if (ret)
2165                         return ret;
2166         }
2167
2168         return 0;
2169 }
2170
2171 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2172 {
2173         struct drm_i915_private *dev_priv = engine->i915;
2174
2175         intel_ring_default_vfuncs(dev_priv, engine);
2176
2177         if (INTEL_GEN(dev_priv) >= 6) {
2178                 /* gen6 bsd needs a special wa for tail updates */
2179                 if (IS_GEN6(dev_priv))
2180                         engine->set_default_submission = gen6_bsd_set_default_submission;
2181                 engine->emit_flush = gen6_bsd_ring_flush;
2182                 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2183         } else {
2184                 engine->emit_flush = bsd_ring_flush;
2185                 if (IS_GEN5(dev_priv))
2186                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2187                 else
2188                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2189         }
2190
2191         return intel_init_ring_buffer(engine);
2192 }
2193
2194 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2195 {
2196         struct drm_i915_private *dev_priv = engine->i915;
2197
2198         intel_ring_default_vfuncs(dev_priv, engine);
2199
2200         engine->emit_flush = gen6_ring_flush;
2201         engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2202
2203         return intel_init_ring_buffer(engine);
2204 }
2205
2206 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2207 {
2208         struct drm_i915_private *dev_priv = engine->i915;
2209
2210         intel_ring_default_vfuncs(dev_priv, engine);
2211
2212         engine->emit_flush = gen6_ring_flush;
2213         engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2214         engine->irq_enable = hsw_vebox_irq_enable;
2215         engine->irq_disable = hsw_vebox_irq_disable;
2216
2217         return intel_init_ring_buffer(engine);
2218 }