drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 static void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         struct intel_engine_cs *ring = req->ring;
  99         u32 cmd;
 100         int ret;
 101
 102         cmd = MI_FLUSH;
 103         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 104                 cmd |= MI_NO_WRITE_FLUSH;
 105
 106         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                 cmd |= MI_READ_FLUSH;
 108
 109         ret = intel_ring_begin(req, 2);
 110         if (ret)
 111                 return ret;
 112
 113         intel_ring_emit(ring, cmd);
 114         intel_ring_emit(ring, MI_NOOP);
 115         intel_ring_advance(ring);
 116
 117         return 0;
 118 }
 119
 120 static int
 121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 122                        u32      invalidate_domains,
 123                        u32      flush_domains)
 124 {
 125         struct intel_engine_cs *ring = req->ring;
 126         struct drm_device *dev = ring->dev;
 127         u32 cmd;
 128         int ret;
 129
 130         /*
 131          * read/write caches:
 132          *
 133          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 134          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 135          * also flushed at 2d versus 3d pipeline switches.
 136          *
 137          * read-only caches:
 138          *
 139          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 140          * MI_READ_FLUSH is set, and is always flushed on 965.
 141          *
 142          * I915_GEM_DOMAIN_COMMAND may not exist?
 143          *
 144          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 145          * invalidated when MI_EXE_FLUSH is set.
 146          *
 147          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 148          * invalidated with every MI_FLUSH.
 149          *
 150          * TLBs:
 151          *
 152          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 153          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 154          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 155          * are flushed at any MI_FLUSH.
 156          */
 157
 158         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 159         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 160                 cmd &= ~MI_NO_WRITE_FLUSH;
 161         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 162                 cmd |= MI_EXE_FLUSH;
 163
 164         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 165             (IS_G4X(dev) || IS_GEN5(dev)))
 166                 cmd |= MI_INVALIDATE_ISP;
 167
 168         ret = intel_ring_begin(req, 2);
 169         if (ret)
 170                 return ret;
 171
 172         intel_ring_emit(ring, cmd);
 173         intel_ring_emit(ring, MI_NOOP);
 174         intel_ring_advance(ring);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 181  * implementing two workarounds on gen6.  From section 1.4.7.1
 182  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 183  *
 184  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 185  * produced by non-pipelined state commands), software needs to first
 186  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 187  * 0.
 188  *
 189  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 190  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 191  *
 192  * And the workaround for these two requires this workaround first:
 193  *
 194  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 195  * BEFORE the pipe-control with a post-sync op and no write-cache
 196  * flushes.
 197  *
 198  * And this last workaround is tricky because of the requirements on
 199  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 200  * volume 2 part 1:
 201  *
 202  *     "1 of the following must also be set:
 203  *      - Render Target Cache Flush Enable ([12] of DW1)
 204  *      - Depth Cache Flush Enable ([0] of DW1)
 205  *      - Stall at Pixel Scoreboard ([1] of DW1)
 206  *      - Depth Stall ([13] of DW1)
 207  *      - Post-Sync Operation ([13] of DW1)
 208  *      - Notify Enable ([8] of DW1)"
 209  *
 210  * The cache flushes require the workaround flush that triggered this
 211  * one, so we can't use it.  Depth stall would trigger the same.
 212  * Post-sync nonzero is what triggered this second workaround, so we
 213  * can't use that one either.  Notify enable is IRQs, which aren't
 214  * really our business.  That leaves only stall at scoreboard.
 215  */
 216 static int
 217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 218 {
 219         struct intel_engine_cs *ring = req->ring;
 220         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 221         int ret;
 222
 223         ret = intel_ring_begin(req, 6);
 224         if (ret)
 225                 return ret;
 226
 227         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 228         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 229                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 230         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 231         intel_ring_emit(ring, 0); /* low dword */
 232         intel_ring_emit(ring, 0); /* high dword */
 233         intel_ring_emit(ring, MI_NOOP);
 234         intel_ring_advance(ring);
 235
 236         ret = intel_ring_begin(req, 6);
 237         if (ret)
 238                 return ret;
 239
 240         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 241         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 242         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 243         intel_ring_emit(ring, 0);
 244         intel_ring_emit(ring, 0);
 245         intel_ring_emit(ring, MI_NOOP);
 246         intel_ring_advance(ring);
 247
 248         return 0;
 249 }
 250
 251 static int
 252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 253                        u32 invalidate_domains, u32 flush_domains)
 254 {
 255         struct intel_engine_cs *ring = req->ring;
 256         u32 flags = 0;
 257         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 258         int ret;
 259
 260         /* Force SNB workarounds for PIPE_CONTROL flushes */
 261         ret = intel_emit_post_sync_nonzero_flush(req);
 262         if (ret)
 263                 return ret;
 264
 265         /* Just flush everything.  Experiments have shown that reducing the
 266          * number of bits based on the write domains has little performance
 267          * impact.
 268          */
 269         if (flush_domains) {
 270                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 271                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 272                 /*
 273                  * Ensure that any following seqno writes only happen
 274                  * when the render cache is indeed flushed.
 275                  */
 276                 flags |= PIPE_CONTROL_CS_STALL;
 277         }
 278         if (invalidate_domains) {
 279                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 280                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 282                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 283                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 284                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 285                 /*
 286                  * TLB invalidate requires a post-sync write.
 287                  */
 288                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 289         }
 290
 291         ret = intel_ring_begin(req, 4);
 292         if (ret)
 293                 return ret;
 294
 295         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 296         intel_ring_emit(ring, flags);
 297         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 298         intel_ring_emit(ring, 0);
 299         intel_ring_advance(ring);
 300
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 306 {
 307         struct intel_engine_cs *ring = req->ring;
 308         int ret;
 309
 310         ret = intel_ring_begin(req, 4);
 311         if (ret)
 312                 return ret;
 313
 314         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 315         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 316                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 317         intel_ring_emit(ring, 0);
 318         intel_ring_emit(ring, 0);
 319         intel_ring_advance(ring);
 320
 321         return 0;
 322 }
 323
 324 static int
 325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 326                        u32 invalidate_domains, u32 flush_domains)
 327 {
 328         struct intel_engine_cs *ring = req->ring;
 329         u32 flags = 0;
 330         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 331         int ret;
 332
 333         /*
 334          * Ensure that any following seqno writes only happen when the render
 335          * cache is indeed flushed.
 336          *
 337          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 338          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 339          * don't try to be clever and just set it unconditionally.
 340          */
 341         flags |= PIPE_CONTROL_CS_STALL;
 342
 343         /* Just flush everything.  Experiments have shown that reducing the
 344          * number of bits based on the write domains has little performance
 345          * impact.
 346          */
 347         if (flush_domains) {
 348                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 349                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 350                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 351         }
 352         if (invalidate_domains) {
 353                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 354                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 355                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 356                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 357                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 358                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 359                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 360                 /*
 361                  * TLB invalidate requires a post-sync write.
 362                  */
 363                 flags |= PIPE_CONTROL_QW_WRITE;
 364                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 365
 366                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 367
 368                 /* Workaround: we must issue a pipe_control with CS-stall bit
 369                  * set before a pipe_control command that has the state cache
 370                  * invalidate bit set. */
 371                 gen7_render_ring_cs_stall_wa(req);
 372         }
 373
 374         ret = intel_ring_begin(req, 4);
 375         if (ret)
 376                 return ret;
 377
 378         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 379         intel_ring_emit(ring, flags);
 380         intel_ring_emit(ring, scratch_addr);
 381         intel_ring_emit(ring, 0);
 382         intel_ring_advance(ring);
 383
 384         return 0;
 385 }
 386
 387 static int
 388 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 389                        u32 flags, u32 scratch_addr)
 390 {
 391         struct intel_engine_cs *ring = req->ring;
 392         int ret;
 393
 394         ret = intel_ring_begin(req, 6);
 395         if (ret)
 396                 return ret;
 397
 398         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 399         intel_ring_emit(ring, flags);
 400         intel_ring_emit(ring, scratch_addr);
 401         intel_ring_emit(ring, 0);
 402         intel_ring_emit(ring, 0);
 403         intel_ring_emit(ring, 0);
 404         intel_ring_advance(ring);
 405
 406         return 0;
 407 }
 408
 409 static int
 410 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 411                        u32 invalidate_domains, u32 flush_domains)
 412 {
 413         u32 flags = 0;
 414         u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 415         int ret;
 416
 417         flags |= PIPE_CONTROL_CS_STALL;
 418
 419         if (flush_domains) {
 420                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 421                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 422                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 423         }
 424         if (invalidate_domains) {
 425                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 426                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 427                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 428                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 429                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 430                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 431                 flags |= PIPE_CONTROL_QW_WRITE;
 432                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 433
 434                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 435                 ret = gen8_emit_pipe_control(req,
 436                                              PIPE_CONTROL_CS_STALL |
 437                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 438                                              0);
 439                 if (ret)
 440                         return ret;
 441         }
 442
 443         return gen8_emit_pipe_control(req, flags, scratch_addr);
 444 }
 445
 446 static void ring_write_tail(struct intel_engine_cs *ring,
 447                             u32 value)
 448 {
 449         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 450         I915_WRITE_TAIL(ring, value);
 451 }
 452
 453 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 454 {
 455         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 456         u64 acthd;
 457
 458         if (INTEL_INFO(ring->dev)->gen >= 8)
 459                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 460                                          RING_ACTHD_UDW(ring->mmio_base));
 461         else if (INTEL_INFO(ring->dev)->gen >= 4)
 462                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 463         else
 464                 acthd = I915_READ(ACTHD);
 465
 466         return acthd;
 467 }
 468
 469 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 470 {
 471         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 472         u32 addr;
 473
 474         addr = dev_priv->status_page_dmah->busaddr;
 475         if (INTEL_INFO(ring->dev)->gen >= 4)
 476                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 477         I915_WRITE(HWS_PGA, addr);
 478 }
 479
 480 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 481 {
 482         struct drm_device *dev = ring->dev;
 483         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 484         i915_reg_t mmio;
 485
 486         /* The ring status page addresses are no longer next to the rest of
 487          * the ring registers as of gen7.
 488          */
 489         if (IS_GEN7(dev)) {
 490                 switch (ring->id) {
 491                 case RCS:
 492                         mmio = RENDER_HWS_PGA_GEN7;
 493                         break;
 494                 case BCS:
 495                         mmio = BLT_HWS_PGA_GEN7;
 496                         break;
 497                 /*
 498                  * VCS2 actually doesn't exist on Gen7. Only shut up
 499                  * gcc switch check warning
 500                  */
 501                 case VCS2:
 502                 case VCS:
 503                         mmio = BSD_HWS_PGA_GEN7;
 504                         break;
 505                 case VECS:
 506                         mmio = VEBOX_HWS_PGA_GEN7;
 507                         break;
 508                 }
 509         } else if (IS_GEN6(ring->dev)) {
 510                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 511         } else {
 512                 /* XXX: gen8 returns to sanity */
 513                 mmio = RING_HWS_PGA(ring->mmio_base);
 514         }
 515
 516         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 517         POSTING_READ(mmio);
 518
 519         /*
 520          * Flush the TLB for this page
 521          *
 522          * FIXME: These two bits have disappeared on gen8, so a question
 523          * arises: do we still need this and if so how should we go about
 524          * invalidating the TLB?
 525          */
 526         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 527                 i915_reg_t reg = RING_INSTPM(ring->mmio_base);
 528
 529                 /* ring should be idle before issuing a sync flush*/
 530                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 531
 532                 I915_WRITE(reg,
 533                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 534                                               INSTPM_SYNC_FLUSH));
 535                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 536                              1000))
 537                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 538                                   ring->name);
 539         }
 540 }
 541
 542 static bool stop_ring(struct intel_engine_cs *ring)
 543 {
 544         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 545
 546         if (!IS_GEN2(ring->dev)) {
 547                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 548                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 549                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 550                         /* Sometimes we observe that the idle flag is not
 551                          * set even though the ring is empty. So double
 552                          * check before giving up.
 553                          */
 554                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 555                                 return false;
 556                 }
 557         }
 558
 559         I915_WRITE_CTL(ring, 0);
 560         I915_WRITE_HEAD(ring, 0);
 561         ring->write_tail(ring, 0);
 562
 563         if (!IS_GEN2(ring->dev)) {
 564                 (void)I915_READ_CTL(ring);
 565                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 566         }
 567
 568         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 569 }
 570
 571 static int init_ring_common(struct intel_engine_cs *ring)
 572 {
 573         struct drm_device *dev = ring->dev;
 574         struct drm_i915_private *dev_priv = dev->dev_private;
 575         struct intel_ringbuffer *ringbuf = ring->buffer;
 576         struct drm_i915_gem_object *obj = ringbuf->obj;
 577         int ret = 0;
 578
 579         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 580
 581         if (!stop_ring(ring)) {
 582                 /* G45 ring initialization often fails to reset head to zero */
 583                 DRM_DEBUG_KMS("%s head not reset to zero "
 584                               "ctl %08x head %08x tail %08x start %08x\n",
 585                               ring->name,
 586                               I915_READ_CTL(ring),
 587                               I915_READ_HEAD(ring),
 588                               I915_READ_TAIL(ring),
 589                               I915_READ_START(ring));
 590
 591                 if (!stop_ring(ring)) {
 592                         DRM_ERROR("failed to set %s head to zero "
 593                                   "ctl %08x head %08x tail %08x start %08x\n",
 594                                   ring->name,
 595                                   I915_READ_CTL(ring),
 596                                   I915_READ_HEAD(ring),
 597                                   I915_READ_TAIL(ring),
 598                                   I915_READ_START(ring));
 599                         ret = -EIO;
 600                         goto out;
 601                 }
 602         }
 603
 604         if (I915_NEED_GFX_HWS(dev))
 605                 intel_ring_setup_status_page(ring);
 606         else
 607                 ring_setup_phys_status_page(ring);
 608
 609         /* Enforce ordering by reading HEAD register back */
 610         I915_READ_HEAD(ring);
 611
 612         /* Initialize the ring. This must happen _after_ we've cleared the ring
 613          * registers with the above sequence (the readback of the HEAD registers
 614          * also enforces ordering), otherwise the hw might lose the new ring
 615          * register values. */
 616         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 617
 618         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 619         if (I915_READ_HEAD(ring))
 620                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 621                           ring->name, I915_READ_HEAD(ring));
 622         I915_WRITE_HEAD(ring, 0);
 623         (void)I915_READ_HEAD(ring);
 624
 625         I915_WRITE_CTL(ring,
 626                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 627                         | RING_VALID);
 628
 629         /* If the head is still not zero, the ring is dead */
 630         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 631                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 632                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 633                 DRM_ERROR("%s initialization failed "
 634                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 635                           ring->name,
 636                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 637                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 638                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 639                 ret = -EIO;
 640                 goto out;
 641         }
 642
 643         ringbuf->last_retired_head = -1;
 644         ringbuf->head = I915_READ_HEAD(ring);
 645         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 646         intel_ring_update_space(ringbuf);
 647
 648         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 649
 650 out:
 651         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 652
 653         return ret;
 654 }
 655
 656 void
 657 intel_fini_pipe_control(struct intel_engine_cs *ring)
 658 {
 659         struct drm_device *dev = ring->dev;
 660
 661         if (ring->scratch.obj == NULL)
 662                 return;
 663
 664         if (INTEL_INFO(dev)->gen >= 5) {
 665                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 666                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 667         }
 668
 669         drm_gem_object_unreference(&ring->scratch.obj->base);
 670         ring->scratch.obj = NULL;
 671 }
 672
 673 int
 674 intel_init_pipe_control(struct intel_engine_cs *ring)
 675 {
 676         int ret;
 677
 678         WARN_ON(ring->scratch.obj);
 679
 680         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 681         if (ring->scratch.obj == NULL) {
 682                 DRM_ERROR("Failed to allocate seqno page\n");
 683                 ret = -ENOMEM;
 684                 goto err;
 685         }
 686
 687         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 688         if (ret)
 689                 goto err_unref;
 690
 691         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 692         if (ret)
 693                 goto err_unref;
 694
 695         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 696         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 697         if (ring->scratch.cpu_page == NULL) {
 698                 ret = -ENOMEM;
 699                 goto err_unpin;
 700         }
 701
 702         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 703                          ring->name, ring->scratch.gtt_offset);
 704         return 0;
 705
 706 err_unpin:
 707         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 708 err_unref:
 709         drm_gem_object_unreference(&ring->scratch.obj->base);
 710 err:
 711         return ret;
 712 }
 713
 714 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 715 {
 716         int ret, i;
 717         struct intel_engine_cs *ring = req->ring;
 718         struct drm_device *dev = ring->dev;
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         struct i915_workarounds *w = &dev_priv->workarounds;
 721
 722         if (w->count == 0)
 723                 return 0;
 724
 725         ring->gpu_caches_dirty = true;
 726         ret = intel_ring_flush_all_caches(req);
 727         if (ret)
 728                 return ret;
 729
 730         ret = intel_ring_begin(req, (w->count * 2 + 2));
 731         if (ret)
 732                 return ret;
 733
 734         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 735         for (i = 0; i < w->count; i++) {
 736                 intel_ring_emit_reg(ring, w->reg[i].addr);
 737                 intel_ring_emit(ring, w->reg[i].value);
 738         }
 739         intel_ring_emit(ring, MI_NOOP);
 740
 741         intel_ring_advance(ring);
 742
 743         ring->gpu_caches_dirty = true;
 744         ret = intel_ring_flush_all_caches(req);
 745         if (ret)
 746                 return ret;
 747
 748         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 749
 750         return 0;
 751 }
 752
 753 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 754 {
 755         int ret;
 756
 757         ret = intel_ring_workarounds_emit(req);
 758         if (ret != 0)
 759                 return ret;
 760
 761         ret = i915_gem_render_state_init(req);
 762         if (ret)
 763                 DRM_ERROR("init render state: %d\n", ret);
 764
 765         return ret;
 766 }
 767
 768 static int wa_add(struct drm_i915_private *dev_priv,
 769                   i915_reg_t addr,
 770                   const u32 mask, const u32 val)
 771 {
 772         const u32 idx = dev_priv->workarounds.count;
 773
 774         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 775                 return -ENOSPC;
 776
 777         dev_priv->workarounds.reg[idx].addr = addr;
 778         dev_priv->workarounds.reg[idx].value = val;
 779         dev_priv->workarounds.reg[idx].mask = mask;
 780
 781         dev_priv->workarounds.count++;
 782
 783         return 0;
 784 }
 785
 786 #define WA_REG(addr, mask, val) do { \
 787                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 788                 if (r) \
 789                         return r; \
 790         } while (0)
 791
 792 #define WA_SET_BIT_MASKED(addr, mask) \
 793         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 794
 795 #define WA_CLR_BIT_MASKED(addr, mask) \
 796         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 797
 798 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 799         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 800
 801 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 802 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 803
 804 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 805
 806 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 807 {
 808         struct drm_device *dev = ring->dev;
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810
 811         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 812
 813         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 814         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 815
 816         /* WaDisablePartialInstShootdown:bdw,chv */
 817         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 818                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 819
 820         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 821          * workaround for for a possible hang in the unlikely event a TLB
 822          * invalidation occurs during a PSD flush.
 823          */
 824         /* WaForceEnableNonCoherent:bdw,chv */
 825         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 826         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 827                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 828                           HDC_FORCE_NON_COHERENT);
 829
 830         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 831          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 832          *  polygons in the same 8x4 pixel/sample area to be processed without
 833          *  stalling waiting for the earlier ones to write to Hierarchical Z
 834          *  buffer."
 835          *
 836          * This optimization is off by default for BDW and CHV; turn it on.
 837          */
 838         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 839
 840         /* Wa4x4STCOptimizationDisable:bdw,chv */
 841         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 842
 843         /*
 844          * BSpec recommends 8x4 when MSAA is used,
 845          * however in practice 16x4 seems fastest.
 846          *
 847          * Note that PS/WM thread counts depend on the WIZ hashing
 848          * disable bit, which we don't touch here, but it's good
 849          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 850          */
 851         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 852                             GEN6_WIZ_HASHING_MASK,
 853                             GEN6_WIZ_HASHING_16x4);
 854
 855         return 0;
 856 }
 857
 858 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 859 {
 860         int ret;
 861         struct drm_device *dev = ring->dev;
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863
 864         ret = gen8_init_workarounds(ring);
 865         if (ret)
 866                 return ret;
 867
 868         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 869         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 870
 871         /* WaDisableDopClockGating:bdw */
 872         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 873                           DOP_CLOCK_GATING_DISABLE);
 874
 875         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 876                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 877
 878         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 879                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 880                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 881                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 882                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 883
 884         return 0;
 885 }
 886
 887 static int chv_init_workarounds(struct intel_engine_cs *ring)
 888 {
 889         int ret;
 890         struct drm_device *dev = ring->dev;
 891         struct drm_i915_private *dev_priv = dev->dev_private;
 892
 893         ret = gen8_init_workarounds(ring);
 894         if (ret)
 895                 return ret;
 896
 897         /* WaDisableThreadStallDopClockGating:chv */
 898         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 899
 900         /* Improve HiZ throughput on CHV. */
 901         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 902
 903         return 0;
 904 }
 905
 906 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 907 {
 908         struct drm_device *dev = ring->dev;
 909         struct drm_i915_private *dev_priv = dev->dev_private;
 910         uint32_t tmp;
 911
 912         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 913         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 914                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 915
 916         /* WaDisableKillLogic:bxt,skl */
 917         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 918                    ECOCHK_DIS_TLB);
 919
 920         /* WaDisablePartialInstShootdown:skl,bxt */
 921         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 922                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 923
 924         /* Syncing dependencies between camera and graphics:skl,bxt */
 925         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 926                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 927
 928         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 929         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 930             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 931                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 932                                   GEN9_DG_MIRROR_FIX_ENABLE);
 933
 934         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 935         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 936             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 937                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 938                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 939                 /*
 940                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 941                  * but we do that in per ctx batchbuffer as there is an issue
 942                  * with this register not getting restored on ctx restore
 943                  */
 944         }
 945
 946         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 947         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
 948                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 949                                   GEN9_ENABLE_YV12_BUGFIX);
 950
 951         /* Wa4x4STCOptimizationDisable:skl,bxt */
 952         /* WaDisablePartialResolveInVc:skl,bxt */
 953         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 954                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 955
 956         /* WaCcsTlbPrefetchDisable:skl,bxt */
 957         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 958                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 959
 960         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 961         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 962             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 963                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 964                                   PIXEL_MASK_CAMMING_DISABLE);
 965
 966         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 967         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 968         if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
 969             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 970                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 971         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 972
 973         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 974         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 975                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 976                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 977
 978         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 979         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 980
 981         return 0;
 982 }
 983
 984 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 985 {
 986         struct drm_device *dev = ring->dev;
 987         struct drm_i915_private *dev_priv = dev->dev_private;
 988         u8 vals[3] = { 0, 0, 0 };
 989         unsigned int i;
 990
 991         for (i = 0; i < 3; i++) {
 992                 u8 ss;
 993
 994                 /*
 995                  * Only consider slices where one, and only one, subslice has 7
 996                  * EUs
 997                  */
 998                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
 999                         continue;
1000
1001                 /*
1002                  * subslice_7eu[i] != 0 (because of the check above) and
1003                  * ss_max == 4 (maximum number of subslices possible per slice)
1004                  *
1005                  * ->    0 <= ss <= 3;
1006                  */
1007                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1008                 vals[i] = 3 - ss;
1009         }
1010
1011         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1012                 return 0;
1013
1014         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1015         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1016                             GEN9_IZ_HASHING_MASK(2) |
1017                             GEN9_IZ_HASHING_MASK(1) |
1018                             GEN9_IZ_HASHING_MASK(0),
1019                             GEN9_IZ_HASHING(2, vals[2]) |
1020                             GEN9_IZ_HASHING(1, vals[1]) |
1021                             GEN9_IZ_HASHING(0, vals[0]));
1022
1023         return 0;
1024 }
1025
1026 static int skl_init_workarounds(struct intel_engine_cs *ring)
1027 {
1028         int ret;
1029         struct drm_device *dev = ring->dev;
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031
1032         ret = gen9_init_workarounds(ring);
1033         if (ret)
1034                 return ret;
1035
1036         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1037                 /* WaDisableHDCInvalidation:skl */
1038                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1039                            BDW_DISABLE_HDC_INVALIDATION);
1040
1041                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1042                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1043                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1044         }
1045
1046         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1047          * involving this register should also be added to WA batch as required.
1048          */
1049         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1050                 /* WaDisableLSQCROPERFforOCL:skl */
1051                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1052                            GEN8_LQSC_RO_PERF_DIS);
1053
1054         /* WaEnableGapsTsvCreditFix:skl */
1055         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1056                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1057                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1058         }
1059
1060         /* WaDisablePowerCompilerClockGating:skl */
1061         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1062                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1063                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1064
1065         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1066                 /*
1067                  *Use Force Non-Coherent whenever executing a 3D context. This
1068                  * is a workaround for a possible hang in the unlikely event
1069                  * a TLB invalidation occurs during a PSD flush.
1070                  */
1071                 /* WaForceEnableNonCoherent:skl */
1072                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1073                                   HDC_FORCE_NON_COHERENT);
1074         }
1075
1076         /* WaBarrierPerformanceFixDisable:skl */
1077         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1078                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1079                                   HDC_FENCE_DEST_SLM_DISABLE |
1080                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1081
1082         /* WaDisableSbeCacheDispatchPortSharing:skl */
1083         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1084                 WA_SET_BIT_MASKED(
1085                         GEN7_HALF_SLICE_CHICKEN1,
1086                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1087
1088         return skl_tune_iz_hashing(ring);
1089 }
1090
1091 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1092 {
1093         int ret;
1094         struct drm_device *dev = ring->dev;
1095         struct drm_i915_private *dev_priv = dev->dev_private;
1096
1097         ret = gen9_init_workarounds(ring);
1098         if (ret)
1099                 return ret;
1100
1101         /* WaStoreMultiplePTEenable:bxt */
1102         /* This is a requirement according to Hardware specification */
1103         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1104                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1105
1106         /* WaSetClckGatingDisableMedia:bxt */
1107         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1108                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1109                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1110         }
1111
1112         /* WaDisableThreadStallDopClockGating:bxt */
1113         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1114                           STALL_DOP_GATING_DISABLE);
1115
1116         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1117         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1118                 WA_SET_BIT_MASKED(
1119                         GEN7_HALF_SLICE_CHICKEN1,
1120                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1121         }
1122
1123         return 0;
1124 }
1125
1126 int init_workarounds_ring(struct intel_engine_cs *ring)
1127 {
1128         struct drm_device *dev = ring->dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130
1131         WARN_ON(ring->id != RCS);
1132
1133         dev_priv->workarounds.count = 0;
1134
1135         if (IS_BROADWELL(dev))
1136                 return bdw_init_workarounds(ring);
1137
1138         if (IS_CHERRYVIEW(dev))
1139                 return chv_init_workarounds(ring);
1140
1141         if (IS_SKYLAKE(dev))
1142                 return skl_init_workarounds(ring);
1143
1144         if (IS_BROXTON(dev))
1145                 return bxt_init_workarounds(ring);
1146
1147         return 0;
1148 }
1149
1150 static int init_render_ring(struct intel_engine_cs *ring)
1151 {
1152         struct drm_device *dev = ring->dev;
1153         struct drm_i915_private *dev_priv = dev->dev_private;
1154         int ret = init_ring_common(ring);
1155         if (ret)
1156                 return ret;
1157
1158         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1159         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1160                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1161
1162         /* We need to disable the AsyncFlip performance optimisations in order
1163          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1164          * programmed to '1' on all products.
1165          *
1166          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1167          */
1168         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1169                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1170
1171         /* Required for the hardware to program scanline values for waiting */
1172         /* WaEnableFlushTlbInvalidationMode:snb */
1173         if (INTEL_INFO(dev)->gen == 6)
1174                 I915_WRITE(GFX_MODE,
1175                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1176
1177         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1178         if (IS_GEN7(dev))
1179                 I915_WRITE(GFX_MODE_GEN7,
1180                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1181                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1182
1183         if (IS_GEN6(dev)) {
1184                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1185                  * "If this bit is set, STCunit will have LRA as replacement
1186                  *  policy. [...] This bit must be reset.  LRA replacement
1187                  *  policy is not supported."
1188                  */
1189                 I915_WRITE(CACHE_MODE_0,
1190                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1191         }
1192
1193         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1194                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1195
1196         if (HAS_L3_DPF(dev))
1197                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1198
1199         return init_workarounds_ring(ring);
1200 }
1201
1202 static void render_ring_cleanup(struct intel_engine_cs *ring)
1203 {
1204         struct drm_device *dev = ring->dev;
1205         struct drm_i915_private *dev_priv = dev->dev_private;
1206
1207         if (dev_priv->semaphore_obj) {
1208                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1209                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1210                 dev_priv->semaphore_obj = NULL;
1211         }
1212
1213         intel_fini_pipe_control(ring);
1214 }
1215
1216 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1217                            unsigned int num_dwords)
1218 {
1219 #define MBOX_UPDATE_DWORDS 8
1220         struct intel_engine_cs *signaller = signaller_req->ring;
1221         struct drm_device *dev = signaller->dev;
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223         struct intel_engine_cs *waiter;
1224         int i, ret, num_rings;
1225
1226         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1227         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1228 #undef MBOX_UPDATE_DWORDS
1229
1230         ret = intel_ring_begin(signaller_req, num_dwords);
1231         if (ret)
1232                 return ret;
1233
1234         for_each_ring(waiter, dev_priv, i) {
1235                 u32 seqno;
1236                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1237                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1238                         continue;
1239
1240                 seqno = i915_gem_request_get_seqno(signaller_req);
1241                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1242                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1243                                            PIPE_CONTROL_QW_WRITE |
1244                                            PIPE_CONTROL_FLUSH_ENABLE);
1245                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1246                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1247                 intel_ring_emit(signaller, seqno);
1248                 intel_ring_emit(signaller, 0);
1249                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1250                                            MI_SEMAPHORE_TARGET(waiter->id));
1251                 intel_ring_emit(signaller, 0);
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1258                            unsigned int num_dwords)
1259 {
1260 #define MBOX_UPDATE_DWORDS 6
1261         struct intel_engine_cs *signaller = signaller_req->ring;
1262         struct drm_device *dev = signaller->dev;
1263         struct drm_i915_private *dev_priv = dev->dev_private;
1264         struct intel_engine_cs *waiter;
1265         int i, ret, num_rings;
1266
1267         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1268         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1269 #undef MBOX_UPDATE_DWORDS
1270
1271         ret = intel_ring_begin(signaller_req, num_dwords);
1272         if (ret)
1273                 return ret;
1274
1275         for_each_ring(waiter, dev_priv, i) {
1276                 u32 seqno;
1277                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1278                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1279                         continue;
1280
1281                 seqno = i915_gem_request_get_seqno(signaller_req);
1282                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1283                                            MI_FLUSH_DW_OP_STOREDW);
1284                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1285                                            MI_FLUSH_DW_USE_GTT);
1286                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1287                 intel_ring_emit(signaller, seqno);
1288                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1289                                            MI_SEMAPHORE_TARGET(waiter->id));
1290                 intel_ring_emit(signaller, 0);
1291         }
1292
1293         return 0;
1294 }
1295
1296 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1297                        unsigned int num_dwords)
1298 {
1299         struct intel_engine_cs *signaller = signaller_req->ring;
1300         struct drm_device *dev = signaller->dev;
1301         struct drm_i915_private *dev_priv = dev->dev_private;
1302         struct intel_engine_cs *useless;
1303         int i, ret, num_rings;
1304
1305 #define MBOX_UPDATE_DWORDS 3
1306         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1307         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1308 #undef MBOX_UPDATE_DWORDS
1309
1310         ret = intel_ring_begin(signaller_req, num_dwords);
1311         if (ret)
1312                 return ret;
1313
1314         for_each_ring(useless, dev_priv, i) {
1315                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1316
1317                 if (i915_mmio_reg_valid(mbox_reg)) {
1318                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1319
1320                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1321                         intel_ring_emit_reg(signaller, mbox_reg);
1322                         intel_ring_emit(signaller, seqno);
1323                 }
1324         }
1325
1326         /* If num_dwords was rounded, make sure the tail pointer is correct */
1327         if (num_rings % 2 == 0)
1328                 intel_ring_emit(signaller, MI_NOOP);
1329
1330         return 0;
1331 }
1332
1333 /**
1334  * gen6_add_request - Update the semaphore mailbox registers
1335  *
1336  * @request - request to write to the ring
1337  *
1338  * Update the mailbox registers in the *other* rings with the current seqno.
1339  * This acts like a signal in the canonical semaphore.
1340  */
1341 static int
1342 gen6_add_request(struct drm_i915_gem_request *req)
1343 {
1344         struct intel_engine_cs *ring = req->ring;
1345         int ret;
1346
1347         if (ring->semaphore.signal)
1348                 ret = ring->semaphore.signal(req, 4);
1349         else
1350                 ret = intel_ring_begin(req, 4);
1351
1352         if (ret)
1353                 return ret;
1354
1355         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1356         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1357         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1358         intel_ring_emit(ring, MI_USER_INTERRUPT);
1359         __intel_ring_advance(ring);
1360
1361         return 0;
1362 }
1363
1364 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1365                                               u32 seqno)
1366 {
1367         struct drm_i915_private *dev_priv = dev->dev_private;
1368         return dev_priv->last_seqno < seqno;
1369 }
1370
1371 /**
1372  * intel_ring_sync - sync the waiter to the signaller on seqno
1373  *
1374  * @waiter - ring that is waiting
1375  * @signaller - ring which has, or will signal
1376  * @seqno - seqno which the waiter will block on
1377  */
1378
1379 static int
1380 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1381                struct intel_engine_cs *signaller,
1382                u32 seqno)
1383 {
1384         struct intel_engine_cs *waiter = waiter_req->ring;
1385         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1386         int ret;
1387
1388         ret = intel_ring_begin(waiter_req, 4);
1389         if (ret)
1390                 return ret;
1391
1392         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1393                                 MI_SEMAPHORE_GLOBAL_GTT |
1394                                 MI_SEMAPHORE_POLL |
1395                                 MI_SEMAPHORE_SAD_GTE_SDD);
1396         intel_ring_emit(waiter, seqno);
1397         intel_ring_emit(waiter,
1398                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1399         intel_ring_emit(waiter,
1400                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1401         intel_ring_advance(waiter);
1402         return 0;
1403 }
1404
1405 static int
1406 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1407                struct intel_engine_cs *signaller,
1408                u32 seqno)
1409 {
1410         struct intel_engine_cs *waiter = waiter_req->ring;
1411         u32 dw1 = MI_SEMAPHORE_MBOX |
1412                   MI_SEMAPHORE_COMPARE |
1413                   MI_SEMAPHORE_REGISTER;
1414         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1415         int ret;
1416
1417         /* Throughout all of the GEM code, seqno passed implies our current
1418          * seqno is >= the last seqno executed. However for hardware the
1419          * comparison is strictly greater than.
1420          */
1421         seqno -= 1;
1422
1423         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1424
1425         ret = intel_ring_begin(waiter_req, 4);
1426         if (ret)
1427                 return ret;
1428
1429         /* If seqno wrap happened, omit the wait with no-ops */
1430         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1431                 intel_ring_emit(waiter, dw1 | wait_mbox);
1432                 intel_ring_emit(waiter, seqno);
1433                 intel_ring_emit(waiter, 0);
1434                 intel_ring_emit(waiter, MI_NOOP);
1435         } else {
1436                 intel_ring_emit(waiter, MI_NOOP);
1437                 intel_ring_emit(waiter, MI_NOOP);
1438                 intel_ring_emit(waiter, MI_NOOP);
1439                 intel_ring_emit(waiter, MI_NOOP);
1440         }
1441         intel_ring_advance(waiter);
1442
1443         return 0;
1444 }
1445
1446 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1447 do {                                                                    \
1448         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1449                  PIPE_CONTROL_DEPTH_STALL);                             \
1450         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1451         intel_ring_emit(ring__, 0);                                                     \
1452         intel_ring_emit(ring__, 0);                                                     \
1453 } while (0)
1454
1455 static int
1456 pc_render_add_request(struct drm_i915_gem_request *req)
1457 {
1458         struct intel_engine_cs *ring = req->ring;
1459         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1460         int ret;
1461
1462         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1463          * incoherent with writes to memory, i.e. completely fubar,
1464          * so we need to use PIPE_NOTIFY instead.
1465          *
1466          * However, we also need to workaround the qword write
1467          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1468          * memory before requesting an interrupt.
1469          */
1470         ret = intel_ring_begin(req, 32);
1471         if (ret)
1472                 return ret;
1473
1474         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1475                         PIPE_CONTROL_WRITE_FLUSH |
1476                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1477         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1478         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1479         intel_ring_emit(ring, 0);
1480         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1481         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1482         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1483         scratch_addr += 2 * CACHELINE_BYTES;
1484         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1485         scratch_addr += 2 * CACHELINE_BYTES;
1486         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1487         scratch_addr += 2 * CACHELINE_BYTES;
1488         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1489         scratch_addr += 2 * CACHELINE_BYTES;
1490         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1491
1492         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1493                         PIPE_CONTROL_WRITE_FLUSH |
1494                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1495                         PIPE_CONTROL_NOTIFY);
1496         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1497         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1498         intel_ring_emit(ring, 0);
1499         __intel_ring_advance(ring);
1500
1501         return 0;
1502 }
1503
1504 static u32
1505 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1506 {
1507         /* Workaround to force correct ordering between irq and seqno writes on
1508          * ivb (and maybe also on snb) by reading from a CS register (like
1509          * ACTHD) before reading the status page. */
1510         if (!lazy_coherency) {
1511                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1512                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1513         }
1514
1515         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1516 }
1517
1518 static u32
1519 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1520 {
1521         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1522 }
1523
1524 static void
1525 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1526 {
1527         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1528 }
1529
1530 static u32
1531 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1532 {
1533         return ring->scratch.cpu_page[0];
1534 }
1535
1536 static void
1537 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1538 {
1539         ring->scratch.cpu_page[0] = seqno;
1540 }
1541
1542 static bool
1543 gen5_ring_get_irq(struct intel_engine_cs *ring)
1544 {
1545         struct drm_device *dev = ring->dev;
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547         unsigned long flags;
1548
1549         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1550                 return false;
1551
1552         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1553         if (ring->irq_refcount++ == 0)
1554                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1555         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1556
1557         return true;
1558 }
1559
1560 static void
1561 gen5_ring_put_irq(struct intel_engine_cs *ring)
1562 {
1563         struct drm_device *dev = ring->dev;
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565         unsigned long flags;
1566
1567         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1568         if (--ring->irq_refcount == 0)
1569                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1570         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1571 }
1572
1573 static bool
1574 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1575 {
1576         struct drm_device *dev = ring->dev;
1577         struct drm_i915_private *dev_priv = dev->dev_private;
1578         unsigned long flags;
1579
1580         if (!intel_irqs_enabled(dev_priv))
1581                 return false;
1582
1583         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1584         if (ring->irq_refcount++ == 0) {
1585                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1586                 I915_WRITE(IMR, dev_priv->irq_mask);
1587                 POSTING_READ(IMR);
1588         }
1589         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1590
1591         return true;
1592 }
1593
1594 static void
1595 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1596 {
1597         struct drm_device *dev = ring->dev;
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         unsigned long flags;
1600
1601         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1602         if (--ring->irq_refcount == 0) {
1603                 dev_priv->irq_mask |= ring->irq_enable_mask;
1604                 I915_WRITE(IMR, dev_priv->irq_mask);
1605                 POSTING_READ(IMR);
1606         }
1607         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1608 }
1609
1610 static bool
1611 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1612 {
1613         struct drm_device *dev = ring->dev;
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615         unsigned long flags;
1616
1617         if (!intel_irqs_enabled(dev_priv))
1618                 return false;
1619
1620         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1621         if (ring->irq_refcount++ == 0) {
1622                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1623                 I915_WRITE16(IMR, dev_priv->irq_mask);
1624                 POSTING_READ16(IMR);
1625         }
1626         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1627
1628         return true;
1629 }
1630
1631 static void
1632 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1633 {
1634         struct drm_device *dev = ring->dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636         unsigned long flags;
1637
1638         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1639         if (--ring->irq_refcount == 0) {
1640                 dev_priv->irq_mask |= ring->irq_enable_mask;
1641                 I915_WRITE16(IMR, dev_priv->irq_mask);
1642                 POSTING_READ16(IMR);
1643         }
1644         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1645 }
1646
1647 static int
1648 bsd_ring_flush(struct drm_i915_gem_request *req,
1649                u32     invalidate_domains,
1650                u32     flush_domains)
1651 {
1652         struct intel_engine_cs *ring = req->ring;
1653         int ret;
1654
1655         ret = intel_ring_begin(req, 2);
1656         if (ret)
1657                 return ret;
1658
1659         intel_ring_emit(ring, MI_FLUSH);
1660         intel_ring_emit(ring, MI_NOOP);
1661         intel_ring_advance(ring);
1662         return 0;
1663 }
1664
1665 static int
1666 i9xx_add_request(struct drm_i915_gem_request *req)
1667 {
1668         struct intel_engine_cs *ring = req->ring;
1669         int ret;
1670
1671         ret = intel_ring_begin(req, 4);
1672         if (ret)
1673                 return ret;
1674
1675         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1676         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1677         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1678         intel_ring_emit(ring, MI_USER_INTERRUPT);
1679         __intel_ring_advance(ring);
1680
1681         return 0;
1682 }
1683
1684 static bool
1685 gen6_ring_get_irq(struct intel_engine_cs *ring)
1686 {
1687         struct drm_device *dev = ring->dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         unsigned long flags;
1690
1691         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1692                 return false;
1693
1694         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1695         if (ring->irq_refcount++ == 0) {
1696                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1697                         I915_WRITE_IMR(ring,
1698                                        ~(ring->irq_enable_mask |
1699                                          GT_PARITY_ERROR(dev)));
1700                 else
1701                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1702                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1703         }
1704         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1705
1706         return true;
1707 }
1708
1709 static void
1710 gen6_ring_put_irq(struct intel_engine_cs *ring)
1711 {
1712         struct drm_device *dev = ring->dev;
1713         struct drm_i915_private *dev_priv = dev->dev_private;
1714         unsigned long flags;
1715
1716         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1717         if (--ring->irq_refcount == 0) {
1718                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1719                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1720                 else
1721                         I915_WRITE_IMR(ring, ~0);
1722                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1723         }
1724         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1725 }
1726
1727 static bool
1728 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1729 {
1730         struct drm_device *dev = ring->dev;
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         unsigned long flags;
1733
1734         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1735                 return false;
1736
1737         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1738         if (ring->irq_refcount++ == 0) {
1739                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1740                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1741         }
1742         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1743
1744         return true;
1745 }
1746
1747 static void
1748 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1749 {
1750         struct drm_device *dev = ring->dev;
1751         struct drm_i915_private *dev_priv = dev->dev_private;
1752         unsigned long flags;
1753
1754         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1755         if (--ring->irq_refcount == 0) {
1756                 I915_WRITE_IMR(ring, ~0);
1757                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1758         }
1759         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1760 }
1761
1762 static bool
1763 gen8_ring_get_irq(struct intel_engine_cs *ring)
1764 {
1765         struct drm_device *dev = ring->dev;
1766         struct drm_i915_private *dev_priv = dev->dev_private;
1767         unsigned long flags;
1768
1769         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1770                 return false;
1771
1772         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1773         if (ring->irq_refcount++ == 0) {
1774                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1775                         I915_WRITE_IMR(ring,
1776                                        ~(ring->irq_enable_mask |
1777                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1778                 } else {
1779                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1780                 }
1781                 POSTING_READ(RING_IMR(ring->mmio_base));
1782         }
1783         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1784
1785         return true;
1786 }
1787
1788 static void
1789 gen8_ring_put_irq(struct intel_engine_cs *ring)
1790 {
1791         struct drm_device *dev = ring->dev;
1792         struct drm_i915_private *dev_priv = dev->dev_private;
1793         unsigned long flags;
1794
1795         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1796         if (--ring->irq_refcount == 0) {
1797                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1798                         I915_WRITE_IMR(ring,
1799                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1800                 } else {
1801                         I915_WRITE_IMR(ring, ~0);
1802                 }
1803                 POSTING_READ(RING_IMR(ring->mmio_base));
1804         }
1805         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1806 }
1807
1808 static int
1809 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1810                          u64 offset, u32 length,
1811                          unsigned dispatch_flags)
1812 {
1813         struct intel_engine_cs *ring = req->ring;
1814         int ret;
1815
1816         ret = intel_ring_begin(req, 2);
1817         if (ret)
1818                 return ret;
1819
1820         intel_ring_emit(ring,
1821                         MI_BATCH_BUFFER_START |
1822                         MI_BATCH_GTT |
1823                         (dispatch_flags & I915_DISPATCH_SECURE ?
1824                          0 : MI_BATCH_NON_SECURE_I965));
1825         intel_ring_emit(ring, offset);
1826         intel_ring_advance(ring);
1827
1828         return 0;
1829 }
1830
1831 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1832 #define I830_BATCH_LIMIT (256*1024)
1833 #define I830_TLB_ENTRIES (2)
1834 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1835 static int
1836 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1837                          u64 offset, u32 len,
1838                          unsigned dispatch_flags)
1839 {
1840         struct intel_engine_cs *ring = req->ring;
1841         u32 cs_offset = ring->scratch.gtt_offset;
1842         int ret;
1843
1844         ret = intel_ring_begin(req, 6);
1845         if (ret)
1846                 return ret;
1847
1848         /* Evict the invalid PTE TLBs */
1849         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1850         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1851         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1852         intel_ring_emit(ring, cs_offset);
1853         intel_ring_emit(ring, 0xdeadbeef);
1854         intel_ring_emit(ring, MI_NOOP);
1855         intel_ring_advance(ring);
1856
1857         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1858                 if (len > I830_BATCH_LIMIT)
1859                         return -ENOSPC;
1860
1861                 ret = intel_ring_begin(req, 6 + 2);
1862                 if (ret)
1863                         return ret;
1864
1865                 /* Blit the batch (which has now all relocs applied) to the
1866                  * stable batch scratch bo area (so that the CS never
1867                  * stumbles over its tlb invalidation bug) ...
1868                  */
1869                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1870                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1871                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1872                 intel_ring_emit(ring, cs_offset);
1873                 intel_ring_emit(ring, 4096);
1874                 intel_ring_emit(ring, offset);
1875
1876                 intel_ring_emit(ring, MI_FLUSH);
1877                 intel_ring_emit(ring, MI_NOOP);
1878                 intel_ring_advance(ring);
1879
1880                 /* ... and execute it. */
1881                 offset = cs_offset;
1882         }
1883
1884         ret = intel_ring_begin(req, 4);
1885         if (ret)
1886                 return ret;
1887
1888         intel_ring_emit(ring, MI_BATCH_BUFFER);
1889         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1890                                         0 : MI_BATCH_NON_SECURE));
1891         intel_ring_emit(ring, offset + len - 8);
1892         intel_ring_emit(ring, MI_NOOP);
1893         intel_ring_advance(ring);
1894
1895         return 0;
1896 }
1897
1898 static int
1899 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1900                          u64 offset, u32 len,
1901                          unsigned dispatch_flags)
1902 {
1903         struct intel_engine_cs *ring = req->ring;
1904         int ret;
1905
1906         ret = intel_ring_begin(req, 2);
1907         if (ret)
1908                 return ret;
1909
1910         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1911         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1912                                         0 : MI_BATCH_NON_SECURE));
1913         intel_ring_advance(ring);
1914
1915         return 0;
1916 }
1917
1918 static void cleanup_status_page(struct intel_engine_cs *ring)
1919 {
1920         struct drm_i915_gem_object *obj;
1921
1922         obj = ring->status_page.obj;
1923         if (obj == NULL)
1924                 return;
1925
1926         kunmap(sg_page(obj->pages->sgl));
1927         i915_gem_object_ggtt_unpin(obj);
1928         drm_gem_object_unreference(&obj->base);
1929         ring->status_page.obj = NULL;
1930 }
1931
1932 static int init_status_page(struct intel_engine_cs *ring)
1933 {
1934         struct drm_i915_gem_object *obj;
1935
1936         if ((obj = ring->status_page.obj) == NULL) {
1937                 unsigned flags;
1938                 int ret;
1939
1940                 obj = i915_gem_alloc_object(ring->dev, 4096);
1941                 if (obj == NULL) {
1942                         DRM_ERROR("Failed to allocate status page\n");
1943                         return -ENOMEM;
1944                 }
1945
1946                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1947                 if (ret)
1948                         goto err_unref;
1949
1950                 flags = 0;
1951                 if (!HAS_LLC(ring->dev))
1952                         /* On g33, we cannot place HWS above 256MiB, so
1953                          * restrict its pinning to the low mappable arena.
1954                          * Though this restriction is not documented for
1955                          * gen4, gen5, or byt, they also behave similarly
1956                          * and hang if the HWS is placed at the top of the
1957                          * GTT. To generalise, it appears that all !llc
1958                          * platforms have issues with us placing the HWS
1959                          * above the mappable region (even though we never
1960                          * actualy map it).
1961                          */
1962                         flags |= PIN_MAPPABLE;
1963                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1964                 if (ret) {
1965 err_unref:
1966                         drm_gem_object_unreference(&obj->base);
1967                         return ret;
1968                 }
1969
1970                 ring->status_page.obj = obj;
1971         }
1972
1973         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1974         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1975         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1976
1977         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1978                         ring->name, ring->status_page.gfx_addr);
1979
1980         return 0;
1981 }
1982
1983 static int init_phys_status_page(struct intel_engine_cs *ring)
1984 {
1985         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1986
1987         if (!dev_priv->status_page_dmah) {
1988                 dev_priv->status_page_dmah =
1989                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1990                 if (!dev_priv->status_page_dmah)
1991                         return -ENOMEM;
1992         }
1993
1994         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1995         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1996
1997         return 0;
1998 }
1999
2000 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2001 {
2002         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2003                 vunmap(ringbuf->virtual_start);
2004         else
2005                 iounmap(ringbuf->virtual_start);
2006         ringbuf->virtual_start = NULL;
2007         i915_gem_object_ggtt_unpin(ringbuf->obj);
2008 }
2009
2010 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2011 {
2012         struct sg_page_iter sg_iter;
2013         struct page **pages;
2014         void *addr;
2015         int i;
2016
2017         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2018         if (pages == NULL)
2019                 return NULL;
2020
2021         i = 0;
2022         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2023                 pages[i++] = sg_page_iter_page(&sg_iter);
2024
2025         addr = vmap(pages, i, 0, PAGE_KERNEL);
2026         drm_free_large(pages);
2027
2028         return addr;
2029 }
2030
2031 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2032                                      struct intel_ringbuffer *ringbuf)
2033 {
2034         struct drm_i915_private *dev_priv = to_i915(dev);
2035         struct drm_i915_gem_object *obj = ringbuf->obj;
2036         int ret;
2037
2038         if (HAS_LLC(dev_priv) && !obj->stolen) {
2039                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2040                 if (ret)
2041                         return ret;
2042
2043                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2044                 if (ret) {
2045                         i915_gem_object_ggtt_unpin(obj);
2046                         return ret;
2047                 }
2048
2049                 ringbuf->virtual_start = vmap_obj(obj);
2050                 if (ringbuf->virtual_start == NULL) {
2051                         i915_gem_object_ggtt_unpin(obj);
2052                         return -ENOMEM;
2053                 }
2054         } else {
2055                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2056                 if (ret)
2057                         return ret;
2058
2059                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2060                 if (ret) {
2061                         i915_gem_object_ggtt_unpin(obj);
2062                         return ret;
2063                 }
2064
2065                 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2066                                                     i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2067                 if (ringbuf->virtual_start == NULL) {
2068                         i915_gem_object_ggtt_unpin(obj);
2069                         return -EINVAL;
2070                 }
2071         }
2072
2073         return 0;
2074 }
2075
2076 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2077 {
2078         drm_gem_object_unreference(&ringbuf->obj->base);
2079         ringbuf->obj = NULL;
2080 }
2081
2082 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2083                                       struct intel_ringbuffer *ringbuf)
2084 {
2085         struct drm_i915_gem_object *obj;
2086
2087         obj = NULL;
2088         if (!HAS_LLC(dev))
2089                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2090         if (obj == NULL)
2091                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2092         if (obj == NULL)
2093                 return -ENOMEM;
2094
2095         /* mark ring buffers as read-only from GPU side by default */
2096         obj->gt_ro = 1;
2097
2098         ringbuf->obj = obj;
2099
2100         return 0;
2101 }
2102
2103 struct intel_ringbuffer *
2104 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2105 {
2106         struct intel_ringbuffer *ring;
2107         int ret;
2108
2109         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2110         if (ring == NULL) {
2111                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2112                                  engine->name);
2113                 return ERR_PTR(-ENOMEM);
2114         }
2115
2116         ring->ring = engine;
2117         list_add(&ring->link, &engine->buffers);
2118
2119         ring->size = size;
2120         /* Workaround an erratum on the i830 which causes a hang if
2121          * the TAIL pointer points to within the last 2 cachelines
2122          * of the buffer.
2123          */
2124         ring->effective_size = size;
2125         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2126                 ring->effective_size -= 2 * CACHELINE_BYTES;
2127
2128         ring->last_retired_head = -1;
2129         intel_ring_update_space(ring);
2130
2131         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2132         if (ret) {
2133                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2134                                  engine->name, ret);
2135                 list_del(&ring->link);
2136                 kfree(ring);
2137                 return ERR_PTR(ret);
2138         }
2139
2140         return ring;
2141 }
2142
2143 void
2144 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2145 {
2146         intel_destroy_ringbuffer_obj(ring);
2147         list_del(&ring->link);
2148         kfree(ring);
2149 }
2150
2151 static int intel_init_ring_buffer(struct drm_device *dev,
2152                                   struct intel_engine_cs *ring)
2153 {
2154         struct intel_ringbuffer *ringbuf;
2155         int ret;
2156
2157         WARN_ON(ring->buffer);
2158
2159         ring->dev = dev;
2160         INIT_LIST_HEAD(&ring->active_list);
2161         INIT_LIST_HEAD(&ring->request_list);
2162         INIT_LIST_HEAD(&ring->execlist_queue);
2163         INIT_LIST_HEAD(&ring->buffers);
2164         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2165         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2166
2167         init_waitqueue_head(&ring->irq_queue);
2168
2169         ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2170         if (IS_ERR(ringbuf))
2171                 return PTR_ERR(ringbuf);
2172         ring->buffer = ringbuf;
2173
2174         if (I915_NEED_GFX_HWS(dev)) {
2175                 ret = init_status_page(ring);
2176                 if (ret)
2177                         goto error;
2178         } else {
2179                 BUG_ON(ring->id != RCS);
2180                 ret = init_phys_status_page(ring);
2181                 if (ret)
2182                         goto error;
2183         }
2184
2185         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2186         if (ret) {
2187                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2188                                 ring->name, ret);
2189                 intel_destroy_ringbuffer_obj(ringbuf);
2190                 goto error;
2191         }
2192
2193         ret = i915_cmd_parser_init_ring(ring);
2194         if (ret)
2195                 goto error;
2196
2197         return 0;
2198
2199 error:
2200         intel_ringbuffer_free(ringbuf);
2201         ring->buffer = NULL;
2202         return ret;
2203 }
2204
2205 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2206 {
2207         struct drm_i915_private *dev_priv;
2208
2209         if (!intel_ring_initialized(ring))
2210                 return;
2211
2212         dev_priv = to_i915(ring->dev);
2213
2214         intel_stop_ring_buffer(ring);
2215         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2216
2217         intel_unpin_ringbuffer_obj(ring->buffer);
2218         intel_ringbuffer_free(ring->buffer);
2219         ring->buffer = NULL;
2220
2221         if (ring->cleanup)
2222                 ring->cleanup(ring);
2223
2224         cleanup_status_page(ring);
2225
2226         i915_cmd_parser_fini_ring(ring);
2227         i915_gem_batch_pool_fini(&ring->batch_pool);
2228 }
2229
2230 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2231 {
2232         struct intel_ringbuffer *ringbuf = ring->buffer;
2233         struct drm_i915_gem_request *request;
2234         unsigned space;
2235         int ret;
2236
2237         if (intel_ring_space(ringbuf) >= n)
2238                 return 0;
2239
2240         /* The whole point of reserving space is to not wait! */
2241         WARN_ON(ringbuf->reserved_in_use);
2242
2243         list_for_each_entry(request, &ring->request_list, list) {
2244                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2245                                            ringbuf->size);
2246                 if (space >= n)
2247                         break;
2248         }
2249
2250         if (WARN_ON(&request->list == &ring->request_list))
2251                 return -ENOSPC;
2252
2253         ret = i915_wait_request(request);
2254         if (ret)
2255                 return ret;
2256
2257         ringbuf->space = space;
2258         return 0;
2259 }
2260
2261 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2262 {
2263         uint32_t __iomem *virt;
2264         int rem = ringbuf->size - ringbuf->tail;
2265
2266         virt = ringbuf->virtual_start + ringbuf->tail;
2267         rem /= 4;
2268         while (rem--)
2269                 iowrite32(MI_NOOP, virt++);
2270
2271         ringbuf->tail = 0;
2272         intel_ring_update_space(ringbuf);
2273 }
2274
2275 int intel_ring_idle(struct intel_engine_cs *ring)
2276 {
2277         struct drm_i915_gem_request *req;
2278
2279         /* Wait upon the last request to be completed */
2280         if (list_empty(&ring->request_list))
2281                 return 0;
2282
2283         req = list_entry(ring->request_list.prev,
2284                         struct drm_i915_gem_request,
2285                         list);
2286
2287         /* Make sure we do not trigger any retires */
2288         return __i915_wait_request(req,
2289                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2290                                    to_i915(ring->dev)->mm.interruptible,
2291                                    NULL, NULL);
2292 }
2293
2294 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2295 {
2296         request->ringbuf = request->ring->buffer;
2297         return 0;
2298 }
2299
2300 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2301 {
2302         /*
2303          * The first call merely notes the reserve request and is common for
2304          * all back ends. The subsequent localised _begin() call actually
2305          * ensures that the reservation is available. Without the begin, if
2306          * the request creator immediately submitted the request without
2307          * adding any commands to it then there might not actually be
2308          * sufficient room for the submission commands.
2309          */
2310         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2311
2312         return intel_ring_begin(request, 0);
2313 }
2314
2315 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2316 {
2317         WARN_ON(ringbuf->reserved_size);
2318         WARN_ON(ringbuf->reserved_in_use);
2319
2320         ringbuf->reserved_size = size;
2321 }
2322
2323 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2324 {
2325         WARN_ON(ringbuf->reserved_in_use);
2326
2327         ringbuf->reserved_size   = 0;
2328         ringbuf->reserved_in_use = false;
2329 }
2330
2331 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2332 {
2333         WARN_ON(ringbuf->reserved_in_use);
2334
2335         ringbuf->reserved_in_use = true;
2336         ringbuf->reserved_tail   = ringbuf->tail;
2337 }
2338
2339 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2340 {
2341         WARN_ON(!ringbuf->reserved_in_use);
2342         if (ringbuf->tail > ringbuf->reserved_tail) {
2343                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2344                      "request reserved size too small: %d vs %d!\n",
2345                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2346         } else {
2347                 /*
2348                  * The ring was wrapped while the reserved space was in use.
2349                  * That means that some unknown amount of the ring tail was
2350                  * no-op filled and skipped. Thus simply adding the ring size
2351                  * to the tail and doing the above space check will not work.
2352                  * Rather than attempt to track how much tail was skipped,
2353                  * it is much simpler to say that also skipping the sanity
2354                  * check every once in a while is not a big issue.
2355                  */
2356         }
2357
2358         ringbuf->reserved_size   = 0;
2359         ringbuf->reserved_in_use = false;
2360 }
2361
2362 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2363 {
2364         struct intel_ringbuffer *ringbuf = ring->buffer;
2365         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2366         int remain_actual = ringbuf->size - ringbuf->tail;
2367         int ret, total_bytes, wait_bytes = 0;
2368         bool need_wrap = false;
2369
2370         if (ringbuf->reserved_in_use)
2371                 total_bytes = bytes;
2372         else
2373                 total_bytes = bytes + ringbuf->reserved_size;
2374
2375         if (unlikely(bytes > remain_usable)) {
2376                 /*
2377                  * Not enough space for the basic request. So need to flush
2378                  * out the remainder and then wait for base + reserved.
2379                  */
2380                 wait_bytes = remain_actual + total_bytes;
2381                 need_wrap = true;
2382         } else {
2383                 if (unlikely(total_bytes > remain_usable)) {
2384                         /*
2385                          * The base request will fit but the reserved space
2386                          * falls off the end. So only need to to wait for the
2387                          * reserved size after flushing out the remainder.
2388                          */
2389                         wait_bytes = remain_actual + ringbuf->reserved_size;
2390                         need_wrap = true;
2391                 } else if (total_bytes > ringbuf->space) {
2392                         /* No wrapping required, just waiting. */
2393                         wait_bytes = total_bytes;
2394                 }
2395         }
2396
2397         if (wait_bytes) {
2398                 ret = ring_wait_for_space(ring, wait_bytes);
2399                 if (unlikely(ret))
2400                         return ret;
2401
2402                 if (need_wrap)
2403                         __wrap_ring_buffer(ringbuf);
2404         }
2405
2406         return 0;
2407 }
2408
2409 int intel_ring_begin(struct drm_i915_gem_request *req,
2410                      int num_dwords)
2411 {
2412         struct intel_engine_cs *ring;
2413         struct drm_i915_private *dev_priv;
2414         int ret;
2415
2416         WARN_ON(req == NULL);
2417         ring = req->ring;
2418         dev_priv = ring->dev->dev_private;
2419
2420         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2421                                    dev_priv->mm.interruptible);
2422         if (ret)
2423                 return ret;
2424
2425         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2426         if (ret)
2427                 return ret;
2428
2429         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2430         return 0;
2431 }
2432
2433 /* Align the ring tail to a cacheline boundary */
2434 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2435 {
2436         struct intel_engine_cs *ring = req->ring;
2437         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2438         int ret;
2439
2440         if (num_dwords == 0)
2441                 return 0;
2442
2443         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2444         ret = intel_ring_begin(req, num_dwords);
2445         if (ret)
2446                 return ret;
2447
2448         while (num_dwords--)
2449                 intel_ring_emit(ring, MI_NOOP);
2450
2451         intel_ring_advance(ring);
2452
2453         return 0;
2454 }
2455
2456 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2457 {
2458         struct drm_device *dev = ring->dev;
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460
2461         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2462                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2463                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2464                 if (HAS_VEBOX(dev))
2465                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2466         }
2467
2468         ring->set_seqno(ring, seqno);
2469         ring->hangcheck.seqno = seqno;
2470 }
2471
2472 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2473                                      u32 value)
2474 {
2475         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2476
2477        /* Every tail move must follow the sequence below */
2478
2479         /* Disable notification that the ring is IDLE. The GT
2480          * will then assume that it is busy and bring it out of rc6.
2481          */
2482         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2483                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2484
2485         /* Clear the context id. Here be magic! */
2486         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2487
2488         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2489         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2490                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2491                      50))
2492                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2493
2494         /* Now that the ring is fully powered up, update the tail */
2495         I915_WRITE_TAIL(ring, value);
2496         POSTING_READ(RING_TAIL(ring->mmio_base));
2497
2498         /* Let the ring send IDLE messages to the GT again,
2499          * and so let it sleep to conserve power when idle.
2500          */
2501         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2502                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2503 }
2504
2505 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2506                                u32 invalidate, u32 flush)
2507 {
2508         struct intel_engine_cs *ring = req->ring;
2509         uint32_t cmd;
2510         int ret;
2511
2512         ret = intel_ring_begin(req, 4);
2513         if (ret)
2514                 return ret;
2515
2516         cmd = MI_FLUSH_DW;
2517         if (INTEL_INFO(ring->dev)->gen >= 8)
2518                 cmd += 1;
2519
2520         /* We always require a command barrier so that subsequent
2521          * commands, such as breadcrumb interrupts, are strictly ordered
2522          * wrt the contents of the write cache being flushed to memory
2523          * (and thus being coherent from the CPU).
2524          */
2525         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2526
2527         /*
2528          * Bspec vol 1c.5 - video engine command streamer:
2529          * "If ENABLED, all TLBs will be invalidated once the flush
2530          * operation is complete. This bit is only valid when the
2531          * Post-Sync Operation field is a value of 1h or 3h."
2532          */
2533         if (invalidate & I915_GEM_GPU_DOMAINS)
2534                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2535
2536         intel_ring_emit(ring, cmd);
2537         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2538         if (INTEL_INFO(ring->dev)->gen >= 8) {
2539                 intel_ring_emit(ring, 0); /* upper addr */
2540                 intel_ring_emit(ring, 0); /* value */
2541         } else  {
2542                 intel_ring_emit(ring, 0);
2543                 intel_ring_emit(ring, MI_NOOP);
2544         }
2545         intel_ring_advance(ring);
2546         return 0;
2547 }
2548
2549 static int
2550 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2551                               u64 offset, u32 len,
2552                               unsigned dispatch_flags)
2553 {
2554         struct intel_engine_cs *ring = req->ring;
2555         bool ppgtt = USES_PPGTT(ring->dev) &&
2556                         !(dispatch_flags & I915_DISPATCH_SECURE);
2557         int ret;
2558
2559         ret = intel_ring_begin(req, 4);
2560         if (ret)
2561                 return ret;
2562
2563         /* FIXME(BDW): Address space and security selectors. */
2564         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2565                         (dispatch_flags & I915_DISPATCH_RS ?
2566                          MI_BATCH_RESOURCE_STREAMER : 0));
2567         intel_ring_emit(ring, lower_32_bits(offset));
2568         intel_ring_emit(ring, upper_32_bits(offset));
2569         intel_ring_emit(ring, MI_NOOP);
2570         intel_ring_advance(ring);
2571
2572         return 0;
2573 }
2574
2575 static int
2576 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2577                              u64 offset, u32 len,
2578                              unsigned dispatch_flags)
2579 {
2580         struct intel_engine_cs *ring = req->ring;
2581         int ret;
2582
2583         ret = intel_ring_begin(req, 2);
2584         if (ret)
2585                 return ret;
2586
2587         intel_ring_emit(ring,
2588                         MI_BATCH_BUFFER_START |
2589                         (dispatch_flags & I915_DISPATCH_SECURE ?
2590                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2591                         (dispatch_flags & I915_DISPATCH_RS ?
2592                          MI_BATCH_RESOURCE_STREAMER : 0));
2593         /* bit0-7 is the length on GEN6+ */
2594         intel_ring_emit(ring, offset);
2595         intel_ring_advance(ring);
2596
2597         return 0;
2598 }
2599
2600 static int
2601 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2602                               u64 offset, u32 len,
2603                               unsigned dispatch_flags)
2604 {
2605         struct intel_engine_cs *ring = req->ring;
2606         int ret;
2607
2608         ret = intel_ring_begin(req, 2);
2609         if (ret)
2610                 return ret;
2611
2612         intel_ring_emit(ring,
2613                         MI_BATCH_BUFFER_START |
2614                         (dispatch_flags & I915_DISPATCH_SECURE ?
2615                          0 : MI_BATCH_NON_SECURE_I965));
2616         /* bit0-7 is the length on GEN6+ */
2617         intel_ring_emit(ring, offset);
2618         intel_ring_advance(ring);
2619
2620         return 0;
2621 }
2622
2623 /* Blitter support (SandyBridge+) */
2624
2625 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2626                            u32 invalidate, u32 flush)
2627 {
2628         struct intel_engine_cs *ring = req->ring;
2629         struct drm_device *dev = ring->dev;
2630         uint32_t cmd;
2631         int ret;
2632
2633         ret = intel_ring_begin(req, 4);
2634         if (ret)
2635                 return ret;
2636
2637         cmd = MI_FLUSH_DW;
2638         if (INTEL_INFO(dev)->gen >= 8)
2639                 cmd += 1;
2640
2641         /* We always require a command barrier so that subsequent
2642          * commands, such as breadcrumb interrupts, are strictly ordered
2643          * wrt the contents of the write cache being flushed to memory
2644          * (and thus being coherent from the CPU).
2645          */
2646         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2647
2648         /*
2649          * Bspec vol 1c.3 - blitter engine command streamer:
2650          * "If ENABLED, all TLBs will be invalidated once the flush
2651          * operation is complete. This bit is only valid when the
2652          * Post-Sync Operation field is a value of 1h or 3h."
2653          */
2654         if (invalidate & I915_GEM_DOMAIN_RENDER)
2655                 cmd |= MI_INVALIDATE_TLB;
2656         intel_ring_emit(ring, cmd);
2657         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2658         if (INTEL_INFO(dev)->gen >= 8) {
2659                 intel_ring_emit(ring, 0); /* upper addr */
2660                 intel_ring_emit(ring, 0); /* value */
2661         } else  {
2662                 intel_ring_emit(ring, 0);
2663                 intel_ring_emit(ring, MI_NOOP);
2664         }
2665         intel_ring_advance(ring);
2666
2667         return 0;
2668 }
2669
2670 int intel_init_render_ring_buffer(struct drm_device *dev)
2671 {
2672         struct drm_i915_private *dev_priv = dev->dev_private;
2673         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2674         struct drm_i915_gem_object *obj;
2675         int ret;
2676
2677         ring->name = "render ring";
2678         ring->id = RCS;
2679         ring->mmio_base = RENDER_RING_BASE;
2680
2681         if (INTEL_INFO(dev)->gen >= 8) {
2682                 if (i915_semaphore_is_enabled(dev)) {
2683                         obj = i915_gem_alloc_object(dev, 4096);
2684                         if (obj == NULL) {
2685                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2686                                 i915.semaphores = 0;
2687                         } else {
2688                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2689                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2690                                 if (ret != 0) {
2691                                         drm_gem_object_unreference(&obj->base);
2692                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2693                                         i915.semaphores = 0;
2694                                 } else
2695                                         dev_priv->semaphore_obj = obj;
2696                         }
2697                 }
2698
2699                 ring->init_context = intel_rcs_ctx_init;
2700                 ring->add_request = gen6_add_request;
2701                 ring->flush = gen8_render_ring_flush;
2702                 ring->irq_get = gen8_ring_get_irq;
2703                 ring->irq_put = gen8_ring_put_irq;
2704                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2705                 ring->get_seqno = gen6_ring_get_seqno;
2706                 ring->set_seqno = ring_set_seqno;
2707                 if (i915_semaphore_is_enabled(dev)) {
2708                         WARN_ON(!dev_priv->semaphore_obj);
2709                         ring->semaphore.sync_to = gen8_ring_sync;
2710                         ring->semaphore.signal = gen8_rcs_signal;
2711                         GEN8_RING_SEMAPHORE_INIT;
2712                 }
2713         } else if (INTEL_INFO(dev)->gen >= 6) {
2714                 ring->init_context = intel_rcs_ctx_init;
2715                 ring->add_request = gen6_add_request;
2716                 ring->flush = gen7_render_ring_flush;
2717                 if (INTEL_INFO(dev)->gen == 6)
2718                         ring->flush = gen6_render_ring_flush;
2719                 ring->irq_get = gen6_ring_get_irq;
2720                 ring->irq_put = gen6_ring_put_irq;
2721                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2722                 ring->get_seqno = gen6_ring_get_seqno;
2723                 ring->set_seqno = ring_set_seqno;
2724                 if (i915_semaphore_is_enabled(dev)) {
2725                         ring->semaphore.sync_to = gen6_ring_sync;
2726                         ring->semaphore.signal = gen6_signal;
2727                         /*
2728                          * The current semaphore is only applied on pre-gen8
2729                          * platform.  And there is no VCS2 ring on the pre-gen8
2730                          * platform. So the semaphore between RCS and VCS2 is
2731                          * initialized as INVALID.  Gen8 will initialize the
2732                          * sema between VCS2 and RCS later.
2733                          */
2734                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2735                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2736                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2737                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2738                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2739                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2740                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2741                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2742                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2743                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2744                 }
2745         } else if (IS_GEN5(dev)) {
2746                 ring->add_request = pc_render_add_request;
2747                 ring->flush = gen4_render_ring_flush;
2748                 ring->get_seqno = pc_render_get_seqno;
2749                 ring->set_seqno = pc_render_set_seqno;
2750                 ring->irq_get = gen5_ring_get_irq;
2751                 ring->irq_put = gen5_ring_put_irq;
2752                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2753                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2754         } else {
2755                 ring->add_request = i9xx_add_request;
2756                 if (INTEL_INFO(dev)->gen < 4)
2757                         ring->flush = gen2_render_ring_flush;
2758                 else
2759                         ring->flush = gen4_render_ring_flush;
2760                 ring->get_seqno = ring_get_seqno;
2761                 ring->set_seqno = ring_set_seqno;
2762                 if (IS_GEN2(dev)) {
2763                         ring->irq_get = i8xx_ring_get_irq;
2764                         ring->irq_put = i8xx_ring_put_irq;
2765                 } else {
2766                         ring->irq_get = i9xx_ring_get_irq;
2767                         ring->irq_put = i9xx_ring_put_irq;
2768                 }
2769                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2770         }
2771         ring->write_tail = ring_write_tail;
2772
2773         if (IS_HASWELL(dev))
2774                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2775         else if (IS_GEN8(dev))
2776                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2777         else if (INTEL_INFO(dev)->gen >= 6)
2778                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2779         else if (INTEL_INFO(dev)->gen >= 4)
2780                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2781         else if (IS_I830(dev) || IS_845G(dev))
2782                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2783         else
2784                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2785         ring->init_hw = init_render_ring;
2786         ring->cleanup = render_ring_cleanup;
2787
2788         /* Workaround batchbuffer to combat CS tlb bug. */
2789         if (HAS_BROKEN_CS_TLB(dev)) {
2790                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2791                 if (obj == NULL) {
2792                         DRM_ERROR("Failed to allocate batch bo\n");
2793                         return -ENOMEM;
2794                 }
2795
2796                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2797                 if (ret != 0) {
2798                         drm_gem_object_unreference(&obj->base);
2799                         DRM_ERROR("Failed to ping batch bo\n");
2800                         return ret;
2801                 }
2802
2803                 ring->scratch.obj = obj;
2804                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2805         }
2806
2807         ret = intel_init_ring_buffer(dev, ring);
2808         if (ret)
2809                 return ret;
2810
2811         if (INTEL_INFO(dev)->gen >= 5) {
2812                 ret = intel_init_pipe_control(ring);
2813                 if (ret)
2814                         return ret;
2815         }
2816
2817         return 0;
2818 }
2819
2820 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2821 {
2822         struct drm_i915_private *dev_priv = dev->dev_private;
2823         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2824
2825         ring->name = "bsd ring";
2826         ring->id = VCS;
2827
2828         ring->write_tail = ring_write_tail;
2829         if (INTEL_INFO(dev)->gen >= 6) {
2830                 ring->mmio_base = GEN6_BSD_RING_BASE;
2831                 /* gen6 bsd needs a special wa for tail updates */
2832                 if (IS_GEN6(dev))
2833                         ring->write_tail = gen6_bsd_ring_write_tail;
2834                 ring->flush = gen6_bsd_ring_flush;
2835                 ring->add_request = gen6_add_request;
2836                 ring->get_seqno = gen6_ring_get_seqno;
2837                 ring->set_seqno = ring_set_seqno;
2838                 if (INTEL_INFO(dev)->gen >= 8) {
2839                         ring->irq_enable_mask =
2840                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2841                         ring->irq_get = gen8_ring_get_irq;
2842                         ring->irq_put = gen8_ring_put_irq;
2843                         ring->dispatch_execbuffer =
2844                                 gen8_ring_dispatch_execbuffer;
2845                         if (i915_semaphore_is_enabled(dev)) {
2846                                 ring->semaphore.sync_to = gen8_ring_sync;
2847                                 ring->semaphore.signal = gen8_xcs_signal;
2848                                 GEN8_RING_SEMAPHORE_INIT;
2849                         }
2850                 } else {
2851                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2852                         ring->irq_get = gen6_ring_get_irq;
2853                         ring->irq_put = gen6_ring_put_irq;
2854                         ring->dispatch_execbuffer =
2855                                 gen6_ring_dispatch_execbuffer;
2856                         if (i915_semaphore_is_enabled(dev)) {
2857                                 ring->semaphore.sync_to = gen6_ring_sync;
2858                                 ring->semaphore.signal = gen6_signal;
2859                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2860                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2861                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2862                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2863                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2864                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2865                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2866                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2867                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2868                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2869                         }
2870                 }
2871         } else {
2872                 ring->mmio_base = BSD_RING_BASE;
2873                 ring->flush = bsd_ring_flush;
2874                 ring->add_request = i9xx_add_request;
2875                 ring->get_seqno = ring_get_seqno;
2876                 ring->set_seqno = ring_set_seqno;
2877                 if (IS_GEN5(dev)) {
2878                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2879                         ring->irq_get = gen5_ring_get_irq;
2880                         ring->irq_put = gen5_ring_put_irq;
2881                 } else {
2882                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2883                         ring->irq_get = i9xx_ring_get_irq;
2884                         ring->irq_put = i9xx_ring_put_irq;
2885                 }
2886                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2887         }
2888         ring->init_hw = init_ring_common;
2889
2890         return intel_init_ring_buffer(dev, ring);
2891 }
2892
2893 /**
2894  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2895  */
2896 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2897 {
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2900
2901         ring->name = "bsd2 ring";
2902         ring->id = VCS2;
2903
2904         ring->write_tail = ring_write_tail;
2905         ring->mmio_base = GEN8_BSD2_RING_BASE;
2906         ring->flush = gen6_bsd_ring_flush;
2907         ring->add_request = gen6_add_request;
2908         ring->get_seqno = gen6_ring_get_seqno;
2909         ring->set_seqno = ring_set_seqno;
2910         ring->irq_enable_mask =
2911                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2912         ring->irq_get = gen8_ring_get_irq;
2913         ring->irq_put = gen8_ring_put_irq;
2914         ring->dispatch_execbuffer =
2915                         gen8_ring_dispatch_execbuffer;
2916         if (i915_semaphore_is_enabled(dev)) {
2917                 ring->semaphore.sync_to = gen8_ring_sync;
2918                 ring->semaphore.signal = gen8_xcs_signal;
2919                 GEN8_RING_SEMAPHORE_INIT;
2920         }
2921         ring->init_hw = init_ring_common;
2922
2923         return intel_init_ring_buffer(dev, ring);
2924 }
2925
2926 int intel_init_blt_ring_buffer(struct drm_device *dev)
2927 {
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2930
2931         ring->name = "blitter ring";
2932         ring->id = BCS;
2933
2934         ring->mmio_base = BLT_RING_BASE;
2935         ring->write_tail = ring_write_tail;
2936         ring->flush = gen6_ring_flush;
2937         ring->add_request = gen6_add_request;
2938         ring->get_seqno = gen6_ring_get_seqno;
2939         ring->set_seqno = ring_set_seqno;
2940         if (INTEL_INFO(dev)->gen >= 8) {
2941                 ring->irq_enable_mask =
2942                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2943                 ring->irq_get = gen8_ring_get_irq;
2944                 ring->irq_put = gen8_ring_put_irq;
2945                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2946                 if (i915_semaphore_is_enabled(dev)) {
2947                         ring->semaphore.sync_to = gen8_ring_sync;
2948                         ring->semaphore.signal = gen8_xcs_signal;
2949                         GEN8_RING_SEMAPHORE_INIT;
2950                 }
2951         } else {
2952                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2953                 ring->irq_get = gen6_ring_get_irq;
2954                 ring->irq_put = gen6_ring_put_irq;
2955                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2956                 if (i915_semaphore_is_enabled(dev)) {
2957                         ring->semaphore.signal = gen6_signal;
2958                         ring->semaphore.sync_to = gen6_ring_sync;
2959                         /*
2960                          * The current semaphore is only applied on pre-gen8
2961                          * platform.  And there is no VCS2 ring on the pre-gen8
2962                          * platform. So the semaphore between BCS and VCS2 is
2963                          * initialized as INVALID.  Gen8 will initialize the
2964                          * sema between BCS and VCS2 later.
2965                          */
2966                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2967                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2968                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2969                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2970                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2971                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2972                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2973                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2974                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2975                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2976                 }
2977         }
2978         ring->init_hw = init_ring_common;
2979
2980         return intel_init_ring_buffer(dev, ring);
2981 }
2982
2983 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2984 {
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2987
2988         ring->name = "video enhancement ring";
2989         ring->id = VECS;
2990
2991         ring->mmio_base = VEBOX_RING_BASE;
2992         ring->write_tail = ring_write_tail;
2993         ring->flush = gen6_ring_flush;
2994         ring->add_request = gen6_add_request;
2995         ring->get_seqno = gen6_ring_get_seqno;
2996         ring->set_seqno = ring_set_seqno;
2997
2998         if (INTEL_INFO(dev)->gen >= 8) {
2999                 ring->irq_enable_mask =
3000                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3001                 ring->irq_get = gen8_ring_get_irq;
3002                 ring->irq_put = gen8_ring_put_irq;
3003                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3004                 if (i915_semaphore_is_enabled(dev)) {
3005                         ring->semaphore.sync_to = gen8_ring_sync;
3006                         ring->semaphore.signal = gen8_xcs_signal;
3007                         GEN8_RING_SEMAPHORE_INIT;
3008                 }
3009         } else {
3010                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3011                 ring->irq_get = hsw_vebox_get_irq;
3012                 ring->irq_put = hsw_vebox_put_irq;
3013                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3014                 if (i915_semaphore_is_enabled(dev)) {
3015                         ring->semaphore.sync_to = gen6_ring_sync;
3016                         ring->semaphore.signal = gen6_signal;
3017                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3018                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3019                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3020                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3021                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3022                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3023                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3024                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3025                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3026                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3027                 }
3028         }
3029         ring->init_hw = init_ring_common;
3030
3031         return intel_init_ring_buffer(dev, ring);
3032 }
3033
3034 int
3035 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3036 {
3037         struct intel_engine_cs *ring = req->ring;
3038         int ret;
3039
3040         if (!ring->gpu_caches_dirty)
3041                 return 0;
3042
3043         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
3044         if (ret)
3045                 return ret;
3046
3047         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3048
3049         ring->gpu_caches_dirty = false;
3050         return 0;
3051 }
3052
3053 int
3054 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3055 {
3056         struct intel_engine_cs *ring = req->ring;
3057         uint32_t flush_domains;
3058         int ret;
3059
3060         flush_domains = 0;
3061         if (ring->gpu_caches_dirty)
3062                 flush_domains = I915_GEM_GPU_DOMAINS;
3063
3064         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3065         if (ret)
3066                 return ret;
3067
3068         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3069
3070         ring->gpu_caches_dirty = false;
3071         return 0;
3072 }
3073
3074 void
3075 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3076 {
3077         int ret;
3078
3079         if (!intel_ring_initialized(ring))
3080                 return;
3081
3082         ret = intel_ring_idle(ring);
3083         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3084                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3085                           ring->name, ret);
3086
3087         stop_ring(ring);
3088 }