2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Panel Self Refresh (PSR/SRD)
27 * Since Haswell Display controller supports Panel Self-Refresh on display
28 * panels witch have a remote frame buffer (RFB) implemented according to PSR
29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
30 * when system is idle but display is on as it eliminates display refresh
31 * request to DDR memory completely as long as the frame buffer for that
32 * display is unchanged.
34 * Panel Self Refresh must be supported by both Hardware (source) and
37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
38 * to power down the link and memory controller. For DSI panels the same idea
39 * is called "manual mode".
41 * The implementation uses the hardware-based PSR support which automatically
42 * enters/exits self-refresh mode. The hardware takes care of sending the
43 * required DP aux message and could even retrain the link (that part isn't
44 * enabled yet though). The hardware also keeps track of any frontbuffer
45 * changes to know when to exit self-refresh mode again. Unfortunately that
46 * part doesn't work too well, hence why the i915 PSR support uses the
47 * software frontbuffer tracking to make sure it doesn't miss a screen
48 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
49 * get called by the frontbuffer tracking code. Note that because of locking
50 * issues the self-refresh re-enable code is done from a work queue, which
51 * must be correctly synchronized/cancelled when shutting down the pipe."
56 #include "intel_drv.h"
59 static bool is_edp_psr(struct intel_dp *intel_dp)
61 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
66 struct drm_i915_private *dev_priv = to_i915(dev);
69 val = I915_READ(VLV_PSRSTAT(pipe)) &
70 VLV_EDP_PSR_CURR_STATE_MASK;
71 return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
72 (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
76 const struct edp_vsc_psr *vsc_psr)
78 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
79 struct drm_device *dev = dig_port->base.base.dev;
80 struct drm_i915_private *dev_priv = to_i915(dev);
81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
82 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
83 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
84 uint32_t *data = (uint32_t *) vsc_psr;
87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
88 the video DIP being updated before program video DIP data buffer
89 registers for DIP being updated. */
90 I915_WRITE(ctl_reg, 0);
91 POSTING_READ(ctl_reg);
93 for (i = 0; i < sizeof(*vsc_psr); i += 4) {
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
98 for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
102 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
103 POSTING_READ(ctl_reg);
106 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
108 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
109 struct drm_device *dev = intel_dig_port->base.base.dev;
110 struct drm_i915_private *dev_priv = to_i915(dev);
111 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
112 enum pipe pipe = to_intel_crtc(crtc)->pipe;
115 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
116 val = I915_READ(VLV_VSCSDP(pipe));
117 val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
118 val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
119 I915_WRITE(VLV_VSCSDP(pipe), val);
122 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
124 struct edp_vsc_psr psr_vsc;
125 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
126 struct drm_device *dev = intel_dig_port->base.base.dev;
127 struct drm_i915_private *dev_priv = to_i915(dev);
129 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
130 memset(&psr_vsc, 0, sizeof(psr_vsc));
131 psr_vsc.sdp_header.HB0 = 0;
132 psr_vsc.sdp_header.HB1 = 0x7;
133 if (dev_priv->psr.colorimetry_support &&
134 dev_priv->psr.y_cord_support) {
135 psr_vsc.sdp_header.HB2 = 0x5;
136 psr_vsc.sdp_header.HB3 = 0x13;
137 } else if (dev_priv->psr.y_cord_support) {
138 psr_vsc.sdp_header.HB2 = 0x4;
139 psr_vsc.sdp_header.HB3 = 0xe;
141 psr_vsc.sdp_header.HB2 = 0x3;
142 psr_vsc.sdp_header.HB3 = 0xc;
145 intel_psr_write_vsc(intel_dp, &psr_vsc);
148 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
150 struct edp_vsc_psr psr_vsc;
152 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
153 memset(&psr_vsc, 0, sizeof(psr_vsc));
154 psr_vsc.sdp_header.HB0 = 0;
155 psr_vsc.sdp_header.HB1 = 0x7;
156 psr_vsc.sdp_header.HB2 = 0x2;
157 psr_vsc.sdp_header.HB3 = 0x8;
158 intel_psr_write_vsc(intel_dp, &psr_vsc);
161 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
163 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
164 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
167 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
170 if (INTEL_INFO(dev_priv)->gen >= 9)
171 return DP_AUX_CH_CTL(port);
173 return EDP_PSR_AUX_CTL;
176 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
177 enum port port, int index)
179 if (INTEL_INFO(dev_priv)->gen >= 9)
180 return DP_AUX_CH_DATA(port, index);
182 return EDP_PSR_AUX_DATA(index);
185 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
187 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
188 struct drm_device *dev = dig_port->base.base.dev;
189 struct drm_i915_private *dev_priv = to_i915(dev);
190 uint32_t aux_clock_divider;
191 i915_reg_t aux_ctl_reg;
192 static const uint8_t aux_msg[] = {
193 [0] = DP_AUX_NATIVE_WRITE << 4,
194 [1] = DP_SET_POWER >> 8,
195 [2] = DP_SET_POWER & 0xff,
197 [4] = DP_SET_POWER_D0,
199 enum port port = dig_port->port;
203 BUILD_BUG_ON(sizeof(aux_msg) > 20);
205 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
207 /* Enable AUX frame sync at sink */
208 if (dev_priv->psr.aux_frame_sync)
209 drm_dp_dpcd_writeb(&intel_dp->aux,
210 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
211 DP_AUX_FRAME_SYNC_ENABLE);
212 /* Enable ALPM at sink for psr2 */
213 if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
214 drm_dp_dpcd_writeb(&intel_dp->aux,
215 DP_RECEIVER_ALPM_CONFIG,
217 if (dev_priv->psr.link_standby)
218 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
219 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
221 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
224 aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
226 /* Setup AUX registers */
227 for (i = 0; i < sizeof(aux_msg); i += 4)
228 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
229 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
231 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
233 I915_WRITE(aux_ctl_reg, aux_ctl);
236 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
238 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
239 struct drm_device *dev = dig_port->base.base.dev;
240 struct drm_i915_private *dev_priv = to_i915(dev);
241 struct drm_crtc *crtc = dig_port->base.base.crtc;
242 enum pipe pipe = to_intel_crtc(crtc)->pipe;
244 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
245 I915_WRITE(VLV_PSRCTL(pipe),
246 VLV_EDP_PSR_MODE_SW_TIMER |
247 VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
251 static void vlv_psr_activate(struct intel_dp *intel_dp)
253 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = to_i915(dev);
256 struct drm_crtc *crtc = dig_port->base.base.crtc;
257 enum pipe pipe = to_intel_crtc(crtc)->pipe;
259 /* Let's do the transition from PSR_state 1 to PSR_state 2
260 * that is PSR transition to active - static frame transmission.
261 * Then Hardware is responsible for the transition to PSR_state 3
262 * that is PSR active - no Remote Frame Buffer (RFB) update.
264 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
265 VLV_EDP_PSR_ACTIVE_ENTRY);
268 static void intel_enable_source_psr1(struct intel_dp *intel_dp)
270 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
271 struct drm_device *dev = dig_port->base.base.dev;
272 struct drm_i915_private *dev_priv = to_i915(dev);
274 uint32_t max_sleep_time = 0x1f;
276 * Let's respect VBT in case VBT asks a higher idle_frame value.
277 * Let's use 6 as the minimum to cover all known cases including
278 * the off-by-one issue that HW has in some cases. Also there are
279 * cases where sink should be able to train
280 * with the 5 or 6 idle patterns.
282 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
283 uint32_t val = EDP_PSR_ENABLE;
285 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
286 val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
288 if (IS_HASWELL(dev_priv))
289 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
291 if (dev_priv->psr.link_standby)
292 val |= EDP_PSR_LINK_STANDBY;
294 if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
295 val |= EDP_PSR_TP1_TIME_2500us;
296 else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
297 val |= EDP_PSR_TP1_TIME_500us;
298 else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
299 val |= EDP_PSR_TP1_TIME_100us;
301 val |= EDP_PSR_TP1_TIME_0us;
303 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
304 val |= EDP_PSR_TP2_TP3_TIME_2500us;
305 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
306 val |= EDP_PSR_TP2_TP3_TIME_500us;
307 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
308 val |= EDP_PSR_TP2_TP3_TIME_100us;
310 val |= EDP_PSR_TP2_TP3_TIME_0us;
312 if (intel_dp_source_supports_hbr2(intel_dp) &&
313 drm_dp_tps3_supported(intel_dp->dpcd))
314 val |= EDP_PSR_TP1_TP3_SEL;
316 val |= EDP_PSR_TP1_TP2_SEL;
318 I915_WRITE(EDP_PSR_CTL, val);
321 static void intel_enable_source_psr2(struct intel_dp *intel_dp)
323 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = to_i915(dev);
327 * Let's respect VBT in case VBT asks a higher idle_frame value.
328 * Let's use 6 as the minimum to cover all known cases including
329 * the off-by-one issue that HW has in some cases. Also there are
330 * cases where sink should be able to train
331 * with the 5 or 6 idle patterns.
333 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
336 val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
338 /* FIXME: selective update is probably totally broken because it doesn't
339 * mesh at all with our frontbuffer tracking. And the hw alone isn't
341 val |= EDP_PSR2_ENABLE |
342 EDP_SU_TRACK_ENABLE |
343 EDP_FRAMES_BEFORE_SU_ENTRY;
345 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
346 val |= EDP_PSR2_TP2_TIME_2500;
347 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
348 val |= EDP_PSR2_TP2_TIME_500;
349 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
350 val |= EDP_PSR2_TP2_TIME_100;
352 val |= EDP_PSR2_TP2_TIME_50;
354 I915_WRITE(EDP_PSR2_CTL, val);
357 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
359 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
360 struct drm_device *dev = dig_port->base.base.dev;
361 struct drm_i915_private *dev_priv = to_i915(dev);
363 /* psr1 and psr2 are mutually exclusive.*/
364 if (dev_priv->psr.psr2_support)
365 intel_enable_source_psr2(intel_dp);
367 intel_enable_source_psr1(intel_dp);
370 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
372 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
373 struct drm_device *dev = dig_port->base.base.dev;
374 struct drm_i915_private *dev_priv = to_i915(dev);
375 struct drm_crtc *crtc = dig_port->base.base.crtc;
376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
377 const struct drm_display_mode *adjusted_mode =
378 &intel_crtc->config->base.adjusted_mode;
381 lockdep_assert_held(&dev_priv->psr.lock);
382 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
383 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
385 dev_priv->psr.source_ok = false;
388 * HSW spec explicitly says PSR is tied to port A.
389 * BDW+ platforms with DDI implementation of PSR have different
390 * PSR registers per transcoder and we only implement transcoder EDP
391 * ones. Since by Display design transcoder EDP is tied to port A
392 * we can safely escape based on the port A.
394 if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
395 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
399 if (!i915.enable_psr) {
400 DRM_DEBUG_KMS("PSR disable by flag\n");
404 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
405 !dev_priv->psr.link_standby) {
406 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
410 if (IS_HASWELL(dev_priv) &&
411 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
413 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
417 if (IS_HASWELL(dev_priv) &&
418 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
419 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
423 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
424 if (psr_setup_time < 0) {
425 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
426 intel_dp->psr_dpcd[1]);
430 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
431 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
432 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
437 /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
438 if (intel_crtc->config->pipe_src_w > 3200 ||
439 intel_crtc->config->pipe_src_h > 2000) {
440 dev_priv->psr.psr2_support = false;
445 * FIXME:enable psr2 only for y-cordinate psr2 panels
446 * After gtc implementation , remove this restriction.
448 if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
449 DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
453 dev_priv->psr.source_ok = true;
457 static void intel_psr_activate(struct intel_dp *intel_dp)
459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
460 struct drm_device *dev = intel_dig_port->base.base.dev;
461 struct drm_i915_private *dev_priv = to_i915(dev);
463 if (dev_priv->psr.psr2_support)
464 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
466 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
467 WARN_ON(dev_priv->psr.active);
468 lockdep_assert_held(&dev_priv->psr.lock);
470 /* Enable/Re-enable PSR on the host */
471 if (HAS_DDI(dev_priv))
472 /* On HSW+ after we enable PSR on source it will activate it
473 * as soon as it match configure idle_frame count. So
474 * we just actually enable it here on activation time.
476 hsw_psr_enable_source(intel_dp);
478 vlv_psr_activate(intel_dp);
480 dev_priv->psr.active = true;
484 * intel_psr_enable - Enable PSR
485 * @intel_dp: Intel DP
487 * This function can only be called after the pipe is fully trained and enabled.
489 void intel_psr_enable(struct intel_dp *intel_dp)
491 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
492 struct drm_device *dev = intel_dig_port->base.base.dev;
493 struct drm_i915_private *dev_priv = to_i915(dev);
494 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
495 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
498 if (!HAS_PSR(dev_priv)) {
499 DRM_DEBUG_KMS("PSR not supported on this platform\n");
503 if (!is_edp_psr(intel_dp)) {
504 DRM_DEBUG_KMS("PSR not supported by this panel\n");
508 mutex_lock(&dev_priv->psr.lock);
509 if (dev_priv->psr.enabled) {
510 DRM_DEBUG_KMS("PSR already in use\n");
514 if (!intel_psr_match_conditions(intel_dp))
517 dev_priv->psr.busy_frontbuffer_bits = 0;
519 if (HAS_DDI(dev_priv)) {
520 if (dev_priv->psr.psr2_support) {
521 skl_psr_setup_su_vsc(intel_dp);
522 chicken = PSR2_VSC_ENABLE_PROG_HEADER;
523 if (dev_priv->psr.y_cord_support)
524 chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
525 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
526 I915_WRITE(EDP_PSR_DEBUG_CTL,
527 EDP_PSR_DEBUG_MASK_MEMUP |
528 EDP_PSR_DEBUG_MASK_HPD |
529 EDP_PSR_DEBUG_MASK_LPSP |
530 EDP_PSR_DEBUG_MASK_MAX_SLEEP |
531 EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
533 /* set up vsc header for psr1 */
534 hsw_psr_setup_vsc(intel_dp);
536 * Per Spec: Avoid continuous PSR exit by masking MEMUP
537 * and HPD. also mask LPSP to avoid dependency on other
538 * drivers that might block runtime_pm besides
539 * preventing other hw tracking issues now we can rely
540 * on frontbuffer tracking.
542 I915_WRITE(EDP_PSR_DEBUG_CTL,
543 EDP_PSR_DEBUG_MASK_MEMUP |
544 EDP_PSR_DEBUG_MASK_HPD |
545 EDP_PSR_DEBUG_MASK_LPSP);
548 /* Enable PSR on the panel */
549 hsw_psr_enable_sink(intel_dp);
551 if (INTEL_GEN(dev_priv) >= 9)
552 intel_psr_activate(intel_dp);
554 vlv_psr_setup_vsc(intel_dp);
556 /* Enable PSR on the panel */
557 vlv_psr_enable_sink(intel_dp);
559 /* On HSW+ enable_source also means go to PSR entry/active
560 * state as soon as idle_frame achieved and here would be
561 * to soon. However on VLV enable_source just enable PSR
562 * but let it on inactive state. So we might do this prior
563 * to active transition, i.e. here.
565 vlv_psr_enable_source(intel_dp);
569 * FIXME: Activation should happen immediately since this function
570 * is just called after pipe is fully trained and enabled.
571 * However on every platform we face issues when first activation
572 * follows a modeset so quickly.
573 * - On VLV/CHV we get bank screen on first activation
574 * - On HSW/BDW we get a recoverable frozen screen until next
575 * exit-activate sequence.
577 if (INTEL_GEN(dev_priv) < 9)
578 schedule_delayed_work(&dev_priv->psr.work,
579 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
581 dev_priv->psr.enabled = intel_dp;
583 mutex_unlock(&dev_priv->psr.lock);
586 static void vlv_psr_disable(struct intel_dp *intel_dp)
588 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
589 struct drm_device *dev = intel_dig_port->base.base.dev;
590 struct drm_i915_private *dev_priv = to_i915(dev);
591 struct intel_crtc *intel_crtc =
592 to_intel_crtc(intel_dig_port->base.base.crtc);
595 if (dev_priv->psr.active) {
596 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
597 if (intel_wait_for_register(dev_priv,
598 VLV_PSRSTAT(intel_crtc->pipe),
599 VLV_EDP_PSR_IN_TRANS,
602 WARN(1, "PSR transition took longer than expected\n");
604 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
605 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
606 val &= ~VLV_EDP_PSR_ENABLE;
607 val &= ~VLV_EDP_PSR_MODE_MASK;
608 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
610 dev_priv->psr.active = false;
612 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
616 static void hsw_psr_disable(struct intel_dp *intel_dp)
618 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
619 struct drm_device *dev = intel_dig_port->base.base.dev;
620 struct drm_i915_private *dev_priv = to_i915(dev);
622 if (dev_priv->psr.active) {
626 if (dev_priv->psr.aux_frame_sync)
627 drm_dp_dpcd_writeb(&intel_dp->aux,
628 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
631 if (dev_priv->psr.psr2_support) {
632 psr_ctl = EDP_PSR2_CTL;
633 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
637 ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
640 psr_ctl = EDP_PSR_STATUS_CTL;
641 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
644 I915_READ(psr_ctl) & ~EDP_PSR_ENABLE);
647 /* Wait till PSR is idle */
648 if (intel_wait_for_register(dev_priv,
649 psr_ctl, psr_status_mask, 0,
651 DRM_ERROR("Timed out waiting for PSR Idle State\n");
653 dev_priv->psr.active = false;
655 if (dev_priv->psr.psr2_support)
656 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
658 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
663 * intel_psr_disable - Disable PSR
664 * @intel_dp: Intel DP
666 * This function needs to be called before disabling pipe.
668 void intel_psr_disable(struct intel_dp *intel_dp)
670 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
671 struct drm_device *dev = intel_dig_port->base.base.dev;
672 struct drm_i915_private *dev_priv = to_i915(dev);
674 mutex_lock(&dev_priv->psr.lock);
675 if (!dev_priv->psr.enabled) {
676 mutex_unlock(&dev_priv->psr.lock);
680 /* Disable PSR on Source */
681 if (HAS_DDI(dev_priv))
682 hsw_psr_disable(intel_dp);
684 vlv_psr_disable(intel_dp);
686 /* Disable PSR on Sink */
687 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
689 dev_priv->psr.enabled = NULL;
690 mutex_unlock(&dev_priv->psr.lock);
692 cancel_delayed_work_sync(&dev_priv->psr.work);
695 static void intel_psr_work(struct work_struct *work)
697 struct drm_i915_private *dev_priv =
698 container_of(work, typeof(*dev_priv), psr.work.work);
699 struct intel_dp *intel_dp = dev_priv->psr.enabled;
700 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
701 enum pipe pipe = to_intel_crtc(crtc)->pipe;
703 /* We have to make sure PSR is ready for re-enable
704 * otherwise it keeps disabled until next full enable/disable cycle.
705 * PSR might take some time to get fully disabled
706 * and be ready for re-enable.
708 if (HAS_DDI(dev_priv)) {
709 if (dev_priv->psr.psr2_support) {
710 if (intel_wait_for_register(dev_priv,
712 EDP_PSR2_STATUS_STATE_MASK,
715 DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
719 if (intel_wait_for_register(dev_priv,
721 EDP_PSR_STATUS_STATE_MASK,
724 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
729 if (intel_wait_for_register(dev_priv,
731 VLV_EDP_PSR_IN_TRANS,
734 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
738 mutex_lock(&dev_priv->psr.lock);
739 intel_dp = dev_priv->psr.enabled;
745 * The delayed work can race with an invalidate hence we need to
746 * recheck. Since psr_flush first clears this and then reschedules we
747 * won't ever miss a flush when bailing out here.
749 if (dev_priv->psr.busy_frontbuffer_bits)
752 intel_psr_activate(intel_dp);
754 mutex_unlock(&dev_priv->psr.lock);
757 static void intel_psr_exit(struct drm_i915_private *dev_priv)
759 struct intel_dp *intel_dp = dev_priv->psr.enabled;
760 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
761 enum pipe pipe = to_intel_crtc(crtc)->pipe;
764 if (!dev_priv->psr.active)
767 if (HAS_DDI(dev_priv)) {
768 if (dev_priv->psr.aux_frame_sync)
769 drm_dp_dpcd_writeb(&intel_dp->aux,
770 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
772 if (dev_priv->psr.psr2_support) {
773 val = I915_READ(EDP_PSR2_CTL);
774 WARN_ON(!(val & EDP_PSR2_ENABLE));
775 I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
777 val = I915_READ(EDP_PSR_CTL);
778 WARN_ON(!(val & EDP_PSR_ENABLE));
779 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
782 val = I915_READ(VLV_PSRCTL(pipe));
784 /* Here we do the transition from PSR_state 3 to PSR_state 5
785 * directly once PSR State 4 that is active with single frame
786 * update can be skipped. PSR_state 5 that is PSR exit then
787 * Hardware is responsible to transition back to PSR_state 1
788 * that is PSR inactive. Same state after
789 * vlv_edp_psr_enable_source.
791 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
792 I915_WRITE(VLV_PSRCTL(pipe), val);
794 /* Send AUX wake up - Spec says after transitioning to PSR
795 * active we have to send AUX wake up by writing 01h in DPCD
796 * 600h of sink device.
797 * XXX: This might slow down the transition, but without this
798 * HW doesn't complete the transition to PSR_state 1 and we
799 * never get the screen updated.
801 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
805 dev_priv->psr.active = false;
809 * intel_psr_single_frame_update - Single Frame Update
810 * @dev_priv: i915 device
811 * @frontbuffer_bits: frontbuffer plane tracking bits
813 * Some platforms support a single frame update feature that is used to
814 * send and update only one frame on Remote Frame Buffer.
815 * So far it is only implemented for Valleyview and Cherryview because
816 * hardware requires this to be done before a page flip.
818 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
819 unsigned frontbuffer_bits)
821 struct drm_crtc *crtc;
826 * Single frame update is already supported on BDW+ but it requires
827 * many W/A and it isn't really needed.
829 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
832 mutex_lock(&dev_priv->psr.lock);
833 if (!dev_priv->psr.enabled) {
834 mutex_unlock(&dev_priv->psr.lock);
838 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
839 pipe = to_intel_crtc(crtc)->pipe;
841 if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
842 val = I915_READ(VLV_PSRCTL(pipe));
845 * We need to set this bit before writing registers for a flip.
846 * This bit will be self-clear when it gets to the PSR active state.
848 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
850 mutex_unlock(&dev_priv->psr.lock);
854 * intel_psr_invalidate - Invalidade PSR
855 * @dev_priv: i915 device
856 * @frontbuffer_bits: frontbuffer plane tracking bits
858 * Since the hardware frontbuffer tracking has gaps we need to integrate
859 * with the software frontbuffer tracking. This function gets called every
860 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
861 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
863 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
865 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
866 unsigned frontbuffer_bits)
868 struct drm_crtc *crtc;
871 mutex_lock(&dev_priv->psr.lock);
872 if (!dev_priv->psr.enabled) {
873 mutex_unlock(&dev_priv->psr.lock);
877 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
878 pipe = to_intel_crtc(crtc)->pipe;
880 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
881 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
883 if (frontbuffer_bits)
884 intel_psr_exit(dev_priv);
886 mutex_unlock(&dev_priv->psr.lock);
890 * intel_psr_flush - Flush PSR
891 * @dev_priv: i915 device
892 * @frontbuffer_bits: frontbuffer plane tracking bits
893 * @origin: which operation caused the flush
895 * Since the hardware frontbuffer tracking has gaps we need to integrate
896 * with the software frontbuffer tracking. This function gets called every
897 * time frontbuffer rendering has completed and flushed out to memory. PSR
898 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
900 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
902 void intel_psr_flush(struct drm_i915_private *dev_priv,
903 unsigned frontbuffer_bits, enum fb_op_origin origin)
905 struct drm_crtc *crtc;
908 mutex_lock(&dev_priv->psr.lock);
909 if (!dev_priv->psr.enabled) {
910 mutex_unlock(&dev_priv->psr.lock);
914 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
915 pipe = to_intel_crtc(crtc)->pipe;
917 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
918 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
920 /* By definition flush = invalidate + flush */
921 if (frontbuffer_bits)
922 intel_psr_exit(dev_priv);
924 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
925 if (!work_busy(&dev_priv->psr.work.work))
926 schedule_delayed_work(&dev_priv->psr.work,
927 msecs_to_jiffies(100));
928 mutex_unlock(&dev_priv->psr.lock);
932 * intel_psr_init - Init basic PSR work and mutex.
933 * @dev_priv: i915 device private
935 * This function is called only once at driver load to initialize basic
938 void intel_psr_init(struct drm_i915_private *dev_priv)
940 dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
941 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
943 /* Per platform default: all disabled. */
944 if (i915.enable_psr == -1)
947 /* Set link_standby x link_off defaults */
948 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
949 /* HSW and BDW require workarounds that we don't implement. */
950 dev_priv->psr.link_standby = false;
951 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
952 /* On VLV and CHV only standby mode is supported. */
953 dev_priv->psr.link_standby = true;
955 /* For new platforms let's respect VBT back again */
956 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
958 /* Override link_standby x link_off defaults */
959 if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
960 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
961 dev_priv->psr.link_standby = true;
963 if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
964 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
965 dev_priv->psr.link_standby = false;
968 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
969 mutex_init(&dev_priv->psr.lock);