drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static bool is_edp_psr(struct intel_dp *intel_dp)
  60 {
  61         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
  62 }
  63
  64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
  65 {
  66         struct drm_i915_private *dev_priv = to_i915(dev);
  67         uint32_t val;
  68
  69         val = I915_READ(VLV_PSRSTAT(pipe)) &
  70               VLV_EDP_PSR_CURR_STATE_MASK;
  71         return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  72                (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
  73 }
  74
  75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
  76                                 const struct edp_vsc_psr *vsc_psr)
  77 {
  78         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  79         struct drm_device *dev = dig_port->base.base.dev;
  80         struct drm_i915_private *dev_priv = to_i915(dev);
  81         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  82         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  83         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
  84         uint32_t *data = (uint32_t *) vsc_psr;
  85         unsigned int i;
  86
  87         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  88            the video DIP being updated before program video DIP data buffer
  89            registers for DIP being updated. */
  90         I915_WRITE(ctl_reg, 0);
  91         POSTING_READ(ctl_reg);
  92
  93         for (i = 0; i < sizeof(*vsc_psr); i += 4) {
  94                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
  95                                                    i >> 2), *data);
  96                 data++;
  97         }
  98         for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
  99                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
 100                                                    i >> 2), 0);
 101
 102         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
 103         POSTING_READ(ctl_reg);
 104 }
 105
 106 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 107 {
 108         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 109         struct drm_device *dev = intel_dig_port->base.base.dev;
 110         struct drm_i915_private *dev_priv = to_i915(dev);
 111         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 112         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 113         uint32_t val;
 114
 115         /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
 116         val  = I915_READ(VLV_VSCSDP(pipe));
 117         val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
 118         val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
 119         I915_WRITE(VLV_VSCSDP(pipe), val);
 120 }
 121
 122 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 123 {
 124         struct edp_vsc_psr psr_vsc;
 125
 126         /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 127         memset(&psr_vsc, 0, sizeof(psr_vsc));
 128         psr_vsc.sdp_header.HB0 = 0;
 129         psr_vsc.sdp_header.HB1 = 0x7;
 130         psr_vsc.sdp_header.HB2 = 0x3;
 131         psr_vsc.sdp_header.HB3 = 0xb;
 132         intel_psr_write_vsc(intel_dp, &psr_vsc);
 133 }
 134
 135 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 136 {
 137         struct edp_vsc_psr psr_vsc;
 138
 139         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 140         memset(&psr_vsc, 0, sizeof(psr_vsc));
 141         psr_vsc.sdp_header.HB0 = 0;
 142         psr_vsc.sdp_header.HB1 = 0x7;
 143         psr_vsc.sdp_header.HB2 = 0x2;
 144         psr_vsc.sdp_header.HB3 = 0x8;
 145         intel_psr_write_vsc(intel_dp, &psr_vsc);
 146 }
 147
 148 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 149 {
 150         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 151                            DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 152 }
 153
 154 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 155                                        enum port port)
 156 {
 157         if (INTEL_INFO(dev_priv)->gen >= 9)
 158                 return DP_AUX_CH_CTL(port);
 159         else
 160                 return EDP_PSR_AUX_CTL;
 161 }
 162
 163 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 164                                         enum port port, int index)
 165 {
 166         if (INTEL_INFO(dev_priv)->gen >= 9)
 167                 return DP_AUX_CH_DATA(port, index);
 168         else
 169                 return EDP_PSR_AUX_DATA(index);
 170 }
 171
 172 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_device *dev = dig_port->base.base.dev;
 176         struct drm_i915_private *dev_priv = to_i915(dev);
 177         uint32_t aux_clock_divider;
 178         i915_reg_t aux_ctl_reg;
 179         static const uint8_t aux_msg[] = {
 180                 [0] = DP_AUX_NATIVE_WRITE << 4,
 181                 [1] = DP_SET_POWER >> 8,
 182                 [2] = DP_SET_POWER & 0xff,
 183                 [3] = 1 - 1,
 184                 [4] = DP_SET_POWER_D0,
 185         };
 186         enum port port = dig_port->port;
 187         u32 aux_ctl;
 188         int i;
 189
 190         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 191
 192         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 193
 194         /* Enable AUX frame sync at sink */
 195         if (dev_priv->psr.aux_frame_sync)
 196                 drm_dp_dpcd_writeb(&intel_dp->aux,
 197                                 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 198                                 DP_AUX_FRAME_SYNC_ENABLE);
 199
 200         if (dev_priv->psr.link_standby)
 201                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 202                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 203         else
 204                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 205                                    DP_PSR_ENABLE);
 206
 207         aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 208
 209         /* Setup AUX registers */
 210         for (i = 0; i < sizeof(aux_msg); i += 4)
 211                 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
 212                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 213
 214         aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
 215                                              aux_clock_divider);
 216         I915_WRITE(aux_ctl_reg, aux_ctl);
 217 }
 218
 219 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         struct drm_device *dev = dig_port->base.base.dev;
 223         struct drm_i915_private *dev_priv = to_i915(dev);
 224         struct drm_crtc *crtc = dig_port->base.base.crtc;
 225         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 226
 227         /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
 228         I915_WRITE(VLV_PSRCTL(pipe),
 229                    VLV_EDP_PSR_MODE_SW_TIMER |
 230                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
 231                    VLV_EDP_PSR_ENABLE);
 232 }
 233
 234 static void vlv_psr_activate(struct intel_dp *intel_dp)
 235 {
 236         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 237         struct drm_device *dev = dig_port->base.base.dev;
 238         struct drm_i915_private *dev_priv = to_i915(dev);
 239         struct drm_crtc *crtc = dig_port->base.base.crtc;
 240         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 241
 242         /* Let's do the transition from PSR_state 1 to PSR_state 2
 243          * that is PSR transition to active - static frame transmission.
 244          * Then Hardware is responsible for the transition to PSR_state 3
 245          * that is PSR active - no Remote Frame Buffer (RFB) update.
 246          */
 247         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
 248                    VLV_EDP_PSR_ACTIVE_ENTRY);
 249 }
 250
 251 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 252 {
 253         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 254         struct drm_device *dev = dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = to_i915(dev);
 256
 257         uint32_t max_sleep_time = 0x1f;
 258         /* Lately it was identified that depending on panel idle frame count
 259          * calculated at HW can be off by 1. So let's use what came
 260          * from VBT + 1.
 261          * There are also other cases where panel demands at least 4
 262          * but VBT is not being set. To cover these 2 cases lets use
 263          * at least 5 when VBT isn't set to be on the safest side.
 264          */
 265         uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1;
 266         uint32_t val = EDP_PSR_ENABLE;
 267
 268         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 269         val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 270
 271         if (IS_HASWELL(dev))
 272                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 273
 274         if (dev_priv->psr.link_standby)
 275                 val |= EDP_PSR_LINK_STANDBY;
 276
 277         if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
 278                 val |= EDP_PSR_TP1_TIME_2500us;
 279         else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
 280                 val |= EDP_PSR_TP1_TIME_500us;
 281         else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
 282                 val |= EDP_PSR_TP1_TIME_100us;
 283         else
 284                 val |= EDP_PSR_TP1_TIME_0us;
 285
 286         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 287                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 288         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 289                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 290         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 291                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 292         else
 293                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 294
 295         if (intel_dp_source_supports_hbr2(intel_dp) &&
 296             drm_dp_tps3_supported(intel_dp->dpcd))
 297                 val |= EDP_PSR_TP1_TP3_SEL;
 298         else
 299                 val |= EDP_PSR_TP1_TP2_SEL;
 300
 301         I915_WRITE(EDP_PSR_CTL, val);
 302
 303         if (!dev_priv->psr.psr2_support)
 304                 return;
 305
 306         /* FIXME: selective update is probably totally broken because it doesn't
 307          * mesh at all with our frontbuffer tracking. And the hw alone isn't
 308          * good enough. */
 309         val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 310
 311         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 312                 val |= EDP_PSR2_TP2_TIME_2500;
 313         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 314                 val |= EDP_PSR2_TP2_TIME_500;
 315         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 316                 val |= EDP_PSR2_TP2_TIME_100;
 317         else
 318                 val |= EDP_PSR2_TP2_TIME_50;
 319
 320         I915_WRITE(EDP_PSR2_CTL, val);
 321 }
 322
 323 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 324 {
 325         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 326         struct drm_device *dev = dig_port->base.base.dev;
 327         struct drm_i915_private *dev_priv = to_i915(dev);
 328         struct drm_crtc *crtc = dig_port->base.base.crtc;
 329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 330         const struct drm_display_mode *adjusted_mode =
 331                 &intel_crtc->config->base.adjusted_mode;
 332         int psr_setup_time;
 333
 334         lockdep_assert_held(&dev_priv->psr.lock);
 335         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 336         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 337
 338         dev_priv->psr.source_ok = false;
 339
 340         /*
 341          * HSW spec explicitly says PSR is tied to port A.
 342          * BDW+ platforms with DDI implementation of PSR have different
 343          * PSR registers per transcoder and we only implement transcoder EDP
 344          * ones. Since by Display design transcoder EDP is tied to port A
 345          * we can safely escape based on the port A.
 346          */
 347         if (HAS_DDI(dev) && dig_port->port != PORT_A) {
 348                 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 349                 return false;
 350         }
 351
 352         if (!i915.enable_psr) {
 353                 DRM_DEBUG_KMS("PSR disable by flag\n");
 354                 return false;
 355         }
 356
 357         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 358             !dev_priv->psr.link_standby) {
 359                 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
 360                 return false;
 361         }
 362
 363         if (IS_HASWELL(dev) &&
 364             I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
 365                       S3D_ENABLE) {
 366                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 367                 return false;
 368         }
 369
 370         if (IS_HASWELL(dev) &&
 371             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 372                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 373                 return false;
 374         }
 375
 376         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 377         if (psr_setup_time < 0) {
 378                 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 379                               intel_dp->psr_dpcd[1]);
 380                 return false;
 381         }
 382
 383         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 384             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 385                 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
 386                               psr_setup_time);
 387                 return false;
 388         }
 389
 390         dev_priv->psr.source_ok = true;
 391         return true;
 392 }
 393
 394 static void intel_psr_activate(struct intel_dp *intel_dp)
 395 {
 396         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 397         struct drm_device *dev = intel_dig_port->base.base.dev;
 398         struct drm_i915_private *dev_priv = to_i915(dev);
 399
 400         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 401         WARN_ON(dev_priv->psr.active);
 402         lockdep_assert_held(&dev_priv->psr.lock);
 403
 404         /* Enable/Re-enable PSR on the host */
 405         if (HAS_DDI(dev))
 406                 /* On HSW+ after we enable PSR on source it will activate it
 407                  * as soon as it match configure idle_frame count. So
 408                  * we just actually enable it here on activation time.
 409                  */
 410                 hsw_psr_enable_source(intel_dp);
 411         else
 412                 vlv_psr_activate(intel_dp);
 413
 414         dev_priv->psr.active = true;
 415 }
 416
 417 /**
 418  * intel_psr_enable - Enable PSR
 419  * @intel_dp: Intel DP
 420  *
 421  * This function can only be called after the pipe is fully trained and enabled.
 422  */
 423 void intel_psr_enable(struct intel_dp *intel_dp)
 424 {
 425         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 426         struct drm_device *dev = intel_dig_port->base.base.dev;
 427         struct drm_i915_private *dev_priv = to_i915(dev);
 428         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 429
 430         if (!HAS_PSR(dev)) {
 431                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
 432                 return;
 433         }
 434
 435         if (!is_edp_psr(intel_dp)) {
 436                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
 437                 return;
 438         }
 439
 440         mutex_lock(&dev_priv->psr.lock);
 441         if (dev_priv->psr.enabled) {
 442                 DRM_DEBUG_KMS("PSR already in use\n");
 443                 goto unlock;
 444         }
 445
 446         if (!intel_psr_match_conditions(intel_dp))
 447                 goto unlock;
 448
 449         dev_priv->psr.busy_frontbuffer_bits = 0;
 450
 451         if (HAS_DDI(dev)) {
 452                 hsw_psr_setup_vsc(intel_dp);
 453
 454                 if (dev_priv->psr.psr2_support) {
 455                         /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
 456                         if (crtc->config->pipe_src_w > 3200 ||
 457                                 crtc->config->pipe_src_h > 2000)
 458                                 dev_priv->psr.psr2_support = false;
 459                         else
 460                                 skl_psr_setup_su_vsc(intel_dp);
 461                 }
 462
 463                 /*
 464                  * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
 465                  * Also mask LPSP to avoid dependency on other drivers that
 466                  * might block runtime_pm besides preventing other hw tracking
 467                  * issues now we can rely on frontbuffer tracking.
 468                  */
 469                 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 470                            EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 471
 472                 /* Enable PSR on the panel */
 473                 hsw_psr_enable_sink(intel_dp);
 474
 475                 if (INTEL_INFO(dev)->gen >= 9)
 476                         intel_psr_activate(intel_dp);
 477         } else {
 478                 vlv_psr_setup_vsc(intel_dp);
 479
 480                 /* Enable PSR on the panel */
 481                 vlv_psr_enable_sink(intel_dp);
 482
 483                 /* On HSW+ enable_source also means go to PSR entry/active
 484                  * state as soon as idle_frame achieved and here would be
 485                  * to soon. However on VLV enable_source just enable PSR
 486                  * but let it on inactive state. So we might do this prior
 487                  * to active transition, i.e. here.
 488                  */
 489                 vlv_psr_enable_source(intel_dp);
 490         }
 491
 492         /*
 493          * FIXME: Activation should happen immediately since this function
 494          * is just called after pipe is fully trained and enabled.
 495          * However on every platform we face issues when first activation
 496          * follows a modeset so quickly.
 497          *     - On VLV/CHV we get bank screen on first activation
 498          *     - On HSW/BDW we get a recoverable frozen screen until next
 499          *       exit-activate sequence.
 500          */
 501         if (INTEL_INFO(dev)->gen < 9)
 502                 schedule_delayed_work(&dev_priv->psr.work,
 503                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 504
 505         dev_priv->psr.enabled = intel_dp;
 506 unlock:
 507         mutex_unlock(&dev_priv->psr.lock);
 508 }
 509
 510 static void vlv_psr_disable(struct intel_dp *intel_dp)
 511 {
 512         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 513         struct drm_device *dev = intel_dig_port->base.base.dev;
 514         struct drm_i915_private *dev_priv = to_i915(dev);
 515         struct intel_crtc *intel_crtc =
 516                 to_intel_crtc(intel_dig_port->base.base.crtc);
 517         uint32_t val;
 518
 519         if (dev_priv->psr.active) {
 520                 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
 521                 if (intel_wait_for_register(dev_priv,
 522                                             VLV_PSRSTAT(intel_crtc->pipe),
 523                                             VLV_EDP_PSR_IN_TRANS,
 524                                             0,
 525                                             1))
 526                         WARN(1, "PSR transition took longer than expected\n");
 527
 528                 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
 529                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 530                 val &= ~VLV_EDP_PSR_ENABLE;
 531                 val &= ~VLV_EDP_PSR_MODE_MASK;
 532                 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
 533
 534                 dev_priv->psr.active = false;
 535         } else {
 536                 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 537         }
 538 }
 539
 540 static void hsw_psr_disable(struct intel_dp *intel_dp)
 541 {
 542         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 543         struct drm_device *dev = intel_dig_port->base.base.dev;
 544         struct drm_i915_private *dev_priv = to_i915(dev);
 545
 546         if (dev_priv->psr.active) {
 547                 I915_WRITE(EDP_PSR_CTL,
 548                            I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 549
 550                 /* Wait till PSR is idle */
 551                 if (intel_wait_for_register(dev_priv,
 552                                             EDP_PSR_STATUS_CTL,
 553                                             EDP_PSR_STATUS_STATE_MASK,
 554                                             0,
 555                                             2000))
 556                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 557
 558                 dev_priv->psr.active = false;
 559         } else {
 560                 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 561         }
 562 }
 563
 564 /**
 565  * intel_psr_disable - Disable PSR
 566  * @intel_dp: Intel DP
 567  *
 568  * This function needs to be called before disabling pipe.
 569  */
 570 void intel_psr_disable(struct intel_dp *intel_dp)
 571 {
 572         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 573         struct drm_device *dev = intel_dig_port->base.base.dev;
 574         struct drm_i915_private *dev_priv = to_i915(dev);
 575
 576         mutex_lock(&dev_priv->psr.lock);
 577         if (!dev_priv->psr.enabled) {
 578                 mutex_unlock(&dev_priv->psr.lock);
 579                 return;
 580         }
 581
 582         /* Disable PSR on Source */
 583         if (HAS_DDI(dev))
 584                 hsw_psr_disable(intel_dp);
 585         else
 586                 vlv_psr_disable(intel_dp);
 587
 588         /* Disable PSR on Sink */
 589         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 590
 591         dev_priv->psr.enabled = NULL;
 592         mutex_unlock(&dev_priv->psr.lock);
 593
 594         cancel_delayed_work_sync(&dev_priv->psr.work);
 595 }
 596
 597 static void intel_psr_work(struct work_struct *work)
 598 {
 599         struct drm_i915_private *dev_priv =
 600                 container_of(work, typeof(*dev_priv), psr.work.work);
 601         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 602         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 603         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 604
 605         /* We have to make sure PSR is ready for re-enable
 606          * otherwise it keeps disabled until next full enable/disable cycle.
 607          * PSR might take some time to get fully disabled
 608          * and be ready for re-enable.
 609          */
 610         if (HAS_DDI(dev_priv)) {
 611                 if (intel_wait_for_register(dev_priv,
 612                                             EDP_PSR_STATUS_CTL,
 613                                             EDP_PSR_STATUS_STATE_MASK,
 614                                             0,
 615                                             50)) {
 616                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 617                         return;
 618                 }
 619         } else {
 620                 if (intel_wait_for_register(dev_priv,
 621                                             VLV_PSRSTAT(pipe),
 622                                             VLV_EDP_PSR_IN_TRANS,
 623                                             0,
 624                                             1)) {
 625                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 626                         return;
 627                 }
 628         }
 629         mutex_lock(&dev_priv->psr.lock);
 630         intel_dp = dev_priv->psr.enabled;
 631
 632         if (!intel_dp)
 633                 goto unlock;
 634
 635         /*
 636          * The delayed work can race with an invalidate hence we need to
 637          * recheck. Since psr_flush first clears this and then reschedules we
 638          * won't ever miss a flush when bailing out here.
 639          */
 640         if (dev_priv->psr.busy_frontbuffer_bits)
 641                 goto unlock;
 642
 643         intel_psr_activate(intel_dp);
 644 unlock:
 645         mutex_unlock(&dev_priv->psr.lock);
 646 }
 647
 648 static void intel_psr_exit(struct drm_device *dev)
 649 {
 650         struct drm_i915_private *dev_priv = to_i915(dev);
 651         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 652         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 653         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 654         u32 val;
 655
 656         if (!dev_priv->psr.active)
 657                 return;
 658
 659         if (HAS_DDI(dev)) {
 660                 val = I915_READ(EDP_PSR_CTL);
 661
 662                 WARN_ON(!(val & EDP_PSR_ENABLE));
 663
 664                 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 665         } else {
 666                 val = I915_READ(VLV_PSRCTL(pipe));
 667
 668                 /* Here we do the transition from PSR_state 3 to PSR_state 5
 669                  * directly once PSR State 4 that is active with single frame
 670                  * update can be skipped. PSR_state 5 that is PSR exit then
 671                  * Hardware is responsible to transition back to PSR_state 1
 672                  * that is PSR inactive. Same state after
 673                  * vlv_edp_psr_enable_source.
 674                  */
 675                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 676                 I915_WRITE(VLV_PSRCTL(pipe), val);
 677
 678                 /* Send AUX wake up - Spec says after transitioning to PSR
 679                  * active we have to send AUX wake up by writing 01h in DPCD
 680                  * 600h of sink device.
 681                  * XXX: This might slow down the transition, but without this
 682                  * HW doesn't complete the transition to PSR_state 1 and we
 683                  * never get the screen updated.
 684                  */
 685                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
 686                                    DP_SET_POWER_D0);
 687         }
 688
 689         dev_priv->psr.active = false;
 690 }
 691
 692 /**
 693  * intel_psr_single_frame_update - Single Frame Update
 694  * @dev: DRM device
 695  * @frontbuffer_bits: frontbuffer plane tracking bits
 696  *
 697  * Some platforms support a single frame update feature that is used to
 698  * send and update only one frame on Remote Frame Buffer.
 699  * So far it is only implemented for Valleyview and Cherryview because
 700  * hardware requires this to be done before a page flip.
 701  */
 702 void intel_psr_single_frame_update(struct drm_device *dev,
 703                                    unsigned frontbuffer_bits)
 704 {
 705         struct drm_i915_private *dev_priv = to_i915(dev);
 706         struct drm_crtc *crtc;
 707         enum pipe pipe;
 708         u32 val;
 709
 710         /*
 711          * Single frame update is already supported on BDW+ but it requires
 712          * many W/A and it isn't really needed.
 713          */
 714         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 715                 return;
 716
 717         mutex_lock(&dev_priv->psr.lock);
 718         if (!dev_priv->psr.enabled) {
 719                 mutex_unlock(&dev_priv->psr.lock);
 720                 return;
 721         }
 722
 723         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 724         pipe = to_intel_crtc(crtc)->pipe;
 725
 726         if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
 727                 val = I915_READ(VLV_PSRCTL(pipe));
 728
 729                 /*
 730                  * We need to set this bit before writing registers for a flip.
 731                  * This bit will be self-clear when it gets to the PSR active state.
 732                  */
 733                 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
 734         }
 735         mutex_unlock(&dev_priv->psr.lock);
 736 }
 737
 738 /**
 739  * intel_psr_invalidate - Invalidade PSR
 740  * @dev: DRM device
 741  * @frontbuffer_bits: frontbuffer plane tracking bits
 742  *
 743  * Since the hardware frontbuffer tracking has gaps we need to integrate
 744  * with the software frontbuffer tracking. This function gets called every
 745  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 746  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 747  *
 748  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 749  */
 750 void intel_psr_invalidate(struct drm_device *dev,
 751                           unsigned frontbuffer_bits)
 752 {
 753         struct drm_i915_private *dev_priv = to_i915(dev);
 754         struct drm_crtc *crtc;
 755         enum pipe pipe;
 756
 757         mutex_lock(&dev_priv->psr.lock);
 758         if (!dev_priv->psr.enabled) {
 759                 mutex_unlock(&dev_priv->psr.lock);
 760                 return;
 761         }
 762
 763         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 764         pipe = to_intel_crtc(crtc)->pipe;
 765
 766         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 767         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 768
 769         if (frontbuffer_bits)
 770                 intel_psr_exit(dev);
 771
 772         mutex_unlock(&dev_priv->psr.lock);
 773 }
 774
 775 /**
 776  * intel_psr_flush - Flush PSR
 777  * @dev: DRM device
 778  * @frontbuffer_bits: frontbuffer plane tracking bits
 779  * @origin: which operation caused the flush
 780  *
 781  * Since the hardware frontbuffer tracking has gaps we need to integrate
 782  * with the software frontbuffer tracking. This function gets called every
 783  * time frontbuffer rendering has completed and flushed out to memory. PSR
 784  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 785  *
 786  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 787  */
 788 void intel_psr_flush(struct drm_device *dev,
 789                      unsigned frontbuffer_bits, enum fb_op_origin origin)
 790 {
 791         struct drm_i915_private *dev_priv = to_i915(dev);
 792         struct drm_crtc *crtc;
 793         enum pipe pipe;
 794
 795         mutex_lock(&dev_priv->psr.lock);
 796         if (!dev_priv->psr.enabled) {
 797                 mutex_unlock(&dev_priv->psr.lock);
 798                 return;
 799         }
 800
 801         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 802         pipe = to_intel_crtc(crtc)->pipe;
 803
 804         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 805         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 806
 807         /* By definition flush = invalidate + flush */
 808         if (frontbuffer_bits)
 809                 intel_psr_exit(dev);
 810
 811         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 812                 if (!work_busy(&dev_priv->psr.work.work))
 813                         schedule_delayed_work(&dev_priv->psr.work,
 814                                               msecs_to_jiffies(100));
 815         mutex_unlock(&dev_priv->psr.lock);
 816 }
 817
 818 /**
 819  * intel_psr_init - Init basic PSR work and mutex.
 820  * @dev: DRM device
 821  *
 822  * This function is  called only once at driver load to initialize basic
 823  * PSR stuff.
 824  */
 825 void intel_psr_init(struct drm_device *dev)
 826 {
 827         struct drm_i915_private *dev_priv = to_i915(dev);
 828
 829         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
 830                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 831
 832         /* Per platform default */
 833         if (i915.enable_psr == -1) {
 834                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 835                         i915.enable_psr = 1;
 836                 else
 837                         i915.enable_psr = 0;
 838         }
 839
 840         /* Set link_standby x link_off defaults */
 841         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 842                 /* HSW and BDW require workarounds that we don't implement. */
 843                 dev_priv->psr.link_standby = false;
 844         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 845                 /* On VLV and CHV only standby mode is supported. */
 846                 dev_priv->psr.link_standby = true;
 847         else
 848                 /* For new platforms let's respect VBT back again */
 849                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 850
 851         /* Override link_standby x link_off defaults */
 852         if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
 853                 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
 854                 dev_priv->psr.link_standby = true;
 855         }
 856         if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
 857                 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
 858                 dev_priv->psr.link_standby = false;
 859         }
 860
 861         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 862         mutex_init(&dev_priv->psr.lock);
 863 }