drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <drm/i915_powerwell.h>
  34
  35 /**
  36  * RC6 is a special power stage which allows the GPU to enter an very
  37  * low-voltage mode when idle, using down to 0V while at this stage.  This
  38  * stage is entered automatically when the GPU is idle when RC6 support is
  39  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  40  *
  41  * There are different RC6 modes available in Intel GPU, which differentiate
  42  * among each other with the latency required to enter and leave RC6 and
  43  * voltage consumed by the GPU in different states.
  44  *
  45  * The combination of the following flags define which states GPU is allowed
  46  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  47  * RC6pp is deepest RC6. Their support by hardware varies according to the
  48  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  49  * which brings the most power savings; deeper states save more power, but
  50  * require higher latency to switch to and wake up.
  51  */
  52 #define INTEL_RC6_ENABLE                        (1<<0)
  53 #define INTEL_RC6p_ENABLE                       (1<<1)
  54 #define INTEL_RC6pp_ENABLE                      (1<<2)
  55
  56 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  57  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  58  * during in-memory transfers and, therefore, reduce the power packet.
  59  *
  60  * The benefits of FBC are mostly visible with solid backgrounds and
  61  * variation-less patterns.
  62  *
  63  * FBC-related functionality can be enabled by the means of the
  64  * i915.i915_enable_fbc parameter
  65  */
  66
  67 static void i8xx_disable_fbc(struct drm_device *dev)
  68 {
  69         struct drm_i915_private *dev_priv = dev->dev_private;
  70         u32 fbc_ctl;
  71
  72         /* Disable compression */
  73         fbc_ctl = I915_READ(FBC_CONTROL);
  74         if ((fbc_ctl & FBC_CTL_EN) == 0)
  75                 return;
  76
  77         fbc_ctl &= ~FBC_CTL_EN;
  78         I915_WRITE(FBC_CONTROL, fbc_ctl);
  79
  80         /* Wait for compressing bit to clear */
  81         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  82                 DRM_DEBUG_KMS("FBC idle timed out\n");
  83                 return;
  84         }
  85
  86         DRM_DEBUG_KMS("disabled FBC\n");
  87 }
  88
  89 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  90 {
  91         struct drm_device *dev = crtc->dev;
  92         struct drm_i915_private *dev_priv = dev->dev_private;
  93         struct drm_framebuffer *fb = crtc->fb;
  94         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  95         struct drm_i915_gem_object *obj = intel_fb->obj;
  96         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  97         int cfb_pitch;
  98         int plane, i;
  99         u32 fbc_ctl, fbc_ctl2;
 100
 101         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 102         if (fb->pitches[0] < cfb_pitch)
 103                 cfb_pitch = fb->pitches[0];
 104
 105         /* FBC_CTL wants 64B units */
 106         cfb_pitch = (cfb_pitch / 64) - 1;
 107         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 108
 109         /* Clear old tags */
 110         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 111                 I915_WRITE(FBC_TAG + (i * 4), 0);
 112
 113         /* Set it up... */
 114         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 115         fbc_ctl2 |= plane;
 116         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 117         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 118
 119         /* enable it... */
 120         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 121         if (IS_I945GM(dev))
 122                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 123         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 124         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 125         fbc_ctl |= obj->fence_reg;
 126         I915_WRITE(FBC_CONTROL, fbc_ctl);
 127
 128         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 129                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 130 }
 131
 132 static bool i8xx_fbc_enabled(struct drm_device *dev)
 133 {
 134         struct drm_i915_private *dev_priv = dev->dev_private;
 135
 136         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 137 }
 138
 139 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 140 {
 141         struct drm_device *dev = crtc->dev;
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         struct drm_framebuffer *fb = crtc->fb;
 144         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 145         struct drm_i915_gem_object *obj = intel_fb->obj;
 146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 147         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 148         unsigned long stall_watermark = 200;
 149         u32 dpfc_ctl;
 150
 151         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 152         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 153         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 154
 155         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 156                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 157                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 158         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 159
 160         /* enable it... */
 161         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 162
 163         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 164 }
 165
 166 static void g4x_disable_fbc(struct drm_device *dev)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         u32 dpfc_ctl;
 170
 171         /* Disable compression */
 172         dpfc_ctl = I915_READ(DPFC_CONTROL);
 173         if (dpfc_ctl & DPFC_CTL_EN) {
 174                 dpfc_ctl &= ~DPFC_CTL_EN;
 175                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 176
 177                 DRM_DEBUG_KMS("disabled FBC\n");
 178         }
 179 }
 180
 181 static bool g4x_fbc_enabled(struct drm_device *dev)
 182 {
 183         struct drm_i915_private *dev_priv = dev->dev_private;
 184
 185         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 186 }
 187
 188 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         u32 blt_ecoskpd;
 192
 193         /* Make sure blitter notifies FBC of writes */
 194         gen6_gt_force_wake_get(dev_priv);
 195         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 196         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 197                 GEN6_BLITTER_LOCK_SHIFT;
 198         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 199         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 200         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 201         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 202                          GEN6_BLITTER_LOCK_SHIFT);
 203         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 204         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 205         gen6_gt_force_wake_put(dev_priv);
 206 }
 207
 208 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 209 {
 210         struct drm_device *dev = crtc->dev;
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         struct drm_framebuffer *fb = crtc->fb;
 213         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 214         struct drm_i915_gem_object *obj = intel_fb->obj;
 215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 216         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 217         unsigned long stall_watermark = 200;
 218         u32 dpfc_ctl;
 219
 220         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 221         dpfc_ctl &= DPFC_RESERVED;
 222         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 223         /* Set persistent mode for front-buffer rendering, ala X. */
 224         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 225         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 226         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 227
 228         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 229                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 230                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 231         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 232         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 233         /* enable it... */
 234         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 235
 236         if (IS_GEN6(dev)) {
 237                 I915_WRITE(SNB_DPFC_CTL_SA,
 238                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 239                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 240                 sandybridge_blit_fbc_update(dev);
 241         }
 242
 243         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 244 }
 245
 246 static void ironlake_disable_fbc(struct drm_device *dev)
 247 {
 248         struct drm_i915_private *dev_priv = dev->dev_private;
 249         u32 dpfc_ctl;
 250
 251         /* Disable compression */
 252         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 253         if (dpfc_ctl & DPFC_CTL_EN) {
 254                 dpfc_ctl &= ~DPFC_CTL_EN;
 255                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 256
 257                 if (IS_HASWELL(dev))
 258                         /* WaFbcDisableDpfcClockGating:hsw */
 259                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 260                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
 261                                    ~HSW_DPFC_GATING_DISABLE);
 262
 263                 DRM_DEBUG_KMS("disabled FBC\n");
 264         }
 265 }
 266
 267 static bool ironlake_fbc_enabled(struct drm_device *dev)
 268 {
 269         struct drm_i915_private *dev_priv = dev->dev_private;
 270
 271         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 272 }
 273
 274 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 275 {
 276         struct drm_device *dev = crtc->dev;
 277         struct drm_i915_private *dev_priv = dev->dev_private;
 278         struct drm_framebuffer *fb = crtc->fb;
 279         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 280         struct drm_i915_gem_object *obj = intel_fb->obj;
 281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 282
 283         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 284
 285         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 286                    IVB_DPFC_CTL_FENCE_EN |
 287                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 288
 289         if (IS_IVYBRIDGE(dev)) {
 290                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 291                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 292         } else {
 293                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 294                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 295                            HSW_BYPASS_FBC_QUEUE);
 296                 /* WaFbcDisableDpfcClockGating:hsw */
 297                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 298                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
 299                            HSW_DPFC_GATING_DISABLE);
 300         }
 301
 302         I915_WRITE(SNB_DPFC_CTL_SA,
 303                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 304         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 305
 306         sandybridge_blit_fbc_update(dev);
 307
 308         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 309 }
 310
 311 bool intel_fbc_enabled(struct drm_device *dev)
 312 {
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314
 315         if (!dev_priv->display.fbc_enabled)
 316                 return false;
 317
 318         return dev_priv->display.fbc_enabled(dev);
 319 }
 320
 321 static void intel_fbc_work_fn(struct work_struct *__work)
 322 {
 323         struct intel_fbc_work *work =
 324                 container_of(to_delayed_work(__work),
 325                              struct intel_fbc_work, work);
 326         struct drm_device *dev = work->crtc->dev;
 327         struct drm_i915_private *dev_priv = dev->dev_private;
 328
 329         mutex_lock(&dev->struct_mutex);
 330         if (work == dev_priv->fbc.fbc_work) {
 331                 /* Double check that we haven't switched fb without cancelling
 332                  * the prior work.
 333                  */
 334                 if (work->crtc->fb == work->fb) {
 335                         dev_priv->display.enable_fbc(work->crtc,
 336                                                      work->interval);
 337
 338                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 339                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 340                         dev_priv->fbc.y = work->crtc->y;
 341                 }
 342
 343                 dev_priv->fbc.fbc_work = NULL;
 344         }
 345         mutex_unlock(&dev->struct_mutex);
 346
 347         kfree(work);
 348 }
 349
 350 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 351 {
 352         if (dev_priv->fbc.fbc_work == NULL)
 353                 return;
 354
 355         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 356
 357         /* Synchronisation is provided by struct_mutex and checking of
 358          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 359          * entirely asynchronously.
 360          */
 361         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 362                 /* tasklet was killed before being run, clean up */
 363                 kfree(dev_priv->fbc.fbc_work);
 364
 365         /* Mark the work as no longer wanted so that if it does
 366          * wake-up (because the work was already running and waiting
 367          * for our mutex), it will discover that is no longer
 368          * necessary to run.
 369          */
 370         dev_priv->fbc.fbc_work = NULL;
 371 }
 372
 373 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 374 {
 375         struct intel_fbc_work *work;
 376         struct drm_device *dev = crtc->dev;
 377         struct drm_i915_private *dev_priv = dev->dev_private;
 378
 379         if (!dev_priv->display.enable_fbc)
 380                 return;
 381
 382         intel_cancel_fbc_work(dev_priv);
 383
 384         work = kzalloc(sizeof(*work), GFP_KERNEL);
 385         if (work == NULL) {
 386                 DRM_ERROR("Failed to allocate FBC work structure\n");
 387                 dev_priv->display.enable_fbc(crtc, interval);
 388                 return;
 389         }
 390
 391         work->crtc = crtc;
 392         work->fb = crtc->fb;
 393         work->interval = interval;
 394         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 395
 396         dev_priv->fbc.fbc_work = work;
 397
 398         /* Delay the actual enabling to let pageflipping cease and the
 399          * display to settle before starting the compression. Note that
 400          * this delay also serves a second purpose: it allows for a
 401          * vblank to pass after disabling the FBC before we attempt
 402          * to modify the control registers.
 403          *
 404          * A more complicated solution would involve tracking vblanks
 405          * following the termination of the page-flipping sequence
 406          * and indeed performing the enable as a co-routine and not
 407          * waiting synchronously upon the vblank.
 408          *
 409          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 410          */
 411         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 412 }
 413
 414 void intel_disable_fbc(struct drm_device *dev)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417
 418         intel_cancel_fbc_work(dev_priv);
 419
 420         if (!dev_priv->display.disable_fbc)
 421                 return;
 422
 423         dev_priv->display.disable_fbc(dev);
 424         dev_priv->fbc.plane = -1;
 425 }
 426
 427 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 428                               enum no_fbc_reason reason)
 429 {
 430         if (dev_priv->fbc.no_fbc_reason == reason)
 431                 return false;
 432
 433         dev_priv->fbc.no_fbc_reason = reason;
 434         return true;
 435 }
 436
 437 /**
 438  * intel_update_fbc - enable/disable FBC as needed
 439  * @dev: the drm_device
 440  *
 441  * Set up the framebuffer compression hardware at mode set time.  We
 442  * enable it if possible:
 443  *   - plane A only (on pre-965)
 444  *   - no pixel mulitply/line duplication
 445  *   - no alpha buffer discard
 446  *   - no dual wide
 447  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 448  *
 449  * We can't assume that any compression will take place (worst case),
 450  * so the compressed buffer has to be the same size as the uncompressed
 451  * one.  It also must reside (along with the line length buffer) in
 452  * stolen memory.
 453  *
 454  * We need to enable/disable FBC on a global basis.
 455  */
 456 void intel_update_fbc(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459         struct drm_crtc *crtc = NULL, *tmp_crtc;
 460         struct intel_crtc *intel_crtc;
 461         struct drm_framebuffer *fb;
 462         struct intel_framebuffer *intel_fb;
 463         struct drm_i915_gem_object *obj;
 464         const struct drm_display_mode *adjusted_mode;
 465         unsigned int max_width, max_height;
 466
 467         if (!I915_HAS_FBC(dev)) {
 468                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 469                 return;
 470         }
 471
 472         if (!i915_powersave) {
 473                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 474                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 475                 return;
 476         }
 477
 478         /*
 479          * If FBC is already on, we just have to verify that we can
 480          * keep it that way...
 481          * Need to disable if:
 482          *   - more than one pipe is active
 483          *   - changing FBC params (stride, fence, mode)
 484          *   - new fb is too large to fit in compressed buffer
 485          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 486          */
 487         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 488                 if (intel_crtc_active(tmp_crtc) &&
 489                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 490                         if (crtc) {
 491                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 492                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 493                                 goto out_disable;
 494                         }
 495                         crtc = tmp_crtc;
 496                 }
 497         }
 498
 499         if (!crtc || crtc->fb == NULL) {
 500                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 501                         DRM_DEBUG_KMS("no output, disabling\n");
 502                 goto out_disable;
 503         }
 504
 505         intel_crtc = to_intel_crtc(crtc);
 506         fb = crtc->fb;
 507         intel_fb = to_intel_framebuffer(fb);
 508         obj = intel_fb->obj;
 509         adjusted_mode = &intel_crtc->config.adjusted_mode;
 510
 511         if (i915_enable_fbc < 0 &&
 512             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 513                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 514                         DRM_DEBUG_KMS("disabled per chip default\n");
 515                 goto out_disable;
 516         }
 517         if (!i915_enable_fbc) {
 518                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 519                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 520                 goto out_disable;
 521         }
 522         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 523             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 524                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 525                         DRM_DEBUG_KMS("mode incompatible with compression, "
 526                                       "disabling\n");
 527                 goto out_disable;
 528         }
 529
 530         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 531                 max_width = 4096;
 532                 max_height = 2048;
 533         } else {
 534                 max_width = 2048;
 535                 max_height = 1536;
 536         }
 537         if (intel_crtc->config.pipe_src_w > max_width ||
 538             intel_crtc->config.pipe_src_h > max_height) {
 539                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 540                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 541                 goto out_disable;
 542         }
 543         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 544             intel_crtc->plane != 0) {
 545                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 546                         DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 547                 goto out_disable;
 548         }
 549
 550         /* The use of a CPU fence is mandatory in order to detect writes
 551          * by the CPU to the scanout and trigger updates to the FBC.
 552          */
 553         if (obj->tiling_mode != I915_TILING_X ||
 554             obj->fence_reg == I915_FENCE_REG_NONE) {
 555                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 556                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 557                 goto out_disable;
 558         }
 559
 560         /* If the kernel debugger is active, always disable compression */
 561         if (in_dbg_master())
 562                 goto out_disable;
 563
 564         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 565                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 566                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 567                 goto out_disable;
 568         }
 569
 570         /* If the scanout has not changed, don't modify the FBC settings.
 571          * Note that we make the fundamental assumption that the fb->obj
 572          * cannot be unpinned (and have its GTT offset and fence revoked)
 573          * without first being decoupled from the scanout and FBC disabled.
 574          */
 575         if (dev_priv->fbc.plane == intel_crtc->plane &&
 576             dev_priv->fbc.fb_id == fb->base.id &&
 577             dev_priv->fbc.y == crtc->y)
 578                 return;
 579
 580         if (intel_fbc_enabled(dev)) {
 581                 /* We update FBC along two paths, after changing fb/crtc
 582                  * configuration (modeswitching) and after page-flipping
 583                  * finishes. For the latter, we know that not only did
 584                  * we disable the FBC at the start of the page-flip
 585                  * sequence, but also more than one vblank has passed.
 586                  *
 587                  * For the former case of modeswitching, it is possible
 588                  * to switch between two FBC valid configurations
 589                  * instantaneously so we do need to disable the FBC
 590                  * before we can modify its control registers. We also
 591                  * have to wait for the next vblank for that to take
 592                  * effect. However, since we delay enabling FBC we can
 593                  * assume that a vblank has passed since disabling and
 594                  * that we can safely alter the registers in the deferred
 595                  * callback.
 596                  *
 597                  * In the scenario that we go from a valid to invalid
 598                  * and then back to valid FBC configuration we have
 599                  * no strict enforcement that a vblank occurred since
 600                  * disabling the FBC. However, along all current pipe
 601                  * disabling paths we do need to wait for a vblank at
 602                  * some point. And we wait before enabling FBC anyway.
 603                  */
 604                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 605                 intel_disable_fbc(dev);
 606         }
 607
 608         intel_enable_fbc(crtc, 500);
 609         dev_priv->fbc.no_fbc_reason = FBC_OK;
 610         return;
 611
 612 out_disable:
 613         /* Multiple disables should be harmless */
 614         if (intel_fbc_enabled(dev)) {
 615                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 616                 intel_disable_fbc(dev);
 617         }
 618         i915_gem_stolen_cleanup_compression(dev);
 619 }
 620
 621 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 622 {
 623         drm_i915_private_t *dev_priv = dev->dev_private;
 624         u32 tmp;
 625
 626         tmp = I915_READ(CLKCFG);
 627
 628         switch (tmp & CLKCFG_FSB_MASK) {
 629         case CLKCFG_FSB_533:
 630                 dev_priv->fsb_freq = 533; /* 133*4 */
 631                 break;
 632         case CLKCFG_FSB_800:
 633                 dev_priv->fsb_freq = 800; /* 200*4 */
 634                 break;
 635         case CLKCFG_FSB_667:
 636                 dev_priv->fsb_freq =  667; /* 167*4 */
 637                 break;
 638         case CLKCFG_FSB_400:
 639                 dev_priv->fsb_freq = 400; /* 100*4 */
 640                 break;
 641         }
 642
 643         switch (tmp & CLKCFG_MEM_MASK) {
 644         case CLKCFG_MEM_533:
 645                 dev_priv->mem_freq = 533;
 646                 break;
 647         case CLKCFG_MEM_667:
 648                 dev_priv->mem_freq = 667;
 649                 break;
 650         case CLKCFG_MEM_800:
 651                 dev_priv->mem_freq = 800;
 652                 break;
 653         }
 654
 655         /* detect pineview DDR3 setting */
 656         tmp = I915_READ(CSHRDDR3CTL);
 657         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 658 }
 659
 660 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 661 {
 662         drm_i915_private_t *dev_priv = dev->dev_private;
 663         u16 ddrpll, csipll;
 664
 665         ddrpll = I915_READ16(DDRMPLL1);
 666         csipll = I915_READ16(CSIPLL0);
 667
 668         switch (ddrpll & 0xff) {
 669         case 0xc:
 670                 dev_priv->mem_freq = 800;
 671                 break;
 672         case 0x10:
 673                 dev_priv->mem_freq = 1066;
 674                 break;
 675         case 0x14:
 676                 dev_priv->mem_freq = 1333;
 677                 break;
 678         case 0x18:
 679                 dev_priv->mem_freq = 1600;
 680                 break;
 681         default:
 682                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 683                                  ddrpll & 0xff);
 684                 dev_priv->mem_freq = 0;
 685                 break;
 686         }
 687
 688         dev_priv->ips.r_t = dev_priv->mem_freq;
 689
 690         switch (csipll & 0x3ff) {
 691         case 0x00c:
 692                 dev_priv->fsb_freq = 3200;
 693                 break;
 694         case 0x00e:
 695                 dev_priv->fsb_freq = 3733;
 696                 break;
 697         case 0x010:
 698                 dev_priv->fsb_freq = 4266;
 699                 break;
 700         case 0x012:
 701                 dev_priv->fsb_freq = 4800;
 702                 break;
 703         case 0x014:
 704                 dev_priv->fsb_freq = 5333;
 705                 break;
 706         case 0x016:
 707                 dev_priv->fsb_freq = 5866;
 708                 break;
 709         case 0x018:
 710                 dev_priv->fsb_freq = 6400;
 711                 break;
 712         default:
 713                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 714                                  csipll & 0x3ff);
 715                 dev_priv->fsb_freq = 0;
 716                 break;
 717         }
 718
 719         if (dev_priv->fsb_freq == 3200) {
 720                 dev_priv->ips.c_m = 0;
 721         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 722                 dev_priv->ips.c_m = 1;
 723         } else {
 724                 dev_priv->ips.c_m = 2;
 725         }
 726 }
 727
 728 static const struct cxsr_latency cxsr_latency_table[] = {
 729         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 730         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 731         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 732         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 733         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 734
 735         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 736         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 737         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 738         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 739         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 740
 741         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 742         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 743         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 744         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 745         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 746
 747         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 748         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 749         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 750         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 751         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 752
 753         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 754         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 755         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 756         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 757         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 758
 759         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 760         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 761         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 762         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 763         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 764 };
 765
 766 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 767                                                          int is_ddr3,
 768                                                          int fsb,
 769                                                          int mem)
 770 {
 771         const struct cxsr_latency *latency;
 772         int i;
 773
 774         if (fsb == 0 || mem == 0)
 775                 return NULL;
 776
 777         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 778                 latency = &cxsr_latency_table[i];
 779                 if (is_desktop == latency->is_desktop &&
 780                     is_ddr3 == latency->is_ddr3 &&
 781                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 782                         return latency;
 783         }
 784
 785         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 786
 787         return NULL;
 788 }
 789
 790 static void pineview_disable_cxsr(struct drm_device *dev)
 791 {
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793
 794         /* deactivate cxsr */
 795         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 796 }
 797
 798 /*
 799  * Latency for FIFO fetches is dependent on several factors:
 800  *   - memory configuration (speed, channels)
 801  *   - chipset
 802  *   - current MCH state
 803  * It can be fairly high in some situations, so here we assume a fairly
 804  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 805  * set this value too high, the FIFO will fetch frequently to stay full)
 806  * and power consumption (set it too low to save power and we might see
 807  * FIFO underruns and display "flicker").
 808  *
 809  * A value of 5us seems to be a good balance; safe for very low end
 810  * platforms but not overly aggressive on lower latency configs.
 811  */
 812 static const int latency_ns = 5000;
 813
 814 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         uint32_t dsparb = I915_READ(DSPARB);
 818         int size;
 819
 820         size = dsparb & 0x7f;
 821         if (plane)
 822                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 823
 824         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 825                       plane ? "B" : "A", size);
 826
 827         return size;
 828 }
 829
 830 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         uint32_t dsparb = I915_READ(DSPARB);
 834         int size;
 835
 836         size = dsparb & 0x1ff;
 837         if (plane)
 838                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 839         size >>= 1; /* Convert to cachelines */
 840
 841         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 842                       plane ? "B" : "A", size);
 843
 844         return size;
 845 }
 846
 847 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 848 {
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850         uint32_t dsparb = I915_READ(DSPARB);
 851         int size;
 852
 853         size = dsparb & 0x7f;
 854         size >>= 2; /* Convert to cachelines */
 855
 856         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 857                       plane ? "B" : "A",
 858                       size);
 859
 860         return size;
 861 }
 862
 863 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         uint32_t dsparb = I915_READ(DSPARB);
 867         int size;
 868
 869         size = dsparb & 0x7f;
 870         size >>= 1; /* Convert to cachelines */
 871
 872         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 873                       plane ? "B" : "A", size);
 874
 875         return size;
 876 }
 877
 878 /* Pineview has different values for various configs */
 879 static const struct intel_watermark_params pineview_display_wm = {
 880         PINEVIEW_DISPLAY_FIFO,
 881         PINEVIEW_MAX_WM,
 882         PINEVIEW_DFT_WM,
 883         PINEVIEW_GUARD_WM,
 884         PINEVIEW_FIFO_LINE_SIZE
 885 };
 886 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 887         PINEVIEW_DISPLAY_FIFO,
 888         PINEVIEW_MAX_WM,
 889         PINEVIEW_DFT_HPLLOFF_WM,
 890         PINEVIEW_GUARD_WM,
 891         PINEVIEW_FIFO_LINE_SIZE
 892 };
 893 static const struct intel_watermark_params pineview_cursor_wm = {
 894         PINEVIEW_CURSOR_FIFO,
 895         PINEVIEW_CURSOR_MAX_WM,
 896         PINEVIEW_CURSOR_DFT_WM,
 897         PINEVIEW_CURSOR_GUARD_WM,
 898         PINEVIEW_FIFO_LINE_SIZE,
 899 };
 900 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 901         PINEVIEW_CURSOR_FIFO,
 902         PINEVIEW_CURSOR_MAX_WM,
 903         PINEVIEW_CURSOR_DFT_WM,
 904         PINEVIEW_CURSOR_GUARD_WM,
 905         PINEVIEW_FIFO_LINE_SIZE
 906 };
 907 static const struct intel_watermark_params g4x_wm_info = {
 908         G4X_FIFO_SIZE,
 909         G4X_MAX_WM,
 910         G4X_MAX_WM,
 911         2,
 912         G4X_FIFO_LINE_SIZE,
 913 };
 914 static const struct intel_watermark_params g4x_cursor_wm_info = {
 915         I965_CURSOR_FIFO,
 916         I965_CURSOR_MAX_WM,
 917         I965_CURSOR_DFT_WM,
 918         2,
 919         G4X_FIFO_LINE_SIZE,
 920 };
 921 static const struct intel_watermark_params valleyview_wm_info = {
 922         VALLEYVIEW_FIFO_SIZE,
 923         VALLEYVIEW_MAX_WM,
 924         VALLEYVIEW_MAX_WM,
 925         2,
 926         G4X_FIFO_LINE_SIZE,
 927 };
 928 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 929         I965_CURSOR_FIFO,
 930         VALLEYVIEW_CURSOR_MAX_WM,
 931         I965_CURSOR_DFT_WM,
 932         2,
 933         G4X_FIFO_LINE_SIZE,
 934 };
 935 static const struct intel_watermark_params i965_cursor_wm_info = {
 936         I965_CURSOR_FIFO,
 937         I965_CURSOR_MAX_WM,
 938         I965_CURSOR_DFT_WM,
 939         2,
 940         I915_FIFO_LINE_SIZE,
 941 };
 942 static const struct intel_watermark_params i945_wm_info = {
 943         I945_FIFO_SIZE,
 944         I915_MAX_WM,
 945         1,
 946         2,
 947         I915_FIFO_LINE_SIZE
 948 };
 949 static const struct intel_watermark_params i915_wm_info = {
 950         I915_FIFO_SIZE,
 951         I915_MAX_WM,
 952         1,
 953         2,
 954         I915_FIFO_LINE_SIZE
 955 };
 956 static const struct intel_watermark_params i855_wm_info = {
 957         I855GM_FIFO_SIZE,
 958         I915_MAX_WM,
 959         1,
 960         2,
 961         I830_FIFO_LINE_SIZE
 962 };
 963 static const struct intel_watermark_params i830_wm_info = {
 964         I830_FIFO_SIZE,
 965         I915_MAX_WM,
 966         1,
 967         2,
 968         I830_FIFO_LINE_SIZE
 969 };
 970
 971 static const struct intel_watermark_params ironlake_display_wm_info = {
 972         ILK_DISPLAY_FIFO,
 973         ILK_DISPLAY_MAXWM,
 974         ILK_DISPLAY_DFTWM,
 975         2,
 976         ILK_FIFO_LINE_SIZE
 977 };
 978 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 979         ILK_CURSOR_FIFO,
 980         ILK_CURSOR_MAXWM,
 981         ILK_CURSOR_DFTWM,
 982         2,
 983         ILK_FIFO_LINE_SIZE
 984 };
 985 static const struct intel_watermark_params ironlake_display_srwm_info = {
 986         ILK_DISPLAY_SR_FIFO,
 987         ILK_DISPLAY_MAX_SRWM,
 988         ILK_DISPLAY_DFT_SRWM,
 989         2,
 990         ILK_FIFO_LINE_SIZE
 991 };
 992 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 993         ILK_CURSOR_SR_FIFO,
 994         ILK_CURSOR_MAX_SRWM,
 995         ILK_CURSOR_DFT_SRWM,
 996         2,
 997         ILK_FIFO_LINE_SIZE
 998 };
 999
1000 static const struct intel_watermark_params sandybridge_display_wm_info = {
1001         SNB_DISPLAY_FIFO,
1002         SNB_DISPLAY_MAXWM,
1003         SNB_DISPLAY_DFTWM,
1004         2,
1005         SNB_FIFO_LINE_SIZE
1006 };
1007 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1008         SNB_CURSOR_FIFO,
1009         SNB_CURSOR_MAXWM,
1010         SNB_CURSOR_DFTWM,
1011         2,
1012         SNB_FIFO_LINE_SIZE
1013 };
1014 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1015         SNB_DISPLAY_SR_FIFO,
1016         SNB_DISPLAY_MAX_SRWM,
1017         SNB_DISPLAY_DFT_SRWM,
1018         2,
1019         SNB_FIFO_LINE_SIZE
1020 };
1021 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1022         SNB_CURSOR_SR_FIFO,
1023         SNB_CURSOR_MAX_SRWM,
1024         SNB_CURSOR_DFT_SRWM,
1025         2,
1026         SNB_FIFO_LINE_SIZE
1027 };
1028
1029
1030 /**
1031  * intel_calculate_wm - calculate watermark level
1032  * @clock_in_khz: pixel clock
1033  * @wm: chip FIFO params
1034  * @pixel_size: display pixel size
1035  * @latency_ns: memory latency for the platform
1036  *
1037  * Calculate the watermark level (the level at which the display plane will
1038  * start fetching from memory again).  Each chip has a different display
1039  * FIFO size and allocation, so the caller needs to figure that out and pass
1040  * in the correct intel_watermark_params structure.
1041  *
1042  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1043  * on the pixel size.  When it reaches the watermark level, it'll start
1044  * fetching FIFO line sized based chunks from memory until the FIFO fills
1045  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1046  * will occur, and a display engine hang could result.
1047  */
1048 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1049                                         const struct intel_watermark_params *wm,
1050                                         int fifo_size,
1051                                         int pixel_size,
1052                                         unsigned long latency_ns)
1053 {
1054         long entries_required, wm_size;
1055
1056         /*
1057          * Note: we need to make sure we don't overflow for various clock &
1058          * latency values.
1059          * clocks go from a few thousand to several hundred thousand.
1060          * latency is usually a few thousand
1061          */
1062         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1063                 1000;
1064         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1065
1066         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1067
1068         wm_size = fifo_size - (entries_required + wm->guard_size);
1069
1070         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1071
1072         /* Don't promote wm_size to unsigned... */
1073         if (wm_size > (long)wm->max_wm)
1074                 wm_size = wm->max_wm;
1075         if (wm_size <= 0)
1076                 wm_size = wm->default_wm;
1077         return wm_size;
1078 }
1079
1080 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1081 {
1082         struct drm_crtc *crtc, *enabled = NULL;
1083
1084         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1085                 if (intel_crtc_active(crtc)) {
1086                         if (enabled)
1087                                 return NULL;
1088                         enabled = crtc;
1089                 }
1090         }
1091
1092         return enabled;
1093 }
1094
1095 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1096 {
1097         struct drm_device *dev = unused_crtc->dev;
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         struct drm_crtc *crtc;
1100         const struct cxsr_latency *latency;
1101         u32 reg;
1102         unsigned long wm;
1103
1104         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1105                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1106         if (!latency) {
1107                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1108                 pineview_disable_cxsr(dev);
1109                 return;
1110         }
1111
1112         crtc = single_enabled_crtc(dev);
1113         if (crtc) {
1114                 const struct drm_display_mode *adjusted_mode;
1115                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1116                 int clock;
1117
1118                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1119                 clock = adjusted_mode->crtc_clock;
1120
1121                 /* Display SR */
1122                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1123                                         pineview_display_wm.fifo_size,
1124                                         pixel_size, latency->display_sr);
1125                 reg = I915_READ(DSPFW1);
1126                 reg &= ~DSPFW_SR_MASK;
1127                 reg |= wm << DSPFW_SR_SHIFT;
1128                 I915_WRITE(DSPFW1, reg);
1129                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1130
1131                 /* cursor SR */
1132                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1133                                         pineview_display_wm.fifo_size,
1134                                         pixel_size, latency->cursor_sr);
1135                 reg = I915_READ(DSPFW3);
1136                 reg &= ~DSPFW_CURSOR_SR_MASK;
1137                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1138                 I915_WRITE(DSPFW3, reg);
1139
1140                 /* Display HPLL off SR */
1141                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1142                                         pineview_display_hplloff_wm.fifo_size,
1143                                         pixel_size, latency->display_hpll_disable);
1144                 reg = I915_READ(DSPFW3);
1145                 reg &= ~DSPFW_HPLL_SR_MASK;
1146                 reg |= wm & DSPFW_HPLL_SR_MASK;
1147                 I915_WRITE(DSPFW3, reg);
1148
1149                 /* cursor HPLL off SR */
1150                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1151                                         pineview_display_hplloff_wm.fifo_size,
1152                                         pixel_size, latency->cursor_hpll_disable);
1153                 reg = I915_READ(DSPFW3);
1154                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1155                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1156                 I915_WRITE(DSPFW3, reg);
1157                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1158
1159                 /* activate cxsr */
1160                 I915_WRITE(DSPFW3,
1161                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1162                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1163         } else {
1164                 pineview_disable_cxsr(dev);
1165                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1166         }
1167 }
1168
1169 static bool g4x_compute_wm0(struct drm_device *dev,
1170                             int plane,
1171                             const struct intel_watermark_params *display,
1172                             int display_latency_ns,
1173                             const struct intel_watermark_params *cursor,
1174                             int cursor_latency_ns,
1175                             int *plane_wm,
1176                             int *cursor_wm)
1177 {
1178         struct drm_crtc *crtc;
1179         const struct drm_display_mode *adjusted_mode;
1180         int htotal, hdisplay, clock, pixel_size;
1181         int line_time_us, line_count;
1182         int entries, tlb_miss;
1183
1184         crtc = intel_get_crtc_for_plane(dev, plane);
1185         if (!intel_crtc_active(crtc)) {
1186                 *cursor_wm = cursor->guard_size;
1187                 *plane_wm = display->guard_size;
1188                 return false;
1189         }
1190
1191         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1192         clock = adjusted_mode->crtc_clock;
1193         htotal = adjusted_mode->htotal;
1194         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1195         pixel_size = crtc->fb->bits_per_pixel / 8;
1196
1197         /* Use the small buffer method to calculate plane watermark */
1198         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1199         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1200         if (tlb_miss > 0)
1201                 entries += tlb_miss;
1202         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1203         *plane_wm = entries + display->guard_size;
1204         if (*plane_wm > (int)display->max_wm)
1205                 *plane_wm = display->max_wm;
1206
1207         /* Use the large buffer method to calculate cursor watermark */
1208         line_time_us = ((htotal * 1000) / clock);
1209         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1210         entries = line_count * 64 * pixel_size;
1211         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1212         if (tlb_miss > 0)
1213                 entries += tlb_miss;
1214         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1215         *cursor_wm = entries + cursor->guard_size;
1216         if (*cursor_wm > (int)cursor->max_wm)
1217                 *cursor_wm = (int)cursor->max_wm;
1218
1219         return true;
1220 }
1221
1222 /*
1223  * Check the wm result.
1224  *
1225  * If any calculated watermark values is larger than the maximum value that
1226  * can be programmed into the associated watermark register, that watermark
1227  * must be disabled.
1228  */
1229 static bool g4x_check_srwm(struct drm_device *dev,
1230                            int display_wm, int cursor_wm,
1231                            const struct intel_watermark_params *display,
1232                            const struct intel_watermark_params *cursor)
1233 {
1234         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1235                       display_wm, cursor_wm);
1236
1237         if (display_wm > display->max_wm) {
1238                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1239                               display_wm, display->max_wm);
1240                 return false;
1241         }
1242
1243         if (cursor_wm > cursor->max_wm) {
1244                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1245                               cursor_wm, cursor->max_wm);
1246                 return false;
1247         }
1248
1249         if (!(display_wm || cursor_wm)) {
1250                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1251                 return false;
1252         }
1253
1254         return true;
1255 }
1256
1257 static bool g4x_compute_srwm(struct drm_device *dev,
1258                              int plane,
1259                              int latency_ns,
1260                              const struct intel_watermark_params *display,
1261                              const struct intel_watermark_params *cursor,
1262                              int *display_wm, int *cursor_wm)
1263 {
1264         struct drm_crtc *crtc;
1265         const struct drm_display_mode *adjusted_mode;
1266         int hdisplay, htotal, pixel_size, clock;
1267         unsigned long line_time_us;
1268         int line_count, line_size;
1269         int small, large;
1270         int entries;
1271
1272         if (!latency_ns) {
1273                 *display_wm = *cursor_wm = 0;
1274                 return false;
1275         }
1276
1277         crtc = intel_get_crtc_for_plane(dev, plane);
1278         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1279         clock = adjusted_mode->crtc_clock;
1280         htotal = adjusted_mode->htotal;
1281         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1282         pixel_size = crtc->fb->bits_per_pixel / 8;
1283
1284         line_time_us = (htotal * 1000) / clock;
1285         line_count = (latency_ns / line_time_us + 1000) / 1000;
1286         line_size = hdisplay * pixel_size;
1287
1288         /* Use the minimum of the small and large buffer method for primary */
1289         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1290         large = line_count * line_size;
1291
1292         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1293         *display_wm = entries + display->guard_size;
1294
1295         /* calculate the self-refresh watermark for display cursor */
1296         entries = line_count * pixel_size * 64;
1297         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1298         *cursor_wm = entries + cursor->guard_size;
1299
1300         return g4x_check_srwm(dev,
1301                               *display_wm, *cursor_wm,
1302                               display, cursor);
1303 }
1304
1305 static bool vlv_compute_drain_latency(struct drm_device *dev,
1306                                      int plane,
1307                                      int *plane_prec_mult,
1308                                      int *plane_dl,
1309                                      int *cursor_prec_mult,
1310                                      int *cursor_dl)
1311 {
1312         struct drm_crtc *crtc;
1313         int clock, pixel_size;
1314         int entries;
1315
1316         crtc = intel_get_crtc_for_plane(dev, plane);
1317         if (!intel_crtc_active(crtc))
1318                 return false;
1319
1320         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1321         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1322
1323         entries = (clock / 1000) * pixel_size;
1324         *plane_prec_mult = (entries > 256) ?
1325                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1326         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1327                                                      pixel_size);
1328
1329         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1330         *cursor_prec_mult = (entries > 256) ?
1331                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1332         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1333
1334         return true;
1335 }
1336
1337 /*
1338  * Update drain latency registers of memory arbiter
1339  *
1340  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1341  * to be programmed. Each plane has a drain latency multiplier and a drain
1342  * latency value.
1343  */
1344
1345 static void vlv_update_drain_latency(struct drm_device *dev)
1346 {
1347         struct drm_i915_private *dev_priv = dev->dev_private;
1348         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1349         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1350         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1351                                                         either 16 or 32 */
1352
1353         /* For plane A, Cursor A */
1354         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1355                                       &cursor_prec_mult, &cursora_dl)) {
1356                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1357                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1358                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1360
1361                 I915_WRITE(VLV_DDL1, cursora_prec |
1362                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1363                                 planea_prec | planea_dl);
1364         }
1365
1366         /* For plane B, Cursor B */
1367         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1368                                       &cursor_prec_mult, &cursorb_dl)) {
1369                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1370                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1371                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1372                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1373
1374                 I915_WRITE(VLV_DDL2, cursorb_prec |
1375                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1376                                 planeb_prec | planeb_dl);
1377         }
1378 }
1379
1380 #define single_plane_enabled(mask) is_power_of_2(mask)
1381
1382 static void valleyview_update_wm(struct drm_crtc *crtc)
1383 {
1384         struct drm_device *dev = crtc->dev;
1385         static const int sr_latency_ns = 12000;
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1388         int plane_sr, cursor_sr;
1389         int ignore_plane_sr, ignore_cursor_sr;
1390         unsigned int enabled = 0;
1391
1392         vlv_update_drain_latency(dev);
1393
1394         if (g4x_compute_wm0(dev, PIPE_A,
1395                             &valleyview_wm_info, latency_ns,
1396                             &valleyview_cursor_wm_info, latency_ns,
1397                             &planea_wm, &cursora_wm))
1398                 enabled |= 1 << PIPE_A;
1399
1400         if (g4x_compute_wm0(dev, PIPE_B,
1401                             &valleyview_wm_info, latency_ns,
1402                             &valleyview_cursor_wm_info, latency_ns,
1403                             &planeb_wm, &cursorb_wm))
1404                 enabled |= 1 << PIPE_B;
1405
1406         if (single_plane_enabled(enabled) &&
1407             g4x_compute_srwm(dev, ffs(enabled) - 1,
1408                              sr_latency_ns,
1409                              &valleyview_wm_info,
1410                              &valleyview_cursor_wm_info,
1411                              &plane_sr, &ignore_cursor_sr) &&
1412             g4x_compute_srwm(dev, ffs(enabled) - 1,
1413                              2*sr_latency_ns,
1414                              &valleyview_wm_info,
1415                              &valleyview_cursor_wm_info,
1416                              &ignore_plane_sr, &cursor_sr)) {
1417                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1418         } else {
1419                 I915_WRITE(FW_BLC_SELF_VLV,
1420                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1421                 plane_sr = cursor_sr = 0;
1422         }
1423
1424         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1425                       planea_wm, cursora_wm,
1426                       planeb_wm, cursorb_wm,
1427                       plane_sr, cursor_sr);
1428
1429         I915_WRITE(DSPFW1,
1430                    (plane_sr << DSPFW_SR_SHIFT) |
1431                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1432                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1433                    planea_wm);
1434         I915_WRITE(DSPFW2,
1435                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1436                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1437         I915_WRITE(DSPFW3,
1438                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1439                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1440 }
1441
1442 static void g4x_update_wm(struct drm_crtc *crtc)
1443 {
1444         struct drm_device *dev = crtc->dev;
1445         static const int sr_latency_ns = 12000;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1448         int plane_sr, cursor_sr;
1449         unsigned int enabled = 0;
1450
1451         if (g4x_compute_wm0(dev, PIPE_A,
1452                             &g4x_wm_info, latency_ns,
1453                             &g4x_cursor_wm_info, latency_ns,
1454                             &planea_wm, &cursora_wm))
1455                 enabled |= 1 << PIPE_A;
1456
1457         if (g4x_compute_wm0(dev, PIPE_B,
1458                             &g4x_wm_info, latency_ns,
1459                             &g4x_cursor_wm_info, latency_ns,
1460                             &planeb_wm, &cursorb_wm))
1461                 enabled |= 1 << PIPE_B;
1462
1463         if (single_plane_enabled(enabled) &&
1464             g4x_compute_srwm(dev, ffs(enabled) - 1,
1465                              sr_latency_ns,
1466                              &g4x_wm_info,
1467                              &g4x_cursor_wm_info,
1468                              &plane_sr, &cursor_sr)) {
1469                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1470         } else {
1471                 I915_WRITE(FW_BLC_SELF,
1472                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1473                 plane_sr = cursor_sr = 0;
1474         }
1475
1476         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1477                       planea_wm, cursora_wm,
1478                       planeb_wm, cursorb_wm,
1479                       plane_sr, cursor_sr);
1480
1481         I915_WRITE(DSPFW1,
1482                    (plane_sr << DSPFW_SR_SHIFT) |
1483                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1484                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1485                    planea_wm);
1486         I915_WRITE(DSPFW2,
1487                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1488                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1489         /* HPLL off in SR has some issues on G4x... disable it */
1490         I915_WRITE(DSPFW3,
1491                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1492                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1493 }
1494
1495 static void i965_update_wm(struct drm_crtc *unused_crtc)
1496 {
1497         struct drm_device *dev = unused_crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         struct drm_crtc *crtc;
1500         int srwm = 1;
1501         int cursor_sr = 16;
1502
1503         /* Calc sr entries for one plane configs */
1504         crtc = single_enabled_crtc(dev);
1505         if (crtc) {
1506                 /* self-refresh has much higher latency */
1507                 static const int sr_latency_ns = 12000;
1508                 const struct drm_display_mode *adjusted_mode =
1509                         &to_intel_crtc(crtc)->config.adjusted_mode;
1510                 int clock = adjusted_mode->crtc_clock;
1511                 int htotal = adjusted_mode->htotal;
1512                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1513                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1514                 unsigned long line_time_us;
1515                 int entries;
1516
1517                 line_time_us = ((htotal * 1000) / clock);
1518
1519                 /* Use ns/us then divide to preserve precision */
1520                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521                         pixel_size * hdisplay;
1522                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1523                 srwm = I965_FIFO_SIZE - entries;
1524                 if (srwm < 0)
1525                         srwm = 1;
1526                 srwm &= 0x1ff;
1527                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1528                               entries, srwm);
1529
1530                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1531                         pixel_size * 64;
1532                 entries = DIV_ROUND_UP(entries,
1533                                           i965_cursor_wm_info.cacheline_size);
1534                 cursor_sr = i965_cursor_wm_info.fifo_size -
1535                         (entries + i965_cursor_wm_info.guard_size);
1536
1537                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1538                         cursor_sr = i965_cursor_wm_info.max_wm;
1539
1540                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1541                               "cursor %d\n", srwm, cursor_sr);
1542
1543                 if (IS_CRESTLINE(dev))
1544                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1545         } else {
1546                 /* Turn off self refresh if both pipes are enabled */
1547                 if (IS_CRESTLINE(dev))
1548                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1549                                    & ~FW_BLC_SELF_EN);
1550         }
1551
1552         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1553                       srwm);
1554
1555         /* 965 has limitations... */
1556         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1557                    (8 << 16) | (8 << 8) | (8 << 0));
1558         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1559         /* update cursor SR watermark */
1560         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1561 }
1562
1563 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1564 {
1565         struct drm_device *dev = unused_crtc->dev;
1566         struct drm_i915_private *dev_priv = dev->dev_private;
1567         const struct intel_watermark_params *wm_info;
1568         uint32_t fwater_lo;
1569         uint32_t fwater_hi;
1570         int cwm, srwm = 1;
1571         int fifo_size;
1572         int planea_wm, planeb_wm;
1573         struct drm_crtc *crtc, *enabled = NULL;
1574
1575         if (IS_I945GM(dev))
1576                 wm_info = &i945_wm_info;
1577         else if (!IS_GEN2(dev))
1578                 wm_info = &i915_wm_info;
1579         else
1580                 wm_info = &i855_wm_info;
1581
1582         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1583         crtc = intel_get_crtc_for_plane(dev, 0);
1584         if (intel_crtc_active(crtc)) {
1585                 const struct drm_display_mode *adjusted_mode;
1586                 int cpp = crtc->fb->bits_per_pixel / 8;
1587                 if (IS_GEN2(dev))
1588                         cpp = 4;
1589
1590                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1591                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1592                                                wm_info, fifo_size, cpp,
1593                                                latency_ns);
1594                 enabled = crtc;
1595         } else
1596                 planea_wm = fifo_size - wm_info->guard_size;
1597
1598         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1599         crtc = intel_get_crtc_for_plane(dev, 1);
1600         if (intel_crtc_active(crtc)) {
1601                 const struct drm_display_mode *adjusted_mode;
1602                 int cpp = crtc->fb->bits_per_pixel / 8;
1603                 if (IS_GEN2(dev))
1604                         cpp = 4;
1605
1606                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1607                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1608                                                wm_info, fifo_size, cpp,
1609                                                latency_ns);
1610                 if (enabled == NULL)
1611                         enabled = crtc;
1612                 else
1613                         enabled = NULL;
1614         } else
1615                 planeb_wm = fifo_size - wm_info->guard_size;
1616
1617         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1618
1619         /*
1620          * Overlay gets an aggressive default since video jitter is bad.
1621          */
1622         cwm = 2;
1623
1624         /* Play safe and disable self-refresh before adjusting watermarks. */
1625         if (IS_I945G(dev) || IS_I945GM(dev))
1626                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1627         else if (IS_I915GM(dev))
1628                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1629
1630         /* Calc sr entries for one plane configs */
1631         if (HAS_FW_BLC(dev) && enabled) {
1632                 /* self-refresh has much higher latency */
1633                 static const int sr_latency_ns = 6000;
1634                 const struct drm_display_mode *adjusted_mode =
1635                         &to_intel_crtc(enabled)->config.adjusted_mode;
1636                 int clock = adjusted_mode->crtc_clock;
1637                 int htotal = adjusted_mode->htotal;
1638                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1639                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1640                 unsigned long line_time_us;
1641                 int entries;
1642
1643                 line_time_us = (htotal * 1000) / clock;
1644
1645                 /* Use ns/us then divide to preserve precision */
1646                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1647                         pixel_size * hdisplay;
1648                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1649                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1650                 srwm = wm_info->fifo_size - entries;
1651                 if (srwm < 0)
1652                         srwm = 1;
1653
1654                 if (IS_I945G(dev) || IS_I945GM(dev))
1655                         I915_WRITE(FW_BLC_SELF,
1656                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1657                 else if (IS_I915GM(dev))
1658                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1659         }
1660
1661         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1662                       planea_wm, planeb_wm, cwm, srwm);
1663
1664         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1665         fwater_hi = (cwm & 0x1f);
1666
1667         /* Set request length to 8 cachelines per fetch */
1668         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1669         fwater_hi = fwater_hi | (1 << 8);
1670
1671         I915_WRITE(FW_BLC, fwater_lo);
1672         I915_WRITE(FW_BLC2, fwater_hi);
1673
1674         if (HAS_FW_BLC(dev)) {
1675                 if (enabled) {
1676                         if (IS_I945G(dev) || IS_I945GM(dev))
1677                                 I915_WRITE(FW_BLC_SELF,
1678                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1679                         else if (IS_I915GM(dev))
1680                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1681                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1682                 } else
1683                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1684         }
1685 }
1686
1687 static void i830_update_wm(struct drm_crtc *unused_crtc)
1688 {
1689         struct drm_device *dev = unused_crtc->dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         struct drm_crtc *crtc;
1692         const struct drm_display_mode *adjusted_mode;
1693         uint32_t fwater_lo;
1694         int planea_wm;
1695
1696         crtc = single_enabled_crtc(dev);
1697         if (crtc == NULL)
1698                 return;
1699
1700         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1701         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1702                                        &i830_wm_info,
1703                                        dev_priv->display.get_fifo_size(dev, 0),
1704                                        4, latency_ns);
1705         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1706         fwater_lo |= (3<<8) | planea_wm;
1707
1708         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1709
1710         I915_WRITE(FW_BLC, fwater_lo);
1711 }
1712
1713 /*
1714  * Check the wm result.
1715  *
1716  * If any calculated watermark values is larger than the maximum value that
1717  * can be programmed into the associated watermark register, that watermark
1718  * must be disabled.
1719  */
1720 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1721                                 int fbc_wm, int display_wm, int cursor_wm,
1722                                 const struct intel_watermark_params *display,
1723                                 const struct intel_watermark_params *cursor)
1724 {
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1728                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1729
1730         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1731                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1732                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1733
1734                 /* fbc has it's own way to disable FBC WM */
1735                 I915_WRITE(DISP_ARB_CTL,
1736                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1737                 return false;
1738         } else if (INTEL_INFO(dev)->gen >= 6) {
1739                 /* enable FBC WM (except on ILK, where it must remain off) */
1740                 I915_WRITE(DISP_ARB_CTL,
1741                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1742         }
1743
1744         if (display_wm > display->max_wm) {
1745                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1746                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1747                 return false;
1748         }
1749
1750         if (cursor_wm > cursor->max_wm) {
1751                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1752                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1753                 return false;
1754         }
1755
1756         if (!(fbc_wm || display_wm || cursor_wm)) {
1757                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1758                 return false;
1759         }
1760
1761         return true;
1762 }
1763
1764 /*
1765  * Compute watermark values of WM[1-3],
1766  */
1767 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1768                                   int latency_ns,
1769                                   const struct intel_watermark_params *display,
1770                                   const struct intel_watermark_params *cursor,
1771                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1772 {
1773         struct drm_crtc *crtc;
1774         const struct drm_display_mode *adjusted_mode;
1775         unsigned long line_time_us;
1776         int hdisplay, htotal, pixel_size, clock;
1777         int line_count, line_size;
1778         int small, large;
1779         int entries;
1780
1781         if (!latency_ns) {
1782                 *fbc_wm = *display_wm = *cursor_wm = 0;
1783                 return false;
1784         }
1785
1786         crtc = intel_get_crtc_for_plane(dev, plane);
1787         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1788         clock = adjusted_mode->crtc_clock;
1789         htotal = adjusted_mode->htotal;
1790         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1791         pixel_size = crtc->fb->bits_per_pixel / 8;
1792
1793         line_time_us = (htotal * 1000) / clock;
1794         line_count = (latency_ns / line_time_us + 1000) / 1000;
1795         line_size = hdisplay * pixel_size;
1796
1797         /* Use the minimum of the small and large buffer method for primary */
1798         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1799         large = line_count * line_size;
1800
1801         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1802         *display_wm = entries + display->guard_size;
1803
1804         /*
1805          * Spec says:
1806          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1807          */
1808         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1809
1810         /* calculate the self-refresh watermark for display cursor */
1811         entries = line_count * pixel_size * 64;
1812         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1813         *cursor_wm = entries + cursor->guard_size;
1814
1815         return ironlake_check_srwm(dev, level,
1816                                    *fbc_wm, *display_wm, *cursor_wm,
1817                                    display, cursor);
1818 }
1819
1820 static void ironlake_update_wm(struct drm_crtc *crtc)
1821 {
1822         struct drm_device *dev = crtc->dev;
1823         struct drm_i915_private *dev_priv = dev->dev_private;
1824         int fbc_wm, plane_wm, cursor_wm;
1825         unsigned int enabled;
1826
1827         enabled = 0;
1828         if (g4x_compute_wm0(dev, PIPE_A,
1829                             &ironlake_display_wm_info,
1830                             dev_priv->wm.pri_latency[0] * 100,
1831                             &ironlake_cursor_wm_info,
1832                             dev_priv->wm.cur_latency[0] * 100,
1833                             &plane_wm, &cursor_wm)) {
1834                 I915_WRITE(WM0_PIPEA_ILK,
1835                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1836                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1837                               " plane %d, " "cursor: %d\n",
1838                               plane_wm, cursor_wm);
1839                 enabled |= 1 << PIPE_A;
1840         }
1841
1842         if (g4x_compute_wm0(dev, PIPE_B,
1843                             &ironlake_display_wm_info,
1844                             dev_priv->wm.pri_latency[0] * 100,
1845                             &ironlake_cursor_wm_info,
1846                             dev_priv->wm.cur_latency[0] * 100,
1847                             &plane_wm, &cursor_wm)) {
1848                 I915_WRITE(WM0_PIPEB_ILK,
1849                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1850                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1851                               " plane %d, cursor: %d\n",
1852                               plane_wm, cursor_wm);
1853                 enabled |= 1 << PIPE_B;
1854         }
1855
1856         /*
1857          * Calculate and update the self-refresh watermark only when one
1858          * display plane is used.
1859          */
1860         I915_WRITE(WM3_LP_ILK, 0);
1861         I915_WRITE(WM2_LP_ILK, 0);
1862         I915_WRITE(WM1_LP_ILK, 0);
1863
1864         if (!single_plane_enabled(enabled))
1865                 return;
1866         enabled = ffs(enabled) - 1;
1867
1868         /* WM1 */
1869         if (!ironlake_compute_srwm(dev, 1, enabled,
1870                                    dev_priv->wm.pri_latency[1] * 500,
1871                                    &ironlake_display_srwm_info,
1872                                    &ironlake_cursor_srwm_info,
1873                                    &fbc_wm, &plane_wm, &cursor_wm))
1874                 return;
1875
1876         I915_WRITE(WM1_LP_ILK,
1877                    WM1_LP_SR_EN |
1878                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1879                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1880                    (plane_wm << WM1_LP_SR_SHIFT) |
1881                    cursor_wm);
1882
1883         /* WM2 */
1884         if (!ironlake_compute_srwm(dev, 2, enabled,
1885                                    dev_priv->wm.pri_latency[2] * 500,
1886                                    &ironlake_display_srwm_info,
1887                                    &ironlake_cursor_srwm_info,
1888                                    &fbc_wm, &plane_wm, &cursor_wm))
1889                 return;
1890
1891         I915_WRITE(WM2_LP_ILK,
1892                    WM2_LP_EN |
1893                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1894                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1895                    (plane_wm << WM1_LP_SR_SHIFT) |
1896                    cursor_wm);
1897
1898         /*
1899          * WM3 is unsupported on ILK, probably because we don't have latency
1900          * data for that power state
1901          */
1902 }
1903
1904 static void sandybridge_update_wm(struct drm_crtc *crtc)
1905 {
1906         struct drm_device *dev = crtc->dev;
1907         struct drm_i915_private *dev_priv = dev->dev_private;
1908         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1909         u32 val;
1910         int fbc_wm, plane_wm, cursor_wm;
1911         unsigned int enabled;
1912
1913         enabled = 0;
1914         if (g4x_compute_wm0(dev, PIPE_A,
1915                             &sandybridge_display_wm_info, latency,
1916                             &sandybridge_cursor_wm_info, latency,
1917                             &plane_wm, &cursor_wm)) {
1918                 val = I915_READ(WM0_PIPEA_ILK);
1919                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1920                 I915_WRITE(WM0_PIPEA_ILK, val |
1921                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1922                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1923                               " plane %d, " "cursor: %d\n",
1924                               plane_wm, cursor_wm);
1925                 enabled |= 1 << PIPE_A;
1926         }
1927
1928         if (g4x_compute_wm0(dev, PIPE_B,
1929                             &sandybridge_display_wm_info, latency,
1930                             &sandybridge_cursor_wm_info, latency,
1931                             &plane_wm, &cursor_wm)) {
1932                 val = I915_READ(WM0_PIPEB_ILK);
1933                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1934                 I915_WRITE(WM0_PIPEB_ILK, val |
1935                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1936                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1937                               " plane %d, cursor: %d\n",
1938                               plane_wm, cursor_wm);
1939                 enabled |= 1 << PIPE_B;
1940         }
1941
1942         /*
1943          * Calculate and update the self-refresh watermark only when one
1944          * display plane is used.
1945          *
1946          * SNB support 3 levels of watermark.
1947          *
1948          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1949          * and disabled in the descending order
1950          *
1951          */
1952         I915_WRITE(WM3_LP_ILK, 0);
1953         I915_WRITE(WM2_LP_ILK, 0);
1954         I915_WRITE(WM1_LP_ILK, 0);
1955
1956         if (!single_plane_enabled(enabled) ||
1957             dev_priv->sprite_scaling_enabled)
1958                 return;
1959         enabled = ffs(enabled) - 1;
1960
1961         /* WM1 */
1962         if (!ironlake_compute_srwm(dev, 1, enabled,
1963                                    dev_priv->wm.pri_latency[1] * 500,
1964                                    &sandybridge_display_srwm_info,
1965                                    &sandybridge_cursor_srwm_info,
1966                                    &fbc_wm, &plane_wm, &cursor_wm))
1967                 return;
1968
1969         I915_WRITE(WM1_LP_ILK,
1970                    WM1_LP_SR_EN |
1971                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1972                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1973                    (plane_wm << WM1_LP_SR_SHIFT) |
1974                    cursor_wm);
1975
1976         /* WM2 */
1977         if (!ironlake_compute_srwm(dev, 2, enabled,
1978                                    dev_priv->wm.pri_latency[2] * 500,
1979                                    &sandybridge_display_srwm_info,
1980                                    &sandybridge_cursor_srwm_info,
1981                                    &fbc_wm, &plane_wm, &cursor_wm))
1982                 return;
1983
1984         I915_WRITE(WM2_LP_ILK,
1985                    WM2_LP_EN |
1986                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1987                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1988                    (plane_wm << WM1_LP_SR_SHIFT) |
1989                    cursor_wm);
1990
1991         /* WM3 */
1992         if (!ironlake_compute_srwm(dev, 3, enabled,
1993                                    dev_priv->wm.pri_latency[3] * 500,
1994                                    &sandybridge_display_srwm_info,
1995                                    &sandybridge_cursor_srwm_info,
1996                                    &fbc_wm, &plane_wm, &cursor_wm))
1997                 return;
1998
1999         I915_WRITE(WM3_LP_ILK,
2000                    WM3_LP_EN |
2001                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2002                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2003                    (plane_wm << WM1_LP_SR_SHIFT) |
2004                    cursor_wm);
2005 }
2006
2007 static void ivybridge_update_wm(struct drm_crtc *crtc)
2008 {
2009         struct drm_device *dev = crtc->dev;
2010         struct drm_i915_private *dev_priv = dev->dev_private;
2011         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
2012         u32 val;
2013         int fbc_wm, plane_wm, cursor_wm;
2014         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2015         unsigned int enabled;
2016
2017         enabled = 0;
2018         if (g4x_compute_wm0(dev, PIPE_A,
2019                             &sandybridge_display_wm_info, latency,
2020                             &sandybridge_cursor_wm_info, latency,
2021                             &plane_wm, &cursor_wm)) {
2022                 val = I915_READ(WM0_PIPEA_ILK);
2023                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2024                 I915_WRITE(WM0_PIPEA_ILK, val |
2025                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2026                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2027                               " plane %d, " "cursor: %d\n",
2028                               plane_wm, cursor_wm);
2029                 enabled |= 1 << PIPE_A;
2030         }
2031
2032         if (g4x_compute_wm0(dev, PIPE_B,
2033                             &sandybridge_display_wm_info, latency,
2034                             &sandybridge_cursor_wm_info, latency,
2035                             &plane_wm, &cursor_wm)) {
2036                 val = I915_READ(WM0_PIPEB_ILK);
2037                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2038                 I915_WRITE(WM0_PIPEB_ILK, val |
2039                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2040                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2041                               " plane %d, cursor: %d\n",
2042                               plane_wm, cursor_wm);
2043                 enabled |= 1 << PIPE_B;
2044         }
2045
2046         if (g4x_compute_wm0(dev, PIPE_C,
2047                             &sandybridge_display_wm_info, latency,
2048                             &sandybridge_cursor_wm_info, latency,
2049                             &plane_wm, &cursor_wm)) {
2050                 val = I915_READ(WM0_PIPEC_IVB);
2051                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2052                 I915_WRITE(WM0_PIPEC_IVB, val |
2053                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2054                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2055                               " plane %d, cursor: %d\n",
2056                               plane_wm, cursor_wm);
2057                 enabled |= 1 << PIPE_C;
2058         }
2059
2060         /*
2061          * Calculate and update the self-refresh watermark only when one
2062          * display plane is used.
2063          *
2064          * SNB support 3 levels of watermark.
2065          *
2066          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2067          * and disabled in the descending order
2068          *
2069          */
2070         I915_WRITE(WM3_LP_ILK, 0);
2071         I915_WRITE(WM2_LP_ILK, 0);
2072         I915_WRITE(WM1_LP_ILK, 0);
2073
2074         if (!single_plane_enabled(enabled) ||
2075             dev_priv->sprite_scaling_enabled)
2076                 return;
2077         enabled = ffs(enabled) - 1;
2078
2079         /* WM1 */
2080         if (!ironlake_compute_srwm(dev, 1, enabled,
2081                                    dev_priv->wm.pri_latency[1] * 500,
2082                                    &sandybridge_display_srwm_info,
2083                                    &sandybridge_cursor_srwm_info,
2084                                    &fbc_wm, &plane_wm, &cursor_wm))
2085                 return;
2086
2087         I915_WRITE(WM1_LP_ILK,
2088                    WM1_LP_SR_EN |
2089                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2090                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2091                    (plane_wm << WM1_LP_SR_SHIFT) |
2092                    cursor_wm);
2093
2094         /* WM2 */
2095         if (!ironlake_compute_srwm(dev, 2, enabled,
2096                                    dev_priv->wm.pri_latency[2] * 500,
2097                                    &sandybridge_display_srwm_info,
2098                                    &sandybridge_cursor_srwm_info,
2099                                    &fbc_wm, &plane_wm, &cursor_wm))
2100                 return;
2101
2102         I915_WRITE(WM2_LP_ILK,
2103                    WM2_LP_EN |
2104                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2105                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2106                    (plane_wm << WM1_LP_SR_SHIFT) |
2107                    cursor_wm);
2108
2109         /* WM3, note we have to correct the cursor latency */
2110         if (!ironlake_compute_srwm(dev, 3, enabled,
2111                                    dev_priv->wm.pri_latency[3] * 500,
2112                                    &sandybridge_display_srwm_info,
2113                                    &sandybridge_cursor_srwm_info,
2114                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2115             !ironlake_compute_srwm(dev, 3, enabled,
2116                                    dev_priv->wm.cur_latency[3] * 500,
2117                                    &sandybridge_display_srwm_info,
2118                                    &sandybridge_cursor_srwm_info,
2119                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2120                 return;
2121
2122         I915_WRITE(WM3_LP_ILK,
2123                    WM3_LP_EN |
2124                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2125                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2126                    (plane_wm << WM1_LP_SR_SHIFT) |
2127                    cursor_wm);
2128 }
2129
2130 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2131                                     struct drm_crtc *crtc)
2132 {
2133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134         uint32_t pixel_rate;
2135
2136         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2137
2138         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2139          * adjust the pixel_rate here. */
2140
2141         if (intel_crtc->config.pch_pfit.enabled) {
2142                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2143                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2144
2145                 pipe_w = intel_crtc->config.pipe_src_w;
2146                 pipe_h = intel_crtc->config.pipe_src_h;
2147                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2148                 pfit_h = pfit_size & 0xFFFF;
2149                 if (pipe_w < pfit_w)
2150                         pipe_w = pfit_w;
2151                 if (pipe_h < pfit_h)
2152                         pipe_h = pfit_h;
2153
2154                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2155                                      pfit_w * pfit_h);
2156         }
2157
2158         return pixel_rate;
2159 }
2160
2161 /* latency must be in 0.1us units. */
2162 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2163                                uint32_t latency)
2164 {
2165         uint64_t ret;
2166
2167         if (WARN(latency == 0, "Latency value missing\n"))
2168                 return UINT_MAX;
2169
2170         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2171         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2172
2173         return ret;
2174 }
2175
2176 /* latency must be in 0.1us units. */
2177 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2178                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2179                                uint32_t latency)
2180 {
2181         uint32_t ret;
2182
2183         if (WARN(latency == 0, "Latency value missing\n"))
2184                 return UINT_MAX;
2185
2186         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2187         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2188         ret = DIV_ROUND_UP(ret, 64) + 2;
2189         return ret;
2190 }
2191
2192 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2193                            uint8_t bytes_per_pixel)
2194 {
2195         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2196 }
2197
2198 struct hsw_pipe_wm_parameters {
2199         bool active;
2200         uint32_t pipe_htotal;
2201         uint32_t pixel_rate;
2202         struct intel_plane_wm_parameters pri;
2203         struct intel_plane_wm_parameters spr;
2204         struct intel_plane_wm_parameters cur;
2205 };
2206
2207 struct hsw_wm_maximums {
2208         uint16_t pri;
2209         uint16_t spr;
2210         uint16_t cur;
2211         uint16_t fbc;
2212 };
2213
2214 /* used in computing the new watermarks state */
2215 struct intel_wm_config {
2216         unsigned int num_pipes_active;
2217         bool sprites_enabled;
2218         bool sprites_scaled;
2219 };
2220
2221 /*
2222  * For both WM_PIPE and WM_LP.
2223  * mem_value must be in 0.1us units.
2224  */
2225 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2226                                    uint32_t mem_value,
2227                                    bool is_lp)
2228 {
2229         uint32_t method1, method2;
2230
2231         if (!params->active || !params->pri.enabled)
2232                 return 0;
2233
2234         method1 = ilk_wm_method1(params->pixel_rate,
2235                                  params->pri.bytes_per_pixel,
2236                                  mem_value);
2237
2238         if (!is_lp)
2239                 return method1;
2240
2241         method2 = ilk_wm_method2(params->pixel_rate,
2242                                  params->pipe_htotal,
2243                                  params->pri.horiz_pixels,
2244                                  params->pri.bytes_per_pixel,
2245                                  mem_value);
2246
2247         return min(method1, method2);
2248 }
2249
2250 /*
2251  * For both WM_PIPE and WM_LP.
2252  * mem_value must be in 0.1us units.
2253  */
2254 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2255                                    uint32_t mem_value)
2256 {
2257         uint32_t method1, method2;
2258
2259         if (!params->active || !params->spr.enabled)
2260                 return 0;
2261
2262         method1 = ilk_wm_method1(params->pixel_rate,
2263                                  params->spr.bytes_per_pixel,
2264                                  mem_value);
2265         method2 = ilk_wm_method2(params->pixel_rate,
2266                                  params->pipe_htotal,
2267                                  params->spr.horiz_pixels,
2268                                  params->spr.bytes_per_pixel,
2269                                  mem_value);
2270         return min(method1, method2);
2271 }
2272
2273 /*
2274  * For both WM_PIPE and WM_LP.
2275  * mem_value must be in 0.1us units.
2276  */
2277 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2278                                    uint32_t mem_value)
2279 {
2280         if (!params->active || !params->cur.enabled)
2281                 return 0;
2282
2283         return ilk_wm_method2(params->pixel_rate,
2284                               params->pipe_htotal,
2285                               params->cur.horiz_pixels,
2286                               params->cur.bytes_per_pixel,
2287                               mem_value);
2288 }
2289
2290 /* Only for WM_LP. */
2291 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2292                                    uint32_t pri_val)
2293 {
2294         if (!params->active || !params->pri.enabled)
2295                 return 0;
2296
2297         return ilk_wm_fbc(pri_val,
2298                           params->pri.horiz_pixels,
2299                           params->pri.bytes_per_pixel);
2300 }
2301
2302 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2303 {
2304         if (INTEL_INFO(dev)->gen >= 7)
2305                 return 768;
2306         else
2307                 return 512;
2308 }
2309
2310 /* Calculate the maximum primary/sprite plane watermark */
2311 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2312                                      int level,
2313                                      const struct intel_wm_config *config,
2314                                      enum intel_ddb_partitioning ddb_partitioning,
2315                                      bool is_sprite)
2316 {
2317         unsigned int fifo_size = ilk_display_fifo_size(dev);
2318         unsigned int max;
2319
2320         /* if sprites aren't enabled, sprites get nothing */
2321         if (is_sprite && !config->sprites_enabled)
2322                 return 0;
2323
2324         /* HSW allows LP1+ watermarks even with multiple pipes */
2325         if (level == 0 || config->num_pipes_active > 1) {
2326                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2327
2328                 /*
2329                  * For some reason the non self refresh
2330                  * FIFO size is only half of the self
2331                  * refresh FIFO size on ILK/SNB.
2332                  */
2333                 if (INTEL_INFO(dev)->gen <= 6)
2334                         fifo_size /= 2;
2335         }
2336
2337         if (config->sprites_enabled) {
2338                 /* level 0 is always calculated with 1:1 split */
2339                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2340                         if (is_sprite)
2341                                 fifo_size *= 5;
2342                         fifo_size /= 6;
2343                 } else {
2344                         fifo_size /= 2;
2345                 }
2346         }
2347
2348         /* clamp to max that the registers can hold */
2349         if (INTEL_INFO(dev)->gen >= 7)
2350                 /* IVB/HSW primary/sprite plane watermarks */
2351                 max = level == 0 ? 127 : 1023;
2352         else if (!is_sprite)
2353                 /* ILK/SNB primary plane watermarks */
2354                 max = level == 0 ? 127 : 511;
2355         else
2356                 /* ILK/SNB sprite plane watermarks */
2357                 max = level == 0 ? 63 : 255;
2358
2359         return min(fifo_size, max);
2360 }
2361
2362 /* Calculate the maximum cursor plane watermark */
2363 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2364                                       int level,
2365                                       const struct intel_wm_config *config)
2366 {
2367         /* HSW LP1+ watermarks w/ multiple pipes */
2368         if (level > 0 && config->num_pipes_active > 1)
2369                 return 64;
2370
2371         /* otherwise just report max that registers can hold */
2372         if (INTEL_INFO(dev)->gen >= 7)
2373                 return level == 0 ? 63 : 255;
2374         else
2375                 return level == 0 ? 31 : 63;
2376 }
2377
2378 /* Calculate the maximum FBC watermark */
2379 static unsigned int ilk_fbc_wm_max(void)
2380 {
2381         /* max that registers can hold */
2382         return 15;
2383 }
2384
2385 static void ilk_compute_wm_maximums(struct drm_device *dev,
2386                                     int level,
2387                                     const struct intel_wm_config *config,
2388                                     enum intel_ddb_partitioning ddb_partitioning,
2389                                     struct hsw_wm_maximums *max)
2390 {
2391         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2392         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2393         max->cur = ilk_cursor_wm_max(dev, level, config);
2394         max->fbc = ilk_fbc_wm_max();
2395 }
2396
2397 static bool ilk_validate_wm_level(int level,
2398                                   const struct hsw_wm_maximums *max,
2399                                   struct intel_wm_level *result)
2400 {
2401         bool ret;
2402
2403         /* already determined to be invalid? */
2404         if (!result->enable)
2405                 return false;
2406
2407         result->enable = result->pri_val <= max->pri &&
2408                          result->spr_val <= max->spr &&
2409                          result->cur_val <= max->cur;
2410
2411         ret = result->enable;
2412
2413         /*
2414          * HACK until we can pre-compute everything,
2415          * and thus fail gracefully if LP0 watermarks
2416          * are exceeded...
2417          */
2418         if (level == 0 && !result->enable) {
2419                 if (result->pri_val > max->pri)
2420                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2421                                       level, result->pri_val, max->pri);
2422                 if (result->spr_val > max->spr)
2423                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2424                                       level, result->spr_val, max->spr);
2425                 if (result->cur_val > max->cur)
2426                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2427                                       level, result->cur_val, max->cur);
2428
2429                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2430                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2431                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2432                 result->enable = true;
2433         }
2434
2435         return ret;
2436 }
2437
2438 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2439                                  int level,
2440                                  const struct hsw_pipe_wm_parameters *p,
2441                                  struct intel_wm_level *result)
2442 {
2443         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2444         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2445         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2446
2447         /* WM1+ latency values stored in 0.5us units */
2448         if (level > 0) {
2449                 pri_latency *= 5;
2450                 spr_latency *= 5;
2451                 cur_latency *= 5;
2452         }
2453
2454         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2455         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2456         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2457         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2458         result->enable = true;
2459 }
2460
2461 static uint32_t
2462 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2463 {
2464         struct drm_i915_private *dev_priv = dev->dev_private;
2465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2466         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2467         u32 linetime, ips_linetime;
2468
2469         if (!intel_crtc_active(crtc))
2470                 return 0;
2471
2472         /* The WM are computed with base on how long it takes to fill a single
2473          * row at the given clock rate, multiplied by 8.
2474          * */
2475         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2476         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2477                                          intel_ddi_get_cdclk_freq(dev_priv));
2478
2479         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2480                PIPE_WM_LINETIME_TIME(linetime);
2481 }
2482
2483 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2484 {
2485         struct drm_i915_private *dev_priv = dev->dev_private;
2486
2487         if (IS_HASWELL(dev)) {
2488                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2489
2490                 wm[0] = (sskpd >> 56) & 0xFF;
2491                 if (wm[0] == 0)
2492                         wm[0] = sskpd & 0xF;
2493                 wm[1] = (sskpd >> 4) & 0xFF;
2494                 wm[2] = (sskpd >> 12) & 0xFF;
2495                 wm[3] = (sskpd >> 20) & 0x1FF;
2496                 wm[4] = (sskpd >> 32) & 0x1FF;
2497         } else if (INTEL_INFO(dev)->gen >= 6) {
2498                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2499
2500                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2501                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2502                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2503                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2504         } else if (INTEL_INFO(dev)->gen >= 5) {
2505                 uint32_t mltr = I915_READ(MLTR_ILK);
2506
2507                 /* ILK primary LP0 latency is 700 ns */
2508                 wm[0] = 7;
2509                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2510                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2511         }
2512 }
2513
2514 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2515 {
2516         /* ILK sprite LP0 latency is 1300 ns */
2517         if (INTEL_INFO(dev)->gen == 5)
2518                 wm[0] = 13;
2519 }
2520
2521 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2522 {
2523         /* ILK cursor LP0 latency is 1300 ns */
2524         if (INTEL_INFO(dev)->gen == 5)
2525                 wm[0] = 13;
2526
2527         /* WaDoubleCursorLP3Latency:ivb */
2528         if (IS_IVYBRIDGE(dev))
2529                 wm[3] *= 2;
2530 }
2531
2532 static int ilk_wm_max_level(const struct drm_device *dev)
2533 {
2534         /* how many WM levels are we expecting */
2535         if (IS_HASWELL(dev))
2536                 return 4;
2537         else if (INTEL_INFO(dev)->gen >= 6)
2538                 return 3;
2539         else
2540                 return 2;
2541 }
2542
2543 static void intel_print_wm_latency(struct drm_device *dev,
2544                                    const char *name,
2545                                    const uint16_t wm[5])
2546 {
2547         int level, max_level = ilk_wm_max_level(dev);
2548
2549         for (level = 0; level <= max_level; level++) {
2550                 unsigned int latency = wm[level];
2551
2552                 if (latency == 0) {
2553                         DRM_ERROR("%s WM%d latency not provided\n",
2554                                   name, level);
2555                         continue;
2556                 }
2557
2558                 /* WM1+ latency values in 0.5us units */
2559                 if (level > 0)
2560                         latency *= 5;
2561
2562                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2563                               name, level, wm[level],
2564                               latency / 10, latency % 10);
2565         }
2566 }
2567
2568 static void intel_setup_wm_latency(struct drm_device *dev)
2569 {
2570         struct drm_i915_private *dev_priv = dev->dev_private;
2571
2572         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2573
2574         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2575                sizeof(dev_priv->wm.pri_latency));
2576         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2577                sizeof(dev_priv->wm.pri_latency));
2578
2579         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2580         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2581
2582         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2583         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2584         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2585 }
2586
2587 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2588                                       struct hsw_pipe_wm_parameters *p,
2589                                       struct intel_wm_config *config)
2590 {
2591         struct drm_device *dev = crtc->dev;
2592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2593         enum pipe pipe = intel_crtc->pipe;
2594         struct drm_plane *plane;
2595
2596         p->active = intel_crtc_active(crtc);
2597         if (p->active) {
2598                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2599                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2600                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2601                 p->cur.bytes_per_pixel = 4;
2602                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2603                 p->cur.horiz_pixels = 64;
2604                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2605                 p->pri.enabled = true;
2606                 p->cur.enabled = true;
2607         }
2608
2609         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2610                 config->num_pipes_active += intel_crtc_active(crtc);
2611
2612         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2613                 struct intel_plane *intel_plane = to_intel_plane(plane);
2614
2615                 if (intel_plane->pipe == pipe)
2616                         p->spr = intel_plane->wm;
2617
2618                 config->sprites_enabled |= intel_plane->wm.enabled;
2619                 config->sprites_scaled |= intel_plane->wm.scaled;
2620         }
2621 }
2622
2623 /* Compute new watermarks for the pipe */
2624 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2625                                   const struct hsw_pipe_wm_parameters *params,
2626                                   struct intel_pipe_wm *pipe_wm)
2627 {
2628         struct drm_device *dev = crtc->dev;
2629         struct drm_i915_private *dev_priv = dev->dev_private;
2630         int level, max_level = ilk_wm_max_level(dev);
2631         /* LP0 watermark maximums depend on this pipe alone */
2632         struct intel_wm_config config = {
2633                 .num_pipes_active = 1,
2634                 .sprites_enabled = params->spr.enabled,
2635                 .sprites_scaled = params->spr.scaled,
2636         };
2637         struct hsw_wm_maximums max;
2638
2639         /* LP0 watermarks always use 1/2 DDB partitioning */
2640         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2641
2642         for (level = 0; level <= max_level; level++)
2643                 ilk_compute_wm_level(dev_priv, level, params,
2644                                      &pipe_wm->wm[level]);
2645
2646         pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2647
2648         /* At least LP0 must be valid */
2649         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2650 }
2651
2652 /*
2653  * Merge the watermarks from all active pipes for a specific level.
2654  */
2655 static void ilk_merge_wm_level(struct drm_device *dev,
2656                                int level,
2657                                struct intel_wm_level *ret_wm)
2658 {
2659         const struct intel_crtc *intel_crtc;
2660
2661         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2662                 const struct intel_wm_level *wm =
2663                         &intel_crtc->wm.active.wm[level];
2664
2665                 if (!wm->enable)
2666                         return;
2667
2668                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2669                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2670                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2671                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2672         }
2673
2674         ret_wm->enable = true;
2675 }
2676
2677 /*
2678  * Merge all low power watermarks for all active pipes.
2679  */
2680 static void ilk_wm_merge(struct drm_device *dev,
2681                          const struct hsw_wm_maximums *max,
2682                          struct intel_pipe_wm *merged)
2683 {
2684         int level, max_level = ilk_wm_max_level(dev);
2685
2686         merged->fbc_wm_enabled = true;
2687
2688         /* merge each WM1+ level */
2689         for (level = 1; level <= max_level; level++) {
2690                 struct intel_wm_level *wm = &merged->wm[level];
2691
2692                 ilk_merge_wm_level(dev, level, wm);
2693
2694                 if (!ilk_validate_wm_level(level, max, wm))
2695                         break;
2696
2697                 /*
2698                  * The spec says it is preferred to disable
2699                  * FBC WMs instead of disabling a WM level.
2700                  */
2701                 if (wm->fbc_val > max->fbc) {
2702                         merged->fbc_wm_enabled = false;
2703                         wm->fbc_val = 0;
2704                 }
2705         }
2706 }
2707
2708 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2709 {
2710         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2711         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2712 }
2713
2714 static void hsw_compute_wm_results(struct drm_device *dev,
2715                                    const struct intel_pipe_wm *merged,
2716                                    enum intel_ddb_partitioning partitioning,
2717                                    struct hsw_wm_values *results)
2718 {
2719         struct intel_crtc *intel_crtc;
2720         int level, wm_lp;
2721
2722         results->enable_fbc_wm = merged->fbc_wm_enabled;
2723         results->partitioning = partitioning;
2724
2725         /* LP1+ register values */
2726         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2727                 const struct intel_wm_level *r;
2728
2729                 level = ilk_wm_lp_to_level(wm_lp, merged);
2730
2731                 r = &merged->wm[level];
2732                 if (!r->enable)
2733                         break;
2734
2735                 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2736                                                           r->fbc_val,
2737                                                           r->pri_val,
2738                                                           r->cur_val);
2739                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2740         }
2741
2742         /* LP0 register values */
2743         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2744                 enum pipe pipe = intel_crtc->pipe;
2745                 const struct intel_wm_level *r =
2746                         &intel_crtc->wm.active.wm[0];
2747
2748                 if (WARN_ON(!r->enable))
2749                         continue;
2750
2751                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2752
2753                 results->wm_pipe[pipe] =
2754                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2755                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2756                         r->cur_val;
2757         }
2758 }
2759
2760 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2761  * case both are at the same level. Prefer r1 in case they're the same. */
2762 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2763                                                   struct intel_pipe_wm *r1,
2764                                                   struct intel_pipe_wm *r2)
2765 {
2766         int level, max_level = ilk_wm_max_level(dev);
2767         int level1 = 0, level2 = 0;
2768
2769         for (level = 1; level <= max_level; level++) {
2770                 if (r1->wm[level].enable)
2771                         level1 = level;
2772                 if (r2->wm[level].enable)
2773                         level2 = level;
2774         }
2775
2776         if (level1 == level2) {
2777                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2778                         return r2;
2779                 else
2780                         return r1;
2781         } else if (level1 > level2) {
2782                 return r1;
2783         } else {
2784                 return r2;
2785         }
2786 }
2787
2788 /* dirty bits used to track which watermarks need changes */
2789 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2790 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2791 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2792 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2793 #define WM_DIRTY_FBC (1 << 24)
2794 #define WM_DIRTY_DDB (1 << 25)
2795
2796 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2797                                          const struct hsw_wm_values *old,
2798                                          const struct hsw_wm_values *new)
2799 {
2800         unsigned int dirty = 0;
2801         enum pipe pipe;
2802         int wm_lp;
2803
2804         for_each_pipe(pipe) {
2805                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2806                         dirty |= WM_DIRTY_LINETIME(pipe);
2807                         /* Must disable LP1+ watermarks too */
2808                         dirty |= WM_DIRTY_LP_ALL;
2809                 }
2810
2811                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2812                         dirty |= WM_DIRTY_PIPE(pipe);
2813                         /* Must disable LP1+ watermarks too */
2814                         dirty |= WM_DIRTY_LP_ALL;
2815                 }
2816         }
2817
2818         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2819                 dirty |= WM_DIRTY_FBC;
2820                 /* Must disable LP1+ watermarks too */
2821                 dirty |= WM_DIRTY_LP_ALL;
2822         }
2823
2824         if (old->partitioning != new->partitioning) {
2825                 dirty |= WM_DIRTY_DDB;
2826                 /* Must disable LP1+ watermarks too */
2827                 dirty |= WM_DIRTY_LP_ALL;
2828         }
2829
2830         /* LP1+ watermarks already deemed dirty, no need to continue */
2831         if (dirty & WM_DIRTY_LP_ALL)
2832                 return dirty;
2833
2834         /* Find the lowest numbered LP1+ watermark in need of an update... */
2835         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2836                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2837                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2838                         break;
2839         }
2840
2841         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2842         for (; wm_lp <= 3; wm_lp++)
2843                 dirty |= WM_DIRTY_LP(wm_lp);
2844
2845         return dirty;
2846 }
2847
2848 /*
2849  * The spec says we shouldn't write when we don't need, because every write
2850  * causes WMs to be re-evaluated, expending some power.
2851  */
2852 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2853                                 struct hsw_wm_values *results)
2854 {
2855         struct hsw_wm_values *previous = &dev_priv->wm.hw;
2856         unsigned int dirty;
2857         uint32_t val;
2858
2859         dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2860         if (!dirty)
2861                 return;
2862
2863         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2864                 I915_WRITE(WM3_LP_ILK, 0);
2865         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2866                 I915_WRITE(WM2_LP_ILK, 0);
2867         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2868                 I915_WRITE(WM1_LP_ILK, 0);
2869
2870         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2871                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2872         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2873                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2874         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2875                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2876
2877         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2878                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2879         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2880                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2881         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2882                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2883
2884         if (dirty & WM_DIRTY_DDB) {
2885                 val = I915_READ(WM_MISC);
2886                 if (results->partitioning == INTEL_DDB_PART_1_2)
2887                         val &= ~WM_MISC_DATA_PARTITION_5_6;
2888                 else
2889                         val |= WM_MISC_DATA_PARTITION_5_6;
2890                 I915_WRITE(WM_MISC, val);
2891         }
2892
2893         if (dirty & WM_DIRTY_FBC) {
2894                 val = I915_READ(DISP_ARB_CTL);
2895                 if (results->enable_fbc_wm)
2896                         val &= ~DISP_FBC_WM_DIS;
2897                 else
2898                         val |= DISP_FBC_WM_DIS;
2899                 I915_WRITE(DISP_ARB_CTL, val);
2900         }
2901
2902         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2903                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2904         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2905                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2906         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2907                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2908
2909         if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2910                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2911         if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2912                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2913         if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2914                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2915
2916         dev_priv->wm.hw = *results;
2917 }
2918
2919 static void haswell_update_wm(struct drm_crtc *crtc)
2920 {
2921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2922         struct drm_device *dev = crtc->dev;
2923         struct drm_i915_private *dev_priv = dev->dev_private;
2924         struct hsw_wm_maximums max;
2925         struct hsw_pipe_wm_parameters params = {};
2926         struct hsw_wm_values results = {};
2927         enum intel_ddb_partitioning partitioning;
2928         struct intel_pipe_wm pipe_wm = {};
2929         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2930         struct intel_wm_config config = {};
2931
2932         hsw_compute_wm_parameters(crtc, &params, &config);
2933
2934         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2935
2936         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2937                 return;
2938
2939         intel_crtc->wm.active = pipe_wm;
2940
2941         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2942         ilk_wm_merge(dev, &max, &lp_wm_1_2);
2943
2944         /* 5/6 split only in single pipe config on IVB+ */
2945         if (INTEL_INFO(dev)->gen >= 7 &&
2946             config.num_pipes_active == 1 && config.sprites_enabled) {
2947                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2948                 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2949
2950                 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2951         } else {
2952                 best_lp_wm = &lp_wm_1_2;
2953         }
2954
2955         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2956                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2957
2958         hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2959
2960         hsw_write_wm_values(dev_priv, &results);
2961 }
2962
2963 static void haswell_update_sprite_wm(struct drm_plane *plane,
2964                                      struct drm_crtc *crtc,
2965                                      uint32_t sprite_width, int pixel_size,
2966                                      bool enabled, bool scaled)
2967 {
2968         struct intel_plane *intel_plane = to_intel_plane(plane);
2969
2970         intel_plane->wm.enabled = enabled;
2971         intel_plane->wm.scaled = scaled;
2972         intel_plane->wm.horiz_pixels = sprite_width;
2973         intel_plane->wm.bytes_per_pixel = pixel_size;
2974
2975         haswell_update_wm(crtc);
2976 }
2977
2978 static bool
2979 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2980                               uint32_t sprite_width, int pixel_size,
2981                               const struct intel_watermark_params *display,
2982                               int display_latency_ns, int *sprite_wm)
2983 {
2984         struct drm_crtc *crtc;
2985         int clock;
2986         int entries, tlb_miss;
2987
2988         crtc = intel_get_crtc_for_plane(dev, plane);
2989         if (!intel_crtc_active(crtc)) {
2990                 *sprite_wm = display->guard_size;
2991                 return false;
2992         }
2993
2994         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2995
2996         /* Use the small buffer method to calculate the sprite watermark */
2997         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2998         tlb_miss = display->fifo_size*display->cacheline_size -
2999                 sprite_width * 8;
3000         if (tlb_miss > 0)
3001                 entries += tlb_miss;
3002         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3003         *sprite_wm = entries + display->guard_size;
3004         if (*sprite_wm > (int)display->max_wm)
3005                 *sprite_wm = display->max_wm;
3006
3007         return true;
3008 }
3009
3010 static bool
3011 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3012                                 uint32_t sprite_width, int pixel_size,
3013                                 const struct intel_watermark_params *display,
3014                                 int latency_ns, int *sprite_wm)
3015 {
3016         struct drm_crtc *crtc;
3017         unsigned long line_time_us;
3018         int clock;
3019         int line_count, line_size;
3020         int small, large;
3021         int entries;
3022
3023         if (!latency_ns) {
3024                 *sprite_wm = 0;
3025                 return false;
3026         }
3027
3028         crtc = intel_get_crtc_for_plane(dev, plane);
3029         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3030         if (!clock) {
3031                 *sprite_wm = 0;
3032                 return false;
3033         }
3034
3035         line_time_us = (sprite_width * 1000) / clock;
3036         if (!line_time_us) {
3037                 *sprite_wm = 0;
3038                 return false;
3039         }
3040
3041         line_count = (latency_ns / line_time_us + 1000) / 1000;
3042         line_size = sprite_width * pixel_size;
3043
3044         /* Use the minimum of the small and large buffer method for primary */
3045         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3046         large = line_count * line_size;
3047
3048         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3049         *sprite_wm = entries + display->guard_size;
3050
3051         return *sprite_wm > 0x3ff ? false : true;
3052 }
3053
3054 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3055                                          struct drm_crtc *crtc,
3056                                          uint32_t sprite_width, int pixel_size,
3057                                          bool enabled, bool scaled)
3058 {
3059         struct drm_device *dev = plane->dev;
3060         struct drm_i915_private *dev_priv = dev->dev_private;
3061         int pipe = to_intel_plane(plane)->pipe;
3062         int latency = dev_priv->wm.spr_latency[0] * 100;        /* In unit 0.1us */
3063         u32 val;
3064         int sprite_wm, reg;
3065         int ret;
3066
3067         if (!enabled)
3068                 return;
3069
3070         switch (pipe) {
3071         case 0:
3072                 reg = WM0_PIPEA_ILK;
3073                 break;
3074         case 1:
3075                 reg = WM0_PIPEB_ILK;
3076                 break;
3077         case 2:
3078                 reg = WM0_PIPEC_IVB;
3079                 break;
3080         default:
3081                 return; /* bad pipe */
3082         }
3083
3084         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3085                                             &sandybridge_display_wm_info,
3086                                             latency, &sprite_wm);
3087         if (!ret) {
3088                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3089                               pipe_name(pipe));
3090                 return;
3091         }
3092
3093         val = I915_READ(reg);
3094         val &= ~WM0_PIPE_SPRITE_MASK;
3095         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3096         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3097
3098
3099         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3100                                               pixel_size,
3101                                               &sandybridge_display_srwm_info,
3102                                               dev_priv->wm.spr_latency[1] * 500,
3103                                               &sprite_wm);
3104         if (!ret) {
3105                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3106                               pipe_name(pipe));
3107                 return;
3108         }
3109         I915_WRITE(WM1S_LP_ILK, sprite_wm);
3110
3111         /* Only IVB has two more LP watermarks for sprite */
3112         if (!IS_IVYBRIDGE(dev))
3113                 return;
3114
3115         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3116                                               pixel_size,
3117                                               &sandybridge_display_srwm_info,
3118                                               dev_priv->wm.spr_latency[2] * 500,
3119                                               &sprite_wm);
3120         if (!ret) {
3121                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3122                               pipe_name(pipe));
3123                 return;
3124         }
3125         I915_WRITE(WM2S_LP_IVB, sprite_wm);
3126
3127         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3128                                               pixel_size,
3129                                               &sandybridge_display_srwm_info,
3130                                               dev_priv->wm.spr_latency[3] * 500,
3131                                               &sprite_wm);
3132         if (!ret) {
3133                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3134                               pipe_name(pipe));
3135                 return;
3136         }
3137         I915_WRITE(WM3S_LP_IVB, sprite_wm);
3138 }
3139
3140 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3141 {
3142         struct drm_device *dev = crtc->dev;
3143         struct drm_i915_private *dev_priv = dev->dev_private;
3144         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3146         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3147         enum pipe pipe = intel_crtc->pipe;
3148         static const unsigned int wm0_pipe_reg[] = {
3149                 [PIPE_A] = WM0_PIPEA_ILK,
3150                 [PIPE_B] = WM0_PIPEB_ILK,
3151                 [PIPE_C] = WM0_PIPEC_IVB,
3152         };
3153
3154         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3155         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3156
3157         if (intel_crtc_active(crtc)) {
3158                 u32 tmp = hw->wm_pipe[pipe];
3159
3160                 /*
3161                  * For active pipes LP0 watermark is marked as
3162                  * enabled, and LP1+ watermaks as disabled since
3163                  * we can't really reverse compute them in case
3164                  * multiple pipes are active.
3165                  */
3166                 active->wm[0].enable = true;
3167                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3168                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3169                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3170                 active->linetime = hw->wm_linetime[pipe];
3171         } else {
3172                 int level, max_level = ilk_wm_max_level(dev);
3173
3174                 /*
3175                  * For inactive pipes, all watermark levels
3176                  * should be marked as enabled but zeroed,
3177                  * which is what we'd compute them to.
3178                  */
3179                 for (level = 0; level <= max_level; level++)
3180                         active->wm[level].enable = true;
3181         }
3182 }
3183
3184 void ilk_wm_get_hw_state(struct drm_device *dev)
3185 {
3186         struct drm_i915_private *dev_priv = dev->dev_private;
3187         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3188         struct drm_crtc *crtc;
3189
3190         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3191                 ilk_pipe_wm_get_hw_state(crtc);
3192
3193         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3194         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3195         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3196
3197         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3198         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3199         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3200
3201         hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3202                 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3203
3204         hw->enable_fbc_wm =
3205                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3206 }
3207
3208 /**
3209  * intel_update_watermarks - update FIFO watermark values based on current modes
3210  *
3211  * Calculate watermark values for the various WM regs based on current mode
3212  * and plane configuration.
3213  *
3214  * There are several cases to deal with here:
3215  *   - normal (i.e. non-self-refresh)
3216  *   - self-refresh (SR) mode
3217  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3218  *   - lines are small relative to FIFO size (buffer can hold more than 2
3219  *     lines), so need to account for TLB latency
3220  *
3221  *   The normal calculation is:
3222  *     watermark = dotclock * bytes per pixel * latency
3223  *   where latency is platform & configuration dependent (we assume pessimal
3224  *   values here).
3225  *
3226  *   The SR calculation is:
3227  *     watermark = (trunc(latency/line time)+1) * surface width *
3228  *       bytes per pixel
3229  *   where
3230  *     line time = htotal / dotclock
3231  *     surface width = hdisplay for normal plane and 64 for cursor
3232  *   and latency is assumed to be high, as above.
3233  *
3234  * The final value programmed to the register should always be rounded up,
3235  * and include an extra 2 entries to account for clock crossings.
3236  *
3237  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3238  * to set the non-SR watermarks to 8.
3239  */
3240 void intel_update_watermarks(struct drm_crtc *crtc)
3241 {
3242         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3243
3244         if (dev_priv->display.update_wm)
3245                 dev_priv->display.update_wm(crtc);
3246 }
3247
3248 void intel_update_sprite_watermarks(struct drm_plane *plane,
3249                                     struct drm_crtc *crtc,
3250                                     uint32_t sprite_width, int pixel_size,
3251                                     bool enabled, bool scaled)
3252 {
3253         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3254
3255         if (dev_priv->display.update_sprite_wm)
3256                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3257                                                    pixel_size, enabled, scaled);
3258 }
3259
3260 static struct drm_i915_gem_object *
3261 intel_alloc_context_page(struct drm_device *dev)
3262 {
3263         struct drm_i915_gem_object *ctx;
3264         int ret;
3265
3266         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3267
3268         ctx = i915_gem_alloc_object(dev, 4096);
3269         if (!ctx) {
3270                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3271                 return NULL;
3272         }
3273
3274         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3275         if (ret) {
3276                 DRM_ERROR("failed to pin power context: %d\n", ret);
3277                 goto err_unref;
3278         }
3279
3280         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3281         if (ret) {
3282                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3283                 goto err_unpin;
3284         }
3285
3286         return ctx;
3287
3288 err_unpin:
3289         i915_gem_object_unpin(ctx);
3290 err_unref:
3291         drm_gem_object_unreference(&ctx->base);
3292         return NULL;
3293 }
3294
3295 /**
3296  * Lock protecting IPS related data structures
3297  */
3298 DEFINE_SPINLOCK(mchdev_lock);
3299
3300 /* Global for IPS driver to get at the current i915 device. Protected by
3301  * mchdev_lock. */
3302 static struct drm_i915_private *i915_mch_dev;
3303
3304 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3305 {
3306         struct drm_i915_private *dev_priv = dev->dev_private;
3307         u16 rgvswctl;
3308
3309         assert_spin_locked(&mchdev_lock);
3310
3311         rgvswctl = I915_READ16(MEMSWCTL);
3312         if (rgvswctl & MEMCTL_CMD_STS) {
3313                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3314                 return false; /* still busy with another command */
3315         }
3316
3317         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3318                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3319         I915_WRITE16(MEMSWCTL, rgvswctl);
3320         POSTING_READ16(MEMSWCTL);
3321
3322         rgvswctl |= MEMCTL_CMD_STS;
3323         I915_WRITE16(MEMSWCTL, rgvswctl);
3324
3325         return true;
3326 }
3327
3328 static void ironlake_enable_drps(struct drm_device *dev)
3329 {
3330         struct drm_i915_private *dev_priv = dev->dev_private;
3331         u32 rgvmodectl = I915_READ(MEMMODECTL);
3332         u8 fmax, fmin, fstart, vstart;
3333
3334         spin_lock_irq(&mchdev_lock);
3335
3336         /* Enable temp reporting */
3337         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3338         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3339
3340         /* 100ms RC evaluation intervals */
3341         I915_WRITE(RCUPEI, 100000);
3342         I915_WRITE(RCDNEI, 100000);
3343
3344         /* Set max/min thresholds to 90ms and 80ms respectively */
3345         I915_WRITE(RCBMAXAVG, 90000);
3346         I915_WRITE(RCBMINAVG, 80000);
3347
3348         I915_WRITE(MEMIHYST, 1);
3349
3350         /* Set up min, max, and cur for interrupt handling */
3351         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3352         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3353         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3354                 MEMMODE_FSTART_SHIFT;
3355
3356         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3357                 PXVFREQ_PX_SHIFT;
3358
3359         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3360         dev_priv->ips.fstart = fstart;
3361
3362         dev_priv->ips.max_delay = fstart;
3363         dev_priv->ips.min_delay = fmin;
3364         dev_priv->ips.cur_delay = fstart;
3365
3366         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3367                          fmax, fmin, fstart);
3368
3369         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3370
3371         /*
3372          * Interrupts will be enabled in ironlake_irq_postinstall
3373          */
3374
3375         I915_WRITE(VIDSTART, vstart);
3376         POSTING_READ(VIDSTART);
3377
3378         rgvmodectl |= MEMMODE_SWMODE_EN;
3379         I915_WRITE(MEMMODECTL, rgvmodectl);
3380
3381         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3382                 DRM_ERROR("stuck trying to change perf mode\n");
3383         mdelay(1);
3384
3385         ironlake_set_drps(dev, fstart);
3386
3387         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3388                 I915_READ(0x112e0);
3389         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3390         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3391         getrawmonotonic(&dev_priv->ips.last_time2);
3392
3393         spin_unlock_irq(&mchdev_lock);
3394 }
3395
3396 static void ironlake_disable_drps(struct drm_device *dev)
3397 {
3398         struct drm_i915_private *dev_priv = dev->dev_private;
3399         u16 rgvswctl;
3400
3401         spin_lock_irq(&mchdev_lock);
3402
3403         rgvswctl = I915_READ16(MEMSWCTL);
3404
3405         /* Ack interrupts, disable EFC interrupt */
3406         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3407         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3408         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3409         I915_WRITE(DEIIR, DE_PCU_EVENT);
3410         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3411
3412         /* Go back to the starting frequency */
3413         ironlake_set_drps(dev, dev_priv->ips.fstart);
3414         mdelay(1);
3415         rgvswctl |= MEMCTL_CMD_STS;
3416         I915_WRITE(MEMSWCTL, rgvswctl);
3417         mdelay(1);
3418
3419         spin_unlock_irq(&mchdev_lock);
3420 }
3421
3422 /* There's a funny hw issue where the hw returns all 0 when reading from
3423  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3424  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3425  * all limits and the gpu stuck at whatever frequency it is at atm).
3426  */
3427 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3428 {
3429         u32 limits;
3430
3431         limits = 0;
3432
3433         if (*val >= dev_priv->rps.max_delay)
3434                 *val = dev_priv->rps.max_delay;
3435         limits |= dev_priv->rps.max_delay << 24;
3436
3437         /* Only set the down limit when we've reached the lowest level to avoid
3438          * getting more interrupts, otherwise leave this clear. This prevents a
3439          * race in the hw when coming out of rc6: There's a tiny window where
3440          * the hw runs at the minimal clock before selecting the desired
3441          * frequency, if the down threshold expires in that window we will not
3442          * receive a down interrupt. */
3443         if (*val <= dev_priv->rps.min_delay) {
3444                 *val = dev_priv->rps.min_delay;
3445                 limits |= dev_priv->rps.min_delay << 16;
3446         }
3447
3448         return limits;
3449 }
3450
3451 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3452 {
3453         int new_power;
3454
3455         new_power = dev_priv->rps.power;
3456         switch (dev_priv->rps.power) {
3457         case LOW_POWER:
3458                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3459                         new_power = BETWEEN;
3460                 break;
3461
3462         case BETWEEN:
3463                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3464                         new_power = LOW_POWER;
3465                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3466                         new_power = HIGH_POWER;
3467                 break;
3468
3469         case HIGH_POWER:
3470                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3471                         new_power = BETWEEN;
3472                 break;
3473         }
3474         /* Max/min bins are special */
3475         if (val == dev_priv->rps.min_delay)
3476                 new_power = LOW_POWER;
3477         if (val == dev_priv->rps.max_delay)
3478                 new_power = HIGH_POWER;
3479         if (new_power == dev_priv->rps.power)
3480                 return;
3481
3482         /* Note the units here are not exactly 1us, but 1280ns. */
3483         switch (new_power) {
3484         case LOW_POWER:
3485                 /* Upclock if more than 95% busy over 16ms */
3486                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3487                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3488
3489                 /* Downclock if less than 85% busy over 32ms */
3490                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3491                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3492
3493                 I915_WRITE(GEN6_RP_CONTROL,
3494                            GEN6_RP_MEDIA_TURBO |
3495                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3496                            GEN6_RP_MEDIA_IS_GFX |
3497                            GEN6_RP_ENABLE |
3498                            GEN6_RP_UP_BUSY_AVG |
3499                            GEN6_RP_DOWN_IDLE_AVG);
3500                 break;
3501
3502         case BETWEEN:
3503                 /* Upclock if more than 90% busy over 13ms */
3504                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3505                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3506
3507                 /* Downclock if less than 75% busy over 32ms */
3508                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3509                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3510
3511                 I915_WRITE(GEN6_RP_CONTROL,
3512                            GEN6_RP_MEDIA_TURBO |
3513                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3514                            GEN6_RP_MEDIA_IS_GFX |
3515                            GEN6_RP_ENABLE |
3516                            GEN6_RP_UP_BUSY_AVG |
3517                            GEN6_RP_DOWN_IDLE_AVG);
3518                 break;
3519
3520         case HIGH_POWER:
3521                 /* Upclock if more than 85% busy over 10ms */
3522                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3523                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3524
3525                 /* Downclock if less than 60% busy over 32ms */
3526                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3527                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3528
3529                 I915_WRITE(GEN6_RP_CONTROL,
3530                            GEN6_RP_MEDIA_TURBO |
3531                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3532                            GEN6_RP_MEDIA_IS_GFX |
3533                            GEN6_RP_ENABLE |
3534                            GEN6_RP_UP_BUSY_AVG |
3535                            GEN6_RP_DOWN_IDLE_AVG);
3536                 break;
3537         }
3538
3539         dev_priv->rps.power = new_power;
3540         dev_priv->rps.last_adj = 0;
3541 }
3542
3543 void gen6_set_rps(struct drm_device *dev, u8 val)
3544 {
3545         struct drm_i915_private *dev_priv = dev->dev_private;
3546         u32 limits = gen6_rps_limits(dev_priv, &val);
3547
3548         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3549         WARN_ON(val > dev_priv->rps.max_delay);
3550         WARN_ON(val < dev_priv->rps.min_delay);
3551
3552         if (val == dev_priv->rps.cur_delay)
3553                 return;
3554
3555         gen6_set_rps_thresholds(dev_priv, val);
3556
3557         if (IS_HASWELL(dev))
3558                 I915_WRITE(GEN6_RPNSWREQ,
3559                            HSW_FREQUENCY(val));
3560         else
3561                 I915_WRITE(GEN6_RPNSWREQ,
3562                            GEN6_FREQUENCY(val) |
3563                            GEN6_OFFSET(0) |
3564                            GEN6_AGGRESSIVE_TURBO);
3565
3566         /* Make sure we continue to get interrupts
3567          * until we hit the minimum or maximum frequencies.
3568          */
3569         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3570
3571         POSTING_READ(GEN6_RPNSWREQ);
3572
3573         dev_priv->rps.cur_delay = val;
3574
3575         trace_intel_gpu_freq_change(val * 50);
3576 }
3577
3578 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3579 {
3580         mutex_lock(&dev_priv->rps.hw_lock);
3581         if (dev_priv->rps.enabled) {
3582                 if (dev_priv->info->is_valleyview)
3583                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3584                 else
3585                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3586                 dev_priv->rps.last_adj = 0;
3587         }
3588         mutex_unlock(&dev_priv->rps.hw_lock);
3589 }
3590
3591 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3592 {
3593         mutex_lock(&dev_priv->rps.hw_lock);
3594         if (dev_priv->rps.enabled) {
3595                 if (dev_priv->info->is_valleyview)
3596                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3597                 else
3598                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3599                 dev_priv->rps.last_adj = 0;
3600         }
3601         mutex_unlock(&dev_priv->rps.hw_lock);
3602 }
3603
3604 /*
3605  * Wait until the previous freq change has completed,
3606  * or the timeout elapsed, and then update our notion
3607  * of the current GPU frequency.
3608  */
3609 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3610 {
3611         u32 pval;
3612
3613         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3614
3615         if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3616                 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3617
3618         pval >>= 8;
3619
3620         if (pval != dev_priv->rps.cur_delay)
3621                 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3622                                  vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3623                                  dev_priv->rps.cur_delay,
3624                                  vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3625
3626         dev_priv->rps.cur_delay = pval;
3627 }
3628
3629 void valleyview_set_rps(struct drm_device *dev, u8 val)
3630 {
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632
3633         gen6_rps_limits(dev_priv, &val);
3634
3635         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3636         WARN_ON(val > dev_priv->rps.max_delay);
3637         WARN_ON(val < dev_priv->rps.min_delay);
3638
3639         vlv_update_rps_cur_delay(dev_priv);
3640
3641         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3642                          vlv_gpu_freq(dev_priv->mem_freq,
3643                                       dev_priv->rps.cur_delay),
3644                          dev_priv->rps.cur_delay,
3645                          vlv_gpu_freq(dev_priv->mem_freq, val), val);
3646
3647         if (val == dev_priv->rps.cur_delay)
3648                 return;
3649
3650         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3651
3652         dev_priv->rps.cur_delay = val;
3653
3654         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3655 }
3656
3657 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3658 {
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660
3661         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3662         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3663         /* Complete PM interrupt masking here doesn't race with the rps work
3664          * item again unmasking PM interrupts because that is using a different
3665          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3666          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3667
3668         spin_lock_irq(&dev_priv->irq_lock);
3669         dev_priv->rps.pm_iir = 0;
3670         spin_unlock_irq(&dev_priv->irq_lock);
3671
3672         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3673 }
3674
3675 static void gen6_disable_rps(struct drm_device *dev)
3676 {
3677         struct drm_i915_private *dev_priv = dev->dev_private;
3678
3679         I915_WRITE(GEN6_RC_CONTROL, 0);
3680         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3681
3682         gen6_disable_rps_interrupts(dev);
3683 }
3684
3685 static void valleyview_disable_rps(struct drm_device *dev)
3686 {
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688
3689         I915_WRITE(GEN6_RC_CONTROL, 0);
3690
3691         gen6_disable_rps_interrupts(dev);
3692
3693         if (dev_priv->vlv_pctx) {
3694                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3695                 dev_priv->vlv_pctx = NULL;
3696         }
3697 }
3698
3699 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3700 {
3701         if (IS_GEN6(dev))
3702                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3703
3704         if (IS_HASWELL(dev))
3705                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3706
3707         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3708                         (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3709                         (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3710                         (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3711 }
3712
3713 int intel_enable_rc6(const struct drm_device *dev)
3714 {
3715         /* No RC6 before Ironlake */
3716         if (INTEL_INFO(dev)->gen < 5)
3717                 return 0;
3718
3719         /* Respect the kernel parameter if it is set */
3720         if (i915_enable_rc6 >= 0)
3721                 return i915_enable_rc6;
3722
3723         /* Disable RC6 on Ironlake */
3724         if (INTEL_INFO(dev)->gen == 5)
3725                 return 0;
3726
3727         if (IS_HASWELL(dev))
3728                 return INTEL_RC6_ENABLE;
3729
3730         /* snb/ivb have more than one rc6 state. */
3731         if (INTEL_INFO(dev)->gen == 6)
3732                 return INTEL_RC6_ENABLE;
3733
3734         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3735 }
3736
3737 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3738 {
3739         struct drm_i915_private *dev_priv = dev->dev_private;
3740         u32 enabled_intrs;
3741
3742         spin_lock_irq(&dev_priv->irq_lock);
3743         WARN_ON(dev_priv->rps.pm_iir);
3744         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3745         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3746         spin_unlock_irq(&dev_priv->irq_lock);
3747
3748         /* only unmask PM interrupts we need. Mask all others. */
3749         enabled_intrs = GEN6_PM_RPS_EVENTS;
3750
3751         /* IVB and SNB hard hangs on looping batchbuffer
3752          * if GEN6_PM_UP_EI_EXPIRED is masked.
3753          */
3754         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3755                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3756
3757         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3758 }
3759
3760 static void gen6_enable_rps(struct drm_device *dev)
3761 {
3762         struct drm_i915_private *dev_priv = dev->dev_private;
3763         struct intel_ring_buffer *ring;
3764         u32 rp_state_cap;
3765         u32 gt_perf_status;
3766         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3767         u32 gtfifodbg;
3768         int rc6_mode;
3769         int i, ret;
3770
3771         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3772
3773         /* Here begins a magic sequence of register writes to enable
3774          * auto-downclocking.
3775          *
3776          * Perhaps there might be some value in exposing these to
3777          * userspace...
3778          */
3779         I915_WRITE(GEN6_RC_STATE, 0);
3780
3781         /* Clear the DBG now so we don't confuse earlier errors */
3782         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3783                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3784                 I915_WRITE(GTFIFODBG, gtfifodbg);
3785         }
3786
3787         gen6_gt_force_wake_get(dev_priv);
3788
3789         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3790         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3791
3792         /* In units of 50MHz */
3793         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3794         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3795         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3796         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3797         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3798         dev_priv->rps.cur_delay = 0;
3799
3800         /* disable the counters and set deterministic thresholds */
3801         I915_WRITE(GEN6_RC_CONTROL, 0);
3802
3803         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3804         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3805         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3806         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3807         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3808
3809         for_each_ring(ring, dev_priv, i)
3810                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3811
3812         I915_WRITE(GEN6_RC_SLEEP, 0);
3813         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3814         if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3815                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3816         else
3817                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3818         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3819         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3820
3821         /* Check if we are enabling RC6 */
3822         rc6_mode = intel_enable_rc6(dev_priv->dev);
3823         if (rc6_mode & INTEL_RC6_ENABLE)
3824                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3825
3826         /* We don't use those on Haswell */
3827         if (!IS_HASWELL(dev)) {
3828                 if (rc6_mode & INTEL_RC6p_ENABLE)
3829                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3830
3831                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3832                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3833         }
3834
3835         intel_print_rc6_info(dev, rc6_mask);
3836
3837         I915_WRITE(GEN6_RC_CONTROL,
3838                    rc6_mask |
3839                    GEN6_RC_CTL_EI_MODE(1) |
3840                    GEN6_RC_CTL_HW_ENABLE);
3841
3842         /* Power down if completely idle for over 50ms */
3843         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3844         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3845
3846         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3847         if (!ret) {
3848                 pcu_mbox = 0;
3849                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3850                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3851                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3852                                          (dev_priv->rps.max_delay & 0xff) * 50,
3853                                          (pcu_mbox & 0xff) * 50);
3854                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3855                 }
3856         } else {
3857                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3858         }
3859
3860         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3861         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3862
3863         gen6_enable_rps_interrupts(dev);
3864
3865         rc6vids = 0;
3866         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3867         if (IS_GEN6(dev) && ret) {
3868                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3869         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3870                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3871                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3872                 rc6vids &= 0xffff00;
3873                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3874                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3875                 if (ret)
3876                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3877         }
3878
3879         gen6_gt_force_wake_put(dev_priv);
3880 }
3881
3882 void gen6_update_ring_freq(struct drm_device *dev)
3883 {
3884         struct drm_i915_private *dev_priv = dev->dev_private;
3885         int min_freq = 15;
3886         unsigned int gpu_freq;
3887         unsigned int max_ia_freq, min_ring_freq;
3888         int scaling_factor = 180;
3889         struct cpufreq_policy *policy;
3890
3891         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3892
3893         policy = cpufreq_cpu_get(0);
3894         if (policy) {
3895                 max_ia_freq = policy->cpuinfo.max_freq;
3896                 cpufreq_cpu_put(policy);
3897         } else {
3898                 /*
3899                  * Default to measured freq if none found, PCU will ensure we
3900                  * don't go over
3901                  */
3902                 max_ia_freq = tsc_khz;
3903         }
3904
3905         /* Convert from kHz to MHz */
3906         max_ia_freq /= 1000;
3907
3908         min_ring_freq = I915_READ(DCLK) & 0xf;
3909         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3910         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3911
3912         /*
3913          * For each potential GPU frequency, load a ring frequency we'd like
3914          * to use for memory access.  We do this by specifying the IA frequency
3915          * the PCU should use as a reference to determine the ring frequency.
3916          */
3917         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3918              gpu_freq--) {
3919                 int diff = dev_priv->rps.max_delay - gpu_freq;
3920                 unsigned int ia_freq = 0, ring_freq = 0;
3921
3922                 if (IS_HASWELL(dev)) {
3923                         ring_freq = mult_frac(gpu_freq, 5, 4);
3924                         ring_freq = max(min_ring_freq, ring_freq);
3925                         /* leave ia_freq as the default, chosen by cpufreq */
3926                 } else {
3927                         /* On older processors, there is no separate ring
3928                          * clock domain, so in order to boost the bandwidth
3929                          * of the ring, we need to upclock the CPU (ia_freq).
3930                          *
3931                          * For GPU frequencies less than 750MHz,
3932                          * just use the lowest ring freq.
3933                          */
3934                         if (gpu_freq < min_freq)
3935                                 ia_freq = 800;
3936                         else
3937                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3938                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3939                 }
3940
3941                 sandybridge_pcode_write(dev_priv,
3942                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3943                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3944                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3945                                         gpu_freq);
3946         }
3947 }
3948
3949 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3950 {
3951         u32 val, rp0;
3952
3953         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3954
3955         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3956         /* Clamp to max */
3957         rp0 = min_t(u32, rp0, 0xea);
3958
3959         return rp0;
3960 }
3961
3962 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3963 {
3964         u32 val, rpe;
3965
3966         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3967         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3968         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3969         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3970
3971         return rpe;
3972 }
3973
3974 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3975 {
3976         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3977 }
3978
3979 static void valleyview_setup_pctx(struct drm_device *dev)
3980 {
3981         struct drm_i915_private *dev_priv = dev->dev_private;
3982         struct drm_i915_gem_object *pctx;
3983         unsigned long pctx_paddr;
3984         u32 pcbr;
3985         int pctx_size = 24*1024;
3986
3987         pcbr = I915_READ(VLV_PCBR);
3988         if (pcbr) {
3989                 /* BIOS set it up already, grab the pre-alloc'd space */
3990                 int pcbr_offset;
3991
3992                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3993                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3994                                                                       pcbr_offset,
3995                                                                       I915_GTT_OFFSET_NONE,
3996                                                                       pctx_size);
3997                 goto out;
3998         }
3999
4000         /*
4001          * From the Gunit register HAS:
4002          * The Gfx driver is expected to program this register and ensure
4003          * proper allocation within Gfx stolen memory.  For example, this
4004          * register should be programmed such than the PCBR range does not
4005          * overlap with other ranges, such as the frame buffer, protected
4006          * memory, or any other relevant ranges.
4007          */
4008         pctx = i915_gem_object_create_stolen(dev, pctx_size);
4009         if (!pctx) {
4010                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4011                 return;
4012         }
4013
4014         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4015         I915_WRITE(VLV_PCBR, pctx_paddr);
4016
4017 out:
4018         dev_priv->vlv_pctx = pctx;
4019 }
4020
4021 static void valleyview_enable_rps(struct drm_device *dev)
4022 {
4023         struct drm_i915_private *dev_priv = dev->dev_private;
4024         struct intel_ring_buffer *ring;
4025         u32 gtfifodbg, val, rc6_mode = 0;
4026         int i;
4027
4028         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4029
4030         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4031                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4032                                  gtfifodbg);
4033                 I915_WRITE(GTFIFODBG, gtfifodbg);
4034         }
4035
4036         valleyview_setup_pctx(dev);
4037
4038         gen6_gt_force_wake_get(dev_priv);
4039
4040         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4041         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4042         I915_WRITE(GEN6_RP_UP_EI, 66000);
4043         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4044
4045         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4046
4047         I915_WRITE(GEN6_RP_CONTROL,
4048                    GEN6_RP_MEDIA_TURBO |
4049                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4050                    GEN6_RP_MEDIA_IS_GFX |
4051                    GEN6_RP_ENABLE |
4052                    GEN6_RP_UP_BUSY_AVG |
4053                    GEN6_RP_DOWN_IDLE_CONT);
4054
4055         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4056         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4057         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4058
4059         for_each_ring(ring, dev_priv, i)
4060                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4061
4062         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
4063
4064         /* allows RC6 residency counter to work */
4065         I915_WRITE(VLV_COUNTER_CONTROL,
4066                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4067                                       VLV_MEDIA_RC6_COUNT_EN |
4068                                       VLV_RENDER_RC6_COUNT_EN));
4069         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4070                 rc6_mode = GEN7_RC_CTL_TO_MODE;
4071
4072         intel_print_rc6_info(dev, rc6_mode);
4073
4074         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4075
4076         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4077         switch ((val >> 6) & 3) {
4078         case 0:
4079         case 1:
4080                 dev_priv->mem_freq = 800;
4081                 break;
4082         case 2:
4083                 dev_priv->mem_freq = 1066;
4084                 break;
4085         case 3:
4086                 dev_priv->mem_freq = 1333;
4087                 break;
4088         }
4089         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4090
4091         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4092         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4093
4094         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4095         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4096                          vlv_gpu_freq(dev_priv->mem_freq,
4097                                       dev_priv->rps.cur_delay),
4098                          dev_priv->rps.cur_delay);
4099
4100         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4101         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4102         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4103                          vlv_gpu_freq(dev_priv->mem_freq,
4104                                       dev_priv->rps.max_delay),
4105                          dev_priv->rps.max_delay);
4106
4107         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4108         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4109                          vlv_gpu_freq(dev_priv->mem_freq,
4110                                       dev_priv->rps.rpe_delay),
4111                          dev_priv->rps.rpe_delay);
4112
4113         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4114         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4115                          vlv_gpu_freq(dev_priv->mem_freq,
4116                                       dev_priv->rps.min_delay),
4117                          dev_priv->rps.min_delay);
4118
4119         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4120                          vlv_gpu_freq(dev_priv->mem_freq,
4121                                       dev_priv->rps.rpe_delay),
4122                          dev_priv->rps.rpe_delay);
4123
4124         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4125
4126         gen6_enable_rps_interrupts(dev);
4127
4128         gen6_gt_force_wake_put(dev_priv);
4129 }
4130
4131 void ironlake_teardown_rc6(struct drm_device *dev)
4132 {
4133         struct drm_i915_private *dev_priv = dev->dev_private;
4134
4135         if (dev_priv->ips.renderctx) {
4136                 i915_gem_object_unpin(dev_priv->ips.renderctx);
4137                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4138                 dev_priv->ips.renderctx = NULL;
4139         }
4140
4141         if (dev_priv->ips.pwrctx) {
4142                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4143                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4144                 dev_priv->ips.pwrctx = NULL;
4145         }
4146 }
4147
4148 static void ironlake_disable_rc6(struct drm_device *dev)
4149 {
4150         struct drm_i915_private *dev_priv = dev->dev_private;
4151
4152         if (I915_READ(PWRCTXA)) {
4153                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4154                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4155                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4156                          50);
4157
4158                 I915_WRITE(PWRCTXA, 0);
4159                 POSTING_READ(PWRCTXA);
4160
4161                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4162                 POSTING_READ(RSTDBYCTL);
4163         }
4164 }
4165
4166 static int ironlake_setup_rc6(struct drm_device *dev)
4167 {
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169
4170         if (dev_priv->ips.renderctx == NULL)
4171                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4172         if (!dev_priv->ips.renderctx)
4173                 return -ENOMEM;
4174
4175         if (dev_priv->ips.pwrctx == NULL)
4176                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4177         if (!dev_priv->ips.pwrctx) {
4178                 ironlake_teardown_rc6(dev);
4179                 return -ENOMEM;
4180         }
4181
4182         return 0;
4183 }
4184
4185 static void ironlake_enable_rc6(struct drm_device *dev)
4186 {
4187         struct drm_i915_private *dev_priv = dev->dev_private;
4188         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4189         bool was_interruptible;
4190         int ret;
4191
4192         /* rc6 disabled by default due to repeated reports of hanging during
4193          * boot and resume.
4194          */
4195         if (!intel_enable_rc6(dev))
4196                 return;
4197
4198         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4199
4200         ret = ironlake_setup_rc6(dev);
4201         if (ret)
4202                 return;
4203
4204         was_interruptible = dev_priv->mm.interruptible;
4205         dev_priv->mm.interruptible = false;
4206
4207         /*
4208          * GPU can automatically power down the render unit if given a page
4209          * to save state.
4210          */
4211         ret = intel_ring_begin(ring, 6);
4212         if (ret) {
4213                 ironlake_teardown_rc6(dev);
4214                 dev_priv->mm.interruptible = was_interruptible;
4215                 return;
4216         }
4217
4218         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4219         intel_ring_emit(ring, MI_SET_CONTEXT);
4220         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4221                         MI_MM_SPACE_GTT |
4222                         MI_SAVE_EXT_STATE_EN |
4223                         MI_RESTORE_EXT_STATE_EN |
4224                         MI_RESTORE_INHIBIT);
4225         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4226         intel_ring_emit(ring, MI_NOOP);
4227         intel_ring_emit(ring, MI_FLUSH);
4228         intel_ring_advance(ring);
4229
4230         /*
4231          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4232          * does an implicit flush, combined with MI_FLUSH above, it should be
4233          * safe to assume that renderctx is valid
4234          */
4235         ret = intel_ring_idle(ring);
4236         dev_priv->mm.interruptible = was_interruptible;
4237         if (ret) {
4238                 DRM_ERROR("failed to enable ironlake power savings\n");
4239                 ironlake_teardown_rc6(dev);
4240                 return;
4241         }
4242
4243         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4244         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4245
4246         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4247 }
4248
4249 static unsigned long intel_pxfreq(u32 vidfreq)
4250 {
4251         unsigned long freq;
4252         int div = (vidfreq & 0x3f0000) >> 16;
4253         int post = (vidfreq & 0x3000) >> 12;
4254         int pre = (vidfreq & 0x7);
4255
4256         if (!pre)
4257                 return 0;
4258
4259         freq = ((div * 133333) / ((1<<post) * pre));
4260
4261         return freq;
4262 }
4263
4264 static const struct cparams {
4265         u16 i;
4266         u16 t;
4267         u16 m;
4268         u16 c;
4269 } cparams[] = {
4270         { 1, 1333, 301, 28664 },
4271         { 1, 1066, 294, 24460 },
4272         { 1, 800, 294, 25192 },
4273         { 0, 1333, 276, 27605 },
4274         { 0, 1066, 276, 27605 },
4275         { 0, 800, 231, 23784 },
4276 };
4277
4278 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4279 {
4280         u64 total_count, diff, ret;
4281         u32 count1, count2, count3, m = 0, c = 0;
4282         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4283         int i;
4284
4285         assert_spin_locked(&mchdev_lock);
4286
4287         diff1 = now - dev_priv->ips.last_time1;
4288
4289         /* Prevent division-by-zero if we are asking too fast.
4290          * Also, we don't get interesting results if we are polling
4291          * faster than once in 10ms, so just return the saved value
4292          * in such cases.
4293          */
4294         if (diff1 <= 10)
4295                 return dev_priv->ips.chipset_power;
4296
4297         count1 = I915_READ(DMIEC);
4298         count2 = I915_READ(DDREC);
4299         count3 = I915_READ(CSIEC);
4300
4301         total_count = count1 + count2 + count3;
4302
4303         /* FIXME: handle per-counter overflow */
4304         if (total_count < dev_priv->ips.last_count1) {
4305                 diff = ~0UL - dev_priv->ips.last_count1;
4306                 diff += total_count;
4307         } else {
4308                 diff = total_count - dev_priv->ips.last_count1;
4309         }
4310
4311         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4312                 if (cparams[i].i == dev_priv->ips.c_m &&
4313                     cparams[i].t == dev_priv->ips.r_t) {
4314                         m = cparams[i].m;
4315                         c = cparams[i].c;
4316                         break;
4317                 }
4318         }
4319
4320         diff = div_u64(diff, diff1);
4321         ret = ((m * diff) + c);
4322         ret = div_u64(ret, 10);
4323
4324         dev_priv->ips.last_count1 = total_count;
4325         dev_priv->ips.last_time1 = now;
4326
4327         dev_priv->ips.chipset_power = ret;
4328
4329         return ret;
4330 }
4331
4332 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4333 {
4334         unsigned long val;
4335
4336         if (dev_priv->info->gen != 5)
4337                 return 0;
4338
4339         spin_lock_irq(&mchdev_lock);
4340
4341         val = __i915_chipset_val(dev_priv);
4342
4343         spin_unlock_irq(&mchdev_lock);
4344
4345         return val;
4346 }
4347
4348 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4349 {
4350         unsigned long m, x, b;
4351         u32 tsfs;
4352
4353         tsfs = I915_READ(TSFS);
4354
4355         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4356         x = I915_READ8(TR1);
4357
4358         b = tsfs & TSFS_INTR_MASK;
4359
4360         return ((m * x) / 127) - b;
4361 }
4362
4363 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4364 {
4365         static const struct v_table {
4366                 u16 vd; /* in .1 mil */
4367                 u16 vm; /* in .1 mil */
4368         } v_table[] = {
4369                 { 0, 0, },
4370                 { 375, 0, },
4371                 { 500, 0, },
4372                 { 625, 0, },
4373                 { 750, 0, },
4374                 { 875, 0, },
4375                 { 1000, 0, },
4376                 { 1125, 0, },
4377                 { 4125, 3000, },
4378                 { 4125, 3000, },
4379                 { 4125, 3000, },
4380                 { 4125, 3000, },
4381                 { 4125, 3000, },
4382                 { 4125, 3000, },
4383                 { 4125, 3000, },
4384                 { 4125, 3000, },
4385                 { 4125, 3000, },
4386                 { 4125, 3000, },
4387                 { 4125, 3000, },
4388                 { 4125, 3000, },
4389                 { 4125, 3000, },
4390                 { 4125, 3000, },
4391                 { 4125, 3000, },
4392                 { 4125, 3000, },
4393                 { 4125, 3000, },
4394                 { 4125, 3000, },
4395                 { 4125, 3000, },
4396                 { 4125, 3000, },
4397                 { 4125, 3000, },
4398                 { 4125, 3000, },
4399                 { 4125, 3000, },
4400                 { 4125, 3000, },
4401                 { 4250, 3125, },
4402                 { 4375, 3250, },
4403                 { 4500, 3375, },
4404                 { 4625, 3500, },
4405                 { 4750, 3625, },
4406                 { 4875, 3750, },
4407                 { 5000, 3875, },
4408                 { 5125, 4000, },
4409                 { 5250, 4125, },
4410                 { 5375, 4250, },
4411                 { 5500, 4375, },
4412                 { 5625, 4500, },
4413                 { 5750, 4625, },
4414                 { 5875, 4750, },
4415                 { 6000, 4875, },
4416                 { 6125, 5000, },
4417                 { 6250, 5125, },
4418                 { 6375, 5250, },
4419                 { 6500, 5375, },
4420                 { 6625, 5500, },
4421                 { 6750, 5625, },
4422                 { 6875, 5750, },
4423                 { 7000, 5875, },
4424                 { 7125, 6000, },
4425                 { 7250, 6125, },
4426                 { 7375, 6250, },
4427                 { 7500, 6375, },
4428                 { 7625, 6500, },
4429                 { 7750, 6625, },
4430                 { 7875, 6750, },
4431                 { 8000, 6875, },
4432                 { 8125, 7000, },
4433                 { 8250, 7125, },
4434                 { 8375, 7250, },
4435                 { 8500, 7375, },
4436                 { 8625, 7500, },
4437                 { 8750, 7625, },
4438                 { 8875, 7750, },
4439                 { 9000, 7875, },
4440                 { 9125, 8000, },
4441                 { 9250, 8125, },
4442                 { 9375, 8250, },
4443                 { 9500, 8375, },
4444                 { 9625, 8500, },
4445                 { 9750, 8625, },
4446                 { 9875, 8750, },
4447                 { 10000, 8875, },
4448                 { 10125, 9000, },
4449                 { 10250, 9125, },
4450                 { 10375, 9250, },
4451                 { 10500, 9375, },
4452                 { 10625, 9500, },
4453                 { 10750, 9625, },
4454                 { 10875, 9750, },
4455                 { 11000, 9875, },
4456                 { 11125, 10000, },
4457                 { 11250, 10125, },
4458                 { 11375, 10250, },
4459                 { 11500, 10375, },
4460                 { 11625, 10500, },
4461                 { 11750, 10625, },
4462                 { 11875, 10750, },
4463                 { 12000, 10875, },
4464                 { 12125, 11000, },
4465                 { 12250, 11125, },
4466                 { 12375, 11250, },
4467                 { 12500, 11375, },
4468                 { 12625, 11500, },
4469                 { 12750, 11625, },
4470                 { 12875, 11750, },
4471                 { 13000, 11875, },
4472                 { 13125, 12000, },
4473                 { 13250, 12125, },
4474                 { 13375, 12250, },
4475                 { 13500, 12375, },
4476                 { 13625, 12500, },
4477                 { 13750, 12625, },
4478                 { 13875, 12750, },
4479                 { 14000, 12875, },
4480                 { 14125, 13000, },
4481                 { 14250, 13125, },
4482                 { 14375, 13250, },
4483                 { 14500, 13375, },
4484                 { 14625, 13500, },
4485                 { 14750, 13625, },
4486                 { 14875, 13750, },
4487                 { 15000, 13875, },
4488                 { 15125, 14000, },
4489                 { 15250, 14125, },
4490                 { 15375, 14250, },
4491                 { 15500, 14375, },
4492                 { 15625, 14500, },
4493                 { 15750, 14625, },
4494                 { 15875, 14750, },
4495                 { 16000, 14875, },
4496                 { 16125, 15000, },
4497         };
4498         if (dev_priv->info->is_mobile)
4499                 return v_table[pxvid].vm;
4500         else
4501                 return v_table[pxvid].vd;
4502 }
4503
4504 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4505 {
4506         struct timespec now, diff1;
4507         u64 diff;
4508         unsigned long diffms;
4509         u32 count;
4510
4511         assert_spin_locked(&mchdev_lock);
4512
4513         getrawmonotonic(&now);
4514         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4515
4516         /* Don't divide by 0 */
4517         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4518         if (!diffms)
4519                 return;
4520
4521         count = I915_READ(GFXEC);
4522
4523         if (count < dev_priv->ips.last_count2) {
4524                 diff = ~0UL - dev_priv->ips.last_count2;
4525                 diff += count;
4526         } else {
4527                 diff = count - dev_priv->ips.last_count2;
4528         }
4529
4530         dev_priv->ips.last_count2 = count;
4531         dev_priv->ips.last_time2 = now;
4532
4533         /* More magic constants... */
4534         diff = diff * 1181;
4535         diff = div_u64(diff, diffms * 10);
4536         dev_priv->ips.gfx_power = diff;
4537 }
4538
4539 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4540 {
4541         if (dev_priv->info->gen != 5)
4542                 return;
4543
4544         spin_lock_irq(&mchdev_lock);
4545
4546         __i915_update_gfx_val(dev_priv);
4547
4548         spin_unlock_irq(&mchdev_lock);
4549 }
4550
4551 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4552 {
4553         unsigned long t, corr, state1, corr2, state2;
4554         u32 pxvid, ext_v;
4555
4556         assert_spin_locked(&mchdev_lock);
4557
4558         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4559         pxvid = (pxvid >> 24) & 0x7f;
4560         ext_v = pvid_to_extvid(dev_priv, pxvid);
4561
4562         state1 = ext_v;
4563
4564         t = i915_mch_val(dev_priv);
4565
4566         /* Revel in the empirically derived constants */
4567
4568         /* Correction factor in 1/100000 units */
4569         if (t > 80)
4570                 corr = ((t * 2349) + 135940);
4571         else if (t >= 50)
4572                 corr = ((t * 964) + 29317);
4573         else /* < 50 */
4574                 corr = ((t * 301) + 1004);
4575
4576         corr = corr * ((150142 * state1) / 10000 - 78642);
4577         corr /= 100000;
4578         corr2 = (corr * dev_priv->ips.corr);
4579
4580         state2 = (corr2 * state1) / 10000;
4581         state2 /= 100; /* convert to mW */
4582
4583         __i915_update_gfx_val(dev_priv);
4584
4585         return dev_priv->ips.gfx_power + state2;
4586 }
4587
4588 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4589 {
4590         unsigned long val;
4591
4592         if (dev_priv->info->gen != 5)
4593                 return 0;
4594
4595         spin_lock_irq(&mchdev_lock);
4596
4597         val = __i915_gfx_val(dev_priv);
4598
4599         spin_unlock_irq(&mchdev_lock);
4600
4601         return val;
4602 }
4603
4604 /**
4605  * i915_read_mch_val - return value for IPS use
4606  *
4607  * Calculate and return a value for the IPS driver to use when deciding whether
4608  * we have thermal and power headroom to increase CPU or GPU power budget.
4609  */
4610 unsigned long i915_read_mch_val(void)
4611 {
4612         struct drm_i915_private *dev_priv;
4613         unsigned long chipset_val, graphics_val, ret = 0;
4614
4615         spin_lock_irq(&mchdev_lock);
4616         if (!i915_mch_dev)
4617                 goto out_unlock;
4618         dev_priv = i915_mch_dev;
4619
4620         chipset_val = __i915_chipset_val(dev_priv);
4621         graphics_val = __i915_gfx_val(dev_priv);
4622
4623         ret = chipset_val + graphics_val;
4624
4625 out_unlock:
4626         spin_unlock_irq(&mchdev_lock);
4627
4628         return ret;
4629 }
4630 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4631
4632 /**
4633  * i915_gpu_raise - raise GPU frequency limit
4634  *
4635  * Raise the limit; IPS indicates we have thermal headroom.
4636  */
4637 bool i915_gpu_raise(void)
4638 {
4639         struct drm_i915_private *dev_priv;
4640         bool ret = true;
4641
4642         spin_lock_irq(&mchdev_lock);
4643         if (!i915_mch_dev) {
4644                 ret = false;
4645                 goto out_unlock;
4646         }
4647         dev_priv = i915_mch_dev;
4648
4649         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4650                 dev_priv->ips.max_delay--;
4651
4652 out_unlock:
4653         spin_unlock_irq(&mchdev_lock);
4654
4655         return ret;
4656 }
4657 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4658
4659 /**
4660  * i915_gpu_lower - lower GPU frequency limit
4661  *
4662  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4663  * frequency maximum.
4664  */
4665 bool i915_gpu_lower(void)
4666 {
4667         struct drm_i915_private *dev_priv;
4668         bool ret = true;
4669
4670         spin_lock_irq(&mchdev_lock);
4671         if (!i915_mch_dev) {
4672                 ret = false;
4673                 goto out_unlock;
4674         }
4675         dev_priv = i915_mch_dev;
4676
4677         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4678                 dev_priv->ips.max_delay++;
4679
4680 out_unlock:
4681         spin_unlock_irq(&mchdev_lock);
4682
4683         return ret;
4684 }
4685 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4686
4687 /**
4688  * i915_gpu_busy - indicate GPU business to IPS
4689  *
4690  * Tell the IPS driver whether or not the GPU is busy.
4691  */
4692 bool i915_gpu_busy(void)
4693 {
4694         struct drm_i915_private *dev_priv;
4695         struct intel_ring_buffer *ring;
4696         bool ret = false;
4697         int i;
4698
4699         spin_lock_irq(&mchdev_lock);
4700         if (!i915_mch_dev)
4701                 goto out_unlock;
4702         dev_priv = i915_mch_dev;
4703
4704         for_each_ring(ring, dev_priv, i)
4705                 ret |= !list_empty(&ring->request_list);
4706
4707 out_unlock:
4708         spin_unlock_irq(&mchdev_lock);
4709
4710         return ret;
4711 }
4712 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4713
4714 /**
4715  * i915_gpu_turbo_disable - disable graphics turbo
4716  *
4717  * Disable graphics turbo by resetting the max frequency and setting the
4718  * current frequency to the default.
4719  */
4720 bool i915_gpu_turbo_disable(void)
4721 {
4722         struct drm_i915_private *dev_priv;
4723         bool ret = true;
4724
4725         spin_lock_irq(&mchdev_lock);
4726         if (!i915_mch_dev) {
4727                 ret = false;
4728                 goto out_unlock;
4729         }
4730         dev_priv = i915_mch_dev;
4731
4732         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4733
4734         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4735                 ret = false;
4736
4737 out_unlock:
4738         spin_unlock_irq(&mchdev_lock);
4739
4740         return ret;
4741 }
4742 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4743
4744 /**
4745  * Tells the intel_ips driver that the i915 driver is now loaded, if
4746  * IPS got loaded first.
4747  *
4748  * This awkward dance is so that neither module has to depend on the
4749  * other in order for IPS to do the appropriate communication of
4750  * GPU turbo limits to i915.
4751  */
4752 static void
4753 ips_ping_for_i915_load(void)
4754 {
4755         void (*link)(void);
4756
4757         link = symbol_get(ips_link_to_i915_driver);
4758         if (link) {
4759                 link();
4760                 symbol_put(ips_link_to_i915_driver);
4761         }
4762 }
4763
4764 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4765 {
4766         /* We only register the i915 ips part with intel-ips once everything is
4767          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4768         spin_lock_irq(&mchdev_lock);
4769         i915_mch_dev = dev_priv;
4770         spin_unlock_irq(&mchdev_lock);
4771
4772         ips_ping_for_i915_load();
4773 }
4774
4775 void intel_gpu_ips_teardown(void)
4776 {
4777         spin_lock_irq(&mchdev_lock);
4778         i915_mch_dev = NULL;
4779         spin_unlock_irq(&mchdev_lock);
4780 }
4781 static void intel_init_emon(struct drm_device *dev)
4782 {
4783         struct drm_i915_private *dev_priv = dev->dev_private;
4784         u32 lcfuse;
4785         u8 pxw[16];
4786         int i;
4787
4788         /* Disable to program */
4789         I915_WRITE(ECR, 0);
4790         POSTING_READ(ECR);
4791
4792         /* Program energy weights for various events */
4793         I915_WRITE(SDEW, 0x15040d00);
4794         I915_WRITE(CSIEW0, 0x007f0000);
4795         I915_WRITE(CSIEW1, 0x1e220004);
4796         I915_WRITE(CSIEW2, 0x04000004);
4797
4798         for (i = 0; i < 5; i++)
4799                 I915_WRITE(PEW + (i * 4), 0);
4800         for (i = 0; i < 3; i++)
4801                 I915_WRITE(DEW + (i * 4), 0);
4802
4803         /* Program P-state weights to account for frequency power adjustment */
4804         for (i = 0; i < 16; i++) {
4805                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4806                 unsigned long freq = intel_pxfreq(pxvidfreq);
4807                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4808                         PXVFREQ_PX_SHIFT;
4809                 unsigned long val;
4810
4811                 val = vid * vid;
4812                 val *= (freq / 1000);
4813                 val *= 255;
4814                 val /= (127*127*900);
4815                 if (val > 0xff)
4816                         DRM_ERROR("bad pxval: %ld\n", val);
4817                 pxw[i] = val;
4818         }
4819         /* Render standby states get 0 weight */
4820         pxw[14] = 0;
4821         pxw[15] = 0;
4822
4823         for (i = 0; i < 4; i++) {
4824                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4825                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4826                 I915_WRITE(PXW + (i * 4), val);
4827         }
4828
4829         /* Adjust magic regs to magic values (more experimental results) */
4830         I915_WRITE(OGW0, 0);
4831         I915_WRITE(OGW1, 0);
4832         I915_WRITE(EG0, 0x00007f00);
4833         I915_WRITE(EG1, 0x0000000e);
4834         I915_WRITE(EG2, 0x000e0000);
4835         I915_WRITE(EG3, 0x68000300);
4836         I915_WRITE(EG4, 0x42000000);
4837         I915_WRITE(EG5, 0x00140031);
4838         I915_WRITE(EG6, 0);
4839         I915_WRITE(EG7, 0);
4840
4841         for (i = 0; i < 8; i++)
4842                 I915_WRITE(PXWL + (i * 4), 0);
4843
4844         /* Enable PMON + select events */
4845         I915_WRITE(ECR, 0x80000019);
4846
4847         lcfuse = I915_READ(LCFUSE02);
4848
4849         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4850 }
4851
4852 void intel_disable_gt_powersave(struct drm_device *dev)
4853 {
4854         struct drm_i915_private *dev_priv = dev->dev_private;
4855
4856         /* Interrupts should be disabled already to avoid re-arming. */
4857         WARN_ON(dev->irq_enabled);
4858
4859         if (IS_IRONLAKE_M(dev)) {
4860                 ironlake_disable_drps(dev);
4861                 ironlake_disable_rc6(dev);
4862         } else if (INTEL_INFO(dev)->gen >= 6) {
4863                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4864                 cancel_work_sync(&dev_priv->rps.work);
4865                 mutex_lock(&dev_priv->rps.hw_lock);
4866                 if (IS_VALLEYVIEW(dev))
4867                         valleyview_disable_rps(dev);
4868                 else
4869                         gen6_disable_rps(dev);
4870                 dev_priv->rps.enabled = false;
4871                 mutex_unlock(&dev_priv->rps.hw_lock);
4872         }
4873 }
4874
4875 static void intel_gen6_powersave_work(struct work_struct *work)
4876 {
4877         struct drm_i915_private *dev_priv =
4878                 container_of(work, struct drm_i915_private,
4879                              rps.delayed_resume_work.work);
4880         struct drm_device *dev = dev_priv->dev;
4881
4882         mutex_lock(&dev_priv->rps.hw_lock);
4883
4884         if (IS_VALLEYVIEW(dev)) {
4885                 valleyview_enable_rps(dev);
4886         } else {
4887                 gen6_enable_rps(dev);
4888                 gen6_update_ring_freq(dev);
4889         }
4890         dev_priv->rps.enabled = true;
4891         mutex_unlock(&dev_priv->rps.hw_lock);
4892 }
4893
4894 void intel_enable_gt_powersave(struct drm_device *dev)
4895 {
4896         struct drm_i915_private *dev_priv = dev->dev_private;
4897
4898         if (IS_IRONLAKE_M(dev)) {
4899                 ironlake_enable_drps(dev);
4900                 ironlake_enable_rc6(dev);
4901                 intel_init_emon(dev);
4902         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4903                 /*
4904                  * PCU communication is slow and this doesn't need to be
4905                  * done at any specific time, so do this out of our fast path
4906                  * to make resume and init faster.
4907                  */
4908                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4909                                       round_jiffies_up_relative(HZ));
4910         }
4911 }
4912
4913 static void ibx_init_clock_gating(struct drm_device *dev)
4914 {
4915         struct drm_i915_private *dev_priv = dev->dev_private;
4916
4917         /*
4918          * On Ibex Peak and Cougar Point, we need to disable clock
4919          * gating for the panel power sequencer or it will fail to
4920          * start up when no ports are active.
4921          */
4922         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4923 }
4924
4925 static void g4x_disable_trickle_feed(struct drm_device *dev)
4926 {
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         int pipe;
4929
4930         for_each_pipe(pipe) {
4931                 I915_WRITE(DSPCNTR(pipe),
4932                            I915_READ(DSPCNTR(pipe)) |
4933                            DISPPLANE_TRICKLE_FEED_DISABLE);
4934                 intel_flush_primary_plane(dev_priv, pipe);
4935         }
4936 }
4937
4938 static void ironlake_init_clock_gating(struct drm_device *dev)
4939 {
4940         struct drm_i915_private *dev_priv = dev->dev_private;
4941         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4942
4943         /*
4944          * Required for FBC
4945          * WaFbcDisableDpfcClockGating:ilk
4946          */
4947         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4948                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4949                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4950
4951         I915_WRITE(PCH_3DCGDIS0,
4952                    MARIUNIT_CLOCK_GATE_DISABLE |
4953                    SVSMUNIT_CLOCK_GATE_DISABLE);
4954         I915_WRITE(PCH_3DCGDIS1,
4955                    VFMUNIT_CLOCK_GATE_DISABLE);
4956
4957         /*
4958          * According to the spec the following bits should be set in
4959          * order to enable memory self-refresh
4960          * The bit 22/21 of 0x42004
4961          * The bit 5 of 0x42020
4962          * The bit 15 of 0x45000
4963          */
4964         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4965                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4966                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4967         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4968         I915_WRITE(DISP_ARB_CTL,
4969                    (I915_READ(DISP_ARB_CTL) |
4970                     DISP_FBC_WM_DIS));
4971         I915_WRITE(WM3_LP_ILK, 0);
4972         I915_WRITE(WM2_LP_ILK, 0);
4973         I915_WRITE(WM1_LP_ILK, 0);
4974
4975         /*
4976          * Based on the document from hardware guys the following bits
4977          * should be set unconditionally in order to enable FBC.
4978          * The bit 22 of 0x42000
4979          * The bit 22 of 0x42004
4980          * The bit 7,8,9 of 0x42020.
4981          */
4982         if (IS_IRONLAKE_M(dev)) {
4983                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4984                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4985                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4986                            ILK_FBCQ_DIS);
4987                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4988                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4989                            ILK_DPARB_GATE);
4990         }
4991
4992         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4993
4994         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4995                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4996                    ILK_ELPIN_409_SELECT);
4997         I915_WRITE(_3D_CHICKEN2,
4998                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4999                    _3D_CHICKEN2_WM_READ_PIPELINED);
5000
5001         /* WaDisableRenderCachePipelinedFlush:ilk */
5002         I915_WRITE(CACHE_MODE_0,
5003                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5004
5005         g4x_disable_trickle_feed(dev);
5006
5007         ibx_init_clock_gating(dev);
5008 }
5009
5010 static void cpt_init_clock_gating(struct drm_device *dev)
5011 {
5012         struct drm_i915_private *dev_priv = dev->dev_private;
5013         int pipe;
5014         uint32_t val;
5015
5016         /*
5017          * On Ibex Peak and Cougar Point, we need to disable clock
5018          * gating for the panel power sequencer or it will fail to
5019          * start up when no ports are active.
5020          */
5021         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5022         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5023                    DPLS_EDP_PPS_FIX_DIS);
5024         /* The below fixes the weird display corruption, a few pixels shifted
5025          * downward, on (only) LVDS of some HP laptops with IVY.
5026          */
5027         for_each_pipe(pipe) {
5028                 val = I915_READ(TRANS_CHICKEN2(pipe));
5029                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5030                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5031                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5032                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5033                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5034                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5035                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5036                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5037         }
5038         /* WADP0ClockGatingDisable */
5039         for_each_pipe(pipe) {
5040                 I915_WRITE(TRANS_CHICKEN1(pipe),
5041                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5042         }
5043 }
5044
5045 static void gen6_check_mch_setup(struct drm_device *dev)
5046 {
5047         struct drm_i915_private *dev_priv = dev->dev_private;
5048         uint32_t tmp;
5049
5050         tmp = I915_READ(MCH_SSKPD);
5051         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5052                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5053                 DRM_INFO("This can cause pipe underruns and display issues.\n");
5054                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5055         }
5056 }
5057
5058 static void gen6_init_clock_gating(struct drm_device *dev)
5059 {
5060         struct drm_i915_private *dev_priv = dev->dev_private;
5061         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5062
5063         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5064
5065         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5066                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5067                    ILK_ELPIN_409_SELECT);
5068
5069         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5070         I915_WRITE(_3D_CHICKEN,
5071                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5072
5073         /* WaSetupGtModeTdRowDispatch:snb */
5074         if (IS_SNB_GT1(dev))
5075                 I915_WRITE(GEN6_GT_MODE,
5076                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5077
5078         I915_WRITE(WM3_LP_ILK, 0);
5079         I915_WRITE(WM2_LP_ILK, 0);
5080         I915_WRITE(WM1_LP_ILK, 0);
5081
5082         I915_WRITE(CACHE_MODE_0,
5083                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5084
5085         I915_WRITE(GEN6_UCGCTL1,
5086                    I915_READ(GEN6_UCGCTL1) |
5087                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5088                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5089
5090         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5091          * gating disable must be set.  Failure to set it results in
5092          * flickering pixels due to Z write ordering failures after
5093          * some amount of runtime in the Mesa "fire" demo, and Unigine
5094          * Sanctuary and Tropics, and apparently anything else with
5095          * alpha test or pixel discard.
5096          *
5097          * According to the spec, bit 11 (RCCUNIT) must also be set,
5098          * but we didn't debug actual testcases to find it out.
5099          *
5100          * Also apply WaDisableVDSUnitClockGating:snb and
5101          * WaDisableRCPBUnitClockGating:snb.
5102          */
5103         I915_WRITE(GEN6_UCGCTL2,
5104                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5105                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5106                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5107
5108         /* Bspec says we need to always set all mask bits. */
5109         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5110                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5111
5112         /*
5113          * According to the spec the following bits should be
5114          * set in order to enable memory self-refresh and fbc:
5115          * The bit21 and bit22 of 0x42000
5116          * The bit21 and bit22 of 0x42004
5117          * The bit5 and bit7 of 0x42020
5118          * The bit14 of 0x70180
5119          * The bit14 of 0x71180
5120          *
5121          * WaFbcAsynchFlipDisableFbcQueue:snb
5122          */
5123         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5124                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5125                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5126         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5127                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5128                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5129         I915_WRITE(ILK_DSPCLK_GATE_D,
5130                    I915_READ(ILK_DSPCLK_GATE_D) |
5131                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5132                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5133
5134         g4x_disable_trickle_feed(dev);
5135
5136         /* The default value should be 0x200 according to docs, but the two
5137          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5138         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5139         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5140
5141         cpt_init_clock_gating(dev);
5142
5143         gen6_check_mch_setup(dev);
5144 }
5145
5146 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5147 {
5148         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5149
5150         reg &= ~GEN7_FF_SCHED_MASK;
5151         reg |= GEN7_FF_TS_SCHED_HW;
5152         reg |= GEN7_FF_VS_SCHED_HW;
5153         reg |= GEN7_FF_DS_SCHED_HW;
5154
5155         if (IS_HASWELL(dev_priv->dev))
5156                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5157
5158         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5159 }
5160
5161 static void lpt_init_clock_gating(struct drm_device *dev)
5162 {
5163         struct drm_i915_private *dev_priv = dev->dev_private;
5164
5165         /*
5166          * TODO: this bit should only be enabled when really needed, then
5167          * disabled when not needed anymore in order to save power.
5168          */
5169         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5170                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5171                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5172                            PCH_LP_PARTITION_LEVEL_DISABLE);
5173
5174         /* WADPOClockGatingDisable:hsw */
5175         I915_WRITE(_TRANSA_CHICKEN1,
5176                    I915_READ(_TRANSA_CHICKEN1) |
5177                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5178 }
5179
5180 static void lpt_suspend_hw(struct drm_device *dev)
5181 {
5182         struct drm_i915_private *dev_priv = dev->dev_private;
5183
5184         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5185                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5186
5187                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5188                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5189         }
5190 }
5191
5192 static void haswell_init_clock_gating(struct drm_device *dev)
5193 {
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195
5196         I915_WRITE(WM3_LP_ILK, 0);
5197         I915_WRITE(WM2_LP_ILK, 0);
5198         I915_WRITE(WM1_LP_ILK, 0);
5199
5200         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5201          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5202          */
5203         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5204
5205         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5206         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5207                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5208
5209         /* WaApplyL3ControlAndL3ChickenMode:hsw */
5210         I915_WRITE(GEN7_L3CNTLREG1,
5211                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5212         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5213                         GEN7_WA_L3_CHICKEN_MODE);
5214
5215         /* This is required by WaCatErrorRejectionIssue:hsw */
5216         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5217                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5218                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5219
5220         /* WaVSRefCountFullforceMissDisable:hsw */
5221         gen7_setup_fixed_func_scheduler(dev_priv);
5222
5223         /* WaDisable4x2SubspanOptimization:hsw */
5224         I915_WRITE(CACHE_MODE_1,
5225                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5226
5227         /* WaSwitchSolVfFArbitrationPriority:hsw */
5228         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5229
5230         /* WaRsPkgCStateDisplayPMReq:hsw */
5231         I915_WRITE(CHICKEN_PAR1_1,
5232                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5233
5234         lpt_init_clock_gating(dev);
5235 }
5236
5237 static void ivybridge_init_clock_gating(struct drm_device *dev)
5238 {
5239         struct drm_i915_private *dev_priv = dev->dev_private;
5240         uint32_t snpcr;
5241
5242         I915_WRITE(WM3_LP_ILK, 0);
5243         I915_WRITE(WM2_LP_ILK, 0);
5244         I915_WRITE(WM1_LP_ILK, 0);
5245
5246         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5247
5248         /* WaDisableEarlyCull:ivb */
5249         I915_WRITE(_3D_CHICKEN3,
5250                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5251
5252         /* WaDisableBackToBackFlipFix:ivb */
5253         I915_WRITE(IVB_CHICKEN3,
5254                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5255                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5256
5257         /* WaDisablePSDDualDispatchEnable:ivb */
5258         if (IS_IVB_GT1(dev))
5259                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5260                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5261         else
5262                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5263                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5264
5265         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5266         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5267                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5268
5269         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5270         I915_WRITE(GEN7_L3CNTLREG1,
5271                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5272         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5273                    GEN7_WA_L3_CHICKEN_MODE);
5274         if (IS_IVB_GT1(dev))
5275                 I915_WRITE(GEN7_ROW_CHICKEN2,
5276                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5277         else
5278                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5279                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5280
5281
5282         /* WaForceL3Serialization:ivb */
5283         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5284                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5285
5286         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5287          * gating disable must be set.  Failure to set it results in
5288          * flickering pixels due to Z write ordering failures after
5289          * some amount of runtime in the Mesa "fire" demo, and Unigine
5290          * Sanctuary and Tropics, and apparently anything else with
5291          * alpha test or pixel discard.
5292          *
5293          * According to the spec, bit 11 (RCCUNIT) must also be set,
5294          * but we didn't debug actual testcases to find it out.
5295          *
5296          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5297          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5298          */
5299         I915_WRITE(GEN6_UCGCTL2,
5300                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5301                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5302
5303         /* This is required by WaCatErrorRejectionIssue:ivb */
5304         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5305                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5306                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5307
5308         g4x_disable_trickle_feed(dev);
5309
5310         /* WaVSRefCountFullforceMissDisable:ivb */
5311         gen7_setup_fixed_func_scheduler(dev_priv);
5312
5313         /* WaDisable4x2SubspanOptimization:ivb */
5314         I915_WRITE(CACHE_MODE_1,
5315                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5316
5317         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5318         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5319         snpcr |= GEN6_MBC_SNPCR_MED;
5320         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5321
5322         if (!HAS_PCH_NOP(dev))
5323                 cpt_init_clock_gating(dev);
5324
5325         gen6_check_mch_setup(dev);
5326 }
5327
5328 static void valleyview_init_clock_gating(struct drm_device *dev)
5329 {
5330         struct drm_i915_private *dev_priv = dev->dev_private;
5331
5332         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5333
5334         /* WaDisableEarlyCull:vlv */
5335         I915_WRITE(_3D_CHICKEN3,
5336                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5337
5338         /* WaDisableBackToBackFlipFix:vlv */
5339         I915_WRITE(IVB_CHICKEN3,
5340                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5341                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5342
5343         /* WaDisablePSDDualDispatchEnable:vlv */
5344         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5345                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5346                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5347
5348         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5349         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5350                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5351
5352         /* WaApplyL3ControlAndL3ChickenMode:vlv */
5353         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5354         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5355
5356         /* WaForceL3Serialization:vlv */
5357         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5358                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5359
5360         /* WaDisableDopClockGating:vlv */
5361         I915_WRITE(GEN7_ROW_CHICKEN2,
5362                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5363
5364         /* This is required by WaCatErrorRejectionIssue:vlv */
5365         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5366                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5367                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5368
5369         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5370          * gating disable must be set.  Failure to set it results in
5371          * flickering pixels due to Z write ordering failures after
5372          * some amount of runtime in the Mesa "fire" demo, and Unigine
5373          * Sanctuary and Tropics, and apparently anything else with
5374          * alpha test or pixel discard.
5375          *
5376          * According to the spec, bit 11 (RCCUNIT) must also be set,
5377          * but we didn't debug actual testcases to find it out.
5378          *
5379          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5380          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5381          *
5382          * Also apply WaDisableVDSUnitClockGating:vlv and
5383          * WaDisableRCPBUnitClockGating:vlv.
5384          */
5385         I915_WRITE(GEN6_UCGCTL2,
5386                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5387                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5388                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5389                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5390                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5391
5392         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5393
5394         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5395
5396         I915_WRITE(CACHE_MODE_1,
5397                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5398
5399         /*
5400          * WaDisableVLVClockGating_VBIIssue:vlv
5401          * Disable clock gating on th GCFG unit to prevent a delay
5402          * in the reporting of vblank events.
5403          */
5404         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5405
5406         /* Conservative clock gating settings for now */
5407         I915_WRITE(0x9400, 0xffffffff);
5408         I915_WRITE(0x9404, 0xffffffff);
5409         I915_WRITE(0x9408, 0xffffffff);
5410         I915_WRITE(0x940c, 0xffffffff);
5411         I915_WRITE(0x9410, 0xffffffff);
5412         I915_WRITE(0x9414, 0xffffffff);
5413         I915_WRITE(0x9418, 0xffffffff);
5414 }
5415
5416 static void g4x_init_clock_gating(struct drm_device *dev)
5417 {
5418         struct drm_i915_private *dev_priv = dev->dev_private;
5419         uint32_t dspclk_gate;
5420
5421         I915_WRITE(RENCLK_GATE_D1, 0);
5422         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5423                    GS_UNIT_CLOCK_GATE_DISABLE |
5424                    CL_UNIT_CLOCK_GATE_DISABLE);
5425         I915_WRITE(RAMCLK_GATE_D, 0);
5426         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5427                 OVRUNIT_CLOCK_GATE_DISABLE |
5428                 OVCUNIT_CLOCK_GATE_DISABLE;
5429         if (IS_GM45(dev))
5430                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5431         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5432
5433         /* WaDisableRenderCachePipelinedFlush */
5434         I915_WRITE(CACHE_MODE_0,
5435                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5436
5437         g4x_disable_trickle_feed(dev);
5438 }
5439
5440 static void crestline_init_clock_gating(struct drm_device *dev)
5441 {
5442         struct drm_i915_private *dev_priv = dev->dev_private;
5443
5444         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5445         I915_WRITE(RENCLK_GATE_D2, 0);
5446         I915_WRITE(DSPCLK_GATE_D, 0);
5447         I915_WRITE(RAMCLK_GATE_D, 0);
5448         I915_WRITE16(DEUC, 0);
5449         I915_WRITE(MI_ARB_STATE,
5450                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5451 }
5452
5453 static void broadwater_init_clock_gating(struct drm_device *dev)
5454 {
5455         struct drm_i915_private *dev_priv = dev->dev_private;
5456
5457         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5458                    I965_RCC_CLOCK_GATE_DISABLE |
5459                    I965_RCPB_CLOCK_GATE_DISABLE |
5460                    I965_ISC_CLOCK_GATE_DISABLE |
5461                    I965_FBC_CLOCK_GATE_DISABLE);
5462         I915_WRITE(RENCLK_GATE_D2, 0);
5463         I915_WRITE(MI_ARB_STATE,
5464                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5465 }
5466
5467 static void gen3_init_clock_gating(struct drm_device *dev)
5468 {
5469         struct drm_i915_private *dev_priv = dev->dev_private;
5470         u32 dstate = I915_READ(D_STATE);
5471
5472         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5473                 DSTATE_DOT_CLOCK_GATING;
5474         I915_WRITE(D_STATE, dstate);
5475
5476         if (IS_PINEVIEW(dev))
5477                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5478
5479         /* IIR "flip pending" means done if this bit is set */
5480         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5481 }
5482
5483 static void i85x_init_clock_gating(struct drm_device *dev)
5484 {
5485         struct drm_i915_private *dev_priv = dev->dev_private;
5486
5487         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5488 }
5489
5490 static void i830_init_clock_gating(struct drm_device *dev)
5491 {
5492         struct drm_i915_private *dev_priv = dev->dev_private;
5493
5494         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5495 }
5496
5497 void intel_init_clock_gating(struct drm_device *dev)
5498 {
5499         struct drm_i915_private *dev_priv = dev->dev_private;
5500
5501         dev_priv->display.init_clock_gating(dev);
5502 }
5503
5504 void intel_suspend_hw(struct drm_device *dev)
5505 {
5506         if (HAS_PCH_LPT(dev))
5507                 lpt_suspend_hw(dev);
5508 }
5509
5510 static bool is_always_on_power_domain(struct drm_device *dev,
5511                                       enum intel_display_power_domain domain)
5512 {
5513         unsigned long always_on_domains;
5514
5515         BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
5516
5517         if (IS_HASWELL(dev)) {
5518                 always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
5519         } else {
5520                 WARN_ON(1);
5521                 return true;
5522         }
5523
5524         return BIT(domain) & always_on_domains;
5525 }
5526
5527 /**
5528  * We should only use the power well if we explicitly asked the hardware to
5529  * enable it, so check if it's enabled and also check if we've requested it to
5530  * be enabled.
5531  */
5532 bool intel_display_power_enabled(struct drm_device *dev,
5533                                  enum intel_display_power_domain domain)
5534 {
5535         struct drm_i915_private *dev_priv = dev->dev_private;
5536
5537         if (!HAS_POWER_WELL(dev))
5538                 return true;
5539
5540         if (is_always_on_power_domain(dev, domain))
5541                 return true;
5542
5543         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5544                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5545 }
5546
5547 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5548 {
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550         bool is_enabled, enable_requested;
5551         uint32_t tmp;
5552
5553         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5554         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5555         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5556
5557         if (enable) {
5558                 if (!enable_requested)
5559                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5560                                    HSW_PWR_WELL_ENABLE_REQUEST);
5561
5562                 if (!is_enabled) {
5563                         DRM_DEBUG_KMS("Enabling power well\n");
5564                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5565                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5566                                 DRM_ERROR("Timeout enabling power well\n");
5567                 }
5568         } else {
5569                 if (enable_requested) {
5570                         unsigned long irqflags;
5571                         enum pipe p;
5572
5573                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5574                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5575                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5576
5577                         /*
5578                          * After this, the registers on the pipes that are part
5579                          * of the power well will become zero, so we have to
5580                          * adjust our counters according to that.
5581                          *
5582                          * FIXME: Should we do this in general in
5583                          * drm_vblank_post_modeset?
5584                          */
5585                         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5586                         for_each_pipe(p)
5587                                 if (p != PIPE_A)
5588                                         dev->vblank[p].last = 0;
5589                         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5590                 }
5591         }
5592 }
5593
5594 static void __intel_power_well_get(struct i915_power_well *power_well)
5595 {
5596         if (!power_well->count++)
5597                 __intel_set_power_well(power_well->device, true);
5598 }
5599
5600 static void __intel_power_well_put(struct i915_power_well *power_well)
5601 {
5602         WARN_ON(!power_well->count);
5603         if (!--power_well->count)
5604                 __intel_set_power_well(power_well->device, false);
5605 }
5606
5607 void intel_display_power_get(struct drm_device *dev,
5608                              enum intel_display_power_domain domain)
5609 {
5610         struct drm_i915_private *dev_priv = dev->dev_private;
5611         struct i915_power_well *power_well = &dev_priv->power_well;
5612
5613         if (!HAS_POWER_WELL(dev))
5614                 return;
5615
5616         if (is_always_on_power_domain(dev, domain))
5617                 return;
5618
5619         mutex_lock(&power_well->lock);
5620         __intel_power_well_get(power_well);
5621         mutex_unlock(&power_well->lock);
5622 }
5623
5624 void intel_display_power_put(struct drm_device *dev,
5625                              enum intel_display_power_domain domain)
5626 {
5627         struct drm_i915_private *dev_priv = dev->dev_private;
5628         struct i915_power_well *power_well = &dev_priv->power_well;
5629
5630         if (!HAS_POWER_WELL(dev))
5631                 return;
5632
5633         if (is_always_on_power_domain(dev, domain))
5634                 return;
5635
5636         mutex_lock(&power_well->lock);
5637         __intel_power_well_put(power_well);
5638         mutex_unlock(&power_well->lock);
5639 }
5640
5641 static struct i915_power_well *hsw_pwr;
5642
5643 /* Display audio driver power well request */
5644 void i915_request_power_well(void)
5645 {
5646         if (WARN_ON(!hsw_pwr))
5647                 return;
5648
5649         mutex_lock(&hsw_pwr->lock);
5650         __intel_power_well_get(hsw_pwr);
5651         mutex_unlock(&hsw_pwr->lock);
5652 }
5653 EXPORT_SYMBOL_GPL(i915_request_power_well);
5654
5655 /* Display audio driver power well release */
5656 void i915_release_power_well(void)
5657 {
5658         if (WARN_ON(!hsw_pwr))
5659                 return;
5660
5661         mutex_lock(&hsw_pwr->lock);
5662         __intel_power_well_put(hsw_pwr);
5663         mutex_unlock(&hsw_pwr->lock);
5664 }
5665 EXPORT_SYMBOL_GPL(i915_release_power_well);
5666
5667 int i915_init_power_well(struct drm_device *dev)
5668 {
5669         struct drm_i915_private *dev_priv = dev->dev_private;
5670
5671         hsw_pwr = &dev_priv->power_well;
5672
5673         hsw_pwr->device = dev;
5674         mutex_init(&hsw_pwr->lock);
5675         hsw_pwr->count = 0;
5676
5677         return 0;
5678 }
5679
5680 void i915_remove_power_well(struct drm_device *dev)
5681 {
5682         hsw_pwr = NULL;
5683 }
5684
5685 void intel_set_power_well(struct drm_device *dev, bool enable)
5686 {
5687         struct drm_i915_private *dev_priv = dev->dev_private;
5688         struct i915_power_well *power_well = &dev_priv->power_well;
5689
5690         if (!HAS_POWER_WELL(dev))
5691                 return;
5692
5693         if (!i915_disable_power_well && !enable)
5694                 return;
5695
5696         mutex_lock(&power_well->lock);
5697
5698         /*
5699          * This function will only ever contribute one
5700          * to the power well reference count. i915_request
5701          * is what tracks whether we have or have not
5702          * added the one to the reference count.
5703          */
5704         if (power_well->i915_request == enable)
5705                 goto out;
5706
5707         power_well->i915_request = enable;
5708
5709         if (enable)
5710                 __intel_power_well_get(power_well);
5711         else
5712                 __intel_power_well_put(power_well);
5713
5714  out:
5715         mutex_unlock(&power_well->lock);
5716 }
5717
5718 static void intel_resume_power_well(struct drm_device *dev)
5719 {
5720         struct drm_i915_private *dev_priv = dev->dev_private;
5721         struct i915_power_well *power_well = &dev_priv->power_well;
5722
5723         if (!HAS_POWER_WELL(dev))
5724                 return;
5725
5726         mutex_lock(&power_well->lock);
5727         __intel_set_power_well(dev, power_well->count > 0);
5728         mutex_unlock(&power_well->lock);
5729 }
5730
5731 /*
5732  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5733  * when not needed anymore. We have 4 registers that can request the power well
5734  * to be enabled, and it will only be disabled if none of the registers is
5735  * requesting it to be enabled.
5736  */
5737 void intel_init_power_well(struct drm_device *dev)
5738 {
5739         struct drm_i915_private *dev_priv = dev->dev_private;
5740
5741         if (!HAS_POWER_WELL(dev))
5742                 return;
5743
5744         /* For now, we need the power well to be always enabled. */
5745         intel_set_power_well(dev, true);
5746         intel_resume_power_well(dev);
5747
5748         /* We're taking over the BIOS, so clear any requests made by it since
5749          * the driver is in charge now. */
5750         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5751                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5752 }
5753
5754 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5755 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5756 {
5757         hsw_disable_package_c8(dev_priv);
5758 }
5759
5760 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5761 {
5762         hsw_enable_package_c8(dev_priv);
5763 }
5764
5765 /* Set up chip specific power management-related functions */
5766 void intel_init_pm(struct drm_device *dev)
5767 {
5768         struct drm_i915_private *dev_priv = dev->dev_private;
5769
5770         if (I915_HAS_FBC(dev)) {
5771                 if (HAS_PCH_SPLIT(dev)) {
5772                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5773                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5774                                 dev_priv->display.enable_fbc =
5775                                         gen7_enable_fbc;
5776                         else
5777                                 dev_priv->display.enable_fbc =
5778                                         ironlake_enable_fbc;
5779                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5780                 } else if (IS_GM45(dev)) {
5781                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5782                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5783                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5784                 } else if (IS_CRESTLINE(dev)) {
5785                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5786                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5787                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5788                 }
5789                 /* 855GM needs testing */
5790         }
5791
5792         /* For cxsr */
5793         if (IS_PINEVIEW(dev))
5794                 i915_pineview_get_mem_freq(dev);
5795         else if (IS_GEN5(dev))
5796                 i915_ironlake_get_mem_freq(dev);
5797
5798         /* For FIFO watermark updates */
5799         if (HAS_PCH_SPLIT(dev)) {
5800                 intel_setup_wm_latency(dev);
5801
5802                 if (IS_GEN5(dev)) {
5803                         if (dev_priv->wm.pri_latency[1] &&
5804                             dev_priv->wm.spr_latency[1] &&
5805                             dev_priv->wm.cur_latency[1])
5806                                 dev_priv->display.update_wm = ironlake_update_wm;
5807                         else {
5808                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5809                                               "Disable CxSR\n");
5810                                 dev_priv->display.update_wm = NULL;
5811                         }
5812                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5813                 } else if (IS_GEN6(dev)) {
5814                         if (dev_priv->wm.pri_latency[0] &&
5815                             dev_priv->wm.spr_latency[0] &&
5816                             dev_priv->wm.cur_latency[0]) {
5817                                 dev_priv->display.update_wm = sandybridge_update_wm;
5818                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5819                         } else {
5820                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5821                                               "Disable CxSR\n");
5822                                 dev_priv->display.update_wm = NULL;
5823                         }
5824                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5825                 } else if (IS_IVYBRIDGE(dev)) {
5826                         if (dev_priv->wm.pri_latency[0] &&
5827                             dev_priv->wm.spr_latency[0] &&
5828                             dev_priv->wm.cur_latency[0]) {
5829                                 dev_priv->display.update_wm = ivybridge_update_wm;
5830                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5831                         } else {
5832                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5833                                               "Disable CxSR\n");
5834                                 dev_priv->display.update_wm = NULL;
5835                         }
5836                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5837                 } else if (IS_HASWELL(dev)) {
5838                         if (dev_priv->wm.pri_latency[0] &&
5839                             dev_priv->wm.spr_latency[0] &&
5840                             dev_priv->wm.cur_latency[0]) {
5841                                 dev_priv->display.update_wm = haswell_update_wm;
5842                                 dev_priv->display.update_sprite_wm =
5843                                         haswell_update_sprite_wm;
5844                         } else {
5845                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5846                                               "Disable CxSR\n");
5847                                 dev_priv->display.update_wm = NULL;
5848                         }
5849                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5850                 } else
5851                         dev_priv->display.update_wm = NULL;
5852         } else if (IS_VALLEYVIEW(dev)) {
5853                 dev_priv->display.update_wm = valleyview_update_wm;
5854                 dev_priv->display.init_clock_gating =
5855                         valleyview_init_clock_gating;
5856         } else if (IS_PINEVIEW(dev)) {
5857                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5858                                             dev_priv->is_ddr3,
5859                                             dev_priv->fsb_freq,
5860                                             dev_priv->mem_freq)) {
5861                         DRM_INFO("failed to find known CxSR latency "
5862                                  "(found ddr%s fsb freq %d, mem freq %d), "
5863                                  "disabling CxSR\n",
5864                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5865                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5866                         /* Disable CxSR and never update its watermark again */
5867                         pineview_disable_cxsr(dev);
5868                         dev_priv->display.update_wm = NULL;
5869                 } else
5870                         dev_priv->display.update_wm = pineview_update_wm;
5871                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5872         } else if (IS_G4X(dev)) {
5873                 dev_priv->display.update_wm = g4x_update_wm;
5874                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5875         } else if (IS_GEN4(dev)) {
5876                 dev_priv->display.update_wm = i965_update_wm;
5877                 if (IS_CRESTLINE(dev))
5878                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5879                 else if (IS_BROADWATER(dev))
5880                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5881         } else if (IS_GEN3(dev)) {
5882                 dev_priv->display.update_wm = i9xx_update_wm;
5883                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5884                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5885         } else if (IS_I865G(dev)) {
5886                 dev_priv->display.update_wm = i830_update_wm;
5887                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5888                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5889         } else if (IS_I85X(dev)) {
5890                 dev_priv->display.update_wm = i9xx_update_wm;
5891                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5892                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5893         } else {
5894                 dev_priv->display.update_wm = i830_update_wm;
5895                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5896                 if (IS_845G(dev))
5897                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5898                 else
5899                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5900         }
5901 }
5902
5903 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5904 {
5905         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5906
5907         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5908                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5909                 return -EAGAIN;
5910         }
5911
5912         I915_WRITE(GEN6_PCODE_DATA, *val);
5913         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5914
5915         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5916                      500)) {
5917                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5918                 return -ETIMEDOUT;
5919         }
5920
5921         *val = I915_READ(GEN6_PCODE_DATA);
5922         I915_WRITE(GEN6_PCODE_DATA, 0);
5923
5924         return 0;
5925 }
5926
5927 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5928 {
5929         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5930
5931         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5932                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5933                 return -EAGAIN;
5934         }
5935
5936         I915_WRITE(GEN6_PCODE_DATA, val);
5937         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5938
5939         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5940                      500)) {
5941                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5942                 return -ETIMEDOUT;
5943         }
5944
5945         I915_WRITE(GEN6_PCODE_DATA, 0);
5946
5947         return 0;
5948 }
5949
5950 int vlv_gpu_freq(int ddr_freq, int val)
5951 {
5952         int mult, base;
5953
5954         switch (ddr_freq) {
5955         case 800:
5956                 mult = 20;
5957                 base = 120;
5958                 break;
5959         case 1066:
5960                 mult = 22;
5961                 base = 133;
5962                 break;
5963         case 1333:
5964                 mult = 21;
5965                 base = 125;
5966                 break;
5967         default:
5968                 return -1;
5969         }
5970
5971         return ((val - 0xbd) * mult) + base;
5972 }
5973
5974 int vlv_freq_opcode(int ddr_freq, int val)
5975 {
5976         int mult, base;
5977
5978         switch (ddr_freq) {
5979         case 800:
5980                 mult = 20;
5981                 base = 120;
5982                 break;
5983         case 1066:
5984                 mult = 22;
5985                 base = 133;
5986                 break;
5987         case 1333:
5988                 mult = 21;
5989                 base = 125;
5990                 break;
5991         default:
5992                 return -1;
5993         }
5994
5995         val /= mult;
5996         val -= base / mult;
5997         val += 0xbd;
5998
5999         if (val > 0xea)
6000                 val = 0xea;
6001
6002         return val;
6003 }
6004
6005 void intel_pm_init(struct drm_device *dev)
6006 {
6007         struct drm_i915_private *dev_priv = dev->dev_private;
6008
6009         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6010                           intel_gen6_powersave_work);
6011 }
6012