drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <drm/i915_powerwell.h>
  34
  35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  36  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  37  * during in-memory transfers and, therefore, reduce the power packet.
  38  *
  39  * The benefits of FBC are mostly visible with solid backgrounds and
  40  * variation-less patterns.
  41  *
  42  * FBC-related functionality can be enabled by the means of the
  43  * i915.i915_enable_fbc parameter
  44  */
  45
  46 static void i8xx_disable_fbc(struct drm_device *dev)
  47 {
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         u32 fbc_ctl;
  50
  51         /* Disable compression */
  52         fbc_ctl = I915_READ(FBC_CONTROL);
  53         if ((fbc_ctl & FBC_CTL_EN) == 0)
  54                 return;
  55
  56         fbc_ctl &= ~FBC_CTL_EN;
  57         I915_WRITE(FBC_CONTROL, fbc_ctl);
  58
  59         /* Wait for compressing bit to clear */
  60         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  61                 DRM_DEBUG_KMS("FBC idle timed out\n");
  62                 return;
  63         }
  64
  65         DRM_DEBUG_KMS("disabled FBC\n");
  66 }
  67
  68 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  69 {
  70         struct drm_device *dev = crtc->dev;
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         struct drm_framebuffer *fb = crtc->fb;
  73         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  74         struct drm_i915_gem_object *obj = intel_fb->obj;
  75         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  76         int cfb_pitch;
  77         int plane, i;
  78         u32 fbc_ctl, fbc_ctl2;
  79
  80         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
  81         if (fb->pitches[0] < cfb_pitch)
  82                 cfb_pitch = fb->pitches[0];
  83
  84         /* FBC_CTL wants 64B units */
  85         cfb_pitch = (cfb_pitch / 64) - 1;
  86         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  87
  88         /* Clear old tags */
  89         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  90                 I915_WRITE(FBC_TAG + (i * 4), 0);
  91
  92         /* Set it up... */
  93         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  94         fbc_ctl2 |= plane;
  95         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  96         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  97
  98         /* enable it... */
  99         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 100         if (IS_I945GM(dev))
 101                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 102         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 103         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 104         fbc_ctl |= obj->fence_reg;
 105         I915_WRITE(FBC_CONTROL, fbc_ctl);
 106
 107         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 108                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 109 }
 110
 111 static bool i8xx_fbc_enabled(struct drm_device *dev)
 112 {
 113         struct drm_i915_private *dev_priv = dev->dev_private;
 114
 115         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 116 }
 117
 118 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 119 {
 120         struct drm_device *dev = crtc->dev;
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122         struct drm_framebuffer *fb = crtc->fb;
 123         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 124         struct drm_i915_gem_object *obj = intel_fb->obj;
 125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 126         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 127         unsigned long stall_watermark = 200;
 128         u32 dpfc_ctl;
 129
 130         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 131         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 132         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 133
 134         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 135                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 136                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 137         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 138
 139         /* enable it... */
 140         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 141
 142         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 143 }
 144
 145 static void g4x_disable_fbc(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = dev->dev_private;
 148         u32 dpfc_ctl;
 149
 150         /* Disable compression */
 151         dpfc_ctl = I915_READ(DPFC_CONTROL);
 152         if (dpfc_ctl & DPFC_CTL_EN) {
 153                 dpfc_ctl &= ~DPFC_CTL_EN;
 154                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 155
 156                 DRM_DEBUG_KMS("disabled FBC\n");
 157         }
 158 }
 159
 160 static bool g4x_fbc_enabled(struct drm_device *dev)
 161 {
 162         struct drm_i915_private *dev_priv = dev->dev_private;
 163
 164         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 165 }
 166
 167 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 168 {
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         u32 blt_ecoskpd;
 171
 172         /* Make sure blitter notifies FBC of writes */
 173         gen6_gt_force_wake_get(dev_priv);
 174         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 175         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 176                 GEN6_BLITTER_LOCK_SHIFT;
 177         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 178         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 179         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 180         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 181                          GEN6_BLITTER_LOCK_SHIFT);
 182         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 183         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 184         gen6_gt_force_wake_put(dev_priv);
 185 }
 186
 187 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 188 {
 189         struct drm_device *dev = crtc->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct drm_framebuffer *fb = crtc->fb;
 192         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 193         struct drm_i915_gem_object *obj = intel_fb->obj;
 194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 195         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 196         unsigned long stall_watermark = 200;
 197         u32 dpfc_ctl;
 198
 199         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 200         dpfc_ctl &= DPFC_RESERVED;
 201         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 202         /* Set persistent mode for front-buffer rendering, ala X. */
 203         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 204         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 205         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 206
 207         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 208                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 209                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 210         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 211         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 212         /* enable it... */
 213         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 214
 215         if (IS_GEN6(dev)) {
 216                 I915_WRITE(SNB_DPFC_CTL_SA,
 217                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 218                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 219                 sandybridge_blit_fbc_update(dev);
 220         }
 221
 222         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 223 }
 224
 225 static void ironlake_disable_fbc(struct drm_device *dev)
 226 {
 227         struct drm_i915_private *dev_priv = dev->dev_private;
 228         u32 dpfc_ctl;
 229
 230         /* Disable compression */
 231         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 232         if (dpfc_ctl & DPFC_CTL_EN) {
 233                 dpfc_ctl &= ~DPFC_CTL_EN;
 234                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 235
 236                 if (IS_IVYBRIDGE(dev))
 237                         /* WaFbcDisableDpfcClockGating:ivb */
 238                         I915_WRITE(ILK_DSPCLK_GATE_D,
 239                                    I915_READ(ILK_DSPCLK_GATE_D) &
 240                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 241
 242                 if (IS_HASWELL(dev))
 243                         /* WaFbcDisableDpfcClockGating:hsw */
 244                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 245                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
 246                                    ~HSW_DPFC_GATING_DISABLE);
 247
 248                 DRM_DEBUG_KMS("disabled FBC\n");
 249         }
 250 }
 251
 252 static bool ironlake_fbc_enabled(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255
 256         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 257 }
 258
 259 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 260 {
 261         struct drm_device *dev = crtc->dev;
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263         struct drm_framebuffer *fb = crtc->fb;
 264         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 265         struct drm_i915_gem_object *obj = intel_fb->obj;
 266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 267
 268         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 269
 270         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 271                    IVB_DPFC_CTL_FENCE_EN |
 272                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 273
 274         if (IS_IVYBRIDGE(dev)) {
 275                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 276                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 277                 /* WaFbcDisableDpfcClockGating:ivb */
 278                 I915_WRITE(ILK_DSPCLK_GATE_D,
 279                            I915_READ(ILK_DSPCLK_GATE_D) |
 280                            ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 281         } else {
 282                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 283                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 284                            HSW_BYPASS_FBC_QUEUE);
 285                 /* WaFbcDisableDpfcClockGating:hsw */
 286                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 287                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
 288                            HSW_DPFC_GATING_DISABLE);
 289         }
 290
 291         I915_WRITE(SNB_DPFC_CTL_SA,
 292                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 293         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 294
 295         sandybridge_blit_fbc_update(dev);
 296
 297         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 298 }
 299
 300 bool intel_fbc_enabled(struct drm_device *dev)
 301 {
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303
 304         if (!dev_priv->display.fbc_enabled)
 305                 return false;
 306
 307         return dev_priv->display.fbc_enabled(dev);
 308 }
 309
 310 static void intel_fbc_work_fn(struct work_struct *__work)
 311 {
 312         struct intel_fbc_work *work =
 313                 container_of(to_delayed_work(__work),
 314                              struct intel_fbc_work, work);
 315         struct drm_device *dev = work->crtc->dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317
 318         mutex_lock(&dev->struct_mutex);
 319         if (work == dev_priv->fbc.fbc_work) {
 320                 /* Double check that we haven't switched fb without cancelling
 321                  * the prior work.
 322                  */
 323                 if (work->crtc->fb == work->fb) {
 324                         dev_priv->display.enable_fbc(work->crtc,
 325                                                      work->interval);
 326
 327                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 328                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 329                         dev_priv->fbc.y = work->crtc->y;
 330                 }
 331
 332                 dev_priv->fbc.fbc_work = NULL;
 333         }
 334         mutex_unlock(&dev->struct_mutex);
 335
 336         kfree(work);
 337 }
 338
 339 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 340 {
 341         if (dev_priv->fbc.fbc_work == NULL)
 342                 return;
 343
 344         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 345
 346         /* Synchronisation is provided by struct_mutex and checking of
 347          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 348          * entirely asynchronously.
 349          */
 350         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 351                 /* tasklet was killed before being run, clean up */
 352                 kfree(dev_priv->fbc.fbc_work);
 353
 354         /* Mark the work as no longer wanted so that if it does
 355          * wake-up (because the work was already running and waiting
 356          * for our mutex), it will discover that is no longer
 357          * necessary to run.
 358          */
 359         dev_priv->fbc.fbc_work = NULL;
 360 }
 361
 362 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 363 {
 364         struct intel_fbc_work *work;
 365         struct drm_device *dev = crtc->dev;
 366         struct drm_i915_private *dev_priv = dev->dev_private;
 367
 368         if (!dev_priv->display.enable_fbc)
 369                 return;
 370
 371         intel_cancel_fbc_work(dev_priv);
 372
 373         work = kzalloc(sizeof(*work), GFP_KERNEL);
 374         if (work == NULL) {
 375                 DRM_ERROR("Failed to allocate FBC work structure\n");
 376                 dev_priv->display.enable_fbc(crtc, interval);
 377                 return;
 378         }
 379
 380         work->crtc = crtc;
 381         work->fb = crtc->fb;
 382         work->interval = interval;
 383         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 384
 385         dev_priv->fbc.fbc_work = work;
 386
 387         /* Delay the actual enabling to let pageflipping cease and the
 388          * display to settle before starting the compression. Note that
 389          * this delay also serves a second purpose: it allows for a
 390          * vblank to pass after disabling the FBC before we attempt
 391          * to modify the control registers.
 392          *
 393          * A more complicated solution would involve tracking vblanks
 394          * following the termination of the page-flipping sequence
 395          * and indeed performing the enable as a co-routine and not
 396          * waiting synchronously upon the vblank.
 397          *
 398          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 399          */
 400         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 401 }
 402
 403 void intel_disable_fbc(struct drm_device *dev)
 404 {
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406
 407         intel_cancel_fbc_work(dev_priv);
 408
 409         if (!dev_priv->display.disable_fbc)
 410                 return;
 411
 412         dev_priv->display.disable_fbc(dev);
 413         dev_priv->fbc.plane = -1;
 414 }
 415
 416 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 417                               enum no_fbc_reason reason)
 418 {
 419         if (dev_priv->fbc.no_fbc_reason == reason)
 420                 return false;
 421
 422         dev_priv->fbc.no_fbc_reason = reason;
 423         return true;
 424 }
 425
 426 /**
 427  * intel_update_fbc - enable/disable FBC as needed
 428  * @dev: the drm_device
 429  *
 430  * Set up the framebuffer compression hardware at mode set time.  We
 431  * enable it if possible:
 432  *   - plane A only (on pre-965)
 433  *   - no pixel mulitply/line duplication
 434  *   - no alpha buffer discard
 435  *   - no dual wide
 436  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 437  *
 438  * We can't assume that any compression will take place (worst case),
 439  * so the compressed buffer has to be the same size as the uncompressed
 440  * one.  It also must reside (along with the line length buffer) in
 441  * stolen memory.
 442  *
 443  * We need to enable/disable FBC on a global basis.
 444  */
 445 void intel_update_fbc(struct drm_device *dev)
 446 {
 447         struct drm_i915_private *dev_priv = dev->dev_private;
 448         struct drm_crtc *crtc = NULL, *tmp_crtc;
 449         struct intel_crtc *intel_crtc;
 450         struct drm_framebuffer *fb;
 451         struct intel_framebuffer *intel_fb;
 452         struct drm_i915_gem_object *obj;
 453         const struct drm_display_mode *adjusted_mode;
 454         unsigned int max_width, max_height;
 455
 456         if (!I915_HAS_FBC(dev)) {
 457                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 458                 return;
 459         }
 460
 461         if (!i915_powersave) {
 462                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 463                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 464                 return;
 465         }
 466
 467         /*
 468          * If FBC is already on, we just have to verify that we can
 469          * keep it that way...
 470          * Need to disable if:
 471          *   - more than one pipe is active
 472          *   - changing FBC params (stride, fence, mode)
 473          *   - new fb is too large to fit in compressed buffer
 474          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 475          */
 476         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 477                 if (intel_crtc_active(tmp_crtc) &&
 478                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 479                         if (crtc) {
 480                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 481                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 482                                 goto out_disable;
 483                         }
 484                         crtc = tmp_crtc;
 485                 }
 486         }
 487
 488         if (!crtc || crtc->fb == NULL) {
 489                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 490                         DRM_DEBUG_KMS("no output, disabling\n");
 491                 goto out_disable;
 492         }
 493
 494         intel_crtc = to_intel_crtc(crtc);
 495         fb = crtc->fb;
 496         intel_fb = to_intel_framebuffer(fb);
 497         obj = intel_fb->obj;
 498         adjusted_mode = &intel_crtc->config.adjusted_mode;
 499
 500         if (i915_enable_fbc < 0 &&
 501             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 502                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 503                         DRM_DEBUG_KMS("disabled per chip default\n");
 504                 goto out_disable;
 505         }
 506         if (!i915_enable_fbc) {
 507                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 508                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 509                 goto out_disable;
 510         }
 511         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 512             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 513                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 514                         DRM_DEBUG_KMS("mode incompatible with compression, "
 515                                       "disabling\n");
 516                 goto out_disable;
 517         }
 518
 519         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 520                 max_width = 4096;
 521                 max_height = 2048;
 522         } else {
 523                 max_width = 2048;
 524                 max_height = 1536;
 525         }
 526         if (intel_crtc->config.pipe_src_w > max_width ||
 527             intel_crtc->config.pipe_src_h > max_height) {
 528                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 529                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 530                 goto out_disable;
 531         }
 532         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 533             intel_crtc->plane != 0) {
 534                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 535                         DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 536                 goto out_disable;
 537         }
 538
 539         /* The use of a CPU fence is mandatory in order to detect writes
 540          * by the CPU to the scanout and trigger updates to the FBC.
 541          */
 542         if (obj->tiling_mode != I915_TILING_X ||
 543             obj->fence_reg == I915_FENCE_REG_NONE) {
 544                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 545                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 546                 goto out_disable;
 547         }
 548
 549         /* If the kernel debugger is active, always disable compression */
 550         if (in_dbg_master())
 551                 goto out_disable;
 552
 553         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 554                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 555                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 556                 goto out_disable;
 557         }
 558
 559         /* If the scanout has not changed, don't modify the FBC settings.
 560          * Note that we make the fundamental assumption that the fb->obj
 561          * cannot be unpinned (and have its GTT offset and fence revoked)
 562          * without first being decoupled from the scanout and FBC disabled.
 563          */
 564         if (dev_priv->fbc.plane == intel_crtc->plane &&
 565             dev_priv->fbc.fb_id == fb->base.id &&
 566             dev_priv->fbc.y == crtc->y)
 567                 return;
 568
 569         if (intel_fbc_enabled(dev)) {
 570                 /* We update FBC along two paths, after changing fb/crtc
 571                  * configuration (modeswitching) and after page-flipping
 572                  * finishes. For the latter, we know that not only did
 573                  * we disable the FBC at the start of the page-flip
 574                  * sequence, but also more than one vblank has passed.
 575                  *
 576                  * For the former case of modeswitching, it is possible
 577                  * to switch between two FBC valid configurations
 578                  * instantaneously so we do need to disable the FBC
 579                  * before we can modify its control registers. We also
 580                  * have to wait for the next vblank for that to take
 581                  * effect. However, since we delay enabling FBC we can
 582                  * assume that a vblank has passed since disabling and
 583                  * that we can safely alter the registers in the deferred
 584                  * callback.
 585                  *
 586                  * In the scenario that we go from a valid to invalid
 587                  * and then back to valid FBC configuration we have
 588                  * no strict enforcement that a vblank occurred since
 589                  * disabling the FBC. However, along all current pipe
 590                  * disabling paths we do need to wait for a vblank at
 591                  * some point. And we wait before enabling FBC anyway.
 592                  */
 593                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 594                 intel_disable_fbc(dev);
 595         }
 596
 597         intel_enable_fbc(crtc, 500);
 598         dev_priv->fbc.no_fbc_reason = FBC_OK;
 599         return;
 600
 601 out_disable:
 602         /* Multiple disables should be harmless */
 603         if (intel_fbc_enabled(dev)) {
 604                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 605                 intel_disable_fbc(dev);
 606         }
 607         i915_gem_stolen_cleanup_compression(dev);
 608 }
 609
 610 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 611 {
 612         drm_i915_private_t *dev_priv = dev->dev_private;
 613         u32 tmp;
 614
 615         tmp = I915_READ(CLKCFG);
 616
 617         switch (tmp & CLKCFG_FSB_MASK) {
 618         case CLKCFG_FSB_533:
 619                 dev_priv->fsb_freq = 533; /* 133*4 */
 620                 break;
 621         case CLKCFG_FSB_800:
 622                 dev_priv->fsb_freq = 800; /* 200*4 */
 623                 break;
 624         case CLKCFG_FSB_667:
 625                 dev_priv->fsb_freq =  667; /* 167*4 */
 626                 break;
 627         case CLKCFG_FSB_400:
 628                 dev_priv->fsb_freq = 400; /* 100*4 */
 629                 break;
 630         }
 631
 632         switch (tmp & CLKCFG_MEM_MASK) {
 633         case CLKCFG_MEM_533:
 634                 dev_priv->mem_freq = 533;
 635                 break;
 636         case CLKCFG_MEM_667:
 637                 dev_priv->mem_freq = 667;
 638                 break;
 639         case CLKCFG_MEM_800:
 640                 dev_priv->mem_freq = 800;
 641                 break;
 642         }
 643
 644         /* detect pineview DDR3 setting */
 645         tmp = I915_READ(CSHRDDR3CTL);
 646         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 647 }
 648
 649 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 650 {
 651         drm_i915_private_t *dev_priv = dev->dev_private;
 652         u16 ddrpll, csipll;
 653
 654         ddrpll = I915_READ16(DDRMPLL1);
 655         csipll = I915_READ16(CSIPLL0);
 656
 657         switch (ddrpll & 0xff) {
 658         case 0xc:
 659                 dev_priv->mem_freq = 800;
 660                 break;
 661         case 0x10:
 662                 dev_priv->mem_freq = 1066;
 663                 break;
 664         case 0x14:
 665                 dev_priv->mem_freq = 1333;
 666                 break;
 667         case 0x18:
 668                 dev_priv->mem_freq = 1600;
 669                 break;
 670         default:
 671                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 672                                  ddrpll & 0xff);
 673                 dev_priv->mem_freq = 0;
 674                 break;
 675         }
 676
 677         dev_priv->ips.r_t = dev_priv->mem_freq;
 678
 679         switch (csipll & 0x3ff) {
 680         case 0x00c:
 681                 dev_priv->fsb_freq = 3200;
 682                 break;
 683         case 0x00e:
 684                 dev_priv->fsb_freq = 3733;
 685                 break;
 686         case 0x010:
 687                 dev_priv->fsb_freq = 4266;
 688                 break;
 689         case 0x012:
 690                 dev_priv->fsb_freq = 4800;
 691                 break;
 692         case 0x014:
 693                 dev_priv->fsb_freq = 5333;
 694                 break;
 695         case 0x016:
 696                 dev_priv->fsb_freq = 5866;
 697                 break;
 698         case 0x018:
 699                 dev_priv->fsb_freq = 6400;
 700                 break;
 701         default:
 702                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 703                                  csipll & 0x3ff);
 704                 dev_priv->fsb_freq = 0;
 705                 break;
 706         }
 707
 708         if (dev_priv->fsb_freq == 3200) {
 709                 dev_priv->ips.c_m = 0;
 710         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 711                 dev_priv->ips.c_m = 1;
 712         } else {
 713                 dev_priv->ips.c_m = 2;
 714         }
 715 }
 716
 717 static const struct cxsr_latency cxsr_latency_table[] = {
 718         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 719         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 720         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 721         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 722         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 723
 724         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 725         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 726         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 727         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 728         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 729
 730         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 731         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 732         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 733         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 734         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 735
 736         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 737         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 738         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 739         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 740         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 741
 742         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 743         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 744         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 745         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 746         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 747
 748         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 749         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 750         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 751         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 752         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 753 };
 754
 755 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 756                                                          int is_ddr3,
 757                                                          int fsb,
 758                                                          int mem)
 759 {
 760         const struct cxsr_latency *latency;
 761         int i;
 762
 763         if (fsb == 0 || mem == 0)
 764                 return NULL;
 765
 766         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 767                 latency = &cxsr_latency_table[i];
 768                 if (is_desktop == latency->is_desktop &&
 769                     is_ddr3 == latency->is_ddr3 &&
 770                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 771                         return latency;
 772         }
 773
 774         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 775
 776         return NULL;
 777 }
 778
 779 static void pineview_disable_cxsr(struct drm_device *dev)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782
 783         /* deactivate cxsr */
 784         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 785 }
 786
 787 /*
 788  * Latency for FIFO fetches is dependent on several factors:
 789  *   - memory configuration (speed, channels)
 790  *   - chipset
 791  *   - current MCH state
 792  * It can be fairly high in some situations, so here we assume a fairly
 793  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 794  * set this value too high, the FIFO will fetch frequently to stay full)
 795  * and power consumption (set it too low to save power and we might see
 796  * FIFO underruns and display "flicker").
 797  *
 798  * A value of 5us seems to be a good balance; safe for very low end
 799  * platforms but not overly aggressive on lower latency configs.
 800  */
 801 static const int latency_ns = 5000;
 802
 803 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         uint32_t dsparb = I915_READ(DSPARB);
 807         int size;
 808
 809         size = dsparb & 0x7f;
 810         if (plane)
 811                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 812
 813         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 814                       plane ? "B" : "A", size);
 815
 816         return size;
 817 }
 818
 819 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 820 {
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822         uint32_t dsparb = I915_READ(DSPARB);
 823         int size;
 824
 825         size = dsparb & 0x1ff;
 826         if (plane)
 827                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 828         size >>= 1; /* Convert to cachelines */
 829
 830         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 831                       plane ? "B" : "A", size);
 832
 833         return size;
 834 }
 835
 836 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 837 {
 838         struct drm_i915_private *dev_priv = dev->dev_private;
 839         uint32_t dsparb = I915_READ(DSPARB);
 840         int size;
 841
 842         size = dsparb & 0x7f;
 843         size >>= 2; /* Convert to cachelines */
 844
 845         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 846                       plane ? "B" : "A",
 847                       size);
 848
 849         return size;
 850 }
 851
 852 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 853 {
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855         uint32_t dsparb = I915_READ(DSPARB);
 856         int size;
 857
 858         size = dsparb & 0x7f;
 859         size >>= 1; /* Convert to cachelines */
 860
 861         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 862                       plane ? "B" : "A", size);
 863
 864         return size;
 865 }
 866
 867 /* Pineview has different values for various configs */
 868 static const struct intel_watermark_params pineview_display_wm = {
 869         PINEVIEW_DISPLAY_FIFO,
 870         PINEVIEW_MAX_WM,
 871         PINEVIEW_DFT_WM,
 872         PINEVIEW_GUARD_WM,
 873         PINEVIEW_FIFO_LINE_SIZE
 874 };
 875 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 876         PINEVIEW_DISPLAY_FIFO,
 877         PINEVIEW_MAX_WM,
 878         PINEVIEW_DFT_HPLLOFF_WM,
 879         PINEVIEW_GUARD_WM,
 880         PINEVIEW_FIFO_LINE_SIZE
 881 };
 882 static const struct intel_watermark_params pineview_cursor_wm = {
 883         PINEVIEW_CURSOR_FIFO,
 884         PINEVIEW_CURSOR_MAX_WM,
 885         PINEVIEW_CURSOR_DFT_WM,
 886         PINEVIEW_CURSOR_GUARD_WM,
 887         PINEVIEW_FIFO_LINE_SIZE,
 888 };
 889 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 890         PINEVIEW_CURSOR_FIFO,
 891         PINEVIEW_CURSOR_MAX_WM,
 892         PINEVIEW_CURSOR_DFT_WM,
 893         PINEVIEW_CURSOR_GUARD_WM,
 894         PINEVIEW_FIFO_LINE_SIZE
 895 };
 896 static const struct intel_watermark_params g4x_wm_info = {
 897         G4X_FIFO_SIZE,
 898         G4X_MAX_WM,
 899         G4X_MAX_WM,
 900         2,
 901         G4X_FIFO_LINE_SIZE,
 902 };
 903 static const struct intel_watermark_params g4x_cursor_wm_info = {
 904         I965_CURSOR_FIFO,
 905         I965_CURSOR_MAX_WM,
 906         I965_CURSOR_DFT_WM,
 907         2,
 908         G4X_FIFO_LINE_SIZE,
 909 };
 910 static const struct intel_watermark_params valleyview_wm_info = {
 911         VALLEYVIEW_FIFO_SIZE,
 912         VALLEYVIEW_MAX_WM,
 913         VALLEYVIEW_MAX_WM,
 914         2,
 915         G4X_FIFO_LINE_SIZE,
 916 };
 917 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 918         I965_CURSOR_FIFO,
 919         VALLEYVIEW_CURSOR_MAX_WM,
 920         I965_CURSOR_DFT_WM,
 921         2,
 922         G4X_FIFO_LINE_SIZE,
 923 };
 924 static const struct intel_watermark_params i965_cursor_wm_info = {
 925         I965_CURSOR_FIFO,
 926         I965_CURSOR_MAX_WM,
 927         I965_CURSOR_DFT_WM,
 928         2,
 929         I915_FIFO_LINE_SIZE,
 930 };
 931 static const struct intel_watermark_params i945_wm_info = {
 932         I945_FIFO_SIZE,
 933         I915_MAX_WM,
 934         1,
 935         2,
 936         I915_FIFO_LINE_SIZE
 937 };
 938 static const struct intel_watermark_params i915_wm_info = {
 939         I915_FIFO_SIZE,
 940         I915_MAX_WM,
 941         1,
 942         2,
 943         I915_FIFO_LINE_SIZE
 944 };
 945 static const struct intel_watermark_params i855_wm_info = {
 946         I855GM_FIFO_SIZE,
 947         I915_MAX_WM,
 948         1,
 949         2,
 950         I830_FIFO_LINE_SIZE
 951 };
 952 static const struct intel_watermark_params i830_wm_info = {
 953         I830_FIFO_SIZE,
 954         I915_MAX_WM,
 955         1,
 956         2,
 957         I830_FIFO_LINE_SIZE
 958 };
 959
 960 static const struct intel_watermark_params ironlake_display_wm_info = {
 961         ILK_DISPLAY_FIFO,
 962         ILK_DISPLAY_MAXWM,
 963         ILK_DISPLAY_DFTWM,
 964         2,
 965         ILK_FIFO_LINE_SIZE
 966 };
 967 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 968         ILK_CURSOR_FIFO,
 969         ILK_CURSOR_MAXWM,
 970         ILK_CURSOR_DFTWM,
 971         2,
 972         ILK_FIFO_LINE_SIZE
 973 };
 974 static const struct intel_watermark_params ironlake_display_srwm_info = {
 975         ILK_DISPLAY_SR_FIFO,
 976         ILK_DISPLAY_MAX_SRWM,
 977         ILK_DISPLAY_DFT_SRWM,
 978         2,
 979         ILK_FIFO_LINE_SIZE
 980 };
 981 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 982         ILK_CURSOR_SR_FIFO,
 983         ILK_CURSOR_MAX_SRWM,
 984         ILK_CURSOR_DFT_SRWM,
 985         2,
 986         ILK_FIFO_LINE_SIZE
 987 };
 988
 989 static const struct intel_watermark_params sandybridge_display_wm_info = {
 990         SNB_DISPLAY_FIFO,
 991         SNB_DISPLAY_MAXWM,
 992         SNB_DISPLAY_DFTWM,
 993         2,
 994         SNB_FIFO_LINE_SIZE
 995 };
 996 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 997         SNB_CURSOR_FIFO,
 998         SNB_CURSOR_MAXWM,
 999         SNB_CURSOR_DFTWM,
1000         2,
1001         SNB_FIFO_LINE_SIZE
1002 };
1003 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004         SNB_DISPLAY_SR_FIFO,
1005         SNB_DISPLAY_MAX_SRWM,
1006         SNB_DISPLAY_DFT_SRWM,
1007         2,
1008         SNB_FIFO_LINE_SIZE
1009 };
1010 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1011         SNB_CURSOR_SR_FIFO,
1012         SNB_CURSOR_MAX_SRWM,
1013         SNB_CURSOR_DFT_SRWM,
1014         2,
1015         SNB_FIFO_LINE_SIZE
1016 };
1017
1018
1019 /**
1020  * intel_calculate_wm - calculate watermark level
1021  * @clock_in_khz: pixel clock
1022  * @wm: chip FIFO params
1023  * @pixel_size: display pixel size
1024  * @latency_ns: memory latency for the platform
1025  *
1026  * Calculate the watermark level (the level at which the display plane will
1027  * start fetching from memory again).  Each chip has a different display
1028  * FIFO size and allocation, so the caller needs to figure that out and pass
1029  * in the correct intel_watermark_params structure.
1030  *
1031  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032  * on the pixel size.  When it reaches the watermark level, it'll start
1033  * fetching FIFO line sized based chunks from memory until the FIFO fills
1034  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1035  * will occur, and a display engine hang could result.
1036  */
1037 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038                                         const struct intel_watermark_params *wm,
1039                                         int fifo_size,
1040                                         int pixel_size,
1041                                         unsigned long latency_ns)
1042 {
1043         long entries_required, wm_size;
1044
1045         /*
1046          * Note: we need to make sure we don't overflow for various clock &
1047          * latency values.
1048          * clocks go from a few thousand to several hundred thousand.
1049          * latency is usually a few thousand
1050          */
1051         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1052                 1000;
1053         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1054
1055         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1056
1057         wm_size = fifo_size - (entries_required + wm->guard_size);
1058
1059         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1060
1061         /* Don't promote wm_size to unsigned... */
1062         if (wm_size > (long)wm->max_wm)
1063                 wm_size = wm->max_wm;
1064         if (wm_size <= 0)
1065                 wm_size = wm->default_wm;
1066         return wm_size;
1067 }
1068
1069 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1070 {
1071         struct drm_crtc *crtc, *enabled = NULL;
1072
1073         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1074                 if (intel_crtc_active(crtc)) {
1075                         if (enabled)
1076                                 return NULL;
1077                         enabled = crtc;
1078                 }
1079         }
1080
1081         return enabled;
1082 }
1083
1084 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1085 {
1086         struct drm_device *dev = unused_crtc->dev;
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088         struct drm_crtc *crtc;
1089         const struct cxsr_latency *latency;
1090         u32 reg;
1091         unsigned long wm;
1092
1093         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1095         if (!latency) {
1096                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097                 pineview_disable_cxsr(dev);
1098                 return;
1099         }
1100
1101         crtc = single_enabled_crtc(dev);
1102         if (crtc) {
1103                 const struct drm_display_mode *adjusted_mode;
1104                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1105                 int clock;
1106
1107                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108                 clock = adjusted_mode->crtc_clock;
1109
1110                 /* Display SR */
1111                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112                                         pineview_display_wm.fifo_size,
1113                                         pixel_size, latency->display_sr);
1114                 reg = I915_READ(DSPFW1);
1115                 reg &= ~DSPFW_SR_MASK;
1116                 reg |= wm << DSPFW_SR_SHIFT;
1117                 I915_WRITE(DSPFW1, reg);
1118                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1119
1120                 /* cursor SR */
1121                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122                                         pineview_display_wm.fifo_size,
1123                                         pixel_size, latency->cursor_sr);
1124                 reg = I915_READ(DSPFW3);
1125                 reg &= ~DSPFW_CURSOR_SR_MASK;
1126                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127                 I915_WRITE(DSPFW3, reg);
1128
1129                 /* Display HPLL off SR */
1130                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131                                         pineview_display_hplloff_wm.fifo_size,
1132                                         pixel_size, latency->display_hpll_disable);
1133                 reg = I915_READ(DSPFW3);
1134                 reg &= ~DSPFW_HPLL_SR_MASK;
1135                 reg |= wm & DSPFW_HPLL_SR_MASK;
1136                 I915_WRITE(DSPFW3, reg);
1137
1138                 /* cursor HPLL off SR */
1139                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140                                         pineview_display_hplloff_wm.fifo_size,
1141                                         pixel_size, latency->cursor_hpll_disable);
1142                 reg = I915_READ(DSPFW3);
1143                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145                 I915_WRITE(DSPFW3, reg);
1146                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1147
1148                 /* activate cxsr */
1149                 I915_WRITE(DSPFW3,
1150                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1151                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1152         } else {
1153                 pineview_disable_cxsr(dev);
1154                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1155         }
1156 }
1157
1158 static bool g4x_compute_wm0(struct drm_device *dev,
1159                             int plane,
1160                             const struct intel_watermark_params *display,
1161                             int display_latency_ns,
1162                             const struct intel_watermark_params *cursor,
1163                             int cursor_latency_ns,
1164                             int *plane_wm,
1165                             int *cursor_wm)
1166 {
1167         struct drm_crtc *crtc;
1168         const struct drm_display_mode *adjusted_mode;
1169         int htotal, hdisplay, clock, pixel_size;
1170         int line_time_us, line_count;
1171         int entries, tlb_miss;
1172
1173         crtc = intel_get_crtc_for_plane(dev, plane);
1174         if (!intel_crtc_active(crtc)) {
1175                 *cursor_wm = cursor->guard_size;
1176                 *plane_wm = display->guard_size;
1177                 return false;
1178         }
1179
1180         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1181         clock = adjusted_mode->crtc_clock;
1182         htotal = adjusted_mode->htotal;
1183         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1184         pixel_size = crtc->fb->bits_per_pixel / 8;
1185
1186         /* Use the small buffer method to calculate plane watermark */
1187         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1189         if (tlb_miss > 0)
1190                 entries += tlb_miss;
1191         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192         *plane_wm = entries + display->guard_size;
1193         if (*plane_wm > (int)display->max_wm)
1194                 *plane_wm = display->max_wm;
1195
1196         /* Use the large buffer method to calculate cursor watermark */
1197         line_time_us = ((htotal * 1000) / clock);
1198         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199         entries = line_count * 64 * pixel_size;
1200         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1201         if (tlb_miss > 0)
1202                 entries += tlb_miss;
1203         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204         *cursor_wm = entries + cursor->guard_size;
1205         if (*cursor_wm > (int)cursor->max_wm)
1206                 *cursor_wm = (int)cursor->max_wm;
1207
1208         return true;
1209 }
1210
1211 /*
1212  * Check the wm result.
1213  *
1214  * If any calculated watermark values is larger than the maximum value that
1215  * can be programmed into the associated watermark register, that watermark
1216  * must be disabled.
1217  */
1218 static bool g4x_check_srwm(struct drm_device *dev,
1219                            int display_wm, int cursor_wm,
1220                            const struct intel_watermark_params *display,
1221                            const struct intel_watermark_params *cursor)
1222 {
1223         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224                       display_wm, cursor_wm);
1225
1226         if (display_wm > display->max_wm) {
1227                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228                               display_wm, display->max_wm);
1229                 return false;
1230         }
1231
1232         if (cursor_wm > cursor->max_wm) {
1233                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234                               cursor_wm, cursor->max_wm);
1235                 return false;
1236         }
1237
1238         if (!(display_wm || cursor_wm)) {
1239                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1240                 return false;
1241         }
1242
1243         return true;
1244 }
1245
1246 static bool g4x_compute_srwm(struct drm_device *dev,
1247                              int plane,
1248                              int latency_ns,
1249                              const struct intel_watermark_params *display,
1250                              const struct intel_watermark_params *cursor,
1251                              int *display_wm, int *cursor_wm)
1252 {
1253         struct drm_crtc *crtc;
1254         const struct drm_display_mode *adjusted_mode;
1255         int hdisplay, htotal, pixel_size, clock;
1256         unsigned long line_time_us;
1257         int line_count, line_size;
1258         int small, large;
1259         int entries;
1260
1261         if (!latency_ns) {
1262                 *display_wm = *cursor_wm = 0;
1263                 return false;
1264         }
1265
1266         crtc = intel_get_crtc_for_plane(dev, plane);
1267         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1268         clock = adjusted_mode->crtc_clock;
1269         htotal = adjusted_mode->htotal;
1270         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1271         pixel_size = crtc->fb->bits_per_pixel / 8;
1272
1273         line_time_us = (htotal * 1000) / clock;
1274         line_count = (latency_ns / line_time_us + 1000) / 1000;
1275         line_size = hdisplay * pixel_size;
1276
1277         /* Use the minimum of the small and large buffer method for primary */
1278         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1279         large = line_count * line_size;
1280
1281         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282         *display_wm = entries + display->guard_size;
1283
1284         /* calculate the self-refresh watermark for display cursor */
1285         entries = line_count * pixel_size * 64;
1286         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1287         *cursor_wm = entries + cursor->guard_size;
1288
1289         return g4x_check_srwm(dev,
1290                               *display_wm, *cursor_wm,
1291                               display, cursor);
1292 }
1293
1294 static bool vlv_compute_drain_latency(struct drm_device *dev,
1295                                      int plane,
1296                                      int *plane_prec_mult,
1297                                      int *plane_dl,
1298                                      int *cursor_prec_mult,
1299                                      int *cursor_dl)
1300 {
1301         struct drm_crtc *crtc;
1302         int clock, pixel_size;
1303         int entries;
1304
1305         crtc = intel_get_crtc_for_plane(dev, plane);
1306         if (!intel_crtc_active(crtc))
1307                 return false;
1308
1309         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1310         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1311
1312         entries = (clock / 1000) * pixel_size;
1313         *plane_prec_mult = (entries > 256) ?
1314                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1315         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1316                                                      pixel_size);
1317
1318         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1319         *cursor_prec_mult = (entries > 256) ?
1320                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1321         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1322
1323         return true;
1324 }
1325
1326 /*
1327  * Update drain latency registers of memory arbiter
1328  *
1329  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330  * to be programmed. Each plane has a drain latency multiplier and a drain
1331  * latency value.
1332  */
1333
1334 static void vlv_update_drain_latency(struct drm_device *dev)
1335 {
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1338         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1339         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1340                                                         either 16 or 32 */
1341
1342         /* For plane A, Cursor A */
1343         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1344                                       &cursor_prec_mult, &cursora_dl)) {
1345                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1347                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1348                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1349
1350                 I915_WRITE(VLV_DDL1, cursora_prec |
1351                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1352                                 planea_prec | planea_dl);
1353         }
1354
1355         /* For plane B, Cursor B */
1356         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1357                                       &cursor_prec_mult, &cursorb_dl)) {
1358                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1360                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1361                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1362
1363                 I915_WRITE(VLV_DDL2, cursorb_prec |
1364                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1365                                 planeb_prec | planeb_dl);
1366         }
1367 }
1368
1369 #define single_plane_enabled(mask) is_power_of_2(mask)
1370
1371 static void valleyview_update_wm(struct drm_crtc *crtc)
1372 {
1373         struct drm_device *dev = crtc->dev;
1374         static const int sr_latency_ns = 12000;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377         int plane_sr, cursor_sr;
1378         int ignore_plane_sr, ignore_cursor_sr;
1379         unsigned int enabled = 0;
1380
1381         vlv_update_drain_latency(dev);
1382
1383         if (g4x_compute_wm0(dev, PIPE_A,
1384                             &valleyview_wm_info, latency_ns,
1385                             &valleyview_cursor_wm_info, latency_ns,
1386                             &planea_wm, &cursora_wm))
1387                 enabled |= 1 << PIPE_A;
1388
1389         if (g4x_compute_wm0(dev, PIPE_B,
1390                             &valleyview_wm_info, latency_ns,
1391                             &valleyview_cursor_wm_info, latency_ns,
1392                             &planeb_wm, &cursorb_wm))
1393                 enabled |= 1 << PIPE_B;
1394
1395         if (single_plane_enabled(enabled) &&
1396             g4x_compute_srwm(dev, ffs(enabled) - 1,
1397                              sr_latency_ns,
1398                              &valleyview_wm_info,
1399                              &valleyview_cursor_wm_info,
1400                              &plane_sr, &ignore_cursor_sr) &&
1401             g4x_compute_srwm(dev, ffs(enabled) - 1,
1402                              2*sr_latency_ns,
1403                              &valleyview_wm_info,
1404                              &valleyview_cursor_wm_info,
1405                              &ignore_plane_sr, &cursor_sr)) {
1406                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1407         } else {
1408                 I915_WRITE(FW_BLC_SELF_VLV,
1409                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1410                 plane_sr = cursor_sr = 0;
1411         }
1412
1413         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414                       planea_wm, cursora_wm,
1415                       planeb_wm, cursorb_wm,
1416                       plane_sr, cursor_sr);
1417
1418         I915_WRITE(DSPFW1,
1419                    (plane_sr << DSPFW_SR_SHIFT) |
1420                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1422                    planea_wm);
1423         I915_WRITE(DSPFW2,
1424                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1425                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1426         I915_WRITE(DSPFW3,
1427                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1429 }
1430
1431 static void g4x_update_wm(struct drm_crtc *crtc)
1432 {
1433         struct drm_device *dev = crtc->dev;
1434         static const int sr_latency_ns = 12000;
1435         struct drm_i915_private *dev_priv = dev->dev_private;
1436         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1437         int plane_sr, cursor_sr;
1438         unsigned int enabled = 0;
1439
1440         if (g4x_compute_wm0(dev, PIPE_A,
1441                             &g4x_wm_info, latency_ns,
1442                             &g4x_cursor_wm_info, latency_ns,
1443                             &planea_wm, &cursora_wm))
1444                 enabled |= 1 << PIPE_A;
1445
1446         if (g4x_compute_wm0(dev, PIPE_B,
1447                             &g4x_wm_info, latency_ns,
1448                             &g4x_cursor_wm_info, latency_ns,
1449                             &planeb_wm, &cursorb_wm))
1450                 enabled |= 1 << PIPE_B;
1451
1452         if (single_plane_enabled(enabled) &&
1453             g4x_compute_srwm(dev, ffs(enabled) - 1,
1454                              sr_latency_ns,
1455                              &g4x_wm_info,
1456                              &g4x_cursor_wm_info,
1457                              &plane_sr, &cursor_sr)) {
1458                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1459         } else {
1460                 I915_WRITE(FW_BLC_SELF,
1461                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1462                 plane_sr = cursor_sr = 0;
1463         }
1464
1465         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1466                       planea_wm, cursora_wm,
1467                       planeb_wm, cursorb_wm,
1468                       plane_sr, cursor_sr);
1469
1470         I915_WRITE(DSPFW1,
1471                    (plane_sr << DSPFW_SR_SHIFT) |
1472                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1473                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1474                    planea_wm);
1475         I915_WRITE(DSPFW2,
1476                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1477                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1478         /* HPLL off in SR has some issues on G4x... disable it */
1479         I915_WRITE(DSPFW3,
1480                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1481                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1482 }
1483
1484 static void i965_update_wm(struct drm_crtc *unused_crtc)
1485 {
1486         struct drm_device *dev = unused_crtc->dev;
1487         struct drm_i915_private *dev_priv = dev->dev_private;
1488         struct drm_crtc *crtc;
1489         int srwm = 1;
1490         int cursor_sr = 16;
1491
1492         /* Calc sr entries for one plane configs */
1493         crtc = single_enabled_crtc(dev);
1494         if (crtc) {
1495                 /* self-refresh has much higher latency */
1496                 static const int sr_latency_ns = 12000;
1497                 const struct drm_display_mode *adjusted_mode =
1498                         &to_intel_crtc(crtc)->config.adjusted_mode;
1499                 int clock = adjusted_mode->crtc_clock;
1500                 int htotal = adjusted_mode->htotal;
1501                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1502                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1503                 unsigned long line_time_us;
1504                 int entries;
1505
1506                 line_time_us = ((htotal * 1000) / clock);
1507
1508                 /* Use ns/us then divide to preserve precision */
1509                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510                         pixel_size * hdisplay;
1511                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512                 srwm = I965_FIFO_SIZE - entries;
1513                 if (srwm < 0)
1514                         srwm = 1;
1515                 srwm &= 0x1ff;
1516                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1517                               entries, srwm);
1518
1519                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1520                         pixel_size * 64;
1521                 entries = DIV_ROUND_UP(entries,
1522                                           i965_cursor_wm_info.cacheline_size);
1523                 cursor_sr = i965_cursor_wm_info.fifo_size -
1524                         (entries + i965_cursor_wm_info.guard_size);
1525
1526                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527                         cursor_sr = i965_cursor_wm_info.max_wm;
1528
1529                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530                               "cursor %d\n", srwm, cursor_sr);
1531
1532                 if (IS_CRESTLINE(dev))
1533                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1534         } else {
1535                 /* Turn off self refresh if both pipes are enabled */
1536                 if (IS_CRESTLINE(dev))
1537                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1538                                    & ~FW_BLC_SELF_EN);
1539         }
1540
1541         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1542                       srwm);
1543
1544         /* 965 has limitations... */
1545         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1546                    (8 << 16) | (8 << 8) | (8 << 0));
1547         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1548         /* update cursor SR watermark */
1549         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1550 }
1551
1552 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1553 {
1554         struct drm_device *dev = unused_crtc->dev;
1555         struct drm_i915_private *dev_priv = dev->dev_private;
1556         const struct intel_watermark_params *wm_info;
1557         uint32_t fwater_lo;
1558         uint32_t fwater_hi;
1559         int cwm, srwm = 1;
1560         int fifo_size;
1561         int planea_wm, planeb_wm;
1562         struct drm_crtc *crtc, *enabled = NULL;
1563
1564         if (IS_I945GM(dev))
1565                 wm_info = &i945_wm_info;
1566         else if (!IS_GEN2(dev))
1567                 wm_info = &i915_wm_info;
1568         else
1569                 wm_info = &i855_wm_info;
1570
1571         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572         crtc = intel_get_crtc_for_plane(dev, 0);
1573         if (intel_crtc_active(crtc)) {
1574                 const struct drm_display_mode *adjusted_mode;
1575                 int cpp = crtc->fb->bits_per_pixel / 8;
1576                 if (IS_GEN2(dev))
1577                         cpp = 4;
1578
1579                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1580                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1581                                                wm_info, fifo_size, cpp,
1582                                                latency_ns);
1583                 enabled = crtc;
1584         } else
1585                 planea_wm = fifo_size - wm_info->guard_size;
1586
1587         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1588         crtc = intel_get_crtc_for_plane(dev, 1);
1589         if (intel_crtc_active(crtc)) {
1590                 const struct drm_display_mode *adjusted_mode;
1591                 int cpp = crtc->fb->bits_per_pixel / 8;
1592                 if (IS_GEN2(dev))
1593                         cpp = 4;
1594
1595                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1596                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1597                                                wm_info, fifo_size, cpp,
1598                                                latency_ns);
1599                 if (enabled == NULL)
1600                         enabled = crtc;
1601                 else
1602                         enabled = NULL;
1603         } else
1604                 planeb_wm = fifo_size - wm_info->guard_size;
1605
1606         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1607
1608         /*
1609          * Overlay gets an aggressive default since video jitter is bad.
1610          */
1611         cwm = 2;
1612
1613         /* Play safe and disable self-refresh before adjusting watermarks. */
1614         if (IS_I945G(dev) || IS_I945GM(dev))
1615                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1616         else if (IS_I915GM(dev))
1617                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1618
1619         /* Calc sr entries for one plane configs */
1620         if (HAS_FW_BLC(dev) && enabled) {
1621                 /* self-refresh has much higher latency */
1622                 static const int sr_latency_ns = 6000;
1623                 const struct drm_display_mode *adjusted_mode =
1624                         &to_intel_crtc(enabled)->config.adjusted_mode;
1625                 int clock = adjusted_mode->crtc_clock;
1626                 int htotal = adjusted_mode->htotal;
1627                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1628                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1629                 unsigned long line_time_us;
1630                 int entries;
1631
1632                 line_time_us = (htotal * 1000) / clock;
1633
1634                 /* Use ns/us then divide to preserve precision */
1635                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636                         pixel_size * hdisplay;
1637                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1638                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1639                 srwm = wm_info->fifo_size - entries;
1640                 if (srwm < 0)
1641                         srwm = 1;
1642
1643                 if (IS_I945G(dev) || IS_I945GM(dev))
1644                         I915_WRITE(FW_BLC_SELF,
1645                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1646                 else if (IS_I915GM(dev))
1647                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1648         }
1649
1650         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1651                       planea_wm, planeb_wm, cwm, srwm);
1652
1653         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1654         fwater_hi = (cwm & 0x1f);
1655
1656         /* Set request length to 8 cachelines per fetch */
1657         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1658         fwater_hi = fwater_hi | (1 << 8);
1659
1660         I915_WRITE(FW_BLC, fwater_lo);
1661         I915_WRITE(FW_BLC2, fwater_hi);
1662
1663         if (HAS_FW_BLC(dev)) {
1664                 if (enabled) {
1665                         if (IS_I945G(dev) || IS_I945GM(dev))
1666                                 I915_WRITE(FW_BLC_SELF,
1667                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1668                         else if (IS_I915GM(dev))
1669                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1670                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1671                 } else
1672                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1673         }
1674 }
1675
1676 static void i830_update_wm(struct drm_crtc *unused_crtc)
1677 {
1678         struct drm_device *dev = unused_crtc->dev;
1679         struct drm_i915_private *dev_priv = dev->dev_private;
1680         struct drm_crtc *crtc;
1681         const struct drm_display_mode *adjusted_mode;
1682         uint32_t fwater_lo;
1683         int planea_wm;
1684
1685         crtc = single_enabled_crtc(dev);
1686         if (crtc == NULL)
1687                 return;
1688
1689         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1690         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1691                                        &i830_wm_info,
1692                                        dev_priv->display.get_fifo_size(dev, 0),
1693                                        4, latency_ns);
1694         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695         fwater_lo |= (3<<8) | planea_wm;
1696
1697         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699         I915_WRITE(FW_BLC, fwater_lo);
1700 }
1701
1702 /*
1703  * Check the wm result.
1704  *
1705  * If any calculated watermark values is larger than the maximum value that
1706  * can be programmed into the associated watermark register, that watermark
1707  * must be disabled.
1708  */
1709 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1710                                 int fbc_wm, int display_wm, int cursor_wm,
1711                                 const struct intel_watermark_params *display,
1712                                 const struct intel_watermark_params *cursor)
1713 {
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715
1716         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1717                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1718
1719         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1720                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1721                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1722
1723                 /* fbc has it's own way to disable FBC WM */
1724                 I915_WRITE(DISP_ARB_CTL,
1725                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1726                 return false;
1727         } else if (INTEL_INFO(dev)->gen >= 6) {
1728                 /* enable FBC WM (except on ILK, where it must remain off) */
1729                 I915_WRITE(DISP_ARB_CTL,
1730                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1731         }
1732
1733         if (display_wm > display->max_wm) {
1734                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1735                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1736                 return false;
1737         }
1738
1739         if (cursor_wm > cursor->max_wm) {
1740                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1741                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1742                 return false;
1743         }
1744
1745         if (!(fbc_wm || display_wm || cursor_wm)) {
1746                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1747                 return false;
1748         }
1749
1750         return true;
1751 }
1752
1753 /*
1754  * Compute watermark values of WM[1-3],
1755  */
1756 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1757                                   int latency_ns,
1758                                   const struct intel_watermark_params *display,
1759                                   const struct intel_watermark_params *cursor,
1760                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1761 {
1762         struct drm_crtc *crtc;
1763         const struct drm_display_mode *adjusted_mode;
1764         unsigned long line_time_us;
1765         int hdisplay, htotal, pixel_size, clock;
1766         int line_count, line_size;
1767         int small, large;
1768         int entries;
1769
1770         if (!latency_ns) {
1771                 *fbc_wm = *display_wm = *cursor_wm = 0;
1772                 return false;
1773         }
1774
1775         crtc = intel_get_crtc_for_plane(dev, plane);
1776         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1777         clock = adjusted_mode->crtc_clock;
1778         htotal = adjusted_mode->htotal;
1779         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1780         pixel_size = crtc->fb->bits_per_pixel / 8;
1781
1782         line_time_us = (htotal * 1000) / clock;
1783         line_count = (latency_ns / line_time_us + 1000) / 1000;
1784         line_size = hdisplay * pixel_size;
1785
1786         /* Use the minimum of the small and large buffer method for primary */
1787         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1788         large = line_count * line_size;
1789
1790         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1791         *display_wm = entries + display->guard_size;
1792
1793         /*
1794          * Spec says:
1795          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1796          */
1797         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1798
1799         /* calculate the self-refresh watermark for display cursor */
1800         entries = line_count * pixel_size * 64;
1801         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1802         *cursor_wm = entries + cursor->guard_size;
1803
1804         return ironlake_check_srwm(dev, level,
1805                                    *fbc_wm, *display_wm, *cursor_wm,
1806                                    display, cursor);
1807 }
1808
1809 static void ironlake_update_wm(struct drm_crtc *crtc)
1810 {
1811         struct drm_device *dev = crtc->dev;
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         int fbc_wm, plane_wm, cursor_wm;
1814         unsigned int enabled;
1815
1816         enabled = 0;
1817         if (g4x_compute_wm0(dev, PIPE_A,
1818                             &ironlake_display_wm_info,
1819                             dev_priv->wm.pri_latency[0] * 100,
1820                             &ironlake_cursor_wm_info,
1821                             dev_priv->wm.cur_latency[0] * 100,
1822                             &plane_wm, &cursor_wm)) {
1823                 I915_WRITE(WM0_PIPEA_ILK,
1824                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1825                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1826                               " plane %d, " "cursor: %d\n",
1827                               plane_wm, cursor_wm);
1828                 enabled |= 1 << PIPE_A;
1829         }
1830
1831         if (g4x_compute_wm0(dev, PIPE_B,
1832                             &ironlake_display_wm_info,
1833                             dev_priv->wm.pri_latency[0] * 100,
1834                             &ironlake_cursor_wm_info,
1835                             dev_priv->wm.cur_latency[0] * 100,
1836                             &plane_wm, &cursor_wm)) {
1837                 I915_WRITE(WM0_PIPEB_ILK,
1838                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1839                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1840                               " plane %d, cursor: %d\n",
1841                               plane_wm, cursor_wm);
1842                 enabled |= 1 << PIPE_B;
1843         }
1844
1845         /*
1846          * Calculate and update the self-refresh watermark only when one
1847          * display plane is used.
1848          */
1849         I915_WRITE(WM3_LP_ILK, 0);
1850         I915_WRITE(WM2_LP_ILK, 0);
1851         I915_WRITE(WM1_LP_ILK, 0);
1852
1853         if (!single_plane_enabled(enabled))
1854                 return;
1855         enabled = ffs(enabled) - 1;
1856
1857         /* WM1 */
1858         if (!ironlake_compute_srwm(dev, 1, enabled,
1859                                    dev_priv->wm.pri_latency[1] * 500,
1860                                    &ironlake_display_srwm_info,
1861                                    &ironlake_cursor_srwm_info,
1862                                    &fbc_wm, &plane_wm, &cursor_wm))
1863                 return;
1864
1865         I915_WRITE(WM1_LP_ILK,
1866                    WM1_LP_SR_EN |
1867                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1868                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1869                    (plane_wm << WM1_LP_SR_SHIFT) |
1870                    cursor_wm);
1871
1872         /* WM2 */
1873         if (!ironlake_compute_srwm(dev, 2, enabled,
1874                                    dev_priv->wm.pri_latency[2] * 500,
1875                                    &ironlake_display_srwm_info,
1876                                    &ironlake_cursor_srwm_info,
1877                                    &fbc_wm, &plane_wm, &cursor_wm))
1878                 return;
1879
1880         I915_WRITE(WM2_LP_ILK,
1881                    WM2_LP_EN |
1882                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1883                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1884                    (plane_wm << WM1_LP_SR_SHIFT) |
1885                    cursor_wm);
1886
1887         /*
1888          * WM3 is unsupported on ILK, probably because we don't have latency
1889          * data for that power state
1890          */
1891 }
1892
1893 static void sandybridge_update_wm(struct drm_crtc *crtc)
1894 {
1895         struct drm_device *dev = crtc->dev;
1896         struct drm_i915_private *dev_priv = dev->dev_private;
1897         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1898         u32 val;
1899         int fbc_wm, plane_wm, cursor_wm;
1900         unsigned int enabled;
1901
1902         enabled = 0;
1903         if (g4x_compute_wm0(dev, PIPE_A,
1904                             &sandybridge_display_wm_info, latency,
1905                             &sandybridge_cursor_wm_info, latency,
1906                             &plane_wm, &cursor_wm)) {
1907                 val = I915_READ(WM0_PIPEA_ILK);
1908                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909                 I915_WRITE(WM0_PIPEA_ILK, val |
1910                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1912                               " plane %d, " "cursor: %d\n",
1913                               plane_wm, cursor_wm);
1914                 enabled |= 1 << PIPE_A;
1915         }
1916
1917         if (g4x_compute_wm0(dev, PIPE_B,
1918                             &sandybridge_display_wm_info, latency,
1919                             &sandybridge_cursor_wm_info, latency,
1920                             &plane_wm, &cursor_wm)) {
1921                 val = I915_READ(WM0_PIPEB_ILK);
1922                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923                 I915_WRITE(WM0_PIPEB_ILK, val |
1924                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1926                               " plane %d, cursor: %d\n",
1927                               plane_wm, cursor_wm);
1928                 enabled |= 1 << PIPE_B;
1929         }
1930
1931         /*
1932          * Calculate and update the self-refresh watermark only when one
1933          * display plane is used.
1934          *
1935          * SNB support 3 levels of watermark.
1936          *
1937          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938          * and disabled in the descending order
1939          *
1940          */
1941         I915_WRITE(WM3_LP_ILK, 0);
1942         I915_WRITE(WM2_LP_ILK, 0);
1943         I915_WRITE(WM1_LP_ILK, 0);
1944
1945         if (!single_plane_enabled(enabled) ||
1946             dev_priv->sprite_scaling_enabled)
1947                 return;
1948         enabled = ffs(enabled) - 1;
1949
1950         /* WM1 */
1951         if (!ironlake_compute_srwm(dev, 1, enabled,
1952                                    dev_priv->wm.pri_latency[1] * 500,
1953                                    &sandybridge_display_srwm_info,
1954                                    &sandybridge_cursor_srwm_info,
1955                                    &fbc_wm, &plane_wm, &cursor_wm))
1956                 return;
1957
1958         I915_WRITE(WM1_LP_ILK,
1959                    WM1_LP_SR_EN |
1960                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1961                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1962                    (plane_wm << WM1_LP_SR_SHIFT) |
1963                    cursor_wm);
1964
1965         /* WM2 */
1966         if (!ironlake_compute_srwm(dev, 2, enabled,
1967                                    dev_priv->wm.pri_latency[2] * 500,
1968                                    &sandybridge_display_srwm_info,
1969                                    &sandybridge_cursor_srwm_info,
1970                                    &fbc_wm, &plane_wm, &cursor_wm))
1971                 return;
1972
1973         I915_WRITE(WM2_LP_ILK,
1974                    WM2_LP_EN |
1975                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1976                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1977                    (plane_wm << WM1_LP_SR_SHIFT) |
1978                    cursor_wm);
1979
1980         /* WM3 */
1981         if (!ironlake_compute_srwm(dev, 3, enabled,
1982                                    dev_priv->wm.pri_latency[3] * 500,
1983                                    &sandybridge_display_srwm_info,
1984                                    &sandybridge_cursor_srwm_info,
1985                                    &fbc_wm, &plane_wm, &cursor_wm))
1986                 return;
1987
1988         I915_WRITE(WM3_LP_ILK,
1989                    WM3_LP_EN |
1990                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1991                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1992                    (plane_wm << WM1_LP_SR_SHIFT) |
1993                    cursor_wm);
1994 }
1995
1996 static void ivybridge_update_wm(struct drm_crtc *crtc)
1997 {
1998         struct drm_device *dev = crtc->dev;
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
2001         u32 val;
2002         int fbc_wm, plane_wm, cursor_wm;
2003         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2004         unsigned int enabled;
2005
2006         enabled = 0;
2007         if (g4x_compute_wm0(dev, PIPE_A,
2008                             &sandybridge_display_wm_info, latency,
2009                             &sandybridge_cursor_wm_info, latency,
2010                             &plane_wm, &cursor_wm)) {
2011                 val = I915_READ(WM0_PIPEA_ILK);
2012                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2013                 I915_WRITE(WM0_PIPEA_ILK, val |
2014                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2015                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2016                               " plane %d, " "cursor: %d\n",
2017                               plane_wm, cursor_wm);
2018                 enabled |= 1 << PIPE_A;
2019         }
2020
2021         if (g4x_compute_wm0(dev, PIPE_B,
2022                             &sandybridge_display_wm_info, latency,
2023                             &sandybridge_cursor_wm_info, latency,
2024                             &plane_wm, &cursor_wm)) {
2025                 val = I915_READ(WM0_PIPEB_ILK);
2026                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2027                 I915_WRITE(WM0_PIPEB_ILK, val |
2028                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2029                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2030                               " plane %d, cursor: %d\n",
2031                               plane_wm, cursor_wm);
2032                 enabled |= 1 << PIPE_B;
2033         }
2034
2035         if (g4x_compute_wm0(dev, PIPE_C,
2036                             &sandybridge_display_wm_info, latency,
2037                             &sandybridge_cursor_wm_info, latency,
2038                             &plane_wm, &cursor_wm)) {
2039                 val = I915_READ(WM0_PIPEC_IVB);
2040                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2041                 I915_WRITE(WM0_PIPEC_IVB, val |
2042                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2043                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2044                               " plane %d, cursor: %d\n",
2045                               plane_wm, cursor_wm);
2046                 enabled |= 1 << PIPE_C;
2047         }
2048
2049         /*
2050          * Calculate and update the self-refresh watermark only when one
2051          * display plane is used.
2052          *
2053          * SNB support 3 levels of watermark.
2054          *
2055          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2056          * and disabled in the descending order
2057          *
2058          */
2059         I915_WRITE(WM3_LP_ILK, 0);
2060         I915_WRITE(WM2_LP_ILK, 0);
2061         I915_WRITE(WM1_LP_ILK, 0);
2062
2063         if (!single_plane_enabled(enabled) ||
2064             dev_priv->sprite_scaling_enabled)
2065                 return;
2066         enabled = ffs(enabled) - 1;
2067
2068         /* WM1 */
2069         if (!ironlake_compute_srwm(dev, 1, enabled,
2070                                    dev_priv->wm.pri_latency[1] * 500,
2071                                    &sandybridge_display_srwm_info,
2072                                    &sandybridge_cursor_srwm_info,
2073                                    &fbc_wm, &plane_wm, &cursor_wm))
2074                 return;
2075
2076         I915_WRITE(WM1_LP_ILK,
2077                    WM1_LP_SR_EN |
2078                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2079                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2080                    (plane_wm << WM1_LP_SR_SHIFT) |
2081                    cursor_wm);
2082
2083         /* WM2 */
2084         if (!ironlake_compute_srwm(dev, 2, enabled,
2085                                    dev_priv->wm.pri_latency[2] * 500,
2086                                    &sandybridge_display_srwm_info,
2087                                    &sandybridge_cursor_srwm_info,
2088                                    &fbc_wm, &plane_wm, &cursor_wm))
2089                 return;
2090
2091         I915_WRITE(WM2_LP_ILK,
2092                    WM2_LP_EN |
2093                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2094                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2095                    (plane_wm << WM1_LP_SR_SHIFT) |
2096                    cursor_wm);
2097
2098         /* WM3, note we have to correct the cursor latency */
2099         if (!ironlake_compute_srwm(dev, 3, enabled,
2100                                    dev_priv->wm.pri_latency[3] * 500,
2101                                    &sandybridge_display_srwm_info,
2102                                    &sandybridge_cursor_srwm_info,
2103                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2104             !ironlake_compute_srwm(dev, 3, enabled,
2105                                    dev_priv->wm.cur_latency[3] * 500,
2106                                    &sandybridge_display_srwm_info,
2107                                    &sandybridge_cursor_srwm_info,
2108                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2109                 return;
2110
2111         I915_WRITE(WM3_LP_ILK,
2112                    WM3_LP_EN |
2113                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2114                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2115                    (plane_wm << WM1_LP_SR_SHIFT) |
2116                    cursor_wm);
2117 }
2118
2119 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2120                                     struct drm_crtc *crtc)
2121 {
2122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2123         uint32_t pixel_rate;
2124
2125         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2126
2127         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2128          * adjust the pixel_rate here. */
2129
2130         if (intel_crtc->config.pch_pfit.enabled) {
2131                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2132                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2133
2134                 pipe_w = intel_crtc->config.pipe_src_w;
2135                 pipe_h = intel_crtc->config.pipe_src_h;
2136                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2137                 pfit_h = pfit_size & 0xFFFF;
2138                 if (pipe_w < pfit_w)
2139                         pipe_w = pfit_w;
2140                 if (pipe_h < pfit_h)
2141                         pipe_h = pfit_h;
2142
2143                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2144                                      pfit_w * pfit_h);
2145         }
2146
2147         return pixel_rate;
2148 }
2149
2150 /* latency must be in 0.1us units. */
2151 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2152                                uint32_t latency)
2153 {
2154         uint64_t ret;
2155
2156         if (WARN(latency == 0, "Latency value missing\n"))
2157                 return UINT_MAX;
2158
2159         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2160         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2161
2162         return ret;
2163 }
2164
2165 /* latency must be in 0.1us units. */
2166 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2167                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2168                                uint32_t latency)
2169 {
2170         uint32_t ret;
2171
2172         if (WARN(latency == 0, "Latency value missing\n"))
2173                 return UINT_MAX;
2174
2175         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2176         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2177         ret = DIV_ROUND_UP(ret, 64) + 2;
2178         return ret;
2179 }
2180
2181 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2182                            uint8_t bytes_per_pixel)
2183 {
2184         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2185 }
2186
2187 struct hsw_pipe_wm_parameters {
2188         bool active;
2189         uint32_t pipe_htotal;
2190         uint32_t pixel_rate;
2191         struct intel_plane_wm_parameters pri;
2192         struct intel_plane_wm_parameters spr;
2193         struct intel_plane_wm_parameters cur;
2194 };
2195
2196 struct hsw_wm_maximums {
2197         uint16_t pri;
2198         uint16_t spr;
2199         uint16_t cur;
2200         uint16_t fbc;
2201 };
2202
2203 /* used in computing the new watermarks state */
2204 struct intel_wm_config {
2205         unsigned int num_pipes_active;
2206         bool sprites_enabled;
2207         bool sprites_scaled;
2208 };
2209
2210 /*
2211  * For both WM_PIPE and WM_LP.
2212  * mem_value must be in 0.1us units.
2213  */
2214 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2215                                    uint32_t mem_value,
2216                                    bool is_lp)
2217 {
2218         uint32_t method1, method2;
2219
2220         if (!params->active || !params->pri.enabled)
2221                 return 0;
2222
2223         method1 = ilk_wm_method1(params->pixel_rate,
2224                                  params->pri.bytes_per_pixel,
2225                                  mem_value);
2226
2227         if (!is_lp)
2228                 return method1;
2229
2230         method2 = ilk_wm_method2(params->pixel_rate,
2231                                  params->pipe_htotal,
2232                                  params->pri.horiz_pixels,
2233                                  params->pri.bytes_per_pixel,
2234                                  mem_value);
2235
2236         return min(method1, method2);
2237 }
2238
2239 /*
2240  * For both WM_PIPE and WM_LP.
2241  * mem_value must be in 0.1us units.
2242  */
2243 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2244                                    uint32_t mem_value)
2245 {
2246         uint32_t method1, method2;
2247
2248         if (!params->active || !params->spr.enabled)
2249                 return 0;
2250
2251         method1 = ilk_wm_method1(params->pixel_rate,
2252                                  params->spr.bytes_per_pixel,
2253                                  mem_value);
2254         method2 = ilk_wm_method2(params->pixel_rate,
2255                                  params->pipe_htotal,
2256                                  params->spr.horiz_pixels,
2257                                  params->spr.bytes_per_pixel,
2258                                  mem_value);
2259         return min(method1, method2);
2260 }
2261
2262 /*
2263  * For both WM_PIPE and WM_LP.
2264  * mem_value must be in 0.1us units.
2265  */
2266 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2267                                    uint32_t mem_value)
2268 {
2269         if (!params->active || !params->cur.enabled)
2270                 return 0;
2271
2272         return ilk_wm_method2(params->pixel_rate,
2273                               params->pipe_htotal,
2274                               params->cur.horiz_pixels,
2275                               params->cur.bytes_per_pixel,
2276                               mem_value);
2277 }
2278
2279 /* Only for WM_LP. */
2280 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2281                                    uint32_t pri_val)
2282 {
2283         if (!params->active || !params->pri.enabled)
2284                 return 0;
2285
2286         return ilk_wm_fbc(pri_val,
2287                           params->pri.horiz_pixels,
2288                           params->pri.bytes_per_pixel);
2289 }
2290
2291 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2292 {
2293         if (INTEL_INFO(dev)->gen >= 7)
2294                 return 768;
2295         else
2296                 return 512;
2297 }
2298
2299 /* Calculate the maximum primary/sprite plane watermark */
2300 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2301                                      int level,
2302                                      const struct intel_wm_config *config,
2303                                      enum intel_ddb_partitioning ddb_partitioning,
2304                                      bool is_sprite)
2305 {
2306         unsigned int fifo_size = ilk_display_fifo_size(dev);
2307         unsigned int max;
2308
2309         /* if sprites aren't enabled, sprites get nothing */
2310         if (is_sprite && !config->sprites_enabled)
2311                 return 0;
2312
2313         /* HSW allows LP1+ watermarks even with multiple pipes */
2314         if (level == 0 || config->num_pipes_active > 1) {
2315                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2316
2317                 /*
2318                  * For some reason the non self refresh
2319                  * FIFO size is only half of the self
2320                  * refresh FIFO size on ILK/SNB.
2321                  */
2322                 if (INTEL_INFO(dev)->gen <= 6)
2323                         fifo_size /= 2;
2324         }
2325
2326         if (config->sprites_enabled) {
2327                 /* level 0 is always calculated with 1:1 split */
2328                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2329                         if (is_sprite)
2330                                 fifo_size *= 5;
2331                         fifo_size /= 6;
2332                 } else {
2333                         fifo_size /= 2;
2334                 }
2335         }
2336
2337         /* clamp to max that the registers can hold */
2338         if (INTEL_INFO(dev)->gen >= 7)
2339                 /* IVB/HSW primary/sprite plane watermarks */
2340                 max = level == 0 ? 127 : 1023;
2341         else if (!is_sprite)
2342                 /* ILK/SNB primary plane watermarks */
2343                 max = level == 0 ? 127 : 511;
2344         else
2345                 /* ILK/SNB sprite plane watermarks */
2346                 max = level == 0 ? 63 : 255;
2347
2348         return min(fifo_size, max);
2349 }
2350
2351 /* Calculate the maximum cursor plane watermark */
2352 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2353                                       int level,
2354                                       const struct intel_wm_config *config)
2355 {
2356         /* HSW LP1+ watermarks w/ multiple pipes */
2357         if (level > 0 && config->num_pipes_active > 1)
2358                 return 64;
2359
2360         /* otherwise just report max that registers can hold */
2361         if (INTEL_INFO(dev)->gen >= 7)
2362                 return level == 0 ? 63 : 255;
2363         else
2364                 return level == 0 ? 31 : 63;
2365 }
2366
2367 /* Calculate the maximum FBC watermark */
2368 static unsigned int ilk_fbc_wm_max(void)
2369 {
2370         /* max that registers can hold */
2371         return 15;
2372 }
2373
2374 static void ilk_wm_max(struct drm_device *dev,
2375                        int level,
2376                        const struct intel_wm_config *config,
2377                        enum intel_ddb_partitioning ddb_partitioning,
2378                        struct hsw_wm_maximums *max)
2379 {
2380         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2381         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2382         max->cur = ilk_cursor_wm_max(dev, level, config);
2383         max->fbc = ilk_fbc_wm_max();
2384 }
2385
2386 static bool ilk_check_wm(int level,
2387                          const struct hsw_wm_maximums *max,
2388                          struct intel_wm_level *result)
2389 {
2390         bool ret;
2391
2392         /* already determined to be invalid? */
2393         if (!result->enable)
2394                 return false;
2395
2396         result->enable = result->pri_val <= max->pri &&
2397                          result->spr_val <= max->spr &&
2398                          result->cur_val <= max->cur;
2399
2400         ret = result->enable;
2401
2402         /*
2403          * HACK until we can pre-compute everything,
2404          * and thus fail gracefully if LP0 watermarks
2405          * are exceeded...
2406          */
2407         if (level == 0 && !result->enable) {
2408                 if (result->pri_val > max->pri)
2409                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2410                                       level, result->pri_val, max->pri);
2411                 if (result->spr_val > max->spr)
2412                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2413                                       level, result->spr_val, max->spr);
2414                 if (result->cur_val > max->cur)
2415                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2416                                       level, result->cur_val, max->cur);
2417
2418                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2419                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2420                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2421                 result->enable = true;
2422         }
2423
2424         DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2425
2426         return ret;
2427 }
2428
2429 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2430                                  int level,
2431                                  const struct hsw_pipe_wm_parameters *p,
2432                                  struct intel_wm_level *result)
2433 {
2434         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2435         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2436         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2437
2438         /* WM1+ latency values stored in 0.5us units */
2439         if (level > 0) {
2440                 pri_latency *= 5;
2441                 spr_latency *= 5;
2442                 cur_latency *= 5;
2443         }
2444
2445         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2446         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2447         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2448         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2449         result->enable = true;
2450 }
2451
2452 static uint32_t
2453 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2454 {
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2458         u32 linetime, ips_linetime;
2459
2460         if (!intel_crtc_active(crtc))
2461                 return 0;
2462
2463         /* The WM are computed with base on how long it takes to fill a single
2464          * row at the given clock rate, multiplied by 8.
2465          * */
2466         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2467         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2468                                          intel_ddi_get_cdclk_freq(dev_priv));
2469
2470         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2471                PIPE_WM_LINETIME_TIME(linetime);
2472 }
2473
2474 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2475 {
2476         struct drm_i915_private *dev_priv = dev->dev_private;
2477
2478         if (IS_HASWELL(dev)) {
2479                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2480
2481                 wm[0] = (sskpd >> 56) & 0xFF;
2482                 if (wm[0] == 0)
2483                         wm[0] = sskpd & 0xF;
2484                 wm[1] = (sskpd >> 4) & 0xFF;
2485                 wm[2] = (sskpd >> 12) & 0xFF;
2486                 wm[3] = (sskpd >> 20) & 0x1FF;
2487                 wm[4] = (sskpd >> 32) & 0x1FF;
2488         } else if (INTEL_INFO(dev)->gen >= 6) {
2489                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2490
2491                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2492                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2493                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2494                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2495         } else if (INTEL_INFO(dev)->gen >= 5) {
2496                 uint32_t mltr = I915_READ(MLTR_ILK);
2497
2498                 /* ILK primary LP0 latency is 700 ns */
2499                 wm[0] = 7;
2500                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2501                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2502         }
2503 }
2504
2505 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2506 {
2507         /* ILK sprite LP0 latency is 1300 ns */
2508         if (INTEL_INFO(dev)->gen == 5)
2509                 wm[0] = 13;
2510 }
2511
2512 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2513 {
2514         /* ILK cursor LP0 latency is 1300 ns */
2515         if (INTEL_INFO(dev)->gen == 5)
2516                 wm[0] = 13;
2517
2518         /* WaDoubleCursorLP3Latency:ivb */
2519         if (IS_IVYBRIDGE(dev))
2520                 wm[3] *= 2;
2521 }
2522
2523 static int ilk_wm_max_level(const struct drm_device *dev)
2524 {
2525         /* how many WM levels are we expecting */
2526         if (IS_HASWELL(dev))
2527                 return 4;
2528         else if (INTEL_INFO(dev)->gen >= 6)
2529                 return 3;
2530         else
2531                 return 2;
2532 }
2533
2534 static void intel_print_wm_latency(struct drm_device *dev,
2535                                    const char *name,
2536                                    const uint16_t wm[5])
2537 {
2538         int level, max_level = ilk_wm_max_level(dev);
2539
2540         for (level = 0; level <= max_level; level++) {
2541                 unsigned int latency = wm[level];
2542
2543                 if (latency == 0) {
2544                         DRM_ERROR("%s WM%d latency not provided\n",
2545                                   name, level);
2546                         continue;
2547                 }
2548
2549                 /* WM1+ latency values in 0.5us units */
2550                 if (level > 0)
2551                         latency *= 5;
2552
2553                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2554                               name, level, wm[level],
2555                               latency / 10, latency % 10);
2556         }
2557 }
2558
2559 static void intel_setup_wm_latency(struct drm_device *dev)
2560 {
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562
2563         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2564
2565         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2566                sizeof(dev_priv->wm.pri_latency));
2567         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2568                sizeof(dev_priv->wm.pri_latency));
2569
2570         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2571         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2572
2573         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2574         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2575         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2576 }
2577
2578 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2579                                       struct hsw_pipe_wm_parameters *p,
2580                                       struct intel_wm_config *config)
2581 {
2582         struct drm_device *dev = crtc->dev;
2583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2584         enum pipe pipe = intel_crtc->pipe;
2585         struct drm_plane *plane;
2586
2587         p->active = intel_crtc_active(crtc);
2588         if (p->active) {
2589                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2590                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2591                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2592                 p->cur.bytes_per_pixel = 4;
2593                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2594                 p->cur.horiz_pixels = 64;
2595                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2596                 p->pri.enabled = true;
2597                 p->cur.enabled = true;
2598         }
2599
2600         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2601                 config->num_pipes_active += intel_crtc_active(crtc);
2602
2603         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2604                 struct intel_plane *intel_plane = to_intel_plane(plane);
2605
2606                 if (intel_plane->pipe == pipe)
2607                         p->spr = intel_plane->wm;
2608
2609                 config->sprites_enabled |= intel_plane->wm.enabled;
2610                 config->sprites_scaled |= intel_plane->wm.scaled;
2611         }
2612 }
2613
2614 /* Compute new watermarks for the pipe */
2615 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2616                                   const struct hsw_pipe_wm_parameters *params,
2617                                   struct intel_pipe_wm *pipe_wm)
2618 {
2619         struct drm_device *dev = crtc->dev;
2620         struct drm_i915_private *dev_priv = dev->dev_private;
2621         int level, max_level = ilk_wm_max_level(dev);
2622         /* LP0 watermark maximums depend on this pipe alone */
2623         struct intel_wm_config config = {
2624                 .num_pipes_active = 1,
2625                 .sprites_enabled = params->spr.enabled,
2626                 .sprites_scaled = params->spr.scaled,
2627         };
2628         struct hsw_wm_maximums max;
2629
2630         /* LP0 watermarks always use 1/2 DDB partitioning */
2631         ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2632
2633         for (level = 0; level <= max_level; level++)
2634                 ilk_compute_wm_level(dev_priv, level, params,
2635                                      &pipe_wm->wm[level]);
2636
2637         pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2638
2639         /* At least LP0 must be valid */
2640         return ilk_check_wm(0, &max, &pipe_wm->wm[0]);
2641 }
2642
2643 /*
2644  * Merge the watermarks from all active pipes for a specific level.
2645  */
2646 static void ilk_merge_wm_level(struct drm_device *dev,
2647                                int level,
2648                                struct intel_wm_level *ret_wm)
2649 {
2650         const struct intel_crtc *intel_crtc;
2651
2652         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2653                 const struct intel_wm_level *wm =
2654                         &intel_crtc->wm.active.wm[level];
2655
2656                 if (!wm->enable)
2657                         return;
2658
2659                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2660                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2661                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2662                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2663         }
2664
2665         ret_wm->enable = true;
2666 }
2667
2668 /*
2669  * Merge all low power watermarks for all active pipes.
2670  */
2671 static void ilk_wm_merge(struct drm_device *dev,
2672                          const struct hsw_wm_maximums *max,
2673                          struct intel_pipe_wm *merged)
2674 {
2675         int level, max_level = ilk_wm_max_level(dev);
2676
2677         merged->fbc_wm_enabled = true;
2678
2679         /* merge each WM1+ level */
2680         for (level = 1; level <= max_level; level++) {
2681                 struct intel_wm_level *wm = &merged->wm[level];
2682
2683                 ilk_merge_wm_level(dev, level, wm);
2684
2685                 if (!ilk_check_wm(level, max, wm))
2686                         break;
2687
2688                 /*
2689                  * The spec says it is preferred to disable
2690                  * FBC WMs instead of disabling a WM level.
2691                  */
2692                 if (wm->fbc_val > max->fbc) {
2693                         merged->fbc_wm_enabled = false;
2694                         wm->fbc_val = 0;
2695                 }
2696         }
2697 }
2698
2699 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2700 {
2701         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2702         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2703 }
2704
2705 static void hsw_compute_wm_results(struct drm_device *dev,
2706                                    const struct intel_pipe_wm *merged,
2707                                    enum intel_ddb_partitioning partitioning,
2708                                    struct hsw_wm_values *results)
2709 {
2710         struct intel_crtc *intel_crtc;
2711         int level, wm_lp;
2712
2713         results->enable_fbc_wm = merged->fbc_wm_enabled;
2714         results->partitioning = partitioning;
2715
2716         /* LP1+ register values */
2717         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2718                 const struct intel_wm_level *r;
2719
2720                 level = ilk_wm_lp_to_level(wm_lp, merged);
2721
2722                 r = &merged->wm[level];
2723                 if (!r->enable)
2724                         break;
2725
2726                 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2727                                                           r->fbc_val,
2728                                                           r->pri_val,
2729                                                           r->cur_val);
2730                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2731         }
2732
2733         /* LP0 register values */
2734         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2735                 enum pipe pipe = intel_crtc->pipe;
2736                 const struct intel_wm_level *r =
2737                         &intel_crtc->wm.active.wm[0];
2738
2739                 if (WARN_ON(!r->enable))
2740                         continue;
2741
2742                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2743
2744                 results->wm_pipe[pipe] =
2745                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2746                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2747                         r->cur_val;
2748         }
2749 }
2750
2751 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2752  * case both are at the same level. Prefer r1 in case they're the same. */
2753 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2754                                                   struct intel_pipe_wm *r1,
2755                                                   struct intel_pipe_wm *r2)
2756 {
2757         int level, max_level = ilk_wm_max_level(dev);
2758         int level1 = 0, level2 = 0;
2759
2760         for (level = 1; level <= max_level; level++) {
2761                 if (r1->wm[level].enable)
2762                         level1 = level;
2763                 if (r2->wm[level].enable)
2764                         level2 = level;
2765         }
2766
2767         if (level1 == level2) {
2768                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2769                         return r2;
2770                 else
2771                         return r1;
2772         } else if (level1 > level2) {
2773                 return r1;
2774         } else {
2775                 return r2;
2776         }
2777 }
2778
2779 /*
2780  * The spec says we shouldn't write when we don't need, because every write
2781  * causes WMs to be re-evaluated, expending some power.
2782  */
2783 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2784                                 struct hsw_wm_values *results)
2785 {
2786         struct hsw_wm_values previous;
2787         uint32_t val;
2788
2789         previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2790         previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2791         previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2792         previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2793         previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2794         previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2795         previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2796         previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2797         previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2798         previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2799         previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2800         previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2801
2802         previous.partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2803                                 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2804
2805         previous.enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2806
2807         if (memcmp(results, &previous, sizeof(*results)) == 0)
2808                 return;
2809
2810         if (previous.wm_lp[2] != 0)
2811                 I915_WRITE(WM3_LP_ILK, 0);
2812         if (previous.wm_lp[1] != 0)
2813                 I915_WRITE(WM2_LP_ILK, 0);
2814         if (previous.wm_lp[0] != 0)
2815                 I915_WRITE(WM1_LP_ILK, 0);
2816
2817         if (previous.wm_pipe[0] != results->wm_pipe[0])
2818                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2819         if (previous.wm_pipe[1] != results->wm_pipe[1])
2820                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2821         if (previous.wm_pipe[2] != results->wm_pipe[2])
2822                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2823
2824         if (previous.wm_linetime[0] != results->wm_linetime[0])
2825                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2826         if (previous.wm_linetime[1] != results->wm_linetime[1])
2827                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2828         if (previous.wm_linetime[2] != results->wm_linetime[2])
2829                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2830
2831         if (previous.partitioning != results->partitioning) {
2832                 val = I915_READ(WM_MISC);
2833                 if (results->partitioning == INTEL_DDB_PART_1_2)
2834                         val &= ~WM_MISC_DATA_PARTITION_5_6;
2835                 else
2836                         val |= WM_MISC_DATA_PARTITION_5_6;
2837                 I915_WRITE(WM_MISC, val);
2838         }
2839
2840         if (previous.enable_fbc_wm != results->enable_fbc_wm) {
2841                 val = I915_READ(DISP_ARB_CTL);
2842                 if (results->enable_fbc_wm)
2843                         val &= ~DISP_FBC_WM_DIS;
2844                 else
2845                         val |= DISP_FBC_WM_DIS;
2846                 I915_WRITE(DISP_ARB_CTL, val);
2847         }
2848
2849         if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2850                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2851         if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2852                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2853         if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2854                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2855
2856         if (results->wm_lp[0] != 0)
2857                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2858         if (results->wm_lp[1] != 0)
2859                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2860         if (results->wm_lp[2] != 0)
2861                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2862
2863         dev_priv->wm.hw = *results;
2864 }
2865
2866 static void haswell_update_wm(struct drm_crtc *crtc)
2867 {
2868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2869         struct drm_device *dev = crtc->dev;
2870         struct drm_i915_private *dev_priv = dev->dev_private;
2871         struct hsw_wm_maximums max;
2872         struct hsw_pipe_wm_parameters params = {};
2873         struct hsw_wm_values results = {};
2874         enum intel_ddb_partitioning partitioning;
2875         struct intel_pipe_wm pipe_wm = {};
2876         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2877         struct intel_wm_config config = {};
2878
2879         hsw_compute_wm_parameters(crtc, &params, &config);
2880
2881         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2882
2883         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2884                 return;
2885
2886         intel_crtc->wm.active = pipe_wm;
2887
2888         ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2889         ilk_wm_merge(dev, &max, &lp_wm_1_2);
2890
2891         /* 5/6 split only in single pipe config on IVB+ */
2892         if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active == 1) {
2893                 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2894                 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2895
2896                 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2897         } else {
2898                 best_lp_wm = &lp_wm_1_2;
2899         }
2900
2901         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2902                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2903
2904         hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2905
2906         hsw_write_wm_values(dev_priv, &results);
2907 }
2908
2909 static void haswell_update_sprite_wm(struct drm_plane *plane,
2910                                      struct drm_crtc *crtc,
2911                                      uint32_t sprite_width, int pixel_size,
2912                                      bool enabled, bool scaled)
2913 {
2914         struct intel_plane *intel_plane = to_intel_plane(plane);
2915
2916         intel_plane->wm.enabled = enabled;
2917         intel_plane->wm.scaled = scaled;
2918         intel_plane->wm.horiz_pixels = sprite_width;
2919         intel_plane->wm.bytes_per_pixel = pixel_size;
2920
2921         haswell_update_wm(crtc);
2922 }
2923
2924 static bool
2925 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2926                               uint32_t sprite_width, int pixel_size,
2927                               const struct intel_watermark_params *display,
2928                               int display_latency_ns, int *sprite_wm)
2929 {
2930         struct drm_crtc *crtc;
2931         int clock;
2932         int entries, tlb_miss;
2933
2934         crtc = intel_get_crtc_for_plane(dev, plane);
2935         if (!intel_crtc_active(crtc)) {
2936                 *sprite_wm = display->guard_size;
2937                 return false;
2938         }
2939
2940         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2941
2942         /* Use the small buffer method to calculate the sprite watermark */
2943         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2944         tlb_miss = display->fifo_size*display->cacheline_size -
2945                 sprite_width * 8;
2946         if (tlb_miss > 0)
2947                 entries += tlb_miss;
2948         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2949         *sprite_wm = entries + display->guard_size;
2950         if (*sprite_wm > (int)display->max_wm)
2951                 *sprite_wm = display->max_wm;
2952
2953         return true;
2954 }
2955
2956 static bool
2957 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2958                                 uint32_t sprite_width, int pixel_size,
2959                                 const struct intel_watermark_params *display,
2960                                 int latency_ns, int *sprite_wm)
2961 {
2962         struct drm_crtc *crtc;
2963         unsigned long line_time_us;
2964         int clock;
2965         int line_count, line_size;
2966         int small, large;
2967         int entries;
2968
2969         if (!latency_ns) {
2970                 *sprite_wm = 0;
2971                 return false;
2972         }
2973
2974         crtc = intel_get_crtc_for_plane(dev, plane);
2975         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2976         if (!clock) {
2977                 *sprite_wm = 0;
2978                 return false;
2979         }
2980
2981         line_time_us = (sprite_width * 1000) / clock;
2982         if (!line_time_us) {
2983                 *sprite_wm = 0;
2984                 return false;
2985         }
2986
2987         line_count = (latency_ns / line_time_us + 1000) / 1000;
2988         line_size = sprite_width * pixel_size;
2989
2990         /* Use the minimum of the small and large buffer method for primary */
2991         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2992         large = line_count * line_size;
2993
2994         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2995         *sprite_wm = entries + display->guard_size;
2996
2997         return *sprite_wm > 0x3ff ? false : true;
2998 }
2999
3000 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3001                                          struct drm_crtc *crtc,
3002                                          uint32_t sprite_width, int pixel_size,
3003                                          bool enabled, bool scaled)
3004 {
3005         struct drm_device *dev = plane->dev;
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         int pipe = to_intel_plane(plane)->pipe;
3008         int latency = dev_priv->wm.spr_latency[0] * 100;        /* In unit 0.1us */
3009         u32 val;
3010         int sprite_wm, reg;
3011         int ret;
3012
3013         if (!enabled)
3014                 return;
3015
3016         switch (pipe) {
3017         case 0:
3018                 reg = WM0_PIPEA_ILK;
3019                 break;
3020         case 1:
3021                 reg = WM0_PIPEB_ILK;
3022                 break;
3023         case 2:
3024                 reg = WM0_PIPEC_IVB;
3025                 break;
3026         default:
3027                 return; /* bad pipe */
3028         }
3029
3030         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3031                                             &sandybridge_display_wm_info,
3032                                             latency, &sprite_wm);
3033         if (!ret) {
3034                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3035                               pipe_name(pipe));
3036                 return;
3037         }
3038
3039         val = I915_READ(reg);
3040         val &= ~WM0_PIPE_SPRITE_MASK;
3041         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3042         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3043
3044
3045         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3046                                               pixel_size,
3047                                               &sandybridge_display_srwm_info,
3048                                               dev_priv->wm.spr_latency[1] * 500,
3049                                               &sprite_wm);
3050         if (!ret) {
3051                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3052                               pipe_name(pipe));
3053                 return;
3054         }
3055         I915_WRITE(WM1S_LP_ILK, sprite_wm);
3056
3057         /* Only IVB has two more LP watermarks for sprite */
3058         if (!IS_IVYBRIDGE(dev))
3059                 return;
3060
3061         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3062                                               pixel_size,
3063                                               &sandybridge_display_srwm_info,
3064                                               dev_priv->wm.spr_latency[2] * 500,
3065                                               &sprite_wm);
3066         if (!ret) {
3067                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3068                               pipe_name(pipe));
3069                 return;
3070         }
3071         I915_WRITE(WM2S_LP_IVB, sprite_wm);
3072
3073         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3074                                               pixel_size,
3075                                               &sandybridge_display_srwm_info,
3076                                               dev_priv->wm.spr_latency[3] * 500,
3077                                               &sprite_wm);
3078         if (!ret) {
3079                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3080                               pipe_name(pipe));
3081                 return;
3082         }
3083         I915_WRITE(WM3S_LP_IVB, sprite_wm);
3084 }
3085
3086 /**
3087  * intel_update_watermarks - update FIFO watermark values based on current modes
3088  *
3089  * Calculate watermark values for the various WM regs based on current mode
3090  * and plane configuration.
3091  *
3092  * There are several cases to deal with here:
3093  *   - normal (i.e. non-self-refresh)
3094  *   - self-refresh (SR) mode
3095  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3096  *   - lines are small relative to FIFO size (buffer can hold more than 2
3097  *     lines), so need to account for TLB latency
3098  *
3099  *   The normal calculation is:
3100  *     watermark = dotclock * bytes per pixel * latency
3101  *   where latency is platform & configuration dependent (we assume pessimal
3102  *   values here).
3103  *
3104  *   The SR calculation is:
3105  *     watermark = (trunc(latency/line time)+1) * surface width *
3106  *       bytes per pixel
3107  *   where
3108  *     line time = htotal / dotclock
3109  *     surface width = hdisplay for normal plane and 64 for cursor
3110  *   and latency is assumed to be high, as above.
3111  *
3112  * The final value programmed to the register should always be rounded up,
3113  * and include an extra 2 entries to account for clock crossings.
3114  *
3115  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3116  * to set the non-SR watermarks to 8.
3117  */
3118 void intel_update_watermarks(struct drm_crtc *crtc)
3119 {
3120         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3121
3122         if (dev_priv->display.update_wm)
3123                 dev_priv->display.update_wm(crtc);
3124 }
3125
3126 void intel_update_sprite_watermarks(struct drm_plane *plane,
3127                                     struct drm_crtc *crtc,
3128                                     uint32_t sprite_width, int pixel_size,
3129                                     bool enabled, bool scaled)
3130 {
3131         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3132
3133         if (dev_priv->display.update_sprite_wm)
3134                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3135                                                    pixel_size, enabled, scaled);
3136 }
3137
3138 static struct drm_i915_gem_object *
3139 intel_alloc_context_page(struct drm_device *dev)
3140 {
3141         struct drm_i915_gem_object *ctx;
3142         int ret;
3143
3144         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3145
3146         ctx = i915_gem_alloc_object(dev, 4096);
3147         if (!ctx) {
3148                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3149                 return NULL;
3150         }
3151
3152         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3153         if (ret) {
3154                 DRM_ERROR("failed to pin power context: %d\n", ret);
3155                 goto err_unref;
3156         }
3157
3158         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3159         if (ret) {
3160                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3161                 goto err_unpin;
3162         }
3163
3164         return ctx;
3165
3166 err_unpin:
3167         i915_gem_object_unpin(ctx);
3168 err_unref:
3169         drm_gem_object_unreference(&ctx->base);
3170         return NULL;
3171 }
3172
3173 /**
3174  * Lock protecting IPS related data structures
3175  */
3176 DEFINE_SPINLOCK(mchdev_lock);
3177
3178 /* Global for IPS driver to get at the current i915 device. Protected by
3179  * mchdev_lock. */
3180 static struct drm_i915_private *i915_mch_dev;
3181
3182 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3183 {
3184         struct drm_i915_private *dev_priv = dev->dev_private;
3185         u16 rgvswctl;
3186
3187         assert_spin_locked(&mchdev_lock);
3188
3189         rgvswctl = I915_READ16(MEMSWCTL);
3190         if (rgvswctl & MEMCTL_CMD_STS) {
3191                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3192                 return false; /* still busy with another command */
3193         }
3194
3195         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3196                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3197         I915_WRITE16(MEMSWCTL, rgvswctl);
3198         POSTING_READ16(MEMSWCTL);
3199
3200         rgvswctl |= MEMCTL_CMD_STS;
3201         I915_WRITE16(MEMSWCTL, rgvswctl);
3202
3203         return true;
3204 }
3205
3206 static void ironlake_enable_drps(struct drm_device *dev)
3207 {
3208         struct drm_i915_private *dev_priv = dev->dev_private;
3209         u32 rgvmodectl = I915_READ(MEMMODECTL);
3210         u8 fmax, fmin, fstart, vstart;
3211
3212         spin_lock_irq(&mchdev_lock);
3213
3214         /* Enable temp reporting */
3215         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3216         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3217
3218         /* 100ms RC evaluation intervals */
3219         I915_WRITE(RCUPEI, 100000);
3220         I915_WRITE(RCDNEI, 100000);
3221
3222         /* Set max/min thresholds to 90ms and 80ms respectively */
3223         I915_WRITE(RCBMAXAVG, 90000);
3224         I915_WRITE(RCBMINAVG, 80000);
3225
3226         I915_WRITE(MEMIHYST, 1);
3227
3228         /* Set up min, max, and cur for interrupt handling */
3229         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3230         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3231         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3232                 MEMMODE_FSTART_SHIFT;
3233
3234         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3235                 PXVFREQ_PX_SHIFT;
3236
3237         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3238         dev_priv->ips.fstart = fstart;
3239
3240         dev_priv->ips.max_delay = fstart;
3241         dev_priv->ips.min_delay = fmin;
3242         dev_priv->ips.cur_delay = fstart;
3243
3244         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3245                          fmax, fmin, fstart);
3246
3247         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3248
3249         /*
3250          * Interrupts will be enabled in ironlake_irq_postinstall
3251          */
3252
3253         I915_WRITE(VIDSTART, vstart);
3254         POSTING_READ(VIDSTART);
3255
3256         rgvmodectl |= MEMMODE_SWMODE_EN;
3257         I915_WRITE(MEMMODECTL, rgvmodectl);
3258
3259         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3260                 DRM_ERROR("stuck trying to change perf mode\n");
3261         mdelay(1);
3262
3263         ironlake_set_drps(dev, fstart);
3264
3265         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3266                 I915_READ(0x112e0);
3267         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3268         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3269         getrawmonotonic(&dev_priv->ips.last_time2);
3270
3271         spin_unlock_irq(&mchdev_lock);
3272 }
3273
3274 static void ironlake_disable_drps(struct drm_device *dev)
3275 {
3276         struct drm_i915_private *dev_priv = dev->dev_private;
3277         u16 rgvswctl;
3278
3279         spin_lock_irq(&mchdev_lock);
3280
3281         rgvswctl = I915_READ16(MEMSWCTL);
3282
3283         /* Ack interrupts, disable EFC interrupt */
3284         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3285         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3286         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3287         I915_WRITE(DEIIR, DE_PCU_EVENT);
3288         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3289
3290         /* Go back to the starting frequency */
3291         ironlake_set_drps(dev, dev_priv->ips.fstart);
3292         mdelay(1);
3293         rgvswctl |= MEMCTL_CMD_STS;
3294         I915_WRITE(MEMSWCTL, rgvswctl);
3295         mdelay(1);
3296
3297         spin_unlock_irq(&mchdev_lock);
3298 }
3299
3300 /* There's a funny hw issue where the hw returns all 0 when reading from
3301  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3302  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3303  * all limits and the gpu stuck at whatever frequency it is at atm).
3304  */
3305 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3306 {
3307         u32 limits;
3308
3309         limits = 0;
3310
3311         if (*val >= dev_priv->rps.max_delay)
3312                 *val = dev_priv->rps.max_delay;
3313         limits |= dev_priv->rps.max_delay << 24;
3314
3315         /* Only set the down limit when we've reached the lowest level to avoid
3316          * getting more interrupts, otherwise leave this clear. This prevents a
3317          * race in the hw when coming out of rc6: There's a tiny window where
3318          * the hw runs at the minimal clock before selecting the desired
3319          * frequency, if the down threshold expires in that window we will not
3320          * receive a down interrupt. */
3321         if (*val <= dev_priv->rps.min_delay) {
3322                 *val = dev_priv->rps.min_delay;
3323                 limits |= dev_priv->rps.min_delay << 16;
3324         }
3325
3326         return limits;
3327 }
3328
3329 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3330 {
3331         int new_power;
3332
3333         new_power = dev_priv->rps.power;
3334         switch (dev_priv->rps.power) {
3335         case LOW_POWER:
3336                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3337                         new_power = BETWEEN;
3338                 break;
3339
3340         case BETWEEN:
3341                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3342                         new_power = LOW_POWER;
3343                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3344                         new_power = HIGH_POWER;
3345                 break;
3346
3347         case HIGH_POWER:
3348                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3349                         new_power = BETWEEN;
3350                 break;
3351         }
3352         /* Max/min bins are special */
3353         if (val == dev_priv->rps.min_delay)
3354                 new_power = LOW_POWER;
3355         if (val == dev_priv->rps.max_delay)
3356                 new_power = HIGH_POWER;
3357         if (new_power == dev_priv->rps.power)
3358                 return;
3359
3360         /* Note the units here are not exactly 1us, but 1280ns. */
3361         switch (new_power) {
3362         case LOW_POWER:
3363                 /* Upclock if more than 95% busy over 16ms */
3364                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3365                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3366
3367                 /* Downclock if less than 85% busy over 32ms */
3368                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3369                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3370
3371                 I915_WRITE(GEN6_RP_CONTROL,
3372                            GEN6_RP_MEDIA_TURBO |
3373                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3374                            GEN6_RP_MEDIA_IS_GFX |
3375                            GEN6_RP_ENABLE |
3376                            GEN6_RP_UP_BUSY_AVG |
3377                            GEN6_RP_DOWN_IDLE_AVG);
3378                 break;
3379
3380         case BETWEEN:
3381                 /* Upclock if more than 90% busy over 13ms */
3382                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3383                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3384
3385                 /* Downclock if less than 75% busy over 32ms */
3386                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3387                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3388
3389                 I915_WRITE(GEN6_RP_CONTROL,
3390                            GEN6_RP_MEDIA_TURBO |
3391                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3392                            GEN6_RP_MEDIA_IS_GFX |
3393                            GEN6_RP_ENABLE |
3394                            GEN6_RP_UP_BUSY_AVG |
3395                            GEN6_RP_DOWN_IDLE_AVG);
3396                 break;
3397
3398         case HIGH_POWER:
3399                 /* Upclock if more than 85% busy over 10ms */
3400                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3401                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3402
3403                 /* Downclock if less than 60% busy over 32ms */
3404                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3405                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3406
3407                 I915_WRITE(GEN6_RP_CONTROL,
3408                            GEN6_RP_MEDIA_TURBO |
3409                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3410                            GEN6_RP_MEDIA_IS_GFX |
3411                            GEN6_RP_ENABLE |
3412                            GEN6_RP_UP_BUSY_AVG |
3413                            GEN6_RP_DOWN_IDLE_AVG);
3414                 break;
3415         }
3416
3417         dev_priv->rps.power = new_power;
3418         dev_priv->rps.last_adj = 0;
3419 }
3420
3421 void gen6_set_rps(struct drm_device *dev, u8 val)
3422 {
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         u32 limits = gen6_rps_limits(dev_priv, &val);
3425
3426         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3427         WARN_ON(val > dev_priv->rps.max_delay);
3428         WARN_ON(val < dev_priv->rps.min_delay);
3429
3430         if (val == dev_priv->rps.cur_delay)
3431                 return;
3432
3433         gen6_set_rps_thresholds(dev_priv, val);
3434
3435         if (IS_HASWELL(dev))
3436                 I915_WRITE(GEN6_RPNSWREQ,
3437                            HSW_FREQUENCY(val));
3438         else
3439                 I915_WRITE(GEN6_RPNSWREQ,
3440                            GEN6_FREQUENCY(val) |
3441                            GEN6_OFFSET(0) |
3442                            GEN6_AGGRESSIVE_TURBO);
3443
3444         /* Make sure we continue to get interrupts
3445          * until we hit the minimum or maximum frequencies.
3446          */
3447         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3448
3449         POSTING_READ(GEN6_RPNSWREQ);
3450
3451         dev_priv->rps.cur_delay = val;
3452
3453         trace_intel_gpu_freq_change(val * 50);
3454 }
3455
3456 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3457 {
3458         mutex_lock(&dev_priv->rps.hw_lock);
3459         if (dev_priv->rps.enabled) {
3460                 if (dev_priv->info->is_valleyview)
3461                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3462                 else
3463                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3464                 dev_priv->rps.last_adj = 0;
3465         }
3466         mutex_unlock(&dev_priv->rps.hw_lock);
3467 }
3468
3469 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3470 {
3471         mutex_lock(&dev_priv->rps.hw_lock);
3472         if (dev_priv->rps.enabled) {
3473                 if (dev_priv->info->is_valleyview)
3474                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3475                 else
3476                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3477                 dev_priv->rps.last_adj = 0;
3478         }
3479         mutex_unlock(&dev_priv->rps.hw_lock);
3480 }
3481
3482 /*
3483  * Wait until the previous freq change has completed,
3484  * or the timeout elapsed, and then update our notion
3485  * of the current GPU frequency.
3486  */
3487 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3488 {
3489         u32 pval;
3490
3491         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3492
3493         if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3494                 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3495
3496         pval >>= 8;
3497
3498         if (pval != dev_priv->rps.cur_delay)
3499                 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3500                                  vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3501                                  dev_priv->rps.cur_delay,
3502                                  vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3503
3504         dev_priv->rps.cur_delay = pval;
3505 }
3506
3507 void valleyview_set_rps(struct drm_device *dev, u8 val)
3508 {
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510
3511         gen6_rps_limits(dev_priv, &val);
3512
3513         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3514         WARN_ON(val > dev_priv->rps.max_delay);
3515         WARN_ON(val < dev_priv->rps.min_delay);
3516
3517         vlv_update_rps_cur_delay(dev_priv);
3518
3519         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3520                          vlv_gpu_freq(dev_priv->mem_freq,
3521                                       dev_priv->rps.cur_delay),
3522                          dev_priv->rps.cur_delay,
3523                          vlv_gpu_freq(dev_priv->mem_freq, val), val);
3524
3525         if (val == dev_priv->rps.cur_delay)
3526                 return;
3527
3528         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3529
3530         dev_priv->rps.cur_delay = val;
3531
3532         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3533 }
3534
3535 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3536 {
3537         struct drm_i915_private *dev_priv = dev->dev_private;
3538
3539         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3540         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3541         /* Complete PM interrupt masking here doesn't race with the rps work
3542          * item again unmasking PM interrupts because that is using a different
3543          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3544          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3545
3546         spin_lock_irq(&dev_priv->irq_lock);
3547         dev_priv->rps.pm_iir = 0;
3548         spin_unlock_irq(&dev_priv->irq_lock);
3549
3550         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3551 }
3552
3553 static void gen6_disable_rps(struct drm_device *dev)
3554 {
3555         struct drm_i915_private *dev_priv = dev->dev_private;
3556
3557         I915_WRITE(GEN6_RC_CONTROL, 0);
3558         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3559
3560         gen6_disable_rps_interrupts(dev);
3561 }
3562
3563 static void valleyview_disable_rps(struct drm_device *dev)
3564 {
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566
3567         I915_WRITE(GEN6_RC_CONTROL, 0);
3568
3569         gen6_disable_rps_interrupts(dev);
3570
3571         if (dev_priv->vlv_pctx) {
3572                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3573                 dev_priv->vlv_pctx = NULL;
3574         }
3575 }
3576
3577 int intel_enable_rc6(const struct drm_device *dev)
3578 {
3579         /* No RC6 before Ironlake */
3580         if (INTEL_INFO(dev)->gen < 5)
3581                 return 0;
3582
3583         /* Respect the kernel parameter if it is set */
3584         if (i915_enable_rc6 >= 0)
3585                 return i915_enable_rc6;
3586
3587         /* Disable RC6 on Ironlake */
3588         if (INTEL_INFO(dev)->gen == 5)
3589                 return 0;
3590
3591         if (IS_HASWELL(dev)) {
3592                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3593                 return INTEL_RC6_ENABLE;
3594         }
3595
3596         /* snb/ivb have more than one rc6 state. */
3597         if (INTEL_INFO(dev)->gen == 6) {
3598                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3599                 return INTEL_RC6_ENABLE;
3600         }
3601
3602         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3603         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3604 }
3605
3606 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3607 {
3608         struct drm_i915_private *dev_priv = dev->dev_private;
3609         u32 enabled_intrs;
3610
3611         spin_lock_irq(&dev_priv->irq_lock);
3612         WARN_ON(dev_priv->rps.pm_iir);
3613         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3614         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3615         spin_unlock_irq(&dev_priv->irq_lock);
3616
3617         /* only unmask PM interrupts we need. Mask all others. */
3618         enabled_intrs = GEN6_PM_RPS_EVENTS;
3619
3620         /* IVB and SNB hard hangs on looping batchbuffer
3621          * if GEN6_PM_UP_EI_EXPIRED is masked.
3622          */
3623         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3624                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3625
3626         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3627 }
3628
3629 static void gen6_enable_rps(struct drm_device *dev)
3630 {
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632         struct intel_ring_buffer *ring;
3633         u32 rp_state_cap;
3634         u32 gt_perf_status;
3635         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3636         u32 gtfifodbg;
3637         int rc6_mode;
3638         int i, ret;
3639
3640         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3641
3642         /* Here begins a magic sequence of register writes to enable
3643          * auto-downclocking.
3644          *
3645          * Perhaps there might be some value in exposing these to
3646          * userspace...
3647          */
3648         I915_WRITE(GEN6_RC_STATE, 0);
3649
3650         /* Clear the DBG now so we don't confuse earlier errors */
3651         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3652                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3653                 I915_WRITE(GTFIFODBG, gtfifodbg);
3654         }
3655
3656         gen6_gt_force_wake_get(dev_priv);
3657
3658         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3659         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3660
3661         /* In units of 50MHz */
3662         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3663         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3664         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3665         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3666         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3667         dev_priv->rps.cur_delay = 0;
3668
3669         /* disable the counters and set deterministic thresholds */
3670         I915_WRITE(GEN6_RC_CONTROL, 0);
3671
3672         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3673         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3674         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3675         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3676         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3677
3678         for_each_ring(ring, dev_priv, i)
3679                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3680
3681         I915_WRITE(GEN6_RC_SLEEP, 0);
3682         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3683         if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3684                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3685         else
3686                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3687         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3688         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3689
3690         /* Check if we are enabling RC6 */
3691         rc6_mode = intel_enable_rc6(dev_priv->dev);
3692         if (rc6_mode & INTEL_RC6_ENABLE)
3693                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3694
3695         /* We don't use those on Haswell */
3696         if (!IS_HASWELL(dev)) {
3697                 if (rc6_mode & INTEL_RC6p_ENABLE)
3698                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3699
3700                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3701                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3702         }
3703
3704         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3705                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3706                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3707                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3708
3709         I915_WRITE(GEN6_RC_CONTROL,
3710                    rc6_mask |
3711                    GEN6_RC_CTL_EI_MODE(1) |
3712                    GEN6_RC_CTL_HW_ENABLE);
3713
3714         /* Power down if completely idle for over 50ms */
3715         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3716         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3717
3718         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3719         if (!ret) {
3720                 pcu_mbox = 0;
3721                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3722                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3723                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3724                                          (dev_priv->rps.max_delay & 0xff) * 50,
3725                                          (pcu_mbox & 0xff) * 50);
3726                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3727                 }
3728         } else {
3729                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3730         }
3731
3732         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3733         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3734
3735         gen6_enable_rps_interrupts(dev);
3736
3737         rc6vids = 0;
3738         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3739         if (IS_GEN6(dev) && ret) {
3740                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3741         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3742                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3743                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3744                 rc6vids &= 0xffff00;
3745                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3746                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3747                 if (ret)
3748                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3749         }
3750
3751         gen6_gt_force_wake_put(dev_priv);
3752 }
3753
3754 void gen6_update_ring_freq(struct drm_device *dev)
3755 {
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757         int min_freq = 15;
3758         unsigned int gpu_freq;
3759         unsigned int max_ia_freq, min_ring_freq;
3760         int scaling_factor = 180;
3761         struct cpufreq_policy *policy;
3762
3763         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3764
3765         policy = cpufreq_cpu_get(0);
3766         if (policy) {
3767                 max_ia_freq = policy->cpuinfo.max_freq;
3768                 cpufreq_cpu_put(policy);
3769         } else {
3770                 /*
3771                  * Default to measured freq if none found, PCU will ensure we
3772                  * don't go over
3773                  */
3774                 max_ia_freq = tsc_khz;
3775         }
3776
3777         /* Convert from kHz to MHz */
3778         max_ia_freq /= 1000;
3779
3780         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3781         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3782         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3783
3784         /*
3785          * For each potential GPU frequency, load a ring frequency we'd like
3786          * to use for memory access.  We do this by specifying the IA frequency
3787          * the PCU should use as a reference to determine the ring frequency.
3788          */
3789         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3790              gpu_freq--) {
3791                 int diff = dev_priv->rps.max_delay - gpu_freq;
3792                 unsigned int ia_freq = 0, ring_freq = 0;
3793
3794                 if (IS_HASWELL(dev)) {
3795                         ring_freq = mult_frac(gpu_freq, 5, 4);
3796                         ring_freq = max(min_ring_freq, ring_freq);
3797                         /* leave ia_freq as the default, chosen by cpufreq */
3798                 } else {
3799                         /* On older processors, there is no separate ring
3800                          * clock domain, so in order to boost the bandwidth
3801                          * of the ring, we need to upclock the CPU (ia_freq).
3802                          *
3803                          * For GPU frequencies less than 750MHz,
3804                          * just use the lowest ring freq.
3805                          */
3806                         if (gpu_freq < min_freq)
3807                                 ia_freq = 800;
3808                         else
3809                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3810                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3811                 }
3812
3813                 sandybridge_pcode_write(dev_priv,
3814                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3815                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3816                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3817                                         gpu_freq);
3818         }
3819 }
3820
3821 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3822 {
3823         u32 val, rp0;
3824
3825         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3826
3827         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3828         /* Clamp to max */
3829         rp0 = min_t(u32, rp0, 0xea);
3830
3831         return rp0;
3832 }
3833
3834 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3835 {
3836         u32 val, rpe;
3837
3838         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3839         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3840         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3841         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3842
3843         return rpe;
3844 }
3845
3846 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3847 {
3848         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3849 }
3850
3851 static void valleyview_setup_pctx(struct drm_device *dev)
3852 {
3853         struct drm_i915_private *dev_priv = dev->dev_private;
3854         struct drm_i915_gem_object *pctx;
3855         unsigned long pctx_paddr;
3856         u32 pcbr;
3857         int pctx_size = 24*1024;
3858
3859         pcbr = I915_READ(VLV_PCBR);
3860         if (pcbr) {
3861                 /* BIOS set it up already, grab the pre-alloc'd space */
3862                 int pcbr_offset;
3863
3864                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3865                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3866                                                                       pcbr_offset,
3867                                                                       I915_GTT_OFFSET_NONE,
3868                                                                       pctx_size);
3869                 goto out;
3870         }
3871
3872         /*
3873          * From the Gunit register HAS:
3874          * The Gfx driver is expected to program this register and ensure
3875          * proper allocation within Gfx stolen memory.  For example, this
3876          * register should be programmed such than the PCBR range does not
3877          * overlap with other ranges, such as the frame buffer, protected
3878          * memory, or any other relevant ranges.
3879          */
3880         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3881         if (!pctx) {
3882                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3883                 return;
3884         }
3885
3886         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3887         I915_WRITE(VLV_PCBR, pctx_paddr);
3888
3889 out:
3890         dev_priv->vlv_pctx = pctx;
3891 }
3892
3893 static void valleyview_enable_rps(struct drm_device *dev)
3894 {
3895         struct drm_i915_private *dev_priv = dev->dev_private;
3896         struct intel_ring_buffer *ring;
3897         u32 gtfifodbg, val, rc6_mode = 0;
3898         int i;
3899
3900         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3901
3902         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3903                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3904                                  gtfifodbg);
3905                 I915_WRITE(GTFIFODBG, gtfifodbg);
3906         }
3907
3908         valleyview_setup_pctx(dev);
3909
3910         gen6_gt_force_wake_get(dev_priv);
3911
3912         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3913         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3914         I915_WRITE(GEN6_RP_UP_EI, 66000);
3915         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3916
3917         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3918
3919         I915_WRITE(GEN6_RP_CONTROL,
3920                    GEN6_RP_MEDIA_TURBO |
3921                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3922                    GEN6_RP_MEDIA_IS_GFX |
3923                    GEN6_RP_ENABLE |
3924                    GEN6_RP_UP_BUSY_AVG |
3925                    GEN6_RP_DOWN_IDLE_CONT);
3926
3927         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3928         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3929         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3930
3931         for_each_ring(ring, dev_priv, i)
3932                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3933
3934         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3935
3936         /* allows RC6 residency counter to work */
3937         I915_WRITE(VLV_COUNTER_CONTROL,
3938                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3939                                       VLV_MEDIA_RC6_COUNT_EN |
3940                                       VLV_RENDER_RC6_COUNT_EN));
3941         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3942                 rc6_mode = GEN7_RC_CTL_TO_MODE;
3943         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3944
3945         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3946         switch ((val >> 6) & 3) {
3947         case 0:
3948         case 1:
3949                 dev_priv->mem_freq = 800;
3950                 break;
3951         case 2:
3952                 dev_priv->mem_freq = 1066;
3953                 break;
3954         case 3:
3955                 dev_priv->mem_freq = 1333;
3956                 break;
3957         }
3958         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3959
3960         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3961         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3962
3963         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3964         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3965                          vlv_gpu_freq(dev_priv->mem_freq,
3966                                       dev_priv->rps.cur_delay),
3967                          dev_priv->rps.cur_delay);
3968
3969         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3970         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3971         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3972                          vlv_gpu_freq(dev_priv->mem_freq,
3973                                       dev_priv->rps.max_delay),
3974                          dev_priv->rps.max_delay);
3975
3976         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3977         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3978                          vlv_gpu_freq(dev_priv->mem_freq,
3979                                       dev_priv->rps.rpe_delay),
3980                          dev_priv->rps.rpe_delay);
3981
3982         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3983         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3984                          vlv_gpu_freq(dev_priv->mem_freq,
3985                                       dev_priv->rps.min_delay),
3986                          dev_priv->rps.min_delay);
3987
3988         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3989                          vlv_gpu_freq(dev_priv->mem_freq,
3990                                       dev_priv->rps.rpe_delay),
3991                          dev_priv->rps.rpe_delay);
3992
3993         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3994
3995         gen6_enable_rps_interrupts(dev);
3996
3997         gen6_gt_force_wake_put(dev_priv);
3998 }
3999
4000 void ironlake_teardown_rc6(struct drm_device *dev)
4001 {
4002         struct drm_i915_private *dev_priv = dev->dev_private;
4003
4004         if (dev_priv->ips.renderctx) {
4005                 i915_gem_object_unpin(dev_priv->ips.renderctx);
4006                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4007                 dev_priv->ips.renderctx = NULL;
4008         }
4009
4010         if (dev_priv->ips.pwrctx) {
4011                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4012                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4013                 dev_priv->ips.pwrctx = NULL;
4014         }
4015 }
4016
4017 static void ironlake_disable_rc6(struct drm_device *dev)
4018 {
4019         struct drm_i915_private *dev_priv = dev->dev_private;
4020
4021         if (I915_READ(PWRCTXA)) {
4022                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4023                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4024                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4025                          50);
4026
4027                 I915_WRITE(PWRCTXA, 0);
4028                 POSTING_READ(PWRCTXA);
4029
4030                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4031                 POSTING_READ(RSTDBYCTL);
4032         }
4033 }
4034
4035 static int ironlake_setup_rc6(struct drm_device *dev)
4036 {
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038
4039         if (dev_priv->ips.renderctx == NULL)
4040                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4041         if (!dev_priv->ips.renderctx)
4042                 return -ENOMEM;
4043
4044         if (dev_priv->ips.pwrctx == NULL)
4045                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4046         if (!dev_priv->ips.pwrctx) {
4047                 ironlake_teardown_rc6(dev);
4048                 return -ENOMEM;
4049         }
4050
4051         return 0;
4052 }
4053
4054 static void ironlake_enable_rc6(struct drm_device *dev)
4055 {
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4058         bool was_interruptible;
4059         int ret;
4060
4061         /* rc6 disabled by default due to repeated reports of hanging during
4062          * boot and resume.
4063          */
4064         if (!intel_enable_rc6(dev))
4065                 return;
4066
4067         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4068
4069         ret = ironlake_setup_rc6(dev);
4070         if (ret)
4071                 return;
4072
4073         was_interruptible = dev_priv->mm.interruptible;
4074         dev_priv->mm.interruptible = false;
4075
4076         /*
4077          * GPU can automatically power down the render unit if given a page
4078          * to save state.
4079          */
4080         ret = intel_ring_begin(ring, 6);
4081         if (ret) {
4082                 ironlake_teardown_rc6(dev);
4083                 dev_priv->mm.interruptible = was_interruptible;
4084                 return;
4085         }
4086
4087         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4088         intel_ring_emit(ring, MI_SET_CONTEXT);
4089         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4090                         MI_MM_SPACE_GTT |
4091                         MI_SAVE_EXT_STATE_EN |
4092                         MI_RESTORE_EXT_STATE_EN |
4093                         MI_RESTORE_INHIBIT);
4094         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4095         intel_ring_emit(ring, MI_NOOP);
4096         intel_ring_emit(ring, MI_FLUSH);
4097         intel_ring_advance(ring);
4098
4099         /*
4100          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4101          * does an implicit flush, combined with MI_FLUSH above, it should be
4102          * safe to assume that renderctx is valid
4103          */
4104         ret = intel_ring_idle(ring);
4105         dev_priv->mm.interruptible = was_interruptible;
4106         if (ret) {
4107                 DRM_ERROR("failed to enable ironlake power savings\n");
4108                 ironlake_teardown_rc6(dev);
4109                 return;
4110         }
4111
4112         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4113         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4114 }
4115
4116 static unsigned long intel_pxfreq(u32 vidfreq)
4117 {
4118         unsigned long freq;
4119         int div = (vidfreq & 0x3f0000) >> 16;
4120         int post = (vidfreq & 0x3000) >> 12;
4121         int pre = (vidfreq & 0x7);
4122
4123         if (!pre)
4124                 return 0;
4125
4126         freq = ((div * 133333) / ((1<<post) * pre));
4127
4128         return freq;
4129 }
4130
4131 static const struct cparams {
4132         u16 i;
4133         u16 t;
4134         u16 m;
4135         u16 c;
4136 } cparams[] = {
4137         { 1, 1333, 301, 28664 },
4138         { 1, 1066, 294, 24460 },
4139         { 1, 800, 294, 25192 },
4140         { 0, 1333, 276, 27605 },
4141         { 0, 1066, 276, 27605 },
4142         { 0, 800, 231, 23784 },
4143 };
4144
4145 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4146 {
4147         u64 total_count, diff, ret;
4148         u32 count1, count2, count3, m = 0, c = 0;
4149         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4150         int i;
4151
4152         assert_spin_locked(&mchdev_lock);
4153
4154         diff1 = now - dev_priv->ips.last_time1;
4155
4156         /* Prevent division-by-zero if we are asking too fast.
4157          * Also, we don't get interesting results if we are polling
4158          * faster than once in 10ms, so just return the saved value
4159          * in such cases.
4160          */
4161         if (diff1 <= 10)
4162                 return dev_priv->ips.chipset_power;
4163
4164         count1 = I915_READ(DMIEC);
4165         count2 = I915_READ(DDREC);
4166         count3 = I915_READ(CSIEC);
4167
4168         total_count = count1 + count2 + count3;
4169
4170         /* FIXME: handle per-counter overflow */
4171         if (total_count < dev_priv->ips.last_count1) {
4172                 diff = ~0UL - dev_priv->ips.last_count1;
4173                 diff += total_count;
4174         } else {
4175                 diff = total_count - dev_priv->ips.last_count1;
4176         }
4177
4178         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4179                 if (cparams[i].i == dev_priv->ips.c_m &&
4180                     cparams[i].t == dev_priv->ips.r_t) {
4181                         m = cparams[i].m;
4182                         c = cparams[i].c;
4183                         break;
4184                 }
4185         }
4186
4187         diff = div_u64(diff, diff1);
4188         ret = ((m * diff) + c);
4189         ret = div_u64(ret, 10);
4190
4191         dev_priv->ips.last_count1 = total_count;
4192         dev_priv->ips.last_time1 = now;
4193
4194         dev_priv->ips.chipset_power = ret;
4195
4196         return ret;
4197 }
4198
4199 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4200 {
4201         unsigned long val;
4202
4203         if (dev_priv->info->gen != 5)
4204                 return 0;
4205
4206         spin_lock_irq(&mchdev_lock);
4207
4208         val = __i915_chipset_val(dev_priv);
4209
4210         spin_unlock_irq(&mchdev_lock);
4211
4212         return val;
4213 }
4214
4215 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4216 {
4217         unsigned long m, x, b;
4218         u32 tsfs;
4219
4220         tsfs = I915_READ(TSFS);
4221
4222         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4223         x = I915_READ8(TR1);
4224
4225         b = tsfs & TSFS_INTR_MASK;
4226
4227         return ((m * x) / 127) - b;
4228 }
4229
4230 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4231 {
4232         static const struct v_table {
4233                 u16 vd; /* in .1 mil */
4234                 u16 vm; /* in .1 mil */
4235         } v_table[] = {
4236                 { 0, 0, },
4237                 { 375, 0, },
4238                 { 500, 0, },
4239                 { 625, 0, },
4240                 { 750, 0, },
4241                 { 875, 0, },
4242                 { 1000, 0, },
4243                 { 1125, 0, },
4244                 { 4125, 3000, },
4245                 { 4125, 3000, },
4246                 { 4125, 3000, },
4247                 { 4125, 3000, },
4248                 { 4125, 3000, },
4249                 { 4125, 3000, },
4250                 { 4125, 3000, },
4251                 { 4125, 3000, },
4252                 { 4125, 3000, },
4253                 { 4125, 3000, },
4254                 { 4125, 3000, },
4255                 { 4125, 3000, },
4256                 { 4125, 3000, },
4257                 { 4125, 3000, },
4258                 { 4125, 3000, },
4259                 { 4125, 3000, },
4260                 { 4125, 3000, },
4261                 { 4125, 3000, },
4262                 { 4125, 3000, },
4263                 { 4125, 3000, },
4264                 { 4125, 3000, },
4265                 { 4125, 3000, },
4266                 { 4125, 3000, },
4267                 { 4125, 3000, },
4268                 { 4250, 3125, },
4269                 { 4375, 3250, },
4270                 { 4500, 3375, },
4271                 { 4625, 3500, },
4272                 { 4750, 3625, },
4273                 { 4875, 3750, },
4274                 { 5000, 3875, },
4275                 { 5125, 4000, },
4276                 { 5250, 4125, },
4277                 { 5375, 4250, },
4278                 { 5500, 4375, },
4279                 { 5625, 4500, },
4280                 { 5750, 4625, },
4281                 { 5875, 4750, },
4282                 { 6000, 4875, },
4283                 { 6125, 5000, },
4284                 { 6250, 5125, },
4285                 { 6375, 5250, },
4286                 { 6500, 5375, },
4287                 { 6625, 5500, },
4288                 { 6750, 5625, },
4289                 { 6875, 5750, },
4290                 { 7000, 5875, },
4291                 { 7125, 6000, },
4292                 { 7250, 6125, },
4293                 { 7375, 6250, },
4294                 { 7500, 6375, },
4295                 { 7625, 6500, },
4296                 { 7750, 6625, },
4297                 { 7875, 6750, },
4298                 { 8000, 6875, },
4299                 { 8125, 7000, },
4300                 { 8250, 7125, },
4301                 { 8375, 7250, },
4302                 { 8500, 7375, },
4303                 { 8625, 7500, },
4304                 { 8750, 7625, },
4305                 { 8875, 7750, },
4306                 { 9000, 7875, },
4307                 { 9125, 8000, },
4308                 { 9250, 8125, },
4309                 { 9375, 8250, },
4310                 { 9500, 8375, },
4311                 { 9625, 8500, },
4312                 { 9750, 8625, },
4313                 { 9875, 8750, },
4314                 { 10000, 8875, },
4315                 { 10125, 9000, },
4316                 { 10250, 9125, },
4317                 { 10375, 9250, },
4318                 { 10500, 9375, },
4319                 { 10625, 9500, },
4320                 { 10750, 9625, },
4321                 { 10875, 9750, },
4322                 { 11000, 9875, },
4323                 { 11125, 10000, },
4324                 { 11250, 10125, },
4325                 { 11375, 10250, },
4326                 { 11500, 10375, },
4327                 { 11625, 10500, },
4328                 { 11750, 10625, },
4329                 { 11875, 10750, },
4330                 { 12000, 10875, },
4331                 { 12125, 11000, },
4332                 { 12250, 11125, },
4333                 { 12375, 11250, },
4334                 { 12500, 11375, },
4335                 { 12625, 11500, },
4336                 { 12750, 11625, },
4337                 { 12875, 11750, },
4338                 { 13000, 11875, },
4339                 { 13125, 12000, },
4340                 { 13250, 12125, },
4341                 { 13375, 12250, },
4342                 { 13500, 12375, },
4343                 { 13625, 12500, },
4344                 { 13750, 12625, },
4345                 { 13875, 12750, },
4346                 { 14000, 12875, },
4347                 { 14125, 13000, },
4348                 { 14250, 13125, },
4349                 { 14375, 13250, },
4350                 { 14500, 13375, },
4351                 { 14625, 13500, },
4352                 { 14750, 13625, },
4353                 { 14875, 13750, },
4354                 { 15000, 13875, },
4355                 { 15125, 14000, },
4356                 { 15250, 14125, },
4357                 { 15375, 14250, },
4358                 { 15500, 14375, },
4359                 { 15625, 14500, },
4360                 { 15750, 14625, },
4361                 { 15875, 14750, },
4362                 { 16000, 14875, },
4363                 { 16125, 15000, },
4364         };
4365         if (dev_priv->info->is_mobile)
4366                 return v_table[pxvid].vm;
4367         else
4368                 return v_table[pxvid].vd;
4369 }
4370
4371 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4372 {
4373         struct timespec now, diff1;
4374         u64 diff;
4375         unsigned long diffms;
4376         u32 count;
4377
4378         assert_spin_locked(&mchdev_lock);
4379
4380         getrawmonotonic(&now);
4381         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4382
4383         /* Don't divide by 0 */
4384         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4385         if (!diffms)
4386                 return;
4387
4388         count = I915_READ(GFXEC);
4389
4390         if (count < dev_priv->ips.last_count2) {
4391                 diff = ~0UL - dev_priv->ips.last_count2;
4392                 diff += count;
4393         } else {
4394                 diff = count - dev_priv->ips.last_count2;
4395         }
4396
4397         dev_priv->ips.last_count2 = count;
4398         dev_priv->ips.last_time2 = now;
4399
4400         /* More magic constants... */
4401         diff = diff * 1181;
4402         diff = div_u64(diff, diffms * 10);
4403         dev_priv->ips.gfx_power = diff;
4404 }
4405
4406 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4407 {
4408         if (dev_priv->info->gen != 5)
4409                 return;
4410
4411         spin_lock_irq(&mchdev_lock);
4412
4413         __i915_update_gfx_val(dev_priv);
4414
4415         spin_unlock_irq(&mchdev_lock);
4416 }
4417
4418 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4419 {
4420         unsigned long t, corr, state1, corr2, state2;
4421         u32 pxvid, ext_v;
4422
4423         assert_spin_locked(&mchdev_lock);
4424
4425         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4426         pxvid = (pxvid >> 24) & 0x7f;
4427         ext_v = pvid_to_extvid(dev_priv, pxvid);
4428
4429         state1 = ext_v;
4430
4431         t = i915_mch_val(dev_priv);
4432
4433         /* Revel in the empirically derived constants */
4434
4435         /* Correction factor in 1/100000 units */
4436         if (t > 80)
4437                 corr = ((t * 2349) + 135940);
4438         else if (t >= 50)
4439                 corr = ((t * 964) + 29317);
4440         else /* < 50 */
4441                 corr = ((t * 301) + 1004);
4442
4443         corr = corr * ((150142 * state1) / 10000 - 78642);
4444         corr /= 100000;
4445         corr2 = (corr * dev_priv->ips.corr);
4446
4447         state2 = (corr2 * state1) / 10000;
4448         state2 /= 100; /* convert to mW */
4449
4450         __i915_update_gfx_val(dev_priv);
4451
4452         return dev_priv->ips.gfx_power + state2;
4453 }
4454
4455 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4456 {
4457         unsigned long val;
4458
4459         if (dev_priv->info->gen != 5)
4460                 return 0;
4461
4462         spin_lock_irq(&mchdev_lock);
4463
4464         val = __i915_gfx_val(dev_priv);
4465
4466         spin_unlock_irq(&mchdev_lock);
4467
4468         return val;
4469 }
4470
4471 /**
4472  * i915_read_mch_val - return value for IPS use
4473  *
4474  * Calculate and return a value for the IPS driver to use when deciding whether
4475  * we have thermal and power headroom to increase CPU or GPU power budget.
4476  */
4477 unsigned long i915_read_mch_val(void)
4478 {
4479         struct drm_i915_private *dev_priv;
4480         unsigned long chipset_val, graphics_val, ret = 0;
4481
4482         spin_lock_irq(&mchdev_lock);
4483         if (!i915_mch_dev)
4484                 goto out_unlock;
4485         dev_priv = i915_mch_dev;
4486
4487         chipset_val = __i915_chipset_val(dev_priv);
4488         graphics_val = __i915_gfx_val(dev_priv);
4489
4490         ret = chipset_val + graphics_val;
4491
4492 out_unlock:
4493         spin_unlock_irq(&mchdev_lock);
4494
4495         return ret;
4496 }
4497 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4498
4499 /**
4500  * i915_gpu_raise - raise GPU frequency limit
4501  *
4502  * Raise the limit; IPS indicates we have thermal headroom.
4503  */
4504 bool i915_gpu_raise(void)
4505 {
4506         struct drm_i915_private *dev_priv;
4507         bool ret = true;
4508
4509         spin_lock_irq(&mchdev_lock);
4510         if (!i915_mch_dev) {
4511                 ret = false;
4512                 goto out_unlock;
4513         }
4514         dev_priv = i915_mch_dev;
4515
4516         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4517                 dev_priv->ips.max_delay--;
4518
4519 out_unlock:
4520         spin_unlock_irq(&mchdev_lock);
4521
4522         return ret;
4523 }
4524 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4525
4526 /**
4527  * i915_gpu_lower - lower GPU frequency limit
4528  *
4529  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4530  * frequency maximum.
4531  */
4532 bool i915_gpu_lower(void)
4533 {
4534         struct drm_i915_private *dev_priv;
4535         bool ret = true;
4536
4537         spin_lock_irq(&mchdev_lock);
4538         if (!i915_mch_dev) {
4539                 ret = false;
4540                 goto out_unlock;
4541         }
4542         dev_priv = i915_mch_dev;
4543
4544         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4545                 dev_priv->ips.max_delay++;
4546
4547 out_unlock:
4548         spin_unlock_irq(&mchdev_lock);
4549
4550         return ret;
4551 }
4552 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4553
4554 /**
4555  * i915_gpu_busy - indicate GPU business to IPS
4556  *
4557  * Tell the IPS driver whether or not the GPU is busy.
4558  */
4559 bool i915_gpu_busy(void)
4560 {
4561         struct drm_i915_private *dev_priv;
4562         struct intel_ring_buffer *ring;
4563         bool ret = false;
4564         int i;
4565
4566         spin_lock_irq(&mchdev_lock);
4567         if (!i915_mch_dev)
4568                 goto out_unlock;
4569         dev_priv = i915_mch_dev;
4570
4571         for_each_ring(ring, dev_priv, i)
4572                 ret |= !list_empty(&ring->request_list);
4573
4574 out_unlock:
4575         spin_unlock_irq(&mchdev_lock);
4576
4577         return ret;
4578 }
4579 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4580
4581 /**
4582  * i915_gpu_turbo_disable - disable graphics turbo
4583  *
4584  * Disable graphics turbo by resetting the max frequency and setting the
4585  * current frequency to the default.
4586  */
4587 bool i915_gpu_turbo_disable(void)
4588 {
4589         struct drm_i915_private *dev_priv;
4590         bool ret = true;
4591
4592         spin_lock_irq(&mchdev_lock);
4593         if (!i915_mch_dev) {
4594                 ret = false;
4595                 goto out_unlock;
4596         }
4597         dev_priv = i915_mch_dev;
4598
4599         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4600
4601         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4602                 ret = false;
4603
4604 out_unlock:
4605         spin_unlock_irq(&mchdev_lock);
4606
4607         return ret;
4608 }
4609 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4610
4611 /**
4612  * Tells the intel_ips driver that the i915 driver is now loaded, if
4613  * IPS got loaded first.
4614  *
4615  * This awkward dance is so that neither module has to depend on the
4616  * other in order for IPS to do the appropriate communication of
4617  * GPU turbo limits to i915.
4618  */
4619 static void
4620 ips_ping_for_i915_load(void)
4621 {
4622         void (*link)(void);
4623
4624         link = symbol_get(ips_link_to_i915_driver);
4625         if (link) {
4626                 link();
4627                 symbol_put(ips_link_to_i915_driver);
4628         }
4629 }
4630
4631 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4632 {
4633         /* We only register the i915 ips part with intel-ips once everything is
4634          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4635         spin_lock_irq(&mchdev_lock);
4636         i915_mch_dev = dev_priv;
4637         spin_unlock_irq(&mchdev_lock);
4638
4639         ips_ping_for_i915_load();
4640 }
4641
4642 void intel_gpu_ips_teardown(void)
4643 {
4644         spin_lock_irq(&mchdev_lock);
4645         i915_mch_dev = NULL;
4646         spin_unlock_irq(&mchdev_lock);
4647 }
4648 static void intel_init_emon(struct drm_device *dev)
4649 {
4650         struct drm_i915_private *dev_priv = dev->dev_private;
4651         u32 lcfuse;
4652         u8 pxw[16];
4653         int i;
4654
4655         /* Disable to program */
4656         I915_WRITE(ECR, 0);
4657         POSTING_READ(ECR);
4658
4659         /* Program energy weights for various events */
4660         I915_WRITE(SDEW, 0x15040d00);
4661         I915_WRITE(CSIEW0, 0x007f0000);
4662         I915_WRITE(CSIEW1, 0x1e220004);
4663         I915_WRITE(CSIEW2, 0x04000004);
4664
4665         for (i = 0; i < 5; i++)
4666                 I915_WRITE(PEW + (i * 4), 0);
4667         for (i = 0; i < 3; i++)
4668                 I915_WRITE(DEW + (i * 4), 0);
4669
4670         /* Program P-state weights to account for frequency power adjustment */
4671         for (i = 0; i < 16; i++) {
4672                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4673                 unsigned long freq = intel_pxfreq(pxvidfreq);
4674                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4675                         PXVFREQ_PX_SHIFT;
4676                 unsigned long val;
4677
4678                 val = vid * vid;
4679                 val *= (freq / 1000);
4680                 val *= 255;
4681                 val /= (127*127*900);
4682                 if (val > 0xff)
4683                         DRM_ERROR("bad pxval: %ld\n", val);
4684                 pxw[i] = val;
4685         }
4686         /* Render standby states get 0 weight */
4687         pxw[14] = 0;
4688         pxw[15] = 0;
4689
4690         for (i = 0; i < 4; i++) {
4691                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4692                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4693                 I915_WRITE(PXW + (i * 4), val);
4694         }
4695
4696         /* Adjust magic regs to magic values (more experimental results) */
4697         I915_WRITE(OGW0, 0);
4698         I915_WRITE(OGW1, 0);
4699         I915_WRITE(EG0, 0x00007f00);
4700         I915_WRITE(EG1, 0x0000000e);
4701         I915_WRITE(EG2, 0x000e0000);
4702         I915_WRITE(EG3, 0x68000300);
4703         I915_WRITE(EG4, 0x42000000);
4704         I915_WRITE(EG5, 0x00140031);
4705         I915_WRITE(EG6, 0);
4706         I915_WRITE(EG7, 0);
4707
4708         for (i = 0; i < 8; i++)
4709                 I915_WRITE(PXWL + (i * 4), 0);
4710
4711         /* Enable PMON + select events */
4712         I915_WRITE(ECR, 0x80000019);
4713
4714         lcfuse = I915_READ(LCFUSE02);
4715
4716         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4717 }
4718
4719 void intel_disable_gt_powersave(struct drm_device *dev)
4720 {
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722
4723         /* Interrupts should be disabled already to avoid re-arming. */
4724         WARN_ON(dev->irq_enabled);
4725
4726         if (IS_IRONLAKE_M(dev)) {
4727                 ironlake_disable_drps(dev);
4728                 ironlake_disable_rc6(dev);
4729         } else if (INTEL_INFO(dev)->gen >= 6) {
4730                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4731                 cancel_work_sync(&dev_priv->rps.work);
4732                 mutex_lock(&dev_priv->rps.hw_lock);
4733                 if (IS_VALLEYVIEW(dev))
4734                         valleyview_disable_rps(dev);
4735                 else
4736                         gen6_disable_rps(dev);
4737                 dev_priv->rps.enabled = false;
4738                 mutex_unlock(&dev_priv->rps.hw_lock);
4739         }
4740 }
4741
4742 static void intel_gen6_powersave_work(struct work_struct *work)
4743 {
4744         struct drm_i915_private *dev_priv =
4745                 container_of(work, struct drm_i915_private,
4746                              rps.delayed_resume_work.work);
4747         struct drm_device *dev = dev_priv->dev;
4748
4749         mutex_lock(&dev_priv->rps.hw_lock);
4750
4751         if (IS_VALLEYVIEW(dev)) {
4752                 valleyview_enable_rps(dev);
4753         } else {
4754                 gen6_enable_rps(dev);
4755                 gen6_update_ring_freq(dev);
4756         }
4757         dev_priv->rps.enabled = true;
4758         mutex_unlock(&dev_priv->rps.hw_lock);
4759 }
4760
4761 void intel_enable_gt_powersave(struct drm_device *dev)
4762 {
4763         struct drm_i915_private *dev_priv = dev->dev_private;
4764
4765         if (IS_IRONLAKE_M(dev)) {
4766                 ironlake_enable_drps(dev);
4767                 ironlake_enable_rc6(dev);
4768                 intel_init_emon(dev);
4769         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4770                 /*
4771                  * PCU communication is slow and this doesn't need to be
4772                  * done at any specific time, so do this out of our fast path
4773                  * to make resume and init faster.
4774                  */
4775                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4776                                       round_jiffies_up_relative(HZ));
4777         }
4778 }
4779
4780 static void ibx_init_clock_gating(struct drm_device *dev)
4781 {
4782         struct drm_i915_private *dev_priv = dev->dev_private;
4783
4784         /*
4785          * On Ibex Peak and Cougar Point, we need to disable clock
4786          * gating for the panel power sequencer or it will fail to
4787          * start up when no ports are active.
4788          */
4789         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4790 }
4791
4792 static void g4x_disable_trickle_feed(struct drm_device *dev)
4793 {
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         int pipe;
4796
4797         for_each_pipe(pipe) {
4798                 I915_WRITE(DSPCNTR(pipe),
4799                            I915_READ(DSPCNTR(pipe)) |
4800                            DISPPLANE_TRICKLE_FEED_DISABLE);
4801                 intel_flush_primary_plane(dev_priv, pipe);
4802         }
4803 }
4804
4805 static void ironlake_init_clock_gating(struct drm_device *dev)
4806 {
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4809
4810         /*
4811          * Required for FBC
4812          * WaFbcDisableDpfcClockGating:ilk
4813          */
4814         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4815                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4816                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4817
4818         I915_WRITE(PCH_3DCGDIS0,
4819                    MARIUNIT_CLOCK_GATE_DISABLE |
4820                    SVSMUNIT_CLOCK_GATE_DISABLE);
4821         I915_WRITE(PCH_3DCGDIS1,
4822                    VFMUNIT_CLOCK_GATE_DISABLE);
4823
4824         /*
4825          * According to the spec the following bits should be set in
4826          * order to enable memory self-refresh
4827          * The bit 22/21 of 0x42004
4828          * The bit 5 of 0x42020
4829          * The bit 15 of 0x45000
4830          */
4831         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4832                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4833                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4834         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4835         I915_WRITE(DISP_ARB_CTL,
4836                    (I915_READ(DISP_ARB_CTL) |
4837                     DISP_FBC_WM_DIS));
4838         I915_WRITE(WM3_LP_ILK, 0);
4839         I915_WRITE(WM2_LP_ILK, 0);
4840         I915_WRITE(WM1_LP_ILK, 0);
4841
4842         /*
4843          * Based on the document from hardware guys the following bits
4844          * should be set unconditionally in order to enable FBC.
4845          * The bit 22 of 0x42000
4846          * The bit 22 of 0x42004
4847          * The bit 7,8,9 of 0x42020.
4848          */
4849         if (IS_IRONLAKE_M(dev)) {
4850                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4851                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4852                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4853                            ILK_FBCQ_DIS);
4854                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4855                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4856                            ILK_DPARB_GATE);
4857         }
4858
4859         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4860
4861         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4862                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4863                    ILK_ELPIN_409_SELECT);
4864         I915_WRITE(_3D_CHICKEN2,
4865                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4866                    _3D_CHICKEN2_WM_READ_PIPELINED);
4867
4868         /* WaDisableRenderCachePipelinedFlush:ilk */
4869         I915_WRITE(CACHE_MODE_0,
4870                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4871
4872         g4x_disable_trickle_feed(dev);
4873
4874         ibx_init_clock_gating(dev);
4875 }
4876
4877 static void cpt_init_clock_gating(struct drm_device *dev)
4878 {
4879         struct drm_i915_private *dev_priv = dev->dev_private;
4880         int pipe;
4881         uint32_t val;
4882
4883         /*
4884          * On Ibex Peak and Cougar Point, we need to disable clock
4885          * gating for the panel power sequencer or it will fail to
4886          * start up when no ports are active.
4887          */
4888         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4889         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4890                    DPLS_EDP_PPS_FIX_DIS);
4891         /* The below fixes the weird display corruption, a few pixels shifted
4892          * downward, on (only) LVDS of some HP laptops with IVY.
4893          */
4894         for_each_pipe(pipe) {
4895                 val = I915_READ(TRANS_CHICKEN2(pipe));
4896                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4897                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4898                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4899                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4900                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4901                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4902                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4903                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4904         }
4905         /* WADP0ClockGatingDisable */
4906         for_each_pipe(pipe) {
4907                 I915_WRITE(TRANS_CHICKEN1(pipe),
4908                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4909         }
4910 }
4911
4912 static void gen6_check_mch_setup(struct drm_device *dev)
4913 {
4914         struct drm_i915_private *dev_priv = dev->dev_private;
4915         uint32_t tmp;
4916
4917         tmp = I915_READ(MCH_SSKPD);
4918         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4919                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4920                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4921                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4922         }
4923 }
4924
4925 static void gen6_init_clock_gating(struct drm_device *dev)
4926 {
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4929
4930         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4931
4932         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4933                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4934                    ILK_ELPIN_409_SELECT);
4935
4936         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4937         I915_WRITE(_3D_CHICKEN,
4938                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4939
4940         /* WaSetupGtModeTdRowDispatch:snb */
4941         if (IS_SNB_GT1(dev))
4942                 I915_WRITE(GEN6_GT_MODE,
4943                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4944
4945         I915_WRITE(WM3_LP_ILK, 0);
4946         I915_WRITE(WM2_LP_ILK, 0);
4947         I915_WRITE(WM1_LP_ILK, 0);
4948
4949         I915_WRITE(CACHE_MODE_0,
4950                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4951
4952         I915_WRITE(GEN6_UCGCTL1,
4953                    I915_READ(GEN6_UCGCTL1) |
4954                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4955                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4956
4957         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4958          * gating disable must be set.  Failure to set it results in
4959          * flickering pixels due to Z write ordering failures after
4960          * some amount of runtime in the Mesa "fire" demo, and Unigine
4961          * Sanctuary and Tropics, and apparently anything else with
4962          * alpha test or pixel discard.
4963          *
4964          * According to the spec, bit 11 (RCCUNIT) must also be set,
4965          * but we didn't debug actual testcases to find it out.
4966          *
4967          * Also apply WaDisableVDSUnitClockGating:snb and
4968          * WaDisableRCPBUnitClockGating:snb.
4969          */
4970         I915_WRITE(GEN6_UCGCTL2,
4971                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4972                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4973                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4974
4975         /* Bspec says we need to always set all mask bits. */
4976         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4977                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4978
4979         /*
4980          * According to the spec the following bits should be
4981          * set in order to enable memory self-refresh and fbc:
4982          * The bit21 and bit22 of 0x42000
4983          * The bit21 and bit22 of 0x42004
4984          * The bit5 and bit7 of 0x42020
4985          * The bit14 of 0x70180
4986          * The bit14 of 0x71180
4987          *
4988          * WaFbcAsynchFlipDisableFbcQueue:snb
4989          */
4990         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4991                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4992                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4993         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4994                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4995                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4996         I915_WRITE(ILK_DSPCLK_GATE_D,
4997                    I915_READ(ILK_DSPCLK_GATE_D) |
4998                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4999                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5000
5001         g4x_disable_trickle_feed(dev);
5002
5003         /* The default value should be 0x200 according to docs, but the two
5004          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5005         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5006         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5007
5008         cpt_init_clock_gating(dev);
5009
5010         gen6_check_mch_setup(dev);
5011 }
5012
5013 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5014 {
5015         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5016
5017         reg &= ~GEN7_FF_SCHED_MASK;
5018         reg |= GEN7_FF_TS_SCHED_HW;
5019         reg |= GEN7_FF_VS_SCHED_HW;
5020         reg |= GEN7_FF_DS_SCHED_HW;
5021
5022         if (IS_HASWELL(dev_priv->dev))
5023                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5024
5025         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5026 }
5027
5028 static void lpt_init_clock_gating(struct drm_device *dev)
5029 {
5030         struct drm_i915_private *dev_priv = dev->dev_private;
5031
5032         /*
5033          * TODO: this bit should only be enabled when really needed, then
5034          * disabled when not needed anymore in order to save power.
5035          */
5036         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5037                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5038                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5039                            PCH_LP_PARTITION_LEVEL_DISABLE);
5040
5041         /* WADPOClockGatingDisable:hsw */
5042         I915_WRITE(_TRANSA_CHICKEN1,
5043                    I915_READ(_TRANSA_CHICKEN1) |
5044                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5045 }
5046
5047 static void lpt_suspend_hw(struct drm_device *dev)
5048 {
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050
5051         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5052                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5053
5054                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5055                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5056         }
5057 }
5058
5059 static void haswell_init_clock_gating(struct drm_device *dev)
5060 {
5061         struct drm_i915_private *dev_priv = dev->dev_private;
5062
5063         I915_WRITE(WM3_LP_ILK, 0);
5064         I915_WRITE(WM2_LP_ILK, 0);
5065         I915_WRITE(WM1_LP_ILK, 0);
5066
5067         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5068          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5069          */
5070         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5071
5072         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5073         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5074                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5075
5076         /* WaApplyL3ControlAndL3ChickenMode:hsw */
5077         I915_WRITE(GEN7_L3CNTLREG1,
5078                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5079         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5080                         GEN7_WA_L3_CHICKEN_MODE);
5081
5082         /* This is required by WaCatErrorRejectionIssue:hsw */
5083         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5084                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5085                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5086
5087         /* WaVSRefCountFullforceMissDisable:hsw */
5088         gen7_setup_fixed_func_scheduler(dev_priv);
5089
5090         /* WaDisable4x2SubspanOptimization:hsw */
5091         I915_WRITE(CACHE_MODE_1,
5092                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5093
5094         /* WaSwitchSolVfFArbitrationPriority:hsw */
5095         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5096
5097         /* WaRsPkgCStateDisplayPMReq:hsw */
5098         I915_WRITE(CHICKEN_PAR1_1,
5099                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5100
5101         lpt_init_clock_gating(dev);
5102 }
5103
5104 static void ivybridge_init_clock_gating(struct drm_device *dev)
5105 {
5106         struct drm_i915_private *dev_priv = dev->dev_private;
5107         uint32_t snpcr;
5108
5109         I915_WRITE(WM3_LP_ILK, 0);
5110         I915_WRITE(WM2_LP_ILK, 0);
5111         I915_WRITE(WM1_LP_ILK, 0);
5112
5113         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5114
5115         /* WaDisableEarlyCull:ivb */
5116         I915_WRITE(_3D_CHICKEN3,
5117                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5118
5119         /* WaDisableBackToBackFlipFix:ivb */
5120         I915_WRITE(IVB_CHICKEN3,
5121                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5122                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5123
5124         /* WaDisablePSDDualDispatchEnable:ivb */
5125         if (IS_IVB_GT1(dev))
5126                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5127                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5128         else
5129                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5130                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5131
5132         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5133         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5134                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5135
5136         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5137         I915_WRITE(GEN7_L3CNTLREG1,
5138                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5139         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5140                    GEN7_WA_L3_CHICKEN_MODE);
5141         if (IS_IVB_GT1(dev))
5142                 I915_WRITE(GEN7_ROW_CHICKEN2,
5143                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5144         else
5145                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5146                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5147
5148
5149         /* WaForceL3Serialization:ivb */
5150         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5151                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5152
5153         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5154          * gating disable must be set.  Failure to set it results in
5155          * flickering pixels due to Z write ordering failures after
5156          * some amount of runtime in the Mesa "fire" demo, and Unigine
5157          * Sanctuary and Tropics, and apparently anything else with
5158          * alpha test or pixel discard.
5159          *
5160          * According to the spec, bit 11 (RCCUNIT) must also be set,
5161          * but we didn't debug actual testcases to find it out.
5162          *
5163          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5164          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5165          */
5166         I915_WRITE(GEN6_UCGCTL2,
5167                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5168                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5169
5170         /* This is required by WaCatErrorRejectionIssue:ivb */
5171         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5172                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5173                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5174
5175         g4x_disable_trickle_feed(dev);
5176
5177         /* WaVSRefCountFullforceMissDisable:ivb */
5178         gen7_setup_fixed_func_scheduler(dev_priv);
5179
5180         /* WaDisable4x2SubspanOptimization:ivb */
5181         I915_WRITE(CACHE_MODE_1,
5182                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5183
5184         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5185         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5186         snpcr |= GEN6_MBC_SNPCR_MED;
5187         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5188
5189         if (!HAS_PCH_NOP(dev))
5190                 cpt_init_clock_gating(dev);
5191
5192         gen6_check_mch_setup(dev);
5193 }
5194
5195 static void valleyview_init_clock_gating(struct drm_device *dev)
5196 {
5197         struct drm_i915_private *dev_priv = dev->dev_private;
5198
5199         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5200
5201         /* WaDisableEarlyCull:vlv */
5202         I915_WRITE(_3D_CHICKEN3,
5203                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5204
5205         /* WaDisableBackToBackFlipFix:vlv */
5206         I915_WRITE(IVB_CHICKEN3,
5207                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5208                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5209
5210         /* WaDisablePSDDualDispatchEnable:vlv */
5211         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5212                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5213                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5214
5215         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5216         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5217                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5218
5219         /* WaApplyL3ControlAndL3ChickenMode:vlv */
5220         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5221         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5222
5223         /* WaForceL3Serialization:vlv */
5224         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5225                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5226
5227         /* WaDisableDopClockGating:vlv */
5228         I915_WRITE(GEN7_ROW_CHICKEN2,
5229                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5230
5231         /* This is required by WaCatErrorRejectionIssue:vlv */
5232         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5233                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5234                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5235
5236         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5237          * gating disable must be set.  Failure to set it results in
5238          * flickering pixels due to Z write ordering failures after
5239          * some amount of runtime in the Mesa "fire" demo, and Unigine
5240          * Sanctuary and Tropics, and apparently anything else with
5241          * alpha test or pixel discard.
5242          *
5243          * According to the spec, bit 11 (RCCUNIT) must also be set,
5244          * but we didn't debug actual testcases to find it out.
5245          *
5246          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5247          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5248          *
5249          * Also apply WaDisableVDSUnitClockGating:vlv and
5250          * WaDisableRCPBUnitClockGating:vlv.
5251          */
5252         I915_WRITE(GEN6_UCGCTL2,
5253                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5254                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5255                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5256                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5257                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5258
5259         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5260
5261         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5262
5263         I915_WRITE(CACHE_MODE_1,
5264                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5265
5266         /*
5267          * WaDisableVLVClockGating_VBIIssue:vlv
5268          * Disable clock gating on th GCFG unit to prevent a delay
5269          * in the reporting of vblank events.
5270          */
5271         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5272
5273         /* Conservative clock gating settings for now */
5274         I915_WRITE(0x9400, 0xffffffff);
5275         I915_WRITE(0x9404, 0xffffffff);
5276         I915_WRITE(0x9408, 0xffffffff);
5277         I915_WRITE(0x940c, 0xffffffff);
5278         I915_WRITE(0x9410, 0xffffffff);
5279         I915_WRITE(0x9414, 0xffffffff);
5280         I915_WRITE(0x9418, 0xffffffff);
5281 }
5282
5283 static void g4x_init_clock_gating(struct drm_device *dev)
5284 {
5285         struct drm_i915_private *dev_priv = dev->dev_private;
5286         uint32_t dspclk_gate;
5287
5288         I915_WRITE(RENCLK_GATE_D1, 0);
5289         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5290                    GS_UNIT_CLOCK_GATE_DISABLE |
5291                    CL_UNIT_CLOCK_GATE_DISABLE);
5292         I915_WRITE(RAMCLK_GATE_D, 0);
5293         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5294                 OVRUNIT_CLOCK_GATE_DISABLE |
5295                 OVCUNIT_CLOCK_GATE_DISABLE;
5296         if (IS_GM45(dev))
5297                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5298         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5299
5300         /* WaDisableRenderCachePipelinedFlush */
5301         I915_WRITE(CACHE_MODE_0,
5302                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5303
5304         g4x_disable_trickle_feed(dev);
5305 }
5306
5307 static void crestline_init_clock_gating(struct drm_device *dev)
5308 {
5309         struct drm_i915_private *dev_priv = dev->dev_private;
5310
5311         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5312         I915_WRITE(RENCLK_GATE_D2, 0);
5313         I915_WRITE(DSPCLK_GATE_D, 0);
5314         I915_WRITE(RAMCLK_GATE_D, 0);
5315         I915_WRITE16(DEUC, 0);
5316         I915_WRITE(MI_ARB_STATE,
5317                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5318 }
5319
5320 static void broadwater_init_clock_gating(struct drm_device *dev)
5321 {
5322         struct drm_i915_private *dev_priv = dev->dev_private;
5323
5324         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5325                    I965_RCC_CLOCK_GATE_DISABLE |
5326                    I965_RCPB_CLOCK_GATE_DISABLE |
5327                    I965_ISC_CLOCK_GATE_DISABLE |
5328                    I965_FBC_CLOCK_GATE_DISABLE);
5329         I915_WRITE(RENCLK_GATE_D2, 0);
5330         I915_WRITE(MI_ARB_STATE,
5331                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5332 }
5333
5334 static void gen3_init_clock_gating(struct drm_device *dev)
5335 {
5336         struct drm_i915_private *dev_priv = dev->dev_private;
5337         u32 dstate = I915_READ(D_STATE);
5338
5339         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5340                 DSTATE_DOT_CLOCK_GATING;
5341         I915_WRITE(D_STATE, dstate);
5342
5343         if (IS_PINEVIEW(dev))
5344                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5345
5346         /* IIR "flip pending" means done if this bit is set */
5347         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5348 }
5349
5350 static void i85x_init_clock_gating(struct drm_device *dev)
5351 {
5352         struct drm_i915_private *dev_priv = dev->dev_private;
5353
5354         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5355 }
5356
5357 static void i830_init_clock_gating(struct drm_device *dev)
5358 {
5359         struct drm_i915_private *dev_priv = dev->dev_private;
5360
5361         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5362 }
5363
5364 void intel_init_clock_gating(struct drm_device *dev)
5365 {
5366         struct drm_i915_private *dev_priv = dev->dev_private;
5367
5368         dev_priv->display.init_clock_gating(dev);
5369 }
5370
5371 void intel_suspend_hw(struct drm_device *dev)
5372 {
5373         if (HAS_PCH_LPT(dev))
5374                 lpt_suspend_hw(dev);
5375 }
5376
5377 /**
5378  * We should only use the power well if we explicitly asked the hardware to
5379  * enable it, so check if it's enabled and also check if we've requested it to
5380  * be enabled.
5381  */
5382 bool intel_display_power_enabled(struct drm_device *dev,
5383                                  enum intel_display_power_domain domain)
5384 {
5385         struct drm_i915_private *dev_priv = dev->dev_private;
5386
5387         if (!HAS_POWER_WELL(dev))
5388                 return true;
5389
5390         switch (domain) {
5391         case POWER_DOMAIN_PIPE_A:
5392         case POWER_DOMAIN_TRANSCODER_EDP:
5393                 return true;
5394         case POWER_DOMAIN_VGA:
5395         case POWER_DOMAIN_PIPE_B:
5396         case POWER_DOMAIN_PIPE_C:
5397         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5398         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5399         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5400         case POWER_DOMAIN_TRANSCODER_A:
5401         case POWER_DOMAIN_TRANSCODER_B:
5402         case POWER_DOMAIN_TRANSCODER_C:
5403                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5404                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5405         default:
5406                 BUG();
5407         }
5408 }
5409
5410 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5411 {
5412         struct drm_i915_private *dev_priv = dev->dev_private;
5413         bool is_enabled, enable_requested;
5414         uint32_t tmp;
5415
5416         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5417         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5418         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5419
5420         if (enable) {
5421                 if (!enable_requested)
5422                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5423                                    HSW_PWR_WELL_ENABLE_REQUEST);
5424
5425                 if (!is_enabled) {
5426                         DRM_DEBUG_KMS("Enabling power well\n");
5427                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5428                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5429                                 DRM_ERROR("Timeout enabling power well\n");
5430                 }
5431         } else {
5432                 if (enable_requested) {
5433                         unsigned long irqflags;
5434                         enum pipe p;
5435
5436                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5437                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5438                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5439
5440                         /*
5441                          * After this, the registers on the pipes that are part
5442                          * of the power well will become zero, so we have to
5443                          * adjust our counters according to that.
5444                          *
5445                          * FIXME: Should we do this in general in
5446                          * drm_vblank_post_modeset?
5447                          */
5448                         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5449                         for_each_pipe(p)
5450                                 if (p != PIPE_A)
5451                                         dev->vblank[p].last = 0;
5452                         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5453                 }
5454         }
5455 }
5456
5457 static void __intel_power_well_get(struct i915_power_well *power_well)
5458 {
5459         if (!power_well->count++)
5460                 __intel_set_power_well(power_well->device, true);
5461 }
5462
5463 static void __intel_power_well_put(struct i915_power_well *power_well)
5464 {
5465         WARN_ON(!power_well->count);
5466         if (!--power_well->count)
5467                 __intel_set_power_well(power_well->device, false);
5468 }
5469
5470 void intel_display_power_get(struct drm_device *dev,
5471                              enum intel_display_power_domain domain)
5472 {
5473         struct drm_i915_private *dev_priv = dev->dev_private;
5474         struct i915_power_well *power_well = &dev_priv->power_well;
5475
5476         if (!HAS_POWER_WELL(dev))
5477                 return;
5478
5479         switch (domain) {
5480         case POWER_DOMAIN_PIPE_A:
5481         case POWER_DOMAIN_TRANSCODER_EDP:
5482                 return;
5483         case POWER_DOMAIN_VGA:
5484         case POWER_DOMAIN_PIPE_B:
5485         case POWER_DOMAIN_PIPE_C:
5486         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5487         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5488         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5489         case POWER_DOMAIN_TRANSCODER_A:
5490         case POWER_DOMAIN_TRANSCODER_B:
5491         case POWER_DOMAIN_TRANSCODER_C:
5492                 spin_lock_irq(&power_well->lock);
5493                 __intel_power_well_get(power_well);
5494                 spin_unlock_irq(&power_well->lock);
5495                 return;
5496         default:
5497                 BUG();
5498         }
5499 }
5500
5501 void intel_display_power_put(struct drm_device *dev,
5502                              enum intel_display_power_domain domain)
5503 {
5504         struct drm_i915_private *dev_priv = dev->dev_private;
5505         struct i915_power_well *power_well = &dev_priv->power_well;
5506
5507         if (!HAS_POWER_WELL(dev))
5508                 return;
5509
5510         switch (domain) {
5511         case POWER_DOMAIN_PIPE_A:
5512         case POWER_DOMAIN_TRANSCODER_EDP:
5513                 return;
5514         case POWER_DOMAIN_VGA:
5515         case POWER_DOMAIN_PIPE_B:
5516         case POWER_DOMAIN_PIPE_C:
5517         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5518         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5519         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5520         case POWER_DOMAIN_TRANSCODER_A:
5521         case POWER_DOMAIN_TRANSCODER_B:
5522         case POWER_DOMAIN_TRANSCODER_C:
5523                 spin_lock_irq(&power_well->lock);
5524                 __intel_power_well_put(power_well);
5525                 spin_unlock_irq(&power_well->lock);
5526                 return;
5527         default:
5528                 BUG();
5529         }
5530 }
5531
5532 static struct i915_power_well *hsw_pwr;
5533
5534 /* Display audio driver power well request */
5535 void i915_request_power_well(void)
5536 {
5537         if (WARN_ON(!hsw_pwr))
5538                 return;
5539
5540         spin_lock_irq(&hsw_pwr->lock);
5541         __intel_power_well_get(hsw_pwr);
5542         spin_unlock_irq(&hsw_pwr->lock);
5543 }
5544 EXPORT_SYMBOL_GPL(i915_request_power_well);
5545
5546 /* Display audio driver power well release */
5547 void i915_release_power_well(void)
5548 {
5549         if (WARN_ON(!hsw_pwr))
5550                 return;
5551
5552         spin_lock_irq(&hsw_pwr->lock);
5553         __intel_power_well_put(hsw_pwr);
5554         spin_unlock_irq(&hsw_pwr->lock);
5555 }
5556 EXPORT_SYMBOL_GPL(i915_release_power_well);
5557
5558 int i915_init_power_well(struct drm_device *dev)
5559 {
5560         struct drm_i915_private *dev_priv = dev->dev_private;
5561
5562         hsw_pwr = &dev_priv->power_well;
5563
5564         hsw_pwr->device = dev;
5565         spin_lock_init(&hsw_pwr->lock);
5566         hsw_pwr->count = 0;
5567
5568         return 0;
5569 }
5570
5571 void i915_remove_power_well(struct drm_device *dev)
5572 {
5573         hsw_pwr = NULL;
5574 }
5575
5576 void intel_set_power_well(struct drm_device *dev, bool enable)
5577 {
5578         struct drm_i915_private *dev_priv = dev->dev_private;
5579         struct i915_power_well *power_well = &dev_priv->power_well;
5580
5581         if (!HAS_POWER_WELL(dev))
5582                 return;
5583
5584         if (!i915_disable_power_well && !enable)
5585                 return;
5586
5587         spin_lock_irq(&power_well->lock);
5588
5589         /*
5590          * This function will only ever contribute one
5591          * to the power well reference count. i915_request
5592          * is what tracks whether we have or have not
5593          * added the one to the reference count.
5594          */
5595         if (power_well->i915_request == enable)
5596                 goto out;
5597
5598         power_well->i915_request = enable;
5599
5600         if (enable)
5601                 __intel_power_well_get(power_well);
5602         else
5603                 __intel_power_well_put(power_well);
5604
5605  out:
5606         spin_unlock_irq(&power_well->lock);
5607 }
5608
5609 static void intel_resume_power_well(struct drm_device *dev)
5610 {
5611         struct drm_i915_private *dev_priv = dev->dev_private;
5612         struct i915_power_well *power_well = &dev_priv->power_well;
5613
5614         if (!HAS_POWER_WELL(dev))
5615                 return;
5616
5617         spin_lock_irq(&power_well->lock);
5618         __intel_set_power_well(dev, power_well->count > 0);
5619         spin_unlock_irq(&power_well->lock);
5620 }
5621
5622 /*
5623  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5624  * when not needed anymore. We have 4 registers that can request the power well
5625  * to be enabled, and it will only be disabled if none of the registers is
5626  * requesting it to be enabled.
5627  */
5628 void intel_init_power_well(struct drm_device *dev)
5629 {
5630         struct drm_i915_private *dev_priv = dev->dev_private;
5631
5632         if (!HAS_POWER_WELL(dev))
5633                 return;
5634
5635         /* For now, we need the power well to be always enabled. */
5636         intel_set_power_well(dev, true);
5637         intel_resume_power_well(dev);
5638
5639         /* We're taking over the BIOS, so clear any requests made by it since
5640          * the driver is in charge now. */
5641         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5642                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5643 }
5644
5645 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5646 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5647 {
5648         hsw_disable_package_c8(dev_priv);
5649 }
5650
5651 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5652 {
5653         hsw_enable_package_c8(dev_priv);
5654 }
5655
5656 /* Set up chip specific power management-related functions */
5657 void intel_init_pm(struct drm_device *dev)
5658 {
5659         struct drm_i915_private *dev_priv = dev->dev_private;
5660
5661         if (I915_HAS_FBC(dev)) {
5662                 if (HAS_PCH_SPLIT(dev)) {
5663                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5664                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5665                                 dev_priv->display.enable_fbc =
5666                                         gen7_enable_fbc;
5667                         else
5668                                 dev_priv->display.enable_fbc =
5669                                         ironlake_enable_fbc;
5670                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5671                 } else if (IS_GM45(dev)) {
5672                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5673                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5674                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5675                 } else if (IS_CRESTLINE(dev)) {
5676                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5677                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5678                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5679                 }
5680                 /* 855GM needs testing */
5681         }
5682
5683         /* For cxsr */
5684         if (IS_PINEVIEW(dev))
5685                 i915_pineview_get_mem_freq(dev);
5686         else if (IS_GEN5(dev))
5687                 i915_ironlake_get_mem_freq(dev);
5688
5689         /* For FIFO watermark updates */
5690         if (HAS_PCH_SPLIT(dev)) {
5691                 intel_setup_wm_latency(dev);
5692
5693                 if (IS_GEN5(dev)) {
5694                         if (dev_priv->wm.pri_latency[1] &&
5695                             dev_priv->wm.spr_latency[1] &&
5696                             dev_priv->wm.cur_latency[1])
5697                                 dev_priv->display.update_wm = ironlake_update_wm;
5698                         else {
5699                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5700                                               "Disable CxSR\n");
5701                                 dev_priv->display.update_wm = NULL;
5702                         }
5703                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5704                 } else if (IS_GEN6(dev)) {
5705                         if (dev_priv->wm.pri_latency[0] &&
5706                             dev_priv->wm.spr_latency[0] &&
5707                             dev_priv->wm.cur_latency[0]) {
5708                                 dev_priv->display.update_wm = sandybridge_update_wm;
5709                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5710                         } else {
5711                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5712                                               "Disable CxSR\n");
5713                                 dev_priv->display.update_wm = NULL;
5714                         }
5715                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5716                 } else if (IS_IVYBRIDGE(dev)) {
5717                         if (dev_priv->wm.pri_latency[0] &&
5718                             dev_priv->wm.spr_latency[0] &&
5719                             dev_priv->wm.cur_latency[0]) {
5720                                 dev_priv->display.update_wm = ivybridge_update_wm;
5721                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5722                         } else {
5723                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5724                                               "Disable CxSR\n");
5725                                 dev_priv->display.update_wm = NULL;
5726                         }
5727                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5728                 } else if (IS_HASWELL(dev)) {
5729                         if (dev_priv->wm.pri_latency[0] &&
5730                             dev_priv->wm.spr_latency[0] &&
5731                             dev_priv->wm.cur_latency[0]) {
5732                                 dev_priv->display.update_wm = haswell_update_wm;
5733                                 dev_priv->display.update_sprite_wm =
5734                                         haswell_update_sprite_wm;
5735                         } else {
5736                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5737                                               "Disable CxSR\n");
5738                                 dev_priv->display.update_wm = NULL;
5739                         }
5740                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5741                 } else
5742                         dev_priv->display.update_wm = NULL;
5743         } else if (IS_VALLEYVIEW(dev)) {
5744                 dev_priv->display.update_wm = valleyview_update_wm;
5745                 dev_priv->display.init_clock_gating =
5746                         valleyview_init_clock_gating;
5747         } else if (IS_PINEVIEW(dev)) {
5748                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5749                                             dev_priv->is_ddr3,
5750                                             dev_priv->fsb_freq,
5751                                             dev_priv->mem_freq)) {
5752                         DRM_INFO("failed to find known CxSR latency "
5753                                  "(found ddr%s fsb freq %d, mem freq %d), "
5754                                  "disabling CxSR\n",
5755                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5756                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5757                         /* Disable CxSR and never update its watermark again */
5758                         pineview_disable_cxsr(dev);
5759                         dev_priv->display.update_wm = NULL;
5760                 } else
5761                         dev_priv->display.update_wm = pineview_update_wm;
5762                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5763         } else if (IS_G4X(dev)) {
5764                 dev_priv->display.update_wm = g4x_update_wm;
5765                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5766         } else if (IS_GEN4(dev)) {
5767                 dev_priv->display.update_wm = i965_update_wm;
5768                 if (IS_CRESTLINE(dev))
5769                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5770                 else if (IS_BROADWATER(dev))
5771                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5772         } else if (IS_GEN3(dev)) {
5773                 dev_priv->display.update_wm = i9xx_update_wm;
5774                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5775                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5776         } else if (IS_I865G(dev)) {
5777                 dev_priv->display.update_wm = i830_update_wm;
5778                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5779                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5780         } else if (IS_I85X(dev)) {
5781                 dev_priv->display.update_wm = i9xx_update_wm;
5782                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5783                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5784         } else {
5785                 dev_priv->display.update_wm = i830_update_wm;
5786                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5787                 if (IS_845G(dev))
5788                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5789                 else
5790                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5791         }
5792 }
5793
5794 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5795 {
5796         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5797
5798         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5799                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5800                 return -EAGAIN;
5801         }
5802
5803         I915_WRITE(GEN6_PCODE_DATA, *val);
5804         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5805
5806         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5807                      500)) {
5808                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5809                 return -ETIMEDOUT;
5810         }
5811
5812         *val = I915_READ(GEN6_PCODE_DATA);
5813         I915_WRITE(GEN6_PCODE_DATA, 0);
5814
5815         return 0;
5816 }
5817
5818 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5819 {
5820         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5821
5822         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5823                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5824                 return -EAGAIN;
5825         }
5826
5827         I915_WRITE(GEN6_PCODE_DATA, val);
5828         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5829
5830         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5831                      500)) {
5832                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5833                 return -ETIMEDOUT;
5834         }
5835
5836         I915_WRITE(GEN6_PCODE_DATA, 0);
5837
5838         return 0;
5839 }
5840
5841 int vlv_gpu_freq(int ddr_freq, int val)
5842 {
5843         int mult, base;
5844
5845         switch (ddr_freq) {
5846         case 800:
5847                 mult = 20;
5848                 base = 120;
5849                 break;
5850         case 1066:
5851                 mult = 22;
5852                 base = 133;
5853                 break;
5854         case 1333:
5855                 mult = 21;
5856                 base = 125;
5857                 break;
5858         default:
5859                 return -1;
5860         }
5861
5862         return ((val - 0xbd) * mult) + base;
5863 }
5864
5865 int vlv_freq_opcode(int ddr_freq, int val)
5866 {
5867         int mult, base;
5868
5869         switch (ddr_freq) {
5870         case 800:
5871                 mult = 20;
5872                 base = 120;
5873                 break;
5874         case 1066:
5875                 mult = 22;
5876                 base = 133;
5877                 break;
5878         case 1333:
5879                 mult = 21;
5880                 base = 125;
5881                 break;
5882         default:
5883                 return -1;
5884         }
5885
5886         val /= mult;
5887         val -= base / mult;
5888         val += 0xbd;
5889
5890         if (val > 0xea)
5891                 val = 0xea;
5892
5893         return val;
5894 }
5895
5896 void intel_pm_init(struct drm_device *dev)
5897 {
5898         struct drm_i915_private *dev_priv = dev->dev_private;
5899
5900         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5901                           intel_gen6_powersave_work);
5902 }
5903