drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <drm/i915_powerwell.h>
  34
  35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  36  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  37  * during in-memory transfers and, therefore, reduce the power packet.
  38  *
  39  * The benefits of FBC are mostly visible with solid backgrounds and
  40  * variation-less patterns.
  41  *
  42  * FBC-related functionality can be enabled by the means of the
  43  * i915.i915_enable_fbc parameter
  44  */
  45
  46 static void i8xx_disable_fbc(struct drm_device *dev)
  47 {
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         u32 fbc_ctl;
  50
  51         /* Disable compression */
  52         fbc_ctl = I915_READ(FBC_CONTROL);
  53         if ((fbc_ctl & FBC_CTL_EN) == 0)
  54                 return;
  55
  56         fbc_ctl &= ~FBC_CTL_EN;
  57         I915_WRITE(FBC_CONTROL, fbc_ctl);
  58
  59         /* Wait for compressing bit to clear */
  60         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  61                 DRM_DEBUG_KMS("FBC idle timed out\n");
  62                 return;
  63         }
  64
  65         DRM_DEBUG_KMS("disabled FBC\n");
  66 }
  67
  68 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  69 {
  70         struct drm_device *dev = crtc->dev;
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         struct drm_framebuffer *fb = crtc->fb;
  73         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  74         struct drm_i915_gem_object *obj = intel_fb->obj;
  75         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  76         int cfb_pitch;
  77         int plane, i;
  78         u32 fbc_ctl, fbc_ctl2;
  79
  80         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
  81         if (fb->pitches[0] < cfb_pitch)
  82                 cfb_pitch = fb->pitches[0];
  83
  84         /* FBC_CTL wants 64B units */
  85         cfb_pitch = (cfb_pitch / 64) - 1;
  86         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  87
  88         /* Clear old tags */
  89         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  90                 I915_WRITE(FBC_TAG + (i * 4), 0);
  91
  92         /* Set it up... */
  93         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  94         fbc_ctl2 |= plane;
  95         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  96         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  97
  98         /* enable it... */
  99         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 100         if (IS_I945GM(dev))
 101                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 102         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 103         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 104         fbc_ctl |= obj->fence_reg;
 105         I915_WRITE(FBC_CONTROL, fbc_ctl);
 106
 107         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 108                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 109 }
 110
 111 static bool i8xx_fbc_enabled(struct drm_device *dev)
 112 {
 113         struct drm_i915_private *dev_priv = dev->dev_private;
 114
 115         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 116 }
 117
 118 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 119 {
 120         struct drm_device *dev = crtc->dev;
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122         struct drm_framebuffer *fb = crtc->fb;
 123         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 124         struct drm_i915_gem_object *obj = intel_fb->obj;
 125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 126         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 127         unsigned long stall_watermark = 200;
 128         u32 dpfc_ctl;
 129
 130         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 131         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 132         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 133
 134         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 135                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 136                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 137         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 138
 139         /* enable it... */
 140         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 141
 142         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 143 }
 144
 145 static void g4x_disable_fbc(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = dev->dev_private;
 148         u32 dpfc_ctl;
 149
 150         /* Disable compression */
 151         dpfc_ctl = I915_READ(DPFC_CONTROL);
 152         if (dpfc_ctl & DPFC_CTL_EN) {
 153                 dpfc_ctl &= ~DPFC_CTL_EN;
 154                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 155
 156                 DRM_DEBUG_KMS("disabled FBC\n");
 157         }
 158 }
 159
 160 static bool g4x_fbc_enabled(struct drm_device *dev)
 161 {
 162         struct drm_i915_private *dev_priv = dev->dev_private;
 163
 164         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 165 }
 166
 167 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 168 {
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         u32 blt_ecoskpd;
 171
 172         /* Make sure blitter notifies FBC of writes */
 173         gen6_gt_force_wake_get(dev_priv);
 174         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 175         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 176                 GEN6_BLITTER_LOCK_SHIFT;
 177         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 178         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 179         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 180         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 181                          GEN6_BLITTER_LOCK_SHIFT);
 182         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 183         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 184         gen6_gt_force_wake_put(dev_priv);
 185 }
 186
 187 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 188 {
 189         struct drm_device *dev = crtc->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct drm_framebuffer *fb = crtc->fb;
 192         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 193         struct drm_i915_gem_object *obj = intel_fb->obj;
 194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 195         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 196         unsigned long stall_watermark = 200;
 197         u32 dpfc_ctl;
 198
 199         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 200         dpfc_ctl &= DPFC_RESERVED;
 201         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 202         /* Set persistent mode for front-buffer rendering, ala X. */
 203         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 204         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 205         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 206
 207         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 208                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 209                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 210         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 211         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 212         /* enable it... */
 213         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 214
 215         if (IS_GEN6(dev)) {
 216                 I915_WRITE(SNB_DPFC_CTL_SA,
 217                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 218                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 219                 sandybridge_blit_fbc_update(dev);
 220         }
 221
 222         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 223 }
 224
 225 static void ironlake_disable_fbc(struct drm_device *dev)
 226 {
 227         struct drm_i915_private *dev_priv = dev->dev_private;
 228         u32 dpfc_ctl;
 229
 230         /* Disable compression */
 231         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 232         if (dpfc_ctl & DPFC_CTL_EN) {
 233                 dpfc_ctl &= ~DPFC_CTL_EN;
 234                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 235
 236                 if (IS_IVYBRIDGE(dev))
 237                         /* WaFbcDisableDpfcClockGating:ivb */
 238                         I915_WRITE(ILK_DSPCLK_GATE_D,
 239                                    I915_READ(ILK_DSPCLK_GATE_D) &
 240                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 241
 242                 if (IS_HASWELL(dev))
 243                         /* WaFbcDisableDpfcClockGating:hsw */
 244                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 245                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
 246                                    ~HSW_DPFC_GATING_DISABLE);
 247
 248                 DRM_DEBUG_KMS("disabled FBC\n");
 249         }
 250 }
 251
 252 static bool ironlake_fbc_enabled(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255
 256         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 257 }
 258
 259 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 260 {
 261         struct drm_device *dev = crtc->dev;
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263         struct drm_framebuffer *fb = crtc->fb;
 264         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 265         struct drm_i915_gem_object *obj = intel_fb->obj;
 266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 267
 268         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 269
 270         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 271                    IVB_DPFC_CTL_FENCE_EN |
 272                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 273
 274         if (IS_IVYBRIDGE(dev)) {
 275                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 276                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 277                 /* WaFbcDisableDpfcClockGating:ivb */
 278                 I915_WRITE(ILK_DSPCLK_GATE_D,
 279                            I915_READ(ILK_DSPCLK_GATE_D) |
 280                            ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 281         } else {
 282                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 283                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 284                            HSW_BYPASS_FBC_QUEUE);
 285                 /* WaFbcDisableDpfcClockGating:hsw */
 286                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 287                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
 288                            HSW_DPFC_GATING_DISABLE);
 289         }
 290
 291         I915_WRITE(SNB_DPFC_CTL_SA,
 292                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 293         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 294
 295         sandybridge_blit_fbc_update(dev);
 296
 297         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 298 }
 299
 300 bool intel_fbc_enabled(struct drm_device *dev)
 301 {
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303
 304         if (!dev_priv->display.fbc_enabled)
 305                 return false;
 306
 307         return dev_priv->display.fbc_enabled(dev);
 308 }
 309
 310 static void intel_fbc_work_fn(struct work_struct *__work)
 311 {
 312         struct intel_fbc_work *work =
 313                 container_of(to_delayed_work(__work),
 314                              struct intel_fbc_work, work);
 315         struct drm_device *dev = work->crtc->dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317
 318         mutex_lock(&dev->struct_mutex);
 319         if (work == dev_priv->fbc.fbc_work) {
 320                 /* Double check that we haven't switched fb without cancelling
 321                  * the prior work.
 322                  */
 323                 if (work->crtc->fb == work->fb) {
 324                         dev_priv->display.enable_fbc(work->crtc,
 325                                                      work->interval);
 326
 327                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 328                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 329                         dev_priv->fbc.y = work->crtc->y;
 330                 }
 331
 332                 dev_priv->fbc.fbc_work = NULL;
 333         }
 334         mutex_unlock(&dev->struct_mutex);
 335
 336         kfree(work);
 337 }
 338
 339 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 340 {
 341         if (dev_priv->fbc.fbc_work == NULL)
 342                 return;
 343
 344         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 345
 346         /* Synchronisation is provided by struct_mutex and checking of
 347          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 348          * entirely asynchronously.
 349          */
 350         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 351                 /* tasklet was killed before being run, clean up */
 352                 kfree(dev_priv->fbc.fbc_work);
 353
 354         /* Mark the work as no longer wanted so that if it does
 355          * wake-up (because the work was already running and waiting
 356          * for our mutex), it will discover that is no longer
 357          * necessary to run.
 358          */
 359         dev_priv->fbc.fbc_work = NULL;
 360 }
 361
 362 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 363 {
 364         struct intel_fbc_work *work;
 365         struct drm_device *dev = crtc->dev;
 366         struct drm_i915_private *dev_priv = dev->dev_private;
 367
 368         if (!dev_priv->display.enable_fbc)
 369                 return;
 370
 371         intel_cancel_fbc_work(dev_priv);
 372
 373         work = kzalloc(sizeof(*work), GFP_KERNEL);
 374         if (work == NULL) {
 375                 DRM_ERROR("Failed to allocate FBC work structure\n");
 376                 dev_priv->display.enable_fbc(crtc, interval);
 377                 return;
 378         }
 379
 380         work->crtc = crtc;
 381         work->fb = crtc->fb;
 382         work->interval = interval;
 383         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 384
 385         dev_priv->fbc.fbc_work = work;
 386
 387         /* Delay the actual enabling to let pageflipping cease and the
 388          * display to settle before starting the compression. Note that
 389          * this delay also serves a second purpose: it allows for a
 390          * vblank to pass after disabling the FBC before we attempt
 391          * to modify the control registers.
 392          *
 393          * A more complicated solution would involve tracking vblanks
 394          * following the termination of the page-flipping sequence
 395          * and indeed performing the enable as a co-routine and not
 396          * waiting synchronously upon the vblank.
 397          *
 398          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 399          */
 400         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 401 }
 402
 403 void intel_disable_fbc(struct drm_device *dev)
 404 {
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406
 407         intel_cancel_fbc_work(dev_priv);
 408
 409         if (!dev_priv->display.disable_fbc)
 410                 return;
 411
 412         dev_priv->display.disable_fbc(dev);
 413         dev_priv->fbc.plane = -1;
 414 }
 415
 416 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 417                               enum no_fbc_reason reason)
 418 {
 419         if (dev_priv->fbc.no_fbc_reason == reason)
 420                 return false;
 421
 422         dev_priv->fbc.no_fbc_reason = reason;
 423         return true;
 424 }
 425
 426 /**
 427  * intel_update_fbc - enable/disable FBC as needed
 428  * @dev: the drm_device
 429  *
 430  * Set up the framebuffer compression hardware at mode set time.  We
 431  * enable it if possible:
 432  *   - plane A only (on pre-965)
 433  *   - no pixel mulitply/line duplication
 434  *   - no alpha buffer discard
 435  *   - no dual wide
 436  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 437  *
 438  * We can't assume that any compression will take place (worst case),
 439  * so the compressed buffer has to be the same size as the uncompressed
 440  * one.  It also must reside (along with the line length buffer) in
 441  * stolen memory.
 442  *
 443  * We need to enable/disable FBC on a global basis.
 444  */
 445 void intel_update_fbc(struct drm_device *dev)
 446 {
 447         struct drm_i915_private *dev_priv = dev->dev_private;
 448         struct drm_crtc *crtc = NULL, *tmp_crtc;
 449         struct intel_crtc *intel_crtc;
 450         struct drm_framebuffer *fb;
 451         struct intel_framebuffer *intel_fb;
 452         struct drm_i915_gem_object *obj;
 453         const struct drm_display_mode *adjusted_mode;
 454         unsigned int max_width, max_height;
 455
 456         if (!I915_HAS_FBC(dev)) {
 457                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 458                 return;
 459         }
 460
 461         if (!i915_powersave) {
 462                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 463                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 464                 return;
 465         }
 466
 467         /*
 468          * If FBC is already on, we just have to verify that we can
 469          * keep it that way...
 470          * Need to disable if:
 471          *   - more than one pipe is active
 472          *   - changing FBC params (stride, fence, mode)
 473          *   - new fb is too large to fit in compressed buffer
 474          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 475          */
 476         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 477                 if (intel_crtc_active(tmp_crtc) &&
 478                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 479                         if (crtc) {
 480                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 481                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 482                                 goto out_disable;
 483                         }
 484                         crtc = tmp_crtc;
 485                 }
 486         }
 487
 488         if (!crtc || crtc->fb == NULL) {
 489                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 490                         DRM_DEBUG_KMS("no output, disabling\n");
 491                 goto out_disable;
 492         }
 493
 494         intel_crtc = to_intel_crtc(crtc);
 495         fb = crtc->fb;
 496         intel_fb = to_intel_framebuffer(fb);
 497         obj = intel_fb->obj;
 498         adjusted_mode = &intel_crtc->config.adjusted_mode;
 499
 500         if (i915_enable_fbc < 0 &&
 501             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 502                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 503                         DRM_DEBUG_KMS("disabled per chip default\n");
 504                 goto out_disable;
 505         }
 506         if (!i915_enable_fbc) {
 507                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 508                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 509                 goto out_disable;
 510         }
 511         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 512             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 513                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 514                         DRM_DEBUG_KMS("mode incompatible with compression, "
 515                                       "disabling\n");
 516                 goto out_disable;
 517         }
 518
 519         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 520                 max_width = 4096;
 521                 max_height = 2048;
 522         } else {
 523                 max_width = 2048;
 524                 max_height = 1536;
 525         }
 526         if (intel_crtc->config.pipe_src_w > max_width ||
 527             intel_crtc->config.pipe_src_h > max_height) {
 528                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 529                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 530                 goto out_disable;
 531         }
 532         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 533             intel_crtc->plane != 0) {
 534                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 535                         DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 536                 goto out_disable;
 537         }
 538
 539         /* The use of a CPU fence is mandatory in order to detect writes
 540          * by the CPU to the scanout and trigger updates to the FBC.
 541          */
 542         if (obj->tiling_mode != I915_TILING_X ||
 543             obj->fence_reg == I915_FENCE_REG_NONE) {
 544                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 545                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 546                 goto out_disable;
 547         }
 548
 549         /* If the kernel debugger is active, always disable compression */
 550         if (in_dbg_master())
 551                 goto out_disable;
 552
 553         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 554                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 555                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 556                 goto out_disable;
 557         }
 558
 559         /* If the scanout has not changed, don't modify the FBC settings.
 560          * Note that we make the fundamental assumption that the fb->obj
 561          * cannot be unpinned (and have its GTT offset and fence revoked)
 562          * without first being decoupled from the scanout and FBC disabled.
 563          */
 564         if (dev_priv->fbc.plane == intel_crtc->plane &&
 565             dev_priv->fbc.fb_id == fb->base.id &&
 566             dev_priv->fbc.y == crtc->y)
 567                 return;
 568
 569         if (intel_fbc_enabled(dev)) {
 570                 /* We update FBC along two paths, after changing fb/crtc
 571                  * configuration (modeswitching) and after page-flipping
 572                  * finishes. For the latter, we know that not only did
 573                  * we disable the FBC at the start of the page-flip
 574                  * sequence, but also more than one vblank has passed.
 575                  *
 576                  * For the former case of modeswitching, it is possible
 577                  * to switch between two FBC valid configurations
 578                  * instantaneously so we do need to disable the FBC
 579                  * before we can modify its control registers. We also
 580                  * have to wait for the next vblank for that to take
 581                  * effect. However, since we delay enabling FBC we can
 582                  * assume that a vblank has passed since disabling and
 583                  * that we can safely alter the registers in the deferred
 584                  * callback.
 585                  *
 586                  * In the scenario that we go from a valid to invalid
 587                  * and then back to valid FBC configuration we have
 588                  * no strict enforcement that a vblank occurred since
 589                  * disabling the FBC. However, along all current pipe
 590                  * disabling paths we do need to wait for a vblank at
 591                  * some point. And we wait before enabling FBC anyway.
 592                  */
 593                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 594                 intel_disable_fbc(dev);
 595         }
 596
 597         intel_enable_fbc(crtc, 500);
 598         dev_priv->fbc.no_fbc_reason = FBC_OK;
 599         return;
 600
 601 out_disable:
 602         /* Multiple disables should be harmless */
 603         if (intel_fbc_enabled(dev)) {
 604                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 605                 intel_disable_fbc(dev);
 606         }
 607         i915_gem_stolen_cleanup_compression(dev);
 608 }
 609
 610 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 611 {
 612         drm_i915_private_t *dev_priv = dev->dev_private;
 613         u32 tmp;
 614
 615         tmp = I915_READ(CLKCFG);
 616
 617         switch (tmp & CLKCFG_FSB_MASK) {
 618         case CLKCFG_FSB_533:
 619                 dev_priv->fsb_freq = 533; /* 133*4 */
 620                 break;
 621         case CLKCFG_FSB_800:
 622                 dev_priv->fsb_freq = 800; /* 200*4 */
 623                 break;
 624         case CLKCFG_FSB_667:
 625                 dev_priv->fsb_freq =  667; /* 167*4 */
 626                 break;
 627         case CLKCFG_FSB_400:
 628                 dev_priv->fsb_freq = 400; /* 100*4 */
 629                 break;
 630         }
 631
 632         switch (tmp & CLKCFG_MEM_MASK) {
 633         case CLKCFG_MEM_533:
 634                 dev_priv->mem_freq = 533;
 635                 break;
 636         case CLKCFG_MEM_667:
 637                 dev_priv->mem_freq = 667;
 638                 break;
 639         case CLKCFG_MEM_800:
 640                 dev_priv->mem_freq = 800;
 641                 break;
 642         }
 643
 644         /* detect pineview DDR3 setting */
 645         tmp = I915_READ(CSHRDDR3CTL);
 646         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 647 }
 648
 649 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 650 {
 651         drm_i915_private_t *dev_priv = dev->dev_private;
 652         u16 ddrpll, csipll;
 653
 654         ddrpll = I915_READ16(DDRMPLL1);
 655         csipll = I915_READ16(CSIPLL0);
 656
 657         switch (ddrpll & 0xff) {
 658         case 0xc:
 659                 dev_priv->mem_freq = 800;
 660                 break;
 661         case 0x10:
 662                 dev_priv->mem_freq = 1066;
 663                 break;
 664         case 0x14:
 665                 dev_priv->mem_freq = 1333;
 666                 break;
 667         case 0x18:
 668                 dev_priv->mem_freq = 1600;
 669                 break;
 670         default:
 671                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 672                                  ddrpll & 0xff);
 673                 dev_priv->mem_freq = 0;
 674                 break;
 675         }
 676
 677         dev_priv->ips.r_t = dev_priv->mem_freq;
 678
 679         switch (csipll & 0x3ff) {
 680         case 0x00c:
 681                 dev_priv->fsb_freq = 3200;
 682                 break;
 683         case 0x00e:
 684                 dev_priv->fsb_freq = 3733;
 685                 break;
 686         case 0x010:
 687                 dev_priv->fsb_freq = 4266;
 688                 break;
 689         case 0x012:
 690                 dev_priv->fsb_freq = 4800;
 691                 break;
 692         case 0x014:
 693                 dev_priv->fsb_freq = 5333;
 694                 break;
 695         case 0x016:
 696                 dev_priv->fsb_freq = 5866;
 697                 break;
 698         case 0x018:
 699                 dev_priv->fsb_freq = 6400;
 700                 break;
 701         default:
 702                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 703                                  csipll & 0x3ff);
 704                 dev_priv->fsb_freq = 0;
 705                 break;
 706         }
 707
 708         if (dev_priv->fsb_freq == 3200) {
 709                 dev_priv->ips.c_m = 0;
 710         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 711                 dev_priv->ips.c_m = 1;
 712         } else {
 713                 dev_priv->ips.c_m = 2;
 714         }
 715 }
 716
 717 static const struct cxsr_latency cxsr_latency_table[] = {
 718         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 719         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 720         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 721         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 722         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 723
 724         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 725         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 726         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 727         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 728         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 729
 730         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 731         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 732         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 733         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 734         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 735
 736         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 737         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 738         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 739         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 740         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 741
 742         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 743         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 744         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 745         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 746         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 747
 748         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 749         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 750         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 751         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 752         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 753 };
 754
 755 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 756                                                          int is_ddr3,
 757                                                          int fsb,
 758                                                          int mem)
 759 {
 760         const struct cxsr_latency *latency;
 761         int i;
 762
 763         if (fsb == 0 || mem == 0)
 764                 return NULL;
 765
 766         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 767                 latency = &cxsr_latency_table[i];
 768                 if (is_desktop == latency->is_desktop &&
 769                     is_ddr3 == latency->is_ddr3 &&
 770                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 771                         return latency;
 772         }
 773
 774         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 775
 776         return NULL;
 777 }
 778
 779 static void pineview_disable_cxsr(struct drm_device *dev)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782
 783         /* deactivate cxsr */
 784         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 785 }
 786
 787 /*
 788  * Latency for FIFO fetches is dependent on several factors:
 789  *   - memory configuration (speed, channels)
 790  *   - chipset
 791  *   - current MCH state
 792  * It can be fairly high in some situations, so here we assume a fairly
 793  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 794  * set this value too high, the FIFO will fetch frequently to stay full)
 795  * and power consumption (set it too low to save power and we might see
 796  * FIFO underruns and display "flicker").
 797  *
 798  * A value of 5us seems to be a good balance; safe for very low end
 799  * platforms but not overly aggressive on lower latency configs.
 800  */
 801 static const int latency_ns = 5000;
 802
 803 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         uint32_t dsparb = I915_READ(DSPARB);
 807         int size;
 808
 809         size = dsparb & 0x7f;
 810         if (plane)
 811                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 812
 813         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 814                       plane ? "B" : "A", size);
 815
 816         return size;
 817 }
 818
 819 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 820 {
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822         uint32_t dsparb = I915_READ(DSPARB);
 823         int size;
 824
 825         size = dsparb & 0x1ff;
 826         if (plane)
 827                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 828         size >>= 1; /* Convert to cachelines */
 829
 830         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 831                       plane ? "B" : "A", size);
 832
 833         return size;
 834 }
 835
 836 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 837 {
 838         struct drm_i915_private *dev_priv = dev->dev_private;
 839         uint32_t dsparb = I915_READ(DSPARB);
 840         int size;
 841
 842         size = dsparb & 0x7f;
 843         size >>= 2; /* Convert to cachelines */
 844
 845         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 846                       plane ? "B" : "A",
 847                       size);
 848
 849         return size;
 850 }
 851
 852 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 853 {
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855         uint32_t dsparb = I915_READ(DSPARB);
 856         int size;
 857
 858         size = dsparb & 0x7f;
 859         size >>= 1; /* Convert to cachelines */
 860
 861         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 862                       plane ? "B" : "A", size);
 863
 864         return size;
 865 }
 866
 867 /* Pineview has different values for various configs */
 868 static const struct intel_watermark_params pineview_display_wm = {
 869         PINEVIEW_DISPLAY_FIFO,
 870         PINEVIEW_MAX_WM,
 871         PINEVIEW_DFT_WM,
 872         PINEVIEW_GUARD_WM,
 873         PINEVIEW_FIFO_LINE_SIZE
 874 };
 875 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 876         PINEVIEW_DISPLAY_FIFO,
 877         PINEVIEW_MAX_WM,
 878         PINEVIEW_DFT_HPLLOFF_WM,
 879         PINEVIEW_GUARD_WM,
 880         PINEVIEW_FIFO_LINE_SIZE
 881 };
 882 static const struct intel_watermark_params pineview_cursor_wm = {
 883         PINEVIEW_CURSOR_FIFO,
 884         PINEVIEW_CURSOR_MAX_WM,
 885         PINEVIEW_CURSOR_DFT_WM,
 886         PINEVIEW_CURSOR_GUARD_WM,
 887         PINEVIEW_FIFO_LINE_SIZE,
 888 };
 889 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 890         PINEVIEW_CURSOR_FIFO,
 891         PINEVIEW_CURSOR_MAX_WM,
 892         PINEVIEW_CURSOR_DFT_WM,
 893         PINEVIEW_CURSOR_GUARD_WM,
 894         PINEVIEW_FIFO_LINE_SIZE
 895 };
 896 static const struct intel_watermark_params g4x_wm_info = {
 897         G4X_FIFO_SIZE,
 898         G4X_MAX_WM,
 899         G4X_MAX_WM,
 900         2,
 901         G4X_FIFO_LINE_SIZE,
 902 };
 903 static const struct intel_watermark_params g4x_cursor_wm_info = {
 904         I965_CURSOR_FIFO,
 905         I965_CURSOR_MAX_WM,
 906         I965_CURSOR_DFT_WM,
 907         2,
 908         G4X_FIFO_LINE_SIZE,
 909 };
 910 static const struct intel_watermark_params valleyview_wm_info = {
 911         VALLEYVIEW_FIFO_SIZE,
 912         VALLEYVIEW_MAX_WM,
 913         VALLEYVIEW_MAX_WM,
 914         2,
 915         G4X_FIFO_LINE_SIZE,
 916 };
 917 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 918         I965_CURSOR_FIFO,
 919         VALLEYVIEW_CURSOR_MAX_WM,
 920         I965_CURSOR_DFT_WM,
 921         2,
 922         G4X_FIFO_LINE_SIZE,
 923 };
 924 static const struct intel_watermark_params i965_cursor_wm_info = {
 925         I965_CURSOR_FIFO,
 926         I965_CURSOR_MAX_WM,
 927         I965_CURSOR_DFT_WM,
 928         2,
 929         I915_FIFO_LINE_SIZE,
 930 };
 931 static const struct intel_watermark_params i945_wm_info = {
 932         I945_FIFO_SIZE,
 933         I915_MAX_WM,
 934         1,
 935         2,
 936         I915_FIFO_LINE_SIZE
 937 };
 938 static const struct intel_watermark_params i915_wm_info = {
 939         I915_FIFO_SIZE,
 940         I915_MAX_WM,
 941         1,
 942         2,
 943         I915_FIFO_LINE_SIZE
 944 };
 945 static const struct intel_watermark_params i855_wm_info = {
 946         I855GM_FIFO_SIZE,
 947         I915_MAX_WM,
 948         1,
 949         2,
 950         I830_FIFO_LINE_SIZE
 951 };
 952 static const struct intel_watermark_params i830_wm_info = {
 953         I830_FIFO_SIZE,
 954         I915_MAX_WM,
 955         1,
 956         2,
 957         I830_FIFO_LINE_SIZE
 958 };
 959
 960 static const struct intel_watermark_params ironlake_display_wm_info = {
 961         ILK_DISPLAY_FIFO,
 962         ILK_DISPLAY_MAXWM,
 963         ILK_DISPLAY_DFTWM,
 964         2,
 965         ILK_FIFO_LINE_SIZE
 966 };
 967 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 968         ILK_CURSOR_FIFO,
 969         ILK_CURSOR_MAXWM,
 970         ILK_CURSOR_DFTWM,
 971         2,
 972         ILK_FIFO_LINE_SIZE
 973 };
 974 static const struct intel_watermark_params ironlake_display_srwm_info = {
 975         ILK_DISPLAY_SR_FIFO,
 976         ILK_DISPLAY_MAX_SRWM,
 977         ILK_DISPLAY_DFT_SRWM,
 978         2,
 979         ILK_FIFO_LINE_SIZE
 980 };
 981 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 982         ILK_CURSOR_SR_FIFO,
 983         ILK_CURSOR_MAX_SRWM,
 984         ILK_CURSOR_DFT_SRWM,
 985         2,
 986         ILK_FIFO_LINE_SIZE
 987 };
 988
 989 static const struct intel_watermark_params sandybridge_display_wm_info = {
 990         SNB_DISPLAY_FIFO,
 991         SNB_DISPLAY_MAXWM,
 992         SNB_DISPLAY_DFTWM,
 993         2,
 994         SNB_FIFO_LINE_SIZE
 995 };
 996 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 997         SNB_CURSOR_FIFO,
 998         SNB_CURSOR_MAXWM,
 999         SNB_CURSOR_DFTWM,
1000         2,
1001         SNB_FIFO_LINE_SIZE
1002 };
1003 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004         SNB_DISPLAY_SR_FIFO,
1005         SNB_DISPLAY_MAX_SRWM,
1006         SNB_DISPLAY_DFT_SRWM,
1007         2,
1008         SNB_FIFO_LINE_SIZE
1009 };
1010 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1011         SNB_CURSOR_SR_FIFO,
1012         SNB_CURSOR_MAX_SRWM,
1013         SNB_CURSOR_DFT_SRWM,
1014         2,
1015         SNB_FIFO_LINE_SIZE
1016 };
1017
1018
1019 /**
1020  * intel_calculate_wm - calculate watermark level
1021  * @clock_in_khz: pixel clock
1022  * @wm: chip FIFO params
1023  * @pixel_size: display pixel size
1024  * @latency_ns: memory latency for the platform
1025  *
1026  * Calculate the watermark level (the level at which the display plane will
1027  * start fetching from memory again).  Each chip has a different display
1028  * FIFO size and allocation, so the caller needs to figure that out and pass
1029  * in the correct intel_watermark_params structure.
1030  *
1031  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032  * on the pixel size.  When it reaches the watermark level, it'll start
1033  * fetching FIFO line sized based chunks from memory until the FIFO fills
1034  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1035  * will occur, and a display engine hang could result.
1036  */
1037 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038                                         const struct intel_watermark_params *wm,
1039                                         int fifo_size,
1040                                         int pixel_size,
1041                                         unsigned long latency_ns)
1042 {
1043         long entries_required, wm_size;
1044
1045         /*
1046          * Note: we need to make sure we don't overflow for various clock &
1047          * latency values.
1048          * clocks go from a few thousand to several hundred thousand.
1049          * latency is usually a few thousand
1050          */
1051         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1052                 1000;
1053         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1054
1055         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1056
1057         wm_size = fifo_size - (entries_required + wm->guard_size);
1058
1059         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1060
1061         /* Don't promote wm_size to unsigned... */
1062         if (wm_size > (long)wm->max_wm)
1063                 wm_size = wm->max_wm;
1064         if (wm_size <= 0)
1065                 wm_size = wm->default_wm;
1066         return wm_size;
1067 }
1068
1069 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1070 {
1071         struct drm_crtc *crtc, *enabled = NULL;
1072
1073         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1074                 if (intel_crtc_active(crtc)) {
1075                         if (enabled)
1076                                 return NULL;
1077                         enabled = crtc;
1078                 }
1079         }
1080
1081         return enabled;
1082 }
1083
1084 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1085 {
1086         struct drm_device *dev = unused_crtc->dev;
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088         struct drm_crtc *crtc;
1089         const struct cxsr_latency *latency;
1090         u32 reg;
1091         unsigned long wm;
1092
1093         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1095         if (!latency) {
1096                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097                 pineview_disable_cxsr(dev);
1098                 return;
1099         }
1100
1101         crtc = single_enabled_crtc(dev);
1102         if (crtc) {
1103                 const struct drm_display_mode *adjusted_mode;
1104                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1105                 int clock;
1106
1107                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108                 clock = adjusted_mode->crtc_clock;
1109
1110                 /* Display SR */
1111                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112                                         pineview_display_wm.fifo_size,
1113                                         pixel_size, latency->display_sr);
1114                 reg = I915_READ(DSPFW1);
1115                 reg &= ~DSPFW_SR_MASK;
1116                 reg |= wm << DSPFW_SR_SHIFT;
1117                 I915_WRITE(DSPFW1, reg);
1118                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1119
1120                 /* cursor SR */
1121                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122                                         pineview_display_wm.fifo_size,
1123                                         pixel_size, latency->cursor_sr);
1124                 reg = I915_READ(DSPFW3);
1125                 reg &= ~DSPFW_CURSOR_SR_MASK;
1126                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127                 I915_WRITE(DSPFW3, reg);
1128
1129                 /* Display HPLL off SR */
1130                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131                                         pineview_display_hplloff_wm.fifo_size,
1132                                         pixel_size, latency->display_hpll_disable);
1133                 reg = I915_READ(DSPFW3);
1134                 reg &= ~DSPFW_HPLL_SR_MASK;
1135                 reg |= wm & DSPFW_HPLL_SR_MASK;
1136                 I915_WRITE(DSPFW3, reg);
1137
1138                 /* cursor HPLL off SR */
1139                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140                                         pineview_display_hplloff_wm.fifo_size,
1141                                         pixel_size, latency->cursor_hpll_disable);
1142                 reg = I915_READ(DSPFW3);
1143                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145                 I915_WRITE(DSPFW3, reg);
1146                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1147
1148                 /* activate cxsr */
1149                 I915_WRITE(DSPFW3,
1150                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1151                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1152         } else {
1153                 pineview_disable_cxsr(dev);
1154                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1155         }
1156 }
1157
1158 static bool g4x_compute_wm0(struct drm_device *dev,
1159                             int plane,
1160                             const struct intel_watermark_params *display,
1161                             int display_latency_ns,
1162                             const struct intel_watermark_params *cursor,
1163                             int cursor_latency_ns,
1164                             int *plane_wm,
1165                             int *cursor_wm)
1166 {
1167         struct drm_crtc *crtc;
1168         const struct drm_display_mode *adjusted_mode;
1169         int htotal, hdisplay, clock, pixel_size;
1170         int line_time_us, line_count;
1171         int entries, tlb_miss;
1172
1173         crtc = intel_get_crtc_for_plane(dev, plane);
1174         if (!intel_crtc_active(crtc)) {
1175                 *cursor_wm = cursor->guard_size;
1176                 *plane_wm = display->guard_size;
1177                 return false;
1178         }
1179
1180         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1181         clock = adjusted_mode->crtc_clock;
1182         htotal = adjusted_mode->htotal;
1183         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1184         pixel_size = crtc->fb->bits_per_pixel / 8;
1185
1186         /* Use the small buffer method to calculate plane watermark */
1187         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1189         if (tlb_miss > 0)
1190                 entries += tlb_miss;
1191         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192         *plane_wm = entries + display->guard_size;
1193         if (*plane_wm > (int)display->max_wm)
1194                 *plane_wm = display->max_wm;
1195
1196         /* Use the large buffer method to calculate cursor watermark */
1197         line_time_us = ((htotal * 1000) / clock);
1198         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199         entries = line_count * 64 * pixel_size;
1200         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1201         if (tlb_miss > 0)
1202                 entries += tlb_miss;
1203         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204         *cursor_wm = entries + cursor->guard_size;
1205         if (*cursor_wm > (int)cursor->max_wm)
1206                 *cursor_wm = (int)cursor->max_wm;
1207
1208         return true;
1209 }
1210
1211 /*
1212  * Check the wm result.
1213  *
1214  * If any calculated watermark values is larger than the maximum value that
1215  * can be programmed into the associated watermark register, that watermark
1216  * must be disabled.
1217  */
1218 static bool g4x_check_srwm(struct drm_device *dev,
1219                            int display_wm, int cursor_wm,
1220                            const struct intel_watermark_params *display,
1221                            const struct intel_watermark_params *cursor)
1222 {
1223         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224                       display_wm, cursor_wm);
1225
1226         if (display_wm > display->max_wm) {
1227                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228                               display_wm, display->max_wm);
1229                 return false;
1230         }
1231
1232         if (cursor_wm > cursor->max_wm) {
1233                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234                               cursor_wm, cursor->max_wm);
1235                 return false;
1236         }
1237
1238         if (!(display_wm || cursor_wm)) {
1239                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1240                 return false;
1241         }
1242
1243         return true;
1244 }
1245
1246 static bool g4x_compute_srwm(struct drm_device *dev,
1247                              int plane,
1248                              int latency_ns,
1249                              const struct intel_watermark_params *display,
1250                              const struct intel_watermark_params *cursor,
1251                              int *display_wm, int *cursor_wm)
1252 {
1253         struct drm_crtc *crtc;
1254         const struct drm_display_mode *adjusted_mode;
1255         int hdisplay, htotal, pixel_size, clock;
1256         unsigned long line_time_us;
1257         int line_count, line_size;
1258         int small, large;
1259         int entries;
1260
1261         if (!latency_ns) {
1262                 *display_wm = *cursor_wm = 0;
1263                 return false;
1264         }
1265
1266         crtc = intel_get_crtc_for_plane(dev, plane);
1267         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1268         clock = adjusted_mode->crtc_clock;
1269         htotal = adjusted_mode->htotal;
1270         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1271         pixel_size = crtc->fb->bits_per_pixel / 8;
1272
1273         line_time_us = (htotal * 1000) / clock;
1274         line_count = (latency_ns / line_time_us + 1000) / 1000;
1275         line_size = hdisplay * pixel_size;
1276
1277         /* Use the minimum of the small and large buffer method for primary */
1278         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1279         large = line_count * line_size;
1280
1281         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282         *display_wm = entries + display->guard_size;
1283
1284         /* calculate the self-refresh watermark for display cursor */
1285         entries = line_count * pixel_size * 64;
1286         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1287         *cursor_wm = entries + cursor->guard_size;
1288
1289         return g4x_check_srwm(dev,
1290                               *display_wm, *cursor_wm,
1291                               display, cursor);
1292 }
1293
1294 static bool vlv_compute_drain_latency(struct drm_device *dev,
1295                                      int plane,
1296                                      int *plane_prec_mult,
1297                                      int *plane_dl,
1298                                      int *cursor_prec_mult,
1299                                      int *cursor_dl)
1300 {
1301         struct drm_crtc *crtc;
1302         int clock, pixel_size;
1303         int entries;
1304
1305         crtc = intel_get_crtc_for_plane(dev, plane);
1306         if (!intel_crtc_active(crtc))
1307                 return false;
1308
1309         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1310         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1311
1312         entries = (clock / 1000) * pixel_size;
1313         *plane_prec_mult = (entries > 256) ?
1314                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1315         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1316                                                      pixel_size);
1317
1318         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1319         *cursor_prec_mult = (entries > 256) ?
1320                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1321         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1322
1323         return true;
1324 }
1325
1326 /*
1327  * Update drain latency registers of memory arbiter
1328  *
1329  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330  * to be programmed. Each plane has a drain latency multiplier and a drain
1331  * latency value.
1332  */
1333
1334 static void vlv_update_drain_latency(struct drm_device *dev)
1335 {
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1338         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1339         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1340                                                         either 16 or 32 */
1341
1342         /* For plane A, Cursor A */
1343         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1344                                       &cursor_prec_mult, &cursora_dl)) {
1345                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1347                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1348                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1349
1350                 I915_WRITE(VLV_DDL1, cursora_prec |
1351                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1352                                 planea_prec | planea_dl);
1353         }
1354
1355         /* For plane B, Cursor B */
1356         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1357                                       &cursor_prec_mult, &cursorb_dl)) {
1358                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1360                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1361                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1362
1363                 I915_WRITE(VLV_DDL2, cursorb_prec |
1364                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1365                                 planeb_prec | planeb_dl);
1366         }
1367 }
1368
1369 #define single_plane_enabled(mask) is_power_of_2(mask)
1370
1371 static void valleyview_update_wm(struct drm_crtc *crtc)
1372 {
1373         struct drm_device *dev = crtc->dev;
1374         static const int sr_latency_ns = 12000;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377         int plane_sr, cursor_sr;
1378         int ignore_plane_sr, ignore_cursor_sr;
1379         unsigned int enabled = 0;
1380
1381         vlv_update_drain_latency(dev);
1382
1383         if (g4x_compute_wm0(dev, PIPE_A,
1384                             &valleyview_wm_info, latency_ns,
1385                             &valleyview_cursor_wm_info, latency_ns,
1386                             &planea_wm, &cursora_wm))
1387                 enabled |= 1 << PIPE_A;
1388
1389         if (g4x_compute_wm0(dev, PIPE_B,
1390                             &valleyview_wm_info, latency_ns,
1391                             &valleyview_cursor_wm_info, latency_ns,
1392                             &planeb_wm, &cursorb_wm))
1393                 enabled |= 1 << PIPE_B;
1394
1395         if (single_plane_enabled(enabled) &&
1396             g4x_compute_srwm(dev, ffs(enabled) - 1,
1397                              sr_latency_ns,
1398                              &valleyview_wm_info,
1399                              &valleyview_cursor_wm_info,
1400                              &plane_sr, &ignore_cursor_sr) &&
1401             g4x_compute_srwm(dev, ffs(enabled) - 1,
1402                              2*sr_latency_ns,
1403                              &valleyview_wm_info,
1404                              &valleyview_cursor_wm_info,
1405                              &ignore_plane_sr, &cursor_sr)) {
1406                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1407         } else {
1408                 I915_WRITE(FW_BLC_SELF_VLV,
1409                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1410                 plane_sr = cursor_sr = 0;
1411         }
1412
1413         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414                       planea_wm, cursora_wm,
1415                       planeb_wm, cursorb_wm,
1416                       plane_sr, cursor_sr);
1417
1418         I915_WRITE(DSPFW1,
1419                    (plane_sr << DSPFW_SR_SHIFT) |
1420                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1422                    planea_wm);
1423         I915_WRITE(DSPFW2,
1424                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1425                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1426         I915_WRITE(DSPFW3,
1427                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1429 }
1430
1431 static void g4x_update_wm(struct drm_crtc *crtc)
1432 {
1433         struct drm_device *dev = crtc->dev;
1434         static const int sr_latency_ns = 12000;
1435         struct drm_i915_private *dev_priv = dev->dev_private;
1436         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1437         int plane_sr, cursor_sr;
1438         unsigned int enabled = 0;
1439
1440         if (g4x_compute_wm0(dev, PIPE_A,
1441                             &g4x_wm_info, latency_ns,
1442                             &g4x_cursor_wm_info, latency_ns,
1443                             &planea_wm, &cursora_wm))
1444                 enabled |= 1 << PIPE_A;
1445
1446         if (g4x_compute_wm0(dev, PIPE_B,
1447                             &g4x_wm_info, latency_ns,
1448                             &g4x_cursor_wm_info, latency_ns,
1449                             &planeb_wm, &cursorb_wm))
1450                 enabled |= 1 << PIPE_B;
1451
1452         if (single_plane_enabled(enabled) &&
1453             g4x_compute_srwm(dev, ffs(enabled) - 1,
1454                              sr_latency_ns,
1455                              &g4x_wm_info,
1456                              &g4x_cursor_wm_info,
1457                              &plane_sr, &cursor_sr)) {
1458                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1459         } else {
1460                 I915_WRITE(FW_BLC_SELF,
1461                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1462                 plane_sr = cursor_sr = 0;
1463         }
1464
1465         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1466                       planea_wm, cursora_wm,
1467                       planeb_wm, cursorb_wm,
1468                       plane_sr, cursor_sr);
1469
1470         I915_WRITE(DSPFW1,
1471                    (plane_sr << DSPFW_SR_SHIFT) |
1472                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1473                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1474                    planea_wm);
1475         I915_WRITE(DSPFW2,
1476                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1477                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1478         /* HPLL off in SR has some issues on G4x... disable it */
1479         I915_WRITE(DSPFW3,
1480                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1481                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1482 }
1483
1484 static void i965_update_wm(struct drm_crtc *unused_crtc)
1485 {
1486         struct drm_device *dev = unused_crtc->dev;
1487         struct drm_i915_private *dev_priv = dev->dev_private;
1488         struct drm_crtc *crtc;
1489         int srwm = 1;
1490         int cursor_sr = 16;
1491
1492         /* Calc sr entries for one plane configs */
1493         crtc = single_enabled_crtc(dev);
1494         if (crtc) {
1495                 /* self-refresh has much higher latency */
1496                 static const int sr_latency_ns = 12000;
1497                 const struct drm_display_mode *adjusted_mode =
1498                         &to_intel_crtc(crtc)->config.adjusted_mode;
1499                 int clock = adjusted_mode->crtc_clock;
1500                 int htotal = adjusted_mode->htotal;
1501                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1502                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1503                 unsigned long line_time_us;
1504                 int entries;
1505
1506                 line_time_us = ((htotal * 1000) / clock);
1507
1508                 /* Use ns/us then divide to preserve precision */
1509                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510                         pixel_size * hdisplay;
1511                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512                 srwm = I965_FIFO_SIZE - entries;
1513                 if (srwm < 0)
1514                         srwm = 1;
1515                 srwm &= 0x1ff;
1516                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1517                               entries, srwm);
1518
1519                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1520                         pixel_size * 64;
1521                 entries = DIV_ROUND_UP(entries,
1522                                           i965_cursor_wm_info.cacheline_size);
1523                 cursor_sr = i965_cursor_wm_info.fifo_size -
1524                         (entries + i965_cursor_wm_info.guard_size);
1525
1526                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527                         cursor_sr = i965_cursor_wm_info.max_wm;
1528
1529                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530                               "cursor %d\n", srwm, cursor_sr);
1531
1532                 if (IS_CRESTLINE(dev))
1533                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1534         } else {
1535                 /* Turn off self refresh if both pipes are enabled */
1536                 if (IS_CRESTLINE(dev))
1537                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1538                                    & ~FW_BLC_SELF_EN);
1539         }
1540
1541         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1542                       srwm);
1543
1544         /* 965 has limitations... */
1545         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1546                    (8 << 16) | (8 << 8) | (8 << 0));
1547         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1548         /* update cursor SR watermark */
1549         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1550 }
1551
1552 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1553 {
1554         struct drm_device *dev = unused_crtc->dev;
1555         struct drm_i915_private *dev_priv = dev->dev_private;
1556         const struct intel_watermark_params *wm_info;
1557         uint32_t fwater_lo;
1558         uint32_t fwater_hi;
1559         int cwm, srwm = 1;
1560         int fifo_size;
1561         int planea_wm, planeb_wm;
1562         struct drm_crtc *crtc, *enabled = NULL;
1563
1564         if (IS_I945GM(dev))
1565                 wm_info = &i945_wm_info;
1566         else if (!IS_GEN2(dev))
1567                 wm_info = &i915_wm_info;
1568         else
1569                 wm_info = &i855_wm_info;
1570
1571         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572         crtc = intel_get_crtc_for_plane(dev, 0);
1573         if (intel_crtc_active(crtc)) {
1574                 const struct drm_display_mode *adjusted_mode;
1575                 int cpp = crtc->fb->bits_per_pixel / 8;
1576                 if (IS_GEN2(dev))
1577                         cpp = 4;
1578
1579                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1580                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1581                                                wm_info, fifo_size, cpp,
1582                                                latency_ns);
1583                 enabled = crtc;
1584         } else
1585                 planea_wm = fifo_size - wm_info->guard_size;
1586
1587         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1588         crtc = intel_get_crtc_for_plane(dev, 1);
1589         if (intel_crtc_active(crtc)) {
1590                 const struct drm_display_mode *adjusted_mode;
1591                 int cpp = crtc->fb->bits_per_pixel / 8;
1592                 if (IS_GEN2(dev))
1593                         cpp = 4;
1594
1595                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1596                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1597                                                wm_info, fifo_size, cpp,
1598                                                latency_ns);
1599                 if (enabled == NULL)
1600                         enabled = crtc;
1601                 else
1602                         enabled = NULL;
1603         } else
1604                 planeb_wm = fifo_size - wm_info->guard_size;
1605
1606         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1607
1608         /*
1609          * Overlay gets an aggressive default since video jitter is bad.
1610          */
1611         cwm = 2;
1612
1613         /* Play safe and disable self-refresh before adjusting watermarks. */
1614         if (IS_I945G(dev) || IS_I945GM(dev))
1615                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1616         else if (IS_I915GM(dev))
1617                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1618
1619         /* Calc sr entries for one plane configs */
1620         if (HAS_FW_BLC(dev) && enabled) {
1621                 /* self-refresh has much higher latency */
1622                 static const int sr_latency_ns = 6000;
1623                 const struct drm_display_mode *adjusted_mode =
1624                         &to_intel_crtc(enabled)->config.adjusted_mode;
1625                 int clock = adjusted_mode->crtc_clock;
1626                 int htotal = adjusted_mode->htotal;
1627                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1628                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1629                 unsigned long line_time_us;
1630                 int entries;
1631
1632                 line_time_us = (htotal * 1000) / clock;
1633
1634                 /* Use ns/us then divide to preserve precision */
1635                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636                         pixel_size * hdisplay;
1637                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1638                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1639                 srwm = wm_info->fifo_size - entries;
1640                 if (srwm < 0)
1641                         srwm = 1;
1642
1643                 if (IS_I945G(dev) || IS_I945GM(dev))
1644                         I915_WRITE(FW_BLC_SELF,
1645                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1646                 else if (IS_I915GM(dev))
1647                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1648         }
1649
1650         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1651                       planea_wm, planeb_wm, cwm, srwm);
1652
1653         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1654         fwater_hi = (cwm & 0x1f);
1655
1656         /* Set request length to 8 cachelines per fetch */
1657         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1658         fwater_hi = fwater_hi | (1 << 8);
1659
1660         I915_WRITE(FW_BLC, fwater_lo);
1661         I915_WRITE(FW_BLC2, fwater_hi);
1662
1663         if (HAS_FW_BLC(dev)) {
1664                 if (enabled) {
1665                         if (IS_I945G(dev) || IS_I945GM(dev))
1666                                 I915_WRITE(FW_BLC_SELF,
1667                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1668                         else if (IS_I915GM(dev))
1669                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1670                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1671                 } else
1672                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1673         }
1674 }
1675
1676 static void i830_update_wm(struct drm_crtc *unused_crtc)
1677 {
1678         struct drm_device *dev = unused_crtc->dev;
1679         struct drm_i915_private *dev_priv = dev->dev_private;
1680         struct drm_crtc *crtc;
1681         const struct drm_display_mode *adjusted_mode;
1682         uint32_t fwater_lo;
1683         int planea_wm;
1684
1685         crtc = single_enabled_crtc(dev);
1686         if (crtc == NULL)
1687                 return;
1688
1689         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1690         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1691                                        &i830_wm_info,
1692                                        dev_priv->display.get_fifo_size(dev, 0),
1693                                        4, latency_ns);
1694         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695         fwater_lo |= (3<<8) | planea_wm;
1696
1697         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699         I915_WRITE(FW_BLC, fwater_lo);
1700 }
1701
1702 /*
1703  * Check the wm result.
1704  *
1705  * If any calculated watermark values is larger than the maximum value that
1706  * can be programmed into the associated watermark register, that watermark
1707  * must be disabled.
1708  */
1709 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1710                                 int fbc_wm, int display_wm, int cursor_wm,
1711                                 const struct intel_watermark_params *display,
1712                                 const struct intel_watermark_params *cursor)
1713 {
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715
1716         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1717                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1718
1719         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1720                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1721                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1722
1723                 /* fbc has it's own way to disable FBC WM */
1724                 I915_WRITE(DISP_ARB_CTL,
1725                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1726                 return false;
1727         } else if (INTEL_INFO(dev)->gen >= 6) {
1728                 /* enable FBC WM (except on ILK, where it must remain off) */
1729                 I915_WRITE(DISP_ARB_CTL,
1730                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1731         }
1732
1733         if (display_wm > display->max_wm) {
1734                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1735                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1736                 return false;
1737         }
1738
1739         if (cursor_wm > cursor->max_wm) {
1740                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1741                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1742                 return false;
1743         }
1744
1745         if (!(fbc_wm || display_wm || cursor_wm)) {
1746                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1747                 return false;
1748         }
1749
1750         return true;
1751 }
1752
1753 /*
1754  * Compute watermark values of WM[1-3],
1755  */
1756 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1757                                   int latency_ns,
1758                                   const struct intel_watermark_params *display,
1759                                   const struct intel_watermark_params *cursor,
1760                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1761 {
1762         struct drm_crtc *crtc;
1763         const struct drm_display_mode *adjusted_mode;
1764         unsigned long line_time_us;
1765         int hdisplay, htotal, pixel_size, clock;
1766         int line_count, line_size;
1767         int small, large;
1768         int entries;
1769
1770         if (!latency_ns) {
1771                 *fbc_wm = *display_wm = *cursor_wm = 0;
1772                 return false;
1773         }
1774
1775         crtc = intel_get_crtc_for_plane(dev, plane);
1776         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1777         clock = adjusted_mode->crtc_clock;
1778         htotal = adjusted_mode->htotal;
1779         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1780         pixel_size = crtc->fb->bits_per_pixel / 8;
1781
1782         line_time_us = (htotal * 1000) / clock;
1783         line_count = (latency_ns / line_time_us + 1000) / 1000;
1784         line_size = hdisplay * pixel_size;
1785
1786         /* Use the minimum of the small and large buffer method for primary */
1787         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1788         large = line_count * line_size;
1789
1790         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1791         *display_wm = entries + display->guard_size;
1792
1793         /*
1794          * Spec says:
1795          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1796          */
1797         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1798
1799         /* calculate the self-refresh watermark for display cursor */
1800         entries = line_count * pixel_size * 64;
1801         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1802         *cursor_wm = entries + cursor->guard_size;
1803
1804         return ironlake_check_srwm(dev, level,
1805                                    *fbc_wm, *display_wm, *cursor_wm,
1806                                    display, cursor);
1807 }
1808
1809 static void ironlake_update_wm(struct drm_crtc *crtc)
1810 {
1811         struct drm_device *dev = crtc->dev;
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         int fbc_wm, plane_wm, cursor_wm;
1814         unsigned int enabled;
1815
1816         enabled = 0;
1817         if (g4x_compute_wm0(dev, PIPE_A,
1818                             &ironlake_display_wm_info,
1819                             dev_priv->wm.pri_latency[0] * 100,
1820                             &ironlake_cursor_wm_info,
1821                             dev_priv->wm.cur_latency[0] * 100,
1822                             &plane_wm, &cursor_wm)) {
1823                 I915_WRITE(WM0_PIPEA_ILK,
1824                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1825                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1826                               " plane %d, " "cursor: %d\n",
1827                               plane_wm, cursor_wm);
1828                 enabled |= 1 << PIPE_A;
1829         }
1830
1831         if (g4x_compute_wm0(dev, PIPE_B,
1832                             &ironlake_display_wm_info,
1833                             dev_priv->wm.pri_latency[0] * 100,
1834                             &ironlake_cursor_wm_info,
1835                             dev_priv->wm.cur_latency[0] * 100,
1836                             &plane_wm, &cursor_wm)) {
1837                 I915_WRITE(WM0_PIPEB_ILK,
1838                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1839                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1840                               " plane %d, cursor: %d\n",
1841                               plane_wm, cursor_wm);
1842                 enabled |= 1 << PIPE_B;
1843         }
1844
1845         /*
1846          * Calculate and update the self-refresh watermark only when one
1847          * display plane is used.
1848          */
1849         I915_WRITE(WM3_LP_ILK, 0);
1850         I915_WRITE(WM2_LP_ILK, 0);
1851         I915_WRITE(WM1_LP_ILK, 0);
1852
1853         if (!single_plane_enabled(enabled))
1854                 return;
1855         enabled = ffs(enabled) - 1;
1856
1857         /* WM1 */
1858         if (!ironlake_compute_srwm(dev, 1, enabled,
1859                                    dev_priv->wm.pri_latency[1] * 500,
1860                                    &ironlake_display_srwm_info,
1861                                    &ironlake_cursor_srwm_info,
1862                                    &fbc_wm, &plane_wm, &cursor_wm))
1863                 return;
1864
1865         I915_WRITE(WM1_LP_ILK,
1866                    WM1_LP_SR_EN |
1867                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1868                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1869                    (plane_wm << WM1_LP_SR_SHIFT) |
1870                    cursor_wm);
1871
1872         /* WM2 */
1873         if (!ironlake_compute_srwm(dev, 2, enabled,
1874                                    dev_priv->wm.pri_latency[2] * 500,
1875                                    &ironlake_display_srwm_info,
1876                                    &ironlake_cursor_srwm_info,
1877                                    &fbc_wm, &plane_wm, &cursor_wm))
1878                 return;
1879
1880         I915_WRITE(WM2_LP_ILK,
1881                    WM2_LP_EN |
1882                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1883                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1884                    (plane_wm << WM1_LP_SR_SHIFT) |
1885                    cursor_wm);
1886
1887         /*
1888          * WM3 is unsupported on ILK, probably because we don't have latency
1889          * data for that power state
1890          */
1891 }
1892
1893 static void sandybridge_update_wm(struct drm_crtc *crtc)
1894 {
1895         struct drm_device *dev = crtc->dev;
1896         struct drm_i915_private *dev_priv = dev->dev_private;
1897         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1898         u32 val;
1899         int fbc_wm, plane_wm, cursor_wm;
1900         unsigned int enabled;
1901
1902         enabled = 0;
1903         if (g4x_compute_wm0(dev, PIPE_A,
1904                             &sandybridge_display_wm_info, latency,
1905                             &sandybridge_cursor_wm_info, latency,
1906                             &plane_wm, &cursor_wm)) {
1907                 val = I915_READ(WM0_PIPEA_ILK);
1908                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909                 I915_WRITE(WM0_PIPEA_ILK, val |
1910                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1912                               " plane %d, " "cursor: %d\n",
1913                               plane_wm, cursor_wm);
1914                 enabled |= 1 << PIPE_A;
1915         }
1916
1917         if (g4x_compute_wm0(dev, PIPE_B,
1918                             &sandybridge_display_wm_info, latency,
1919                             &sandybridge_cursor_wm_info, latency,
1920                             &plane_wm, &cursor_wm)) {
1921                 val = I915_READ(WM0_PIPEB_ILK);
1922                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923                 I915_WRITE(WM0_PIPEB_ILK, val |
1924                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1926                               " plane %d, cursor: %d\n",
1927                               plane_wm, cursor_wm);
1928                 enabled |= 1 << PIPE_B;
1929         }
1930
1931         /*
1932          * Calculate and update the self-refresh watermark only when one
1933          * display plane is used.
1934          *
1935          * SNB support 3 levels of watermark.
1936          *
1937          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938          * and disabled in the descending order
1939          *
1940          */
1941         I915_WRITE(WM3_LP_ILK, 0);
1942         I915_WRITE(WM2_LP_ILK, 0);
1943         I915_WRITE(WM1_LP_ILK, 0);
1944
1945         if (!single_plane_enabled(enabled) ||
1946             dev_priv->sprite_scaling_enabled)
1947                 return;
1948         enabled = ffs(enabled) - 1;
1949
1950         /* WM1 */
1951         if (!ironlake_compute_srwm(dev, 1, enabled,
1952                                    dev_priv->wm.pri_latency[1] * 500,
1953                                    &sandybridge_display_srwm_info,
1954                                    &sandybridge_cursor_srwm_info,
1955                                    &fbc_wm, &plane_wm, &cursor_wm))
1956                 return;
1957
1958         I915_WRITE(WM1_LP_ILK,
1959                    WM1_LP_SR_EN |
1960                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1961                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1962                    (plane_wm << WM1_LP_SR_SHIFT) |
1963                    cursor_wm);
1964
1965         /* WM2 */
1966         if (!ironlake_compute_srwm(dev, 2, enabled,
1967                                    dev_priv->wm.pri_latency[2] * 500,
1968                                    &sandybridge_display_srwm_info,
1969                                    &sandybridge_cursor_srwm_info,
1970                                    &fbc_wm, &plane_wm, &cursor_wm))
1971                 return;
1972
1973         I915_WRITE(WM2_LP_ILK,
1974                    WM2_LP_EN |
1975                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1976                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1977                    (plane_wm << WM1_LP_SR_SHIFT) |
1978                    cursor_wm);
1979
1980         /* WM3 */
1981         if (!ironlake_compute_srwm(dev, 3, enabled,
1982                                    dev_priv->wm.pri_latency[3] * 500,
1983                                    &sandybridge_display_srwm_info,
1984                                    &sandybridge_cursor_srwm_info,
1985                                    &fbc_wm, &plane_wm, &cursor_wm))
1986                 return;
1987
1988         I915_WRITE(WM3_LP_ILK,
1989                    WM3_LP_EN |
1990                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1991                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1992                    (plane_wm << WM1_LP_SR_SHIFT) |
1993                    cursor_wm);
1994 }
1995
1996 static void ivybridge_update_wm(struct drm_crtc *crtc)
1997 {
1998         struct drm_device *dev = crtc->dev;
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
2001         u32 val;
2002         int fbc_wm, plane_wm, cursor_wm;
2003         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2004         unsigned int enabled;
2005
2006         enabled = 0;
2007         if (g4x_compute_wm0(dev, PIPE_A,
2008                             &sandybridge_display_wm_info, latency,
2009                             &sandybridge_cursor_wm_info, latency,
2010                             &plane_wm, &cursor_wm)) {
2011                 val = I915_READ(WM0_PIPEA_ILK);
2012                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2013                 I915_WRITE(WM0_PIPEA_ILK, val |
2014                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2015                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2016                               " plane %d, " "cursor: %d\n",
2017                               plane_wm, cursor_wm);
2018                 enabled |= 1 << PIPE_A;
2019         }
2020
2021         if (g4x_compute_wm0(dev, PIPE_B,
2022                             &sandybridge_display_wm_info, latency,
2023                             &sandybridge_cursor_wm_info, latency,
2024                             &plane_wm, &cursor_wm)) {
2025                 val = I915_READ(WM0_PIPEB_ILK);
2026                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2027                 I915_WRITE(WM0_PIPEB_ILK, val |
2028                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2029                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2030                               " plane %d, cursor: %d\n",
2031                               plane_wm, cursor_wm);
2032                 enabled |= 1 << PIPE_B;
2033         }
2034
2035         if (g4x_compute_wm0(dev, PIPE_C,
2036                             &sandybridge_display_wm_info, latency,
2037                             &sandybridge_cursor_wm_info, latency,
2038                             &plane_wm, &cursor_wm)) {
2039                 val = I915_READ(WM0_PIPEC_IVB);
2040                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2041                 I915_WRITE(WM0_PIPEC_IVB, val |
2042                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2043                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2044                               " plane %d, cursor: %d\n",
2045                               plane_wm, cursor_wm);
2046                 enabled |= 1 << PIPE_C;
2047         }
2048
2049         /*
2050          * Calculate and update the self-refresh watermark only when one
2051          * display plane is used.
2052          *
2053          * SNB support 3 levels of watermark.
2054          *
2055          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2056          * and disabled in the descending order
2057          *
2058          */
2059         I915_WRITE(WM3_LP_ILK, 0);
2060         I915_WRITE(WM2_LP_ILK, 0);
2061         I915_WRITE(WM1_LP_ILK, 0);
2062
2063         if (!single_plane_enabled(enabled) ||
2064             dev_priv->sprite_scaling_enabled)
2065                 return;
2066         enabled = ffs(enabled) - 1;
2067
2068         /* WM1 */
2069         if (!ironlake_compute_srwm(dev, 1, enabled,
2070                                    dev_priv->wm.pri_latency[1] * 500,
2071                                    &sandybridge_display_srwm_info,
2072                                    &sandybridge_cursor_srwm_info,
2073                                    &fbc_wm, &plane_wm, &cursor_wm))
2074                 return;
2075
2076         I915_WRITE(WM1_LP_ILK,
2077                    WM1_LP_SR_EN |
2078                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2079                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2080                    (plane_wm << WM1_LP_SR_SHIFT) |
2081                    cursor_wm);
2082
2083         /* WM2 */
2084         if (!ironlake_compute_srwm(dev, 2, enabled,
2085                                    dev_priv->wm.pri_latency[2] * 500,
2086                                    &sandybridge_display_srwm_info,
2087                                    &sandybridge_cursor_srwm_info,
2088                                    &fbc_wm, &plane_wm, &cursor_wm))
2089                 return;
2090
2091         I915_WRITE(WM2_LP_ILK,
2092                    WM2_LP_EN |
2093                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2094                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2095                    (plane_wm << WM1_LP_SR_SHIFT) |
2096                    cursor_wm);
2097
2098         /* WM3, note we have to correct the cursor latency */
2099         if (!ironlake_compute_srwm(dev, 3, enabled,
2100                                    dev_priv->wm.pri_latency[3] * 500,
2101                                    &sandybridge_display_srwm_info,
2102                                    &sandybridge_cursor_srwm_info,
2103                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2104             !ironlake_compute_srwm(dev, 3, enabled,
2105                                    dev_priv->wm.cur_latency[3] * 500,
2106                                    &sandybridge_display_srwm_info,
2107                                    &sandybridge_cursor_srwm_info,
2108                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2109                 return;
2110
2111         I915_WRITE(WM3_LP_ILK,
2112                    WM3_LP_EN |
2113                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2114                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2115                    (plane_wm << WM1_LP_SR_SHIFT) |
2116                    cursor_wm);
2117 }
2118
2119 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2120                                     struct drm_crtc *crtc)
2121 {
2122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2123         uint32_t pixel_rate;
2124
2125         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2126
2127         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2128          * adjust the pixel_rate here. */
2129
2130         if (intel_crtc->config.pch_pfit.enabled) {
2131                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2132                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2133
2134                 pipe_w = intel_crtc->config.pipe_src_w;
2135                 pipe_h = intel_crtc->config.pipe_src_h;
2136                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2137                 pfit_h = pfit_size & 0xFFFF;
2138                 if (pipe_w < pfit_w)
2139                         pipe_w = pfit_w;
2140                 if (pipe_h < pfit_h)
2141                         pipe_h = pfit_h;
2142
2143                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2144                                      pfit_w * pfit_h);
2145         }
2146
2147         return pixel_rate;
2148 }
2149
2150 /* latency must be in 0.1us units. */
2151 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2152                                uint32_t latency)
2153 {
2154         uint64_t ret;
2155
2156         if (WARN(latency == 0, "Latency value missing\n"))
2157                 return UINT_MAX;
2158
2159         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2160         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2161
2162         return ret;
2163 }
2164
2165 /* latency must be in 0.1us units. */
2166 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2167                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2168                                uint32_t latency)
2169 {
2170         uint32_t ret;
2171
2172         if (WARN(latency == 0, "Latency value missing\n"))
2173                 return UINT_MAX;
2174
2175         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2176         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2177         ret = DIV_ROUND_UP(ret, 64) + 2;
2178         return ret;
2179 }
2180
2181 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2182                            uint8_t bytes_per_pixel)
2183 {
2184         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2185 }
2186
2187 struct hsw_pipe_wm_parameters {
2188         bool active;
2189         uint32_t pipe_htotal;
2190         uint32_t pixel_rate;
2191         struct intel_plane_wm_parameters pri;
2192         struct intel_plane_wm_parameters spr;
2193         struct intel_plane_wm_parameters cur;
2194 };
2195
2196 struct hsw_wm_maximums {
2197         uint16_t pri;
2198         uint16_t spr;
2199         uint16_t cur;
2200         uint16_t fbc;
2201 };
2202
2203 /* used in computing the new watermarks state */
2204 struct intel_wm_config {
2205         unsigned int num_pipes_active;
2206         bool sprites_enabled;
2207         bool sprites_scaled;
2208 };
2209
2210 /*
2211  * For both WM_PIPE and WM_LP.
2212  * mem_value must be in 0.1us units.
2213  */
2214 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2215                                    uint32_t mem_value,
2216                                    bool is_lp)
2217 {
2218         uint32_t method1, method2;
2219
2220         if (!params->active || !params->pri.enabled)
2221                 return 0;
2222
2223         method1 = ilk_wm_method1(params->pixel_rate,
2224                                  params->pri.bytes_per_pixel,
2225                                  mem_value);
2226
2227         if (!is_lp)
2228                 return method1;
2229
2230         method2 = ilk_wm_method2(params->pixel_rate,
2231                                  params->pipe_htotal,
2232                                  params->pri.horiz_pixels,
2233                                  params->pri.bytes_per_pixel,
2234                                  mem_value);
2235
2236         return min(method1, method2);
2237 }
2238
2239 /*
2240  * For both WM_PIPE and WM_LP.
2241  * mem_value must be in 0.1us units.
2242  */
2243 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2244                                    uint32_t mem_value)
2245 {
2246         uint32_t method1, method2;
2247
2248         if (!params->active || !params->spr.enabled)
2249                 return 0;
2250
2251         method1 = ilk_wm_method1(params->pixel_rate,
2252                                  params->spr.bytes_per_pixel,
2253                                  mem_value);
2254         method2 = ilk_wm_method2(params->pixel_rate,
2255                                  params->pipe_htotal,
2256                                  params->spr.horiz_pixels,
2257                                  params->spr.bytes_per_pixel,
2258                                  mem_value);
2259         return min(method1, method2);
2260 }
2261
2262 /*
2263  * For both WM_PIPE and WM_LP.
2264  * mem_value must be in 0.1us units.
2265  */
2266 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2267                                    uint32_t mem_value)
2268 {
2269         if (!params->active || !params->cur.enabled)
2270                 return 0;
2271
2272         return ilk_wm_method2(params->pixel_rate,
2273                               params->pipe_htotal,
2274                               params->cur.horiz_pixels,
2275                               params->cur.bytes_per_pixel,
2276                               mem_value);
2277 }
2278
2279 /* Only for WM_LP. */
2280 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2281                                    uint32_t pri_val)
2282 {
2283         if (!params->active || !params->pri.enabled)
2284                 return 0;
2285
2286         return ilk_wm_fbc(pri_val,
2287                           params->pri.horiz_pixels,
2288                           params->pri.bytes_per_pixel);
2289 }
2290
2291 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2292 {
2293         if (INTEL_INFO(dev)->gen >= 7)
2294                 return 768;
2295         else
2296                 return 512;
2297 }
2298
2299 /* Calculate the maximum primary/sprite plane watermark */
2300 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2301                                      int level,
2302                                      const struct intel_wm_config *config,
2303                                      enum intel_ddb_partitioning ddb_partitioning,
2304                                      bool is_sprite)
2305 {
2306         unsigned int fifo_size = ilk_display_fifo_size(dev);
2307         unsigned int max;
2308
2309         /* if sprites aren't enabled, sprites get nothing */
2310         if (is_sprite && !config->sprites_enabled)
2311                 return 0;
2312
2313         /* HSW allows LP1+ watermarks even with multiple pipes */
2314         if (level == 0 || config->num_pipes_active > 1) {
2315                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2316
2317                 /*
2318                  * For some reason the non self refresh
2319                  * FIFO size is only half of the self
2320                  * refresh FIFO size on ILK/SNB.
2321                  */
2322                 if (INTEL_INFO(dev)->gen <= 6)
2323                         fifo_size /= 2;
2324         }
2325
2326         if (config->sprites_enabled) {
2327                 /* level 0 is always calculated with 1:1 split */
2328                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2329                         if (is_sprite)
2330                                 fifo_size *= 5;
2331                         fifo_size /= 6;
2332                 } else {
2333                         fifo_size /= 2;
2334                 }
2335         }
2336
2337         /* clamp to max that the registers can hold */
2338         if (INTEL_INFO(dev)->gen >= 7)
2339                 /* IVB/HSW primary/sprite plane watermarks */
2340                 max = level == 0 ? 127 : 1023;
2341         else if (!is_sprite)
2342                 /* ILK/SNB primary plane watermarks */
2343                 max = level == 0 ? 127 : 511;
2344         else
2345                 /* ILK/SNB sprite plane watermarks */
2346                 max = level == 0 ? 63 : 255;
2347
2348         return min(fifo_size, max);
2349 }
2350
2351 /* Calculate the maximum cursor plane watermark */
2352 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2353                                       int level,
2354                                       const struct intel_wm_config *config)
2355 {
2356         /* HSW LP1+ watermarks w/ multiple pipes */
2357         if (level > 0 && config->num_pipes_active > 1)
2358                 return 64;
2359
2360         /* otherwise just report max that registers can hold */
2361         if (INTEL_INFO(dev)->gen >= 7)
2362                 return level == 0 ? 63 : 255;
2363         else
2364                 return level == 0 ? 31 : 63;
2365 }
2366
2367 /* Calculate the maximum FBC watermark */
2368 static unsigned int ilk_fbc_wm_max(void)
2369 {
2370         /* max that registers can hold */
2371         return 15;
2372 }
2373
2374 static void ilk_compute_wm_maximums(struct drm_device *dev,
2375                                     int level,
2376                                     const struct intel_wm_config *config,
2377                                     enum intel_ddb_partitioning ddb_partitioning,
2378                                     struct hsw_wm_maximums *max)
2379 {
2380         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2381         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2382         max->cur = ilk_cursor_wm_max(dev, level, config);
2383         max->fbc = ilk_fbc_wm_max();
2384 }
2385
2386 static bool ilk_check_wm(int level,
2387                          const struct hsw_wm_maximums *max,
2388                          struct intel_wm_level *result)
2389 {
2390         bool ret;
2391
2392         /* already determined to be invalid? */
2393         if (!result->enable)
2394                 return false;
2395
2396         result->enable = result->pri_val <= max->pri &&
2397                          result->spr_val <= max->spr &&
2398                          result->cur_val <= max->cur;
2399
2400         ret = result->enable;
2401
2402         /*
2403          * HACK until we can pre-compute everything,
2404          * and thus fail gracefully if LP0 watermarks
2405          * are exceeded...
2406          */
2407         if (level == 0 && !result->enable) {
2408                 if (result->pri_val > max->pri)
2409                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2410                                       level, result->pri_val, max->pri);
2411                 if (result->spr_val > max->spr)
2412                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2413                                       level, result->spr_val, max->spr);
2414                 if (result->cur_val > max->cur)
2415                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2416                                       level, result->cur_val, max->cur);
2417
2418                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2419                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2420                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2421                 result->enable = true;
2422         }
2423
2424         return ret;
2425 }
2426
2427 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2428                                  int level,
2429                                  const struct hsw_pipe_wm_parameters *p,
2430                                  struct intel_wm_level *result)
2431 {
2432         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2433         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2434         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2435
2436         /* WM1+ latency values stored in 0.5us units */
2437         if (level > 0) {
2438                 pri_latency *= 5;
2439                 spr_latency *= 5;
2440                 cur_latency *= 5;
2441         }
2442
2443         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2444         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2445         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2446         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2447         result->enable = true;
2448 }
2449
2450 static uint32_t
2451 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2452 {
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2455         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2456         u32 linetime, ips_linetime;
2457
2458         if (!intel_crtc_active(crtc))
2459                 return 0;
2460
2461         /* The WM are computed with base on how long it takes to fill a single
2462          * row at the given clock rate, multiplied by 8.
2463          * */
2464         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2465         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2466                                          intel_ddi_get_cdclk_freq(dev_priv));
2467
2468         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2469                PIPE_WM_LINETIME_TIME(linetime);
2470 }
2471
2472 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2473 {
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475
2476         if (IS_HASWELL(dev)) {
2477                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2478
2479                 wm[0] = (sskpd >> 56) & 0xFF;
2480                 if (wm[0] == 0)
2481                         wm[0] = sskpd & 0xF;
2482                 wm[1] = (sskpd >> 4) & 0xFF;
2483                 wm[2] = (sskpd >> 12) & 0xFF;
2484                 wm[3] = (sskpd >> 20) & 0x1FF;
2485                 wm[4] = (sskpd >> 32) & 0x1FF;
2486         } else if (INTEL_INFO(dev)->gen >= 6) {
2487                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2488
2489                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2490                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2491                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2492                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2493         } else if (INTEL_INFO(dev)->gen >= 5) {
2494                 uint32_t mltr = I915_READ(MLTR_ILK);
2495
2496                 /* ILK primary LP0 latency is 700 ns */
2497                 wm[0] = 7;
2498                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2499                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2500         }
2501 }
2502
2503 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2504 {
2505         /* ILK sprite LP0 latency is 1300 ns */
2506         if (INTEL_INFO(dev)->gen == 5)
2507                 wm[0] = 13;
2508 }
2509
2510 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2511 {
2512         /* ILK cursor LP0 latency is 1300 ns */
2513         if (INTEL_INFO(dev)->gen == 5)
2514                 wm[0] = 13;
2515
2516         /* WaDoubleCursorLP3Latency:ivb */
2517         if (IS_IVYBRIDGE(dev))
2518                 wm[3] *= 2;
2519 }
2520
2521 static int ilk_wm_max_level(const struct drm_device *dev)
2522 {
2523         /* how many WM levels are we expecting */
2524         if (IS_HASWELL(dev))
2525                 return 4;
2526         else if (INTEL_INFO(dev)->gen >= 6)
2527                 return 3;
2528         else
2529                 return 2;
2530 }
2531
2532 static void intel_print_wm_latency(struct drm_device *dev,
2533                                    const char *name,
2534                                    const uint16_t wm[5])
2535 {
2536         int level, max_level = ilk_wm_max_level(dev);
2537
2538         for (level = 0; level <= max_level; level++) {
2539                 unsigned int latency = wm[level];
2540
2541                 if (latency == 0) {
2542                         DRM_ERROR("%s WM%d latency not provided\n",
2543                                   name, level);
2544                         continue;
2545                 }
2546
2547                 /* WM1+ latency values in 0.5us units */
2548                 if (level > 0)
2549                         latency *= 5;
2550
2551                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2552                               name, level, wm[level],
2553                               latency / 10, latency % 10);
2554         }
2555 }
2556
2557 static void intel_setup_wm_latency(struct drm_device *dev)
2558 {
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560
2561         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2562
2563         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2564                sizeof(dev_priv->wm.pri_latency));
2565         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2566                sizeof(dev_priv->wm.pri_latency));
2567
2568         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2569         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2570
2571         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2572         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2573         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2574 }
2575
2576 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2577                                       struct hsw_pipe_wm_parameters *p,
2578                                       struct intel_wm_config *config)
2579 {
2580         struct drm_device *dev = crtc->dev;
2581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2582         enum pipe pipe = intel_crtc->pipe;
2583         struct drm_plane *plane;
2584
2585         p->active = intel_crtc_active(crtc);
2586         if (p->active) {
2587                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2588                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2589                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2590                 p->cur.bytes_per_pixel = 4;
2591                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2592                 p->cur.horiz_pixels = 64;
2593                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2594                 p->pri.enabled = true;
2595                 p->cur.enabled = true;
2596         }
2597
2598         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2599                 config->num_pipes_active += intel_crtc_active(crtc);
2600
2601         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2602                 struct intel_plane *intel_plane = to_intel_plane(plane);
2603
2604                 if (intel_plane->pipe == pipe)
2605                         p->spr = intel_plane->wm;
2606
2607                 config->sprites_enabled |= intel_plane->wm.enabled;
2608                 config->sprites_scaled |= intel_plane->wm.scaled;
2609         }
2610 }
2611
2612 /* Compute new watermarks for the pipe */
2613 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2614                                   const struct hsw_pipe_wm_parameters *params,
2615                                   struct intel_pipe_wm *pipe_wm)
2616 {
2617         struct drm_device *dev = crtc->dev;
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619         int level, max_level = ilk_wm_max_level(dev);
2620         /* LP0 watermark maximums depend on this pipe alone */
2621         struct intel_wm_config config = {
2622                 .num_pipes_active = 1,
2623                 .sprites_enabled = params->spr.enabled,
2624                 .sprites_scaled = params->spr.scaled,
2625         };
2626         struct hsw_wm_maximums max;
2627
2628         /* LP0 watermarks always use 1/2 DDB partitioning */
2629         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2630
2631         for (level = 0; level <= max_level; level++)
2632                 ilk_compute_wm_level(dev_priv, level, params,
2633                                      &pipe_wm->wm[level]);
2634
2635         pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2636
2637         /* At least LP0 must be valid */
2638         return ilk_check_wm(0, &max, &pipe_wm->wm[0]);
2639 }
2640
2641 /*
2642  * Merge the watermarks from all active pipes for a specific level.
2643  */
2644 static void ilk_merge_wm_level(struct drm_device *dev,
2645                                int level,
2646                                struct intel_wm_level *ret_wm)
2647 {
2648         const struct intel_crtc *intel_crtc;
2649
2650         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2651                 const struct intel_wm_level *wm =
2652                         &intel_crtc->wm.active.wm[level];
2653
2654                 if (!wm->enable)
2655                         return;
2656
2657                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2658                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2659                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2660                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2661         }
2662
2663         ret_wm->enable = true;
2664 }
2665
2666 /*
2667  * Merge all low power watermarks for all active pipes.
2668  */
2669 static void ilk_wm_merge(struct drm_device *dev,
2670                          const struct hsw_wm_maximums *max,
2671                          struct intel_pipe_wm *merged)
2672 {
2673         int level, max_level = ilk_wm_max_level(dev);
2674
2675         merged->fbc_wm_enabled = true;
2676
2677         /* merge each WM1+ level */
2678         for (level = 1; level <= max_level; level++) {
2679                 struct intel_wm_level *wm = &merged->wm[level];
2680
2681                 ilk_merge_wm_level(dev, level, wm);
2682
2683                 if (!ilk_check_wm(level, max, wm))
2684                         break;
2685
2686                 /*
2687                  * The spec says it is preferred to disable
2688                  * FBC WMs instead of disabling a WM level.
2689                  */
2690                 if (wm->fbc_val > max->fbc) {
2691                         merged->fbc_wm_enabled = false;
2692                         wm->fbc_val = 0;
2693                 }
2694         }
2695 }
2696
2697 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2698 {
2699         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2700         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2701 }
2702
2703 static void hsw_compute_wm_results(struct drm_device *dev,
2704                                    const struct intel_pipe_wm *merged,
2705                                    enum intel_ddb_partitioning partitioning,
2706                                    struct hsw_wm_values *results)
2707 {
2708         struct intel_crtc *intel_crtc;
2709         int level, wm_lp;
2710
2711         results->enable_fbc_wm = merged->fbc_wm_enabled;
2712         results->partitioning = partitioning;
2713
2714         /* LP1+ register values */
2715         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2716                 const struct intel_wm_level *r;
2717
2718                 level = ilk_wm_lp_to_level(wm_lp, merged);
2719
2720                 r = &merged->wm[level];
2721                 if (!r->enable)
2722                         break;
2723
2724                 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2725                                                           r->fbc_val,
2726                                                           r->pri_val,
2727                                                           r->cur_val);
2728                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2729         }
2730
2731         /* LP0 register values */
2732         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2733                 enum pipe pipe = intel_crtc->pipe;
2734                 const struct intel_wm_level *r =
2735                         &intel_crtc->wm.active.wm[0];
2736
2737                 if (WARN_ON(!r->enable))
2738                         continue;
2739
2740                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2741
2742                 results->wm_pipe[pipe] =
2743                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2744                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2745                         r->cur_val;
2746         }
2747 }
2748
2749 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2750  * case both are at the same level. Prefer r1 in case they're the same. */
2751 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2752                                                   struct intel_pipe_wm *r1,
2753                                                   struct intel_pipe_wm *r2)
2754 {
2755         int level, max_level = ilk_wm_max_level(dev);
2756         int level1 = 0, level2 = 0;
2757
2758         for (level = 1; level <= max_level; level++) {
2759                 if (r1->wm[level].enable)
2760                         level1 = level;
2761                 if (r2->wm[level].enable)
2762                         level2 = level;
2763         }
2764
2765         if (level1 == level2) {
2766                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2767                         return r2;
2768                 else
2769                         return r1;
2770         } else if (level1 > level2) {
2771                 return r1;
2772         } else {
2773                 return r2;
2774         }
2775 }
2776
2777 /* dirty bits used to track which watermarks need changes */
2778 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2779 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2780 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2781 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2782 #define WM_DIRTY_FBC (1 << 24)
2783 #define WM_DIRTY_DDB (1 << 25)
2784
2785 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2786                                          const struct hsw_wm_values *old,
2787                                          const struct hsw_wm_values *new)
2788 {
2789         unsigned int dirty = 0;
2790         enum pipe pipe;
2791         int wm_lp;
2792
2793         for_each_pipe(pipe) {
2794                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2795                         dirty |= WM_DIRTY_LINETIME(pipe);
2796                         /* Must disable LP1+ watermarks too */
2797                         dirty |= WM_DIRTY_LP_ALL;
2798                 }
2799
2800                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2801                         dirty |= WM_DIRTY_PIPE(pipe);
2802                         /* Must disable LP1+ watermarks too */
2803                         dirty |= WM_DIRTY_LP_ALL;
2804                 }
2805         }
2806
2807         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2808                 dirty |= WM_DIRTY_FBC;
2809                 /* Must disable LP1+ watermarks too */
2810                 dirty |= WM_DIRTY_LP_ALL;
2811         }
2812
2813         if (old->partitioning != new->partitioning) {
2814                 dirty |= WM_DIRTY_DDB;
2815                 /* Must disable LP1+ watermarks too */
2816                 dirty |= WM_DIRTY_LP_ALL;
2817         }
2818
2819         /* LP1+ watermarks already deemed dirty, no need to continue */
2820         if (dirty & WM_DIRTY_LP_ALL)
2821                 return dirty;
2822
2823         /* Find the lowest numbered LP1+ watermark in need of an update... */
2824         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2825                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2826                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2827                         break;
2828         }
2829
2830         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2831         for (; wm_lp <= 3; wm_lp++)
2832                 dirty |= WM_DIRTY_LP(wm_lp);
2833
2834         return dirty;
2835 }
2836
2837 /*
2838  * The spec says we shouldn't write when we don't need, because every write
2839  * causes WMs to be re-evaluated, expending some power.
2840  */
2841 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2842                                 struct hsw_wm_values *results)
2843 {
2844         struct hsw_wm_values *previous = &dev_priv->wm.hw;
2845         unsigned int dirty;
2846         uint32_t val;
2847
2848         dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2849         if (!dirty)
2850                 return;
2851
2852         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2853                 I915_WRITE(WM3_LP_ILK, 0);
2854         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2855                 I915_WRITE(WM2_LP_ILK, 0);
2856         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2857                 I915_WRITE(WM1_LP_ILK, 0);
2858
2859         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2860                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2861         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2862                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2863         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2864                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2865
2866         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2867                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2868         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2869                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2870         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2871                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2872
2873         if (dirty & WM_DIRTY_DDB) {
2874                 val = I915_READ(WM_MISC);
2875                 if (results->partitioning == INTEL_DDB_PART_1_2)
2876                         val &= ~WM_MISC_DATA_PARTITION_5_6;
2877                 else
2878                         val |= WM_MISC_DATA_PARTITION_5_6;
2879                 I915_WRITE(WM_MISC, val);
2880         }
2881
2882         if (dirty & WM_DIRTY_FBC) {
2883                 val = I915_READ(DISP_ARB_CTL);
2884                 if (results->enable_fbc_wm)
2885                         val &= ~DISP_FBC_WM_DIS;
2886                 else
2887                         val |= DISP_FBC_WM_DIS;
2888                 I915_WRITE(DISP_ARB_CTL, val);
2889         }
2890
2891         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2892                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2893         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2894                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2895         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2896                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2897
2898         if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2899                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2900         if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2901                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2902         if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2903                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2904
2905         dev_priv->wm.hw = *results;
2906 }
2907
2908 static void haswell_update_wm(struct drm_crtc *crtc)
2909 {
2910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2911         struct drm_device *dev = crtc->dev;
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         struct hsw_wm_maximums max;
2914         struct hsw_pipe_wm_parameters params = {};
2915         struct hsw_wm_values results = {};
2916         enum intel_ddb_partitioning partitioning;
2917         struct intel_pipe_wm pipe_wm = {};
2918         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2919         struct intel_wm_config config = {};
2920
2921         hsw_compute_wm_parameters(crtc, &params, &config);
2922
2923         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2924
2925         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2926                 return;
2927
2928         intel_crtc->wm.active = pipe_wm;
2929
2930         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2931         ilk_wm_merge(dev, &max, &lp_wm_1_2);
2932
2933         /* 5/6 split only in single pipe config on IVB+ */
2934         if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active == 1) {
2935                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2936                 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2937
2938                 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2939         } else {
2940                 best_lp_wm = &lp_wm_1_2;
2941         }
2942
2943         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2944                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2945
2946         hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2947
2948         hsw_write_wm_values(dev_priv, &results);
2949 }
2950
2951 static void haswell_update_sprite_wm(struct drm_plane *plane,
2952                                      struct drm_crtc *crtc,
2953                                      uint32_t sprite_width, int pixel_size,
2954                                      bool enabled, bool scaled)
2955 {
2956         struct intel_plane *intel_plane = to_intel_plane(plane);
2957
2958         intel_plane->wm.enabled = enabled;
2959         intel_plane->wm.scaled = scaled;
2960         intel_plane->wm.horiz_pixels = sprite_width;
2961         intel_plane->wm.bytes_per_pixel = pixel_size;
2962
2963         haswell_update_wm(crtc);
2964 }
2965
2966 static bool
2967 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2968                               uint32_t sprite_width, int pixel_size,
2969                               const struct intel_watermark_params *display,
2970                               int display_latency_ns, int *sprite_wm)
2971 {
2972         struct drm_crtc *crtc;
2973         int clock;
2974         int entries, tlb_miss;
2975
2976         crtc = intel_get_crtc_for_plane(dev, plane);
2977         if (!intel_crtc_active(crtc)) {
2978                 *sprite_wm = display->guard_size;
2979                 return false;
2980         }
2981
2982         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2983
2984         /* Use the small buffer method to calculate the sprite watermark */
2985         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2986         tlb_miss = display->fifo_size*display->cacheline_size -
2987                 sprite_width * 8;
2988         if (tlb_miss > 0)
2989                 entries += tlb_miss;
2990         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2991         *sprite_wm = entries + display->guard_size;
2992         if (*sprite_wm > (int)display->max_wm)
2993                 *sprite_wm = display->max_wm;
2994
2995         return true;
2996 }
2997
2998 static bool
2999 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3000                                 uint32_t sprite_width, int pixel_size,
3001                                 const struct intel_watermark_params *display,
3002                                 int latency_ns, int *sprite_wm)
3003 {
3004         struct drm_crtc *crtc;
3005         unsigned long line_time_us;
3006         int clock;
3007         int line_count, line_size;
3008         int small, large;
3009         int entries;
3010
3011         if (!latency_ns) {
3012                 *sprite_wm = 0;
3013                 return false;
3014         }
3015
3016         crtc = intel_get_crtc_for_plane(dev, plane);
3017         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3018         if (!clock) {
3019                 *sprite_wm = 0;
3020                 return false;
3021         }
3022
3023         line_time_us = (sprite_width * 1000) / clock;
3024         if (!line_time_us) {
3025                 *sprite_wm = 0;
3026                 return false;
3027         }
3028
3029         line_count = (latency_ns / line_time_us + 1000) / 1000;
3030         line_size = sprite_width * pixel_size;
3031
3032         /* Use the minimum of the small and large buffer method for primary */
3033         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3034         large = line_count * line_size;
3035
3036         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3037         *sprite_wm = entries + display->guard_size;
3038
3039         return *sprite_wm > 0x3ff ? false : true;
3040 }
3041
3042 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3043                                          struct drm_crtc *crtc,
3044                                          uint32_t sprite_width, int pixel_size,
3045                                          bool enabled, bool scaled)
3046 {
3047         struct drm_device *dev = plane->dev;
3048         struct drm_i915_private *dev_priv = dev->dev_private;
3049         int pipe = to_intel_plane(plane)->pipe;
3050         int latency = dev_priv->wm.spr_latency[0] * 100;        /* In unit 0.1us */
3051         u32 val;
3052         int sprite_wm, reg;
3053         int ret;
3054
3055         if (!enabled)
3056                 return;
3057
3058         switch (pipe) {
3059         case 0:
3060                 reg = WM0_PIPEA_ILK;
3061                 break;
3062         case 1:
3063                 reg = WM0_PIPEB_ILK;
3064                 break;
3065         case 2:
3066                 reg = WM0_PIPEC_IVB;
3067                 break;
3068         default:
3069                 return; /* bad pipe */
3070         }
3071
3072         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3073                                             &sandybridge_display_wm_info,
3074                                             latency, &sprite_wm);
3075         if (!ret) {
3076                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3077                               pipe_name(pipe));
3078                 return;
3079         }
3080
3081         val = I915_READ(reg);
3082         val &= ~WM0_PIPE_SPRITE_MASK;
3083         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3084         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3085
3086
3087         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3088                                               pixel_size,
3089                                               &sandybridge_display_srwm_info,
3090                                               dev_priv->wm.spr_latency[1] * 500,
3091                                               &sprite_wm);
3092         if (!ret) {
3093                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3094                               pipe_name(pipe));
3095                 return;
3096         }
3097         I915_WRITE(WM1S_LP_ILK, sprite_wm);
3098
3099         /* Only IVB has two more LP watermarks for sprite */
3100         if (!IS_IVYBRIDGE(dev))
3101                 return;
3102
3103         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3104                                               pixel_size,
3105                                               &sandybridge_display_srwm_info,
3106                                               dev_priv->wm.spr_latency[2] * 500,
3107                                               &sprite_wm);
3108         if (!ret) {
3109                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3110                               pipe_name(pipe));
3111                 return;
3112         }
3113         I915_WRITE(WM2S_LP_IVB, sprite_wm);
3114
3115         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3116                                               pixel_size,
3117                                               &sandybridge_display_srwm_info,
3118                                               dev_priv->wm.spr_latency[3] * 500,
3119                                               &sprite_wm);
3120         if (!ret) {
3121                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3122                               pipe_name(pipe));
3123                 return;
3124         }
3125         I915_WRITE(WM3S_LP_IVB, sprite_wm);
3126 }
3127
3128 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3129 {
3130         struct drm_device *dev = crtc->dev;
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3134         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3135         enum pipe pipe = intel_crtc->pipe;
3136         static const unsigned int wm0_pipe_reg[] = {
3137                 [PIPE_A] = WM0_PIPEA_ILK,
3138                 [PIPE_B] = WM0_PIPEB_ILK,
3139                 [PIPE_C] = WM0_PIPEC_IVB,
3140         };
3141
3142         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3143         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3144
3145         if (intel_crtc_active(crtc)) {
3146                 u32 tmp = hw->wm_pipe[pipe];
3147
3148                 /*
3149                  * For active pipes LP0 watermark is marked as
3150                  * enabled, and LP1+ watermaks as disabled since
3151                  * we can't really reverse compute them in case
3152                  * multiple pipes are active.
3153                  */
3154                 active->wm[0].enable = true;
3155                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3156                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3157                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3158                 active->linetime = hw->wm_linetime[pipe];
3159         } else {
3160                 int level, max_level = ilk_wm_max_level(dev);
3161
3162                 /*
3163                  * For inactive pipes, all watermark levels
3164                  * should be marked as enabled but zeroed,
3165                  * which is what we'd compute them to.
3166                  */
3167                 for (level = 0; level <= max_level; level++)
3168                         active->wm[level].enable = true;
3169         }
3170 }
3171
3172 void ilk_wm_get_hw_state(struct drm_device *dev)
3173 {
3174         struct drm_i915_private *dev_priv = dev->dev_private;
3175         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3176         struct drm_crtc *crtc;
3177
3178         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3179                 ilk_pipe_wm_get_hw_state(crtc);
3180
3181         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3182         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3183         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3184
3185         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3186         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3187         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3188
3189         hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3190                 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3191
3192         hw->enable_fbc_wm =
3193                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3194 }
3195
3196 /**
3197  * intel_update_watermarks - update FIFO watermark values based on current modes
3198  *
3199  * Calculate watermark values for the various WM regs based on current mode
3200  * and plane configuration.
3201  *
3202  * There are several cases to deal with here:
3203  *   - normal (i.e. non-self-refresh)
3204  *   - self-refresh (SR) mode
3205  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3206  *   - lines are small relative to FIFO size (buffer can hold more than 2
3207  *     lines), so need to account for TLB latency
3208  *
3209  *   The normal calculation is:
3210  *     watermark = dotclock * bytes per pixel * latency
3211  *   where latency is platform & configuration dependent (we assume pessimal
3212  *   values here).
3213  *
3214  *   The SR calculation is:
3215  *     watermark = (trunc(latency/line time)+1) * surface width *
3216  *       bytes per pixel
3217  *   where
3218  *     line time = htotal / dotclock
3219  *     surface width = hdisplay for normal plane and 64 for cursor
3220  *   and latency is assumed to be high, as above.
3221  *
3222  * The final value programmed to the register should always be rounded up,
3223  * and include an extra 2 entries to account for clock crossings.
3224  *
3225  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3226  * to set the non-SR watermarks to 8.
3227  */
3228 void intel_update_watermarks(struct drm_crtc *crtc)
3229 {
3230         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3231
3232         if (dev_priv->display.update_wm)
3233                 dev_priv->display.update_wm(crtc);
3234 }
3235
3236 void intel_update_sprite_watermarks(struct drm_plane *plane,
3237                                     struct drm_crtc *crtc,
3238                                     uint32_t sprite_width, int pixel_size,
3239                                     bool enabled, bool scaled)
3240 {
3241         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3242
3243         if (dev_priv->display.update_sprite_wm)
3244                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3245                                                    pixel_size, enabled, scaled);
3246 }
3247
3248 static struct drm_i915_gem_object *
3249 intel_alloc_context_page(struct drm_device *dev)
3250 {
3251         struct drm_i915_gem_object *ctx;
3252         int ret;
3253
3254         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3255
3256         ctx = i915_gem_alloc_object(dev, 4096);
3257         if (!ctx) {
3258                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3259                 return NULL;
3260         }
3261
3262         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3263         if (ret) {
3264                 DRM_ERROR("failed to pin power context: %d\n", ret);
3265                 goto err_unref;
3266         }
3267
3268         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3269         if (ret) {
3270                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3271                 goto err_unpin;
3272         }
3273
3274         return ctx;
3275
3276 err_unpin:
3277         i915_gem_object_unpin(ctx);
3278 err_unref:
3279         drm_gem_object_unreference(&ctx->base);
3280         return NULL;
3281 }
3282
3283 /**
3284  * Lock protecting IPS related data structures
3285  */
3286 DEFINE_SPINLOCK(mchdev_lock);
3287
3288 /* Global for IPS driver to get at the current i915 device. Protected by
3289  * mchdev_lock. */
3290 static struct drm_i915_private *i915_mch_dev;
3291
3292 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3293 {
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295         u16 rgvswctl;
3296
3297         assert_spin_locked(&mchdev_lock);
3298
3299         rgvswctl = I915_READ16(MEMSWCTL);
3300         if (rgvswctl & MEMCTL_CMD_STS) {
3301                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3302                 return false; /* still busy with another command */
3303         }
3304
3305         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3306                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3307         I915_WRITE16(MEMSWCTL, rgvswctl);
3308         POSTING_READ16(MEMSWCTL);
3309
3310         rgvswctl |= MEMCTL_CMD_STS;
3311         I915_WRITE16(MEMSWCTL, rgvswctl);
3312
3313         return true;
3314 }
3315
3316 static void ironlake_enable_drps(struct drm_device *dev)
3317 {
3318         struct drm_i915_private *dev_priv = dev->dev_private;
3319         u32 rgvmodectl = I915_READ(MEMMODECTL);
3320         u8 fmax, fmin, fstart, vstart;
3321
3322         spin_lock_irq(&mchdev_lock);
3323
3324         /* Enable temp reporting */
3325         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3326         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3327
3328         /* 100ms RC evaluation intervals */
3329         I915_WRITE(RCUPEI, 100000);
3330         I915_WRITE(RCDNEI, 100000);
3331
3332         /* Set max/min thresholds to 90ms and 80ms respectively */
3333         I915_WRITE(RCBMAXAVG, 90000);
3334         I915_WRITE(RCBMINAVG, 80000);
3335
3336         I915_WRITE(MEMIHYST, 1);
3337
3338         /* Set up min, max, and cur for interrupt handling */
3339         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3340         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3341         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3342                 MEMMODE_FSTART_SHIFT;
3343
3344         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3345                 PXVFREQ_PX_SHIFT;
3346
3347         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3348         dev_priv->ips.fstart = fstart;
3349
3350         dev_priv->ips.max_delay = fstart;
3351         dev_priv->ips.min_delay = fmin;
3352         dev_priv->ips.cur_delay = fstart;
3353
3354         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3355                          fmax, fmin, fstart);
3356
3357         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3358
3359         /*
3360          * Interrupts will be enabled in ironlake_irq_postinstall
3361          */
3362
3363         I915_WRITE(VIDSTART, vstart);
3364         POSTING_READ(VIDSTART);
3365
3366         rgvmodectl |= MEMMODE_SWMODE_EN;
3367         I915_WRITE(MEMMODECTL, rgvmodectl);
3368
3369         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3370                 DRM_ERROR("stuck trying to change perf mode\n");
3371         mdelay(1);
3372
3373         ironlake_set_drps(dev, fstart);
3374
3375         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3376                 I915_READ(0x112e0);
3377         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3378         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3379         getrawmonotonic(&dev_priv->ips.last_time2);
3380
3381         spin_unlock_irq(&mchdev_lock);
3382 }
3383
3384 static void ironlake_disable_drps(struct drm_device *dev)
3385 {
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         u16 rgvswctl;
3388
3389         spin_lock_irq(&mchdev_lock);
3390
3391         rgvswctl = I915_READ16(MEMSWCTL);
3392
3393         /* Ack interrupts, disable EFC interrupt */
3394         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3395         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3396         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3397         I915_WRITE(DEIIR, DE_PCU_EVENT);
3398         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3399
3400         /* Go back to the starting frequency */
3401         ironlake_set_drps(dev, dev_priv->ips.fstart);
3402         mdelay(1);
3403         rgvswctl |= MEMCTL_CMD_STS;
3404         I915_WRITE(MEMSWCTL, rgvswctl);
3405         mdelay(1);
3406
3407         spin_unlock_irq(&mchdev_lock);
3408 }
3409
3410 /* There's a funny hw issue where the hw returns all 0 when reading from
3411  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3412  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3413  * all limits and the gpu stuck at whatever frequency it is at atm).
3414  */
3415 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3416 {
3417         u32 limits;
3418
3419         limits = 0;
3420
3421         if (*val >= dev_priv->rps.max_delay)
3422                 *val = dev_priv->rps.max_delay;
3423         limits |= dev_priv->rps.max_delay << 24;
3424
3425         /* Only set the down limit when we've reached the lowest level to avoid
3426          * getting more interrupts, otherwise leave this clear. This prevents a
3427          * race in the hw when coming out of rc6: There's a tiny window where
3428          * the hw runs at the minimal clock before selecting the desired
3429          * frequency, if the down threshold expires in that window we will not
3430          * receive a down interrupt. */
3431         if (*val <= dev_priv->rps.min_delay) {
3432                 *val = dev_priv->rps.min_delay;
3433                 limits |= dev_priv->rps.min_delay << 16;
3434         }
3435
3436         return limits;
3437 }
3438
3439 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3440 {
3441         int new_power;
3442
3443         new_power = dev_priv->rps.power;
3444         switch (dev_priv->rps.power) {
3445         case LOW_POWER:
3446                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3447                         new_power = BETWEEN;
3448                 break;
3449
3450         case BETWEEN:
3451                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3452                         new_power = LOW_POWER;
3453                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3454                         new_power = HIGH_POWER;
3455                 break;
3456
3457         case HIGH_POWER:
3458                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3459                         new_power = BETWEEN;
3460                 break;
3461         }
3462         /* Max/min bins are special */
3463         if (val == dev_priv->rps.min_delay)
3464                 new_power = LOW_POWER;
3465         if (val == dev_priv->rps.max_delay)
3466                 new_power = HIGH_POWER;
3467         if (new_power == dev_priv->rps.power)
3468                 return;
3469
3470         /* Note the units here are not exactly 1us, but 1280ns. */
3471         switch (new_power) {
3472         case LOW_POWER:
3473                 /* Upclock if more than 95% busy over 16ms */
3474                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3475                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3476
3477                 /* Downclock if less than 85% busy over 32ms */
3478                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3479                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3480
3481                 I915_WRITE(GEN6_RP_CONTROL,
3482                            GEN6_RP_MEDIA_TURBO |
3483                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3484                            GEN6_RP_MEDIA_IS_GFX |
3485                            GEN6_RP_ENABLE |
3486                            GEN6_RP_UP_BUSY_AVG |
3487                            GEN6_RP_DOWN_IDLE_AVG);
3488                 break;
3489
3490         case BETWEEN:
3491                 /* Upclock if more than 90% busy over 13ms */
3492                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3493                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3494
3495                 /* Downclock if less than 75% busy over 32ms */
3496                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3497                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3498
3499                 I915_WRITE(GEN6_RP_CONTROL,
3500                            GEN6_RP_MEDIA_TURBO |
3501                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3502                            GEN6_RP_MEDIA_IS_GFX |
3503                            GEN6_RP_ENABLE |
3504                            GEN6_RP_UP_BUSY_AVG |
3505                            GEN6_RP_DOWN_IDLE_AVG);
3506                 break;
3507
3508         case HIGH_POWER:
3509                 /* Upclock if more than 85% busy over 10ms */
3510                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3511                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3512
3513                 /* Downclock if less than 60% busy over 32ms */
3514                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3515                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3516
3517                 I915_WRITE(GEN6_RP_CONTROL,
3518                            GEN6_RP_MEDIA_TURBO |
3519                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3520                            GEN6_RP_MEDIA_IS_GFX |
3521                            GEN6_RP_ENABLE |
3522                            GEN6_RP_UP_BUSY_AVG |
3523                            GEN6_RP_DOWN_IDLE_AVG);
3524                 break;
3525         }
3526
3527         dev_priv->rps.power = new_power;
3528         dev_priv->rps.last_adj = 0;
3529 }
3530
3531 void gen6_set_rps(struct drm_device *dev, u8 val)
3532 {
3533         struct drm_i915_private *dev_priv = dev->dev_private;
3534         u32 limits = gen6_rps_limits(dev_priv, &val);
3535
3536         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3537         WARN_ON(val > dev_priv->rps.max_delay);
3538         WARN_ON(val < dev_priv->rps.min_delay);
3539
3540         if (val == dev_priv->rps.cur_delay)
3541                 return;
3542
3543         gen6_set_rps_thresholds(dev_priv, val);
3544
3545         if (IS_HASWELL(dev))
3546                 I915_WRITE(GEN6_RPNSWREQ,
3547                            HSW_FREQUENCY(val));
3548         else
3549                 I915_WRITE(GEN6_RPNSWREQ,
3550                            GEN6_FREQUENCY(val) |
3551                            GEN6_OFFSET(0) |
3552                            GEN6_AGGRESSIVE_TURBO);
3553
3554         /* Make sure we continue to get interrupts
3555          * until we hit the minimum or maximum frequencies.
3556          */
3557         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3558
3559         POSTING_READ(GEN6_RPNSWREQ);
3560
3561         dev_priv->rps.cur_delay = val;
3562
3563         trace_intel_gpu_freq_change(val * 50);
3564 }
3565
3566 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3567 {
3568         mutex_lock(&dev_priv->rps.hw_lock);
3569         if (dev_priv->rps.enabled) {
3570                 if (dev_priv->info->is_valleyview)
3571                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3572                 else
3573                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3574                 dev_priv->rps.last_adj = 0;
3575         }
3576         mutex_unlock(&dev_priv->rps.hw_lock);
3577 }
3578
3579 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3580 {
3581         mutex_lock(&dev_priv->rps.hw_lock);
3582         if (dev_priv->rps.enabled) {
3583                 if (dev_priv->info->is_valleyview)
3584                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3585                 else
3586                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3587                 dev_priv->rps.last_adj = 0;
3588         }
3589         mutex_unlock(&dev_priv->rps.hw_lock);
3590 }
3591
3592 /*
3593  * Wait until the previous freq change has completed,
3594  * or the timeout elapsed, and then update our notion
3595  * of the current GPU frequency.
3596  */
3597 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3598 {
3599         u32 pval;
3600
3601         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3602
3603         if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3604                 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3605
3606         pval >>= 8;
3607
3608         if (pval != dev_priv->rps.cur_delay)
3609                 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3610                                  vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3611                                  dev_priv->rps.cur_delay,
3612                                  vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3613
3614         dev_priv->rps.cur_delay = pval;
3615 }
3616
3617 void valleyview_set_rps(struct drm_device *dev, u8 val)
3618 {
3619         struct drm_i915_private *dev_priv = dev->dev_private;
3620
3621         gen6_rps_limits(dev_priv, &val);
3622
3623         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3624         WARN_ON(val > dev_priv->rps.max_delay);
3625         WARN_ON(val < dev_priv->rps.min_delay);
3626
3627         vlv_update_rps_cur_delay(dev_priv);
3628
3629         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3630                          vlv_gpu_freq(dev_priv->mem_freq,
3631                                       dev_priv->rps.cur_delay),
3632                          dev_priv->rps.cur_delay,
3633                          vlv_gpu_freq(dev_priv->mem_freq, val), val);
3634
3635         if (val == dev_priv->rps.cur_delay)
3636                 return;
3637
3638         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3639
3640         dev_priv->rps.cur_delay = val;
3641
3642         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3643 }
3644
3645 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3646 {
3647         struct drm_i915_private *dev_priv = dev->dev_private;
3648
3649         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3650         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3651         /* Complete PM interrupt masking here doesn't race with the rps work
3652          * item again unmasking PM interrupts because that is using a different
3653          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3654          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3655
3656         spin_lock_irq(&dev_priv->irq_lock);
3657         dev_priv->rps.pm_iir = 0;
3658         spin_unlock_irq(&dev_priv->irq_lock);
3659
3660         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3661 }
3662
3663 static void gen6_disable_rps(struct drm_device *dev)
3664 {
3665         struct drm_i915_private *dev_priv = dev->dev_private;
3666
3667         I915_WRITE(GEN6_RC_CONTROL, 0);
3668         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3669
3670         gen6_disable_rps_interrupts(dev);
3671 }
3672
3673 static void valleyview_disable_rps(struct drm_device *dev)
3674 {
3675         struct drm_i915_private *dev_priv = dev->dev_private;
3676
3677         I915_WRITE(GEN6_RC_CONTROL, 0);
3678
3679         gen6_disable_rps_interrupts(dev);
3680
3681         if (dev_priv->vlv_pctx) {
3682                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3683                 dev_priv->vlv_pctx = NULL;
3684         }
3685 }
3686
3687 int intel_enable_rc6(const struct drm_device *dev)
3688 {
3689         /* No RC6 before Ironlake */
3690         if (INTEL_INFO(dev)->gen < 5)
3691                 return 0;
3692
3693         /* Respect the kernel parameter if it is set */
3694         if (i915_enable_rc6 >= 0)
3695                 return i915_enable_rc6;
3696
3697         /* Disable RC6 on Ironlake */
3698         if (INTEL_INFO(dev)->gen == 5)
3699                 return 0;
3700
3701         if (IS_HASWELL(dev)) {
3702                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3703                 return INTEL_RC6_ENABLE;
3704         }
3705
3706         /* snb/ivb have more than one rc6 state. */
3707         if (INTEL_INFO(dev)->gen == 6) {
3708                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3709                 return INTEL_RC6_ENABLE;
3710         }
3711
3712         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3713         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3714 }
3715
3716 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3717 {
3718         struct drm_i915_private *dev_priv = dev->dev_private;
3719         u32 enabled_intrs;
3720
3721         spin_lock_irq(&dev_priv->irq_lock);
3722         WARN_ON(dev_priv->rps.pm_iir);
3723         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3724         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3725         spin_unlock_irq(&dev_priv->irq_lock);
3726
3727         /* only unmask PM interrupts we need. Mask all others. */
3728         enabled_intrs = GEN6_PM_RPS_EVENTS;
3729
3730         /* IVB and SNB hard hangs on looping batchbuffer
3731          * if GEN6_PM_UP_EI_EXPIRED is masked.
3732          */
3733         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3734                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3735
3736         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3737 }
3738
3739 static void gen6_enable_rps(struct drm_device *dev)
3740 {
3741         struct drm_i915_private *dev_priv = dev->dev_private;
3742         struct intel_ring_buffer *ring;
3743         u32 rp_state_cap;
3744         u32 gt_perf_status;
3745         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3746         u32 gtfifodbg;
3747         int rc6_mode;
3748         int i, ret;
3749
3750         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3751
3752         /* Here begins a magic sequence of register writes to enable
3753          * auto-downclocking.
3754          *
3755          * Perhaps there might be some value in exposing these to
3756          * userspace...
3757          */
3758         I915_WRITE(GEN6_RC_STATE, 0);
3759
3760         /* Clear the DBG now so we don't confuse earlier errors */
3761         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3762                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3763                 I915_WRITE(GTFIFODBG, gtfifodbg);
3764         }
3765
3766         gen6_gt_force_wake_get(dev_priv);
3767
3768         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3769         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3770
3771         /* In units of 50MHz */
3772         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3773         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3774         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3775         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3776         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3777         dev_priv->rps.cur_delay = 0;
3778
3779         /* disable the counters and set deterministic thresholds */
3780         I915_WRITE(GEN6_RC_CONTROL, 0);
3781
3782         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3783         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3784         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3785         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3786         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3787
3788         for_each_ring(ring, dev_priv, i)
3789                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3790
3791         I915_WRITE(GEN6_RC_SLEEP, 0);
3792         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3793         if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3794                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3795         else
3796                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3797         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3798         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3799
3800         /* Check if we are enabling RC6 */
3801         rc6_mode = intel_enable_rc6(dev_priv->dev);
3802         if (rc6_mode & INTEL_RC6_ENABLE)
3803                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3804
3805         /* We don't use those on Haswell */
3806         if (!IS_HASWELL(dev)) {
3807                 if (rc6_mode & INTEL_RC6p_ENABLE)
3808                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3809
3810                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3811                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3812         }
3813
3814         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3815                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3816                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3817                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3818
3819         I915_WRITE(GEN6_RC_CONTROL,
3820                    rc6_mask |
3821                    GEN6_RC_CTL_EI_MODE(1) |
3822                    GEN6_RC_CTL_HW_ENABLE);
3823
3824         /* Power down if completely idle for over 50ms */
3825         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3826         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3827
3828         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3829         if (!ret) {
3830                 pcu_mbox = 0;
3831                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3832                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3833                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3834                                          (dev_priv->rps.max_delay & 0xff) * 50,
3835                                          (pcu_mbox & 0xff) * 50);
3836                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3837                 }
3838         } else {
3839                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3840         }
3841
3842         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3843         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3844
3845         gen6_enable_rps_interrupts(dev);
3846
3847         rc6vids = 0;
3848         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3849         if (IS_GEN6(dev) && ret) {
3850                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3851         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3852                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3853                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3854                 rc6vids &= 0xffff00;
3855                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3856                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3857                 if (ret)
3858                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3859         }
3860
3861         gen6_gt_force_wake_put(dev_priv);
3862 }
3863
3864 void gen6_update_ring_freq(struct drm_device *dev)
3865 {
3866         struct drm_i915_private *dev_priv = dev->dev_private;
3867         int min_freq = 15;
3868         unsigned int gpu_freq;
3869         unsigned int max_ia_freq, min_ring_freq;
3870         int scaling_factor = 180;
3871         struct cpufreq_policy *policy;
3872
3873         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3874
3875         policy = cpufreq_cpu_get(0);
3876         if (policy) {
3877                 max_ia_freq = policy->cpuinfo.max_freq;
3878                 cpufreq_cpu_put(policy);
3879         } else {
3880                 /*
3881                  * Default to measured freq if none found, PCU will ensure we
3882                  * don't go over
3883                  */
3884                 max_ia_freq = tsc_khz;
3885         }
3886
3887         /* Convert from kHz to MHz */
3888         max_ia_freq /= 1000;
3889
3890         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3891         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3892         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3893
3894         /*
3895          * For each potential GPU frequency, load a ring frequency we'd like
3896          * to use for memory access.  We do this by specifying the IA frequency
3897          * the PCU should use as a reference to determine the ring frequency.
3898          */
3899         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3900              gpu_freq--) {
3901                 int diff = dev_priv->rps.max_delay - gpu_freq;
3902                 unsigned int ia_freq = 0, ring_freq = 0;
3903
3904                 if (IS_HASWELL(dev)) {
3905                         ring_freq = mult_frac(gpu_freq, 5, 4);
3906                         ring_freq = max(min_ring_freq, ring_freq);
3907                         /* leave ia_freq as the default, chosen by cpufreq */
3908                 } else {
3909                         /* On older processors, there is no separate ring
3910                          * clock domain, so in order to boost the bandwidth
3911                          * of the ring, we need to upclock the CPU (ia_freq).
3912                          *
3913                          * For GPU frequencies less than 750MHz,
3914                          * just use the lowest ring freq.
3915                          */
3916                         if (gpu_freq < min_freq)
3917                                 ia_freq = 800;
3918                         else
3919                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3920                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3921                 }
3922
3923                 sandybridge_pcode_write(dev_priv,
3924                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3925                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3926                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3927                                         gpu_freq);
3928         }
3929 }
3930
3931 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3932 {
3933         u32 val, rp0;
3934
3935         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3936
3937         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3938         /* Clamp to max */
3939         rp0 = min_t(u32, rp0, 0xea);
3940
3941         return rp0;
3942 }
3943
3944 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3945 {
3946         u32 val, rpe;
3947
3948         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3949         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3950         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3951         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3952
3953         return rpe;
3954 }
3955
3956 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3957 {
3958         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3959 }
3960
3961 static void valleyview_setup_pctx(struct drm_device *dev)
3962 {
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964         struct drm_i915_gem_object *pctx;
3965         unsigned long pctx_paddr;
3966         u32 pcbr;
3967         int pctx_size = 24*1024;
3968
3969         pcbr = I915_READ(VLV_PCBR);
3970         if (pcbr) {
3971                 /* BIOS set it up already, grab the pre-alloc'd space */
3972                 int pcbr_offset;
3973
3974                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3975                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3976                                                                       pcbr_offset,
3977                                                                       I915_GTT_OFFSET_NONE,
3978                                                                       pctx_size);
3979                 goto out;
3980         }
3981
3982         /*
3983          * From the Gunit register HAS:
3984          * The Gfx driver is expected to program this register and ensure
3985          * proper allocation within Gfx stolen memory.  For example, this
3986          * register should be programmed such than the PCBR range does not
3987          * overlap with other ranges, such as the frame buffer, protected
3988          * memory, or any other relevant ranges.
3989          */
3990         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3991         if (!pctx) {
3992                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3993                 return;
3994         }
3995
3996         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3997         I915_WRITE(VLV_PCBR, pctx_paddr);
3998
3999 out:
4000         dev_priv->vlv_pctx = pctx;
4001 }
4002
4003 static void valleyview_enable_rps(struct drm_device *dev)
4004 {
4005         struct drm_i915_private *dev_priv = dev->dev_private;
4006         struct intel_ring_buffer *ring;
4007         u32 gtfifodbg, val, rc6_mode = 0;
4008         int i;
4009
4010         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4011
4012         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4013                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4014                                  gtfifodbg);
4015                 I915_WRITE(GTFIFODBG, gtfifodbg);
4016         }
4017
4018         valleyview_setup_pctx(dev);
4019
4020         gen6_gt_force_wake_get(dev_priv);
4021
4022         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4023         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4024         I915_WRITE(GEN6_RP_UP_EI, 66000);
4025         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4026
4027         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4028
4029         I915_WRITE(GEN6_RP_CONTROL,
4030                    GEN6_RP_MEDIA_TURBO |
4031                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4032                    GEN6_RP_MEDIA_IS_GFX |
4033                    GEN6_RP_ENABLE |
4034                    GEN6_RP_UP_BUSY_AVG |
4035                    GEN6_RP_DOWN_IDLE_CONT);
4036
4037         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4038         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4039         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4040
4041         for_each_ring(ring, dev_priv, i)
4042                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4043
4044         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
4045
4046         /* allows RC6 residency counter to work */
4047         I915_WRITE(VLV_COUNTER_CONTROL,
4048                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4049                                       VLV_MEDIA_RC6_COUNT_EN |
4050                                       VLV_RENDER_RC6_COUNT_EN));
4051         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4052                 rc6_mode = GEN7_RC_CTL_TO_MODE;
4053         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4054
4055         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4056         switch ((val >> 6) & 3) {
4057         case 0:
4058         case 1:
4059                 dev_priv->mem_freq = 800;
4060                 break;
4061         case 2:
4062                 dev_priv->mem_freq = 1066;
4063                 break;
4064         case 3:
4065                 dev_priv->mem_freq = 1333;
4066                 break;
4067         }
4068         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4069
4070         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4071         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4072
4073         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4074         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4075                          vlv_gpu_freq(dev_priv->mem_freq,
4076                                       dev_priv->rps.cur_delay),
4077                          dev_priv->rps.cur_delay);
4078
4079         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4080         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4081         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4082                          vlv_gpu_freq(dev_priv->mem_freq,
4083                                       dev_priv->rps.max_delay),
4084                          dev_priv->rps.max_delay);
4085
4086         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4087         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4088                          vlv_gpu_freq(dev_priv->mem_freq,
4089                                       dev_priv->rps.rpe_delay),
4090                          dev_priv->rps.rpe_delay);
4091
4092         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4093         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4094                          vlv_gpu_freq(dev_priv->mem_freq,
4095                                       dev_priv->rps.min_delay),
4096                          dev_priv->rps.min_delay);
4097
4098         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4099                          vlv_gpu_freq(dev_priv->mem_freq,
4100                                       dev_priv->rps.rpe_delay),
4101                          dev_priv->rps.rpe_delay);
4102
4103         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4104
4105         gen6_enable_rps_interrupts(dev);
4106
4107         gen6_gt_force_wake_put(dev_priv);
4108 }
4109
4110 void ironlake_teardown_rc6(struct drm_device *dev)
4111 {
4112         struct drm_i915_private *dev_priv = dev->dev_private;
4113
4114         if (dev_priv->ips.renderctx) {
4115                 i915_gem_object_unpin(dev_priv->ips.renderctx);
4116                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4117                 dev_priv->ips.renderctx = NULL;
4118         }
4119
4120         if (dev_priv->ips.pwrctx) {
4121                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4122                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4123                 dev_priv->ips.pwrctx = NULL;
4124         }
4125 }
4126
4127 static void ironlake_disable_rc6(struct drm_device *dev)
4128 {
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130
4131         if (I915_READ(PWRCTXA)) {
4132                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4133                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4134                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4135                          50);
4136
4137                 I915_WRITE(PWRCTXA, 0);
4138                 POSTING_READ(PWRCTXA);
4139
4140                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4141                 POSTING_READ(RSTDBYCTL);
4142         }
4143 }
4144
4145 static int ironlake_setup_rc6(struct drm_device *dev)
4146 {
4147         struct drm_i915_private *dev_priv = dev->dev_private;
4148
4149         if (dev_priv->ips.renderctx == NULL)
4150                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4151         if (!dev_priv->ips.renderctx)
4152                 return -ENOMEM;
4153
4154         if (dev_priv->ips.pwrctx == NULL)
4155                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4156         if (!dev_priv->ips.pwrctx) {
4157                 ironlake_teardown_rc6(dev);
4158                 return -ENOMEM;
4159         }
4160
4161         return 0;
4162 }
4163
4164 static void ironlake_enable_rc6(struct drm_device *dev)
4165 {
4166         struct drm_i915_private *dev_priv = dev->dev_private;
4167         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4168         bool was_interruptible;
4169         int ret;
4170
4171         /* rc6 disabled by default due to repeated reports of hanging during
4172          * boot and resume.
4173          */
4174         if (!intel_enable_rc6(dev))
4175                 return;
4176
4177         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4178
4179         ret = ironlake_setup_rc6(dev);
4180         if (ret)
4181                 return;
4182
4183         was_interruptible = dev_priv->mm.interruptible;
4184         dev_priv->mm.interruptible = false;
4185
4186         /*
4187          * GPU can automatically power down the render unit if given a page
4188          * to save state.
4189          */
4190         ret = intel_ring_begin(ring, 6);
4191         if (ret) {
4192                 ironlake_teardown_rc6(dev);
4193                 dev_priv->mm.interruptible = was_interruptible;
4194                 return;
4195         }
4196
4197         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4198         intel_ring_emit(ring, MI_SET_CONTEXT);
4199         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4200                         MI_MM_SPACE_GTT |
4201                         MI_SAVE_EXT_STATE_EN |
4202                         MI_RESTORE_EXT_STATE_EN |
4203                         MI_RESTORE_INHIBIT);
4204         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4205         intel_ring_emit(ring, MI_NOOP);
4206         intel_ring_emit(ring, MI_FLUSH);
4207         intel_ring_advance(ring);
4208
4209         /*
4210          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4211          * does an implicit flush, combined with MI_FLUSH above, it should be
4212          * safe to assume that renderctx is valid
4213          */
4214         ret = intel_ring_idle(ring);
4215         dev_priv->mm.interruptible = was_interruptible;
4216         if (ret) {
4217                 DRM_ERROR("failed to enable ironlake power savings\n");
4218                 ironlake_teardown_rc6(dev);
4219                 return;
4220         }
4221
4222         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4223         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4224 }
4225
4226 static unsigned long intel_pxfreq(u32 vidfreq)
4227 {
4228         unsigned long freq;
4229         int div = (vidfreq & 0x3f0000) >> 16;
4230         int post = (vidfreq & 0x3000) >> 12;
4231         int pre = (vidfreq & 0x7);
4232
4233         if (!pre)
4234                 return 0;
4235
4236         freq = ((div * 133333) / ((1<<post) * pre));
4237
4238         return freq;
4239 }
4240
4241 static const struct cparams {
4242         u16 i;
4243         u16 t;
4244         u16 m;
4245         u16 c;
4246 } cparams[] = {
4247         { 1, 1333, 301, 28664 },
4248         { 1, 1066, 294, 24460 },
4249         { 1, 800, 294, 25192 },
4250         { 0, 1333, 276, 27605 },
4251         { 0, 1066, 276, 27605 },
4252         { 0, 800, 231, 23784 },
4253 };
4254
4255 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4256 {
4257         u64 total_count, diff, ret;
4258         u32 count1, count2, count3, m = 0, c = 0;
4259         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4260         int i;
4261
4262         assert_spin_locked(&mchdev_lock);
4263
4264         diff1 = now - dev_priv->ips.last_time1;
4265
4266         /* Prevent division-by-zero if we are asking too fast.
4267          * Also, we don't get interesting results if we are polling
4268          * faster than once in 10ms, so just return the saved value
4269          * in such cases.
4270          */
4271         if (diff1 <= 10)
4272                 return dev_priv->ips.chipset_power;
4273
4274         count1 = I915_READ(DMIEC);
4275         count2 = I915_READ(DDREC);
4276         count3 = I915_READ(CSIEC);
4277
4278         total_count = count1 + count2 + count3;
4279
4280         /* FIXME: handle per-counter overflow */
4281         if (total_count < dev_priv->ips.last_count1) {
4282                 diff = ~0UL - dev_priv->ips.last_count1;
4283                 diff += total_count;
4284         } else {
4285                 diff = total_count - dev_priv->ips.last_count1;
4286         }
4287
4288         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4289                 if (cparams[i].i == dev_priv->ips.c_m &&
4290                     cparams[i].t == dev_priv->ips.r_t) {
4291                         m = cparams[i].m;
4292                         c = cparams[i].c;
4293                         break;
4294                 }
4295         }
4296
4297         diff = div_u64(diff, diff1);
4298         ret = ((m * diff) + c);
4299         ret = div_u64(ret, 10);
4300
4301         dev_priv->ips.last_count1 = total_count;
4302         dev_priv->ips.last_time1 = now;
4303
4304         dev_priv->ips.chipset_power = ret;
4305
4306         return ret;
4307 }
4308
4309 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4310 {
4311         unsigned long val;
4312
4313         if (dev_priv->info->gen != 5)
4314                 return 0;
4315
4316         spin_lock_irq(&mchdev_lock);
4317
4318         val = __i915_chipset_val(dev_priv);
4319
4320         spin_unlock_irq(&mchdev_lock);
4321
4322         return val;
4323 }
4324
4325 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4326 {
4327         unsigned long m, x, b;
4328         u32 tsfs;
4329
4330         tsfs = I915_READ(TSFS);
4331
4332         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4333         x = I915_READ8(TR1);
4334
4335         b = tsfs & TSFS_INTR_MASK;
4336
4337         return ((m * x) / 127) - b;
4338 }
4339
4340 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4341 {
4342         static const struct v_table {
4343                 u16 vd; /* in .1 mil */
4344                 u16 vm; /* in .1 mil */
4345         } v_table[] = {
4346                 { 0, 0, },
4347                 { 375, 0, },
4348                 { 500, 0, },
4349                 { 625, 0, },
4350                 { 750, 0, },
4351                 { 875, 0, },
4352                 { 1000, 0, },
4353                 { 1125, 0, },
4354                 { 4125, 3000, },
4355                 { 4125, 3000, },
4356                 { 4125, 3000, },
4357                 { 4125, 3000, },
4358                 { 4125, 3000, },
4359                 { 4125, 3000, },
4360                 { 4125, 3000, },
4361                 { 4125, 3000, },
4362                 { 4125, 3000, },
4363                 { 4125, 3000, },
4364                 { 4125, 3000, },
4365                 { 4125, 3000, },
4366                 { 4125, 3000, },
4367                 { 4125, 3000, },
4368                 { 4125, 3000, },
4369                 { 4125, 3000, },
4370                 { 4125, 3000, },
4371                 { 4125, 3000, },
4372                 { 4125, 3000, },
4373                 { 4125, 3000, },
4374                 { 4125, 3000, },
4375                 { 4125, 3000, },
4376                 { 4125, 3000, },
4377                 { 4125, 3000, },
4378                 { 4250, 3125, },
4379                 { 4375, 3250, },
4380                 { 4500, 3375, },
4381                 { 4625, 3500, },
4382                 { 4750, 3625, },
4383                 { 4875, 3750, },
4384                 { 5000, 3875, },
4385                 { 5125, 4000, },
4386                 { 5250, 4125, },
4387                 { 5375, 4250, },
4388                 { 5500, 4375, },
4389                 { 5625, 4500, },
4390                 { 5750, 4625, },
4391                 { 5875, 4750, },
4392                 { 6000, 4875, },
4393                 { 6125, 5000, },
4394                 { 6250, 5125, },
4395                 { 6375, 5250, },
4396                 { 6500, 5375, },
4397                 { 6625, 5500, },
4398                 { 6750, 5625, },
4399                 { 6875, 5750, },
4400                 { 7000, 5875, },
4401                 { 7125, 6000, },
4402                 { 7250, 6125, },
4403                 { 7375, 6250, },
4404                 { 7500, 6375, },
4405                 { 7625, 6500, },
4406                 { 7750, 6625, },
4407                 { 7875, 6750, },
4408                 { 8000, 6875, },
4409                 { 8125, 7000, },
4410                 { 8250, 7125, },
4411                 { 8375, 7250, },
4412                 { 8500, 7375, },
4413                 { 8625, 7500, },
4414                 { 8750, 7625, },
4415                 { 8875, 7750, },
4416                 { 9000, 7875, },
4417                 { 9125, 8000, },
4418                 { 9250, 8125, },
4419                 { 9375, 8250, },
4420                 { 9500, 8375, },
4421                 { 9625, 8500, },
4422                 { 9750, 8625, },
4423                 { 9875, 8750, },
4424                 { 10000, 8875, },
4425                 { 10125, 9000, },
4426                 { 10250, 9125, },
4427                 { 10375, 9250, },
4428                 { 10500, 9375, },
4429                 { 10625, 9500, },
4430                 { 10750, 9625, },
4431                 { 10875, 9750, },
4432                 { 11000, 9875, },
4433                 { 11125, 10000, },
4434                 { 11250, 10125, },
4435                 { 11375, 10250, },
4436                 { 11500, 10375, },
4437                 { 11625, 10500, },
4438                 { 11750, 10625, },
4439                 { 11875, 10750, },
4440                 { 12000, 10875, },
4441                 { 12125, 11000, },
4442                 { 12250, 11125, },
4443                 { 12375, 11250, },
4444                 { 12500, 11375, },
4445                 { 12625, 11500, },
4446                 { 12750, 11625, },
4447                 { 12875, 11750, },
4448                 { 13000, 11875, },
4449                 { 13125, 12000, },
4450                 { 13250, 12125, },
4451                 { 13375, 12250, },
4452                 { 13500, 12375, },
4453                 { 13625, 12500, },
4454                 { 13750, 12625, },
4455                 { 13875, 12750, },
4456                 { 14000, 12875, },
4457                 { 14125, 13000, },
4458                 { 14250, 13125, },
4459                 { 14375, 13250, },
4460                 { 14500, 13375, },
4461                 { 14625, 13500, },
4462                 { 14750, 13625, },
4463                 { 14875, 13750, },
4464                 { 15000, 13875, },
4465                 { 15125, 14000, },
4466                 { 15250, 14125, },
4467                 { 15375, 14250, },
4468                 { 15500, 14375, },
4469                 { 15625, 14500, },
4470                 { 15750, 14625, },
4471                 { 15875, 14750, },
4472                 { 16000, 14875, },
4473                 { 16125, 15000, },
4474         };
4475         if (dev_priv->info->is_mobile)
4476                 return v_table[pxvid].vm;
4477         else
4478                 return v_table[pxvid].vd;
4479 }
4480
4481 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4482 {
4483         struct timespec now, diff1;
4484         u64 diff;
4485         unsigned long diffms;
4486         u32 count;
4487
4488         assert_spin_locked(&mchdev_lock);
4489
4490         getrawmonotonic(&now);
4491         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4492
4493         /* Don't divide by 0 */
4494         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4495         if (!diffms)
4496                 return;
4497
4498         count = I915_READ(GFXEC);
4499
4500         if (count < dev_priv->ips.last_count2) {
4501                 diff = ~0UL - dev_priv->ips.last_count2;
4502                 diff += count;
4503         } else {
4504                 diff = count - dev_priv->ips.last_count2;
4505         }
4506
4507         dev_priv->ips.last_count2 = count;
4508         dev_priv->ips.last_time2 = now;
4509
4510         /* More magic constants... */
4511         diff = diff * 1181;
4512         diff = div_u64(diff, diffms * 10);
4513         dev_priv->ips.gfx_power = diff;
4514 }
4515
4516 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4517 {
4518         if (dev_priv->info->gen != 5)
4519                 return;
4520
4521         spin_lock_irq(&mchdev_lock);
4522
4523         __i915_update_gfx_val(dev_priv);
4524
4525         spin_unlock_irq(&mchdev_lock);
4526 }
4527
4528 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4529 {
4530         unsigned long t, corr, state1, corr2, state2;
4531         u32 pxvid, ext_v;
4532
4533         assert_spin_locked(&mchdev_lock);
4534
4535         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4536         pxvid = (pxvid >> 24) & 0x7f;
4537         ext_v = pvid_to_extvid(dev_priv, pxvid);
4538
4539         state1 = ext_v;
4540
4541         t = i915_mch_val(dev_priv);
4542
4543         /* Revel in the empirically derived constants */
4544
4545         /* Correction factor in 1/100000 units */
4546         if (t > 80)
4547                 corr = ((t * 2349) + 135940);
4548         else if (t >= 50)
4549                 corr = ((t * 964) + 29317);
4550         else /* < 50 */
4551                 corr = ((t * 301) + 1004);
4552
4553         corr = corr * ((150142 * state1) / 10000 - 78642);
4554         corr /= 100000;
4555         corr2 = (corr * dev_priv->ips.corr);
4556
4557         state2 = (corr2 * state1) / 10000;
4558         state2 /= 100; /* convert to mW */
4559
4560         __i915_update_gfx_val(dev_priv);
4561
4562         return dev_priv->ips.gfx_power + state2;
4563 }
4564
4565 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4566 {
4567         unsigned long val;
4568
4569         if (dev_priv->info->gen != 5)
4570                 return 0;
4571
4572         spin_lock_irq(&mchdev_lock);
4573
4574         val = __i915_gfx_val(dev_priv);
4575
4576         spin_unlock_irq(&mchdev_lock);
4577
4578         return val;
4579 }
4580
4581 /**
4582  * i915_read_mch_val - return value for IPS use
4583  *
4584  * Calculate and return a value for the IPS driver to use when deciding whether
4585  * we have thermal and power headroom to increase CPU or GPU power budget.
4586  */
4587 unsigned long i915_read_mch_val(void)
4588 {
4589         struct drm_i915_private *dev_priv;
4590         unsigned long chipset_val, graphics_val, ret = 0;
4591
4592         spin_lock_irq(&mchdev_lock);
4593         if (!i915_mch_dev)
4594                 goto out_unlock;
4595         dev_priv = i915_mch_dev;
4596
4597         chipset_val = __i915_chipset_val(dev_priv);
4598         graphics_val = __i915_gfx_val(dev_priv);
4599
4600         ret = chipset_val + graphics_val;
4601
4602 out_unlock:
4603         spin_unlock_irq(&mchdev_lock);
4604
4605         return ret;
4606 }
4607 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4608
4609 /**
4610  * i915_gpu_raise - raise GPU frequency limit
4611  *
4612  * Raise the limit; IPS indicates we have thermal headroom.
4613  */
4614 bool i915_gpu_raise(void)
4615 {
4616         struct drm_i915_private *dev_priv;
4617         bool ret = true;
4618
4619         spin_lock_irq(&mchdev_lock);
4620         if (!i915_mch_dev) {
4621                 ret = false;
4622                 goto out_unlock;
4623         }
4624         dev_priv = i915_mch_dev;
4625
4626         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4627                 dev_priv->ips.max_delay--;
4628
4629 out_unlock:
4630         spin_unlock_irq(&mchdev_lock);
4631
4632         return ret;
4633 }
4634 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4635
4636 /**
4637  * i915_gpu_lower - lower GPU frequency limit
4638  *
4639  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4640  * frequency maximum.
4641  */
4642 bool i915_gpu_lower(void)
4643 {
4644         struct drm_i915_private *dev_priv;
4645         bool ret = true;
4646
4647         spin_lock_irq(&mchdev_lock);
4648         if (!i915_mch_dev) {
4649                 ret = false;
4650                 goto out_unlock;
4651         }
4652         dev_priv = i915_mch_dev;
4653
4654         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4655                 dev_priv->ips.max_delay++;
4656
4657 out_unlock:
4658         spin_unlock_irq(&mchdev_lock);
4659
4660         return ret;
4661 }
4662 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4663
4664 /**
4665  * i915_gpu_busy - indicate GPU business to IPS
4666  *
4667  * Tell the IPS driver whether or not the GPU is busy.
4668  */
4669 bool i915_gpu_busy(void)
4670 {
4671         struct drm_i915_private *dev_priv;
4672         struct intel_ring_buffer *ring;
4673         bool ret = false;
4674         int i;
4675
4676         spin_lock_irq(&mchdev_lock);
4677         if (!i915_mch_dev)
4678                 goto out_unlock;
4679         dev_priv = i915_mch_dev;
4680
4681         for_each_ring(ring, dev_priv, i)
4682                 ret |= !list_empty(&ring->request_list);
4683
4684 out_unlock:
4685         spin_unlock_irq(&mchdev_lock);
4686
4687         return ret;
4688 }
4689 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4690
4691 /**
4692  * i915_gpu_turbo_disable - disable graphics turbo
4693  *
4694  * Disable graphics turbo by resetting the max frequency and setting the
4695  * current frequency to the default.
4696  */
4697 bool i915_gpu_turbo_disable(void)
4698 {
4699         struct drm_i915_private *dev_priv;
4700         bool ret = true;
4701
4702         spin_lock_irq(&mchdev_lock);
4703         if (!i915_mch_dev) {
4704                 ret = false;
4705                 goto out_unlock;
4706         }
4707         dev_priv = i915_mch_dev;
4708
4709         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4710
4711         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4712                 ret = false;
4713
4714 out_unlock:
4715         spin_unlock_irq(&mchdev_lock);
4716
4717         return ret;
4718 }
4719 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4720
4721 /**
4722  * Tells the intel_ips driver that the i915 driver is now loaded, if
4723  * IPS got loaded first.
4724  *
4725  * This awkward dance is so that neither module has to depend on the
4726  * other in order for IPS to do the appropriate communication of
4727  * GPU turbo limits to i915.
4728  */
4729 static void
4730 ips_ping_for_i915_load(void)
4731 {
4732         void (*link)(void);
4733
4734         link = symbol_get(ips_link_to_i915_driver);
4735         if (link) {
4736                 link();
4737                 symbol_put(ips_link_to_i915_driver);
4738         }
4739 }
4740
4741 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4742 {
4743         /* We only register the i915 ips part with intel-ips once everything is
4744          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4745         spin_lock_irq(&mchdev_lock);
4746         i915_mch_dev = dev_priv;
4747         spin_unlock_irq(&mchdev_lock);
4748
4749         ips_ping_for_i915_load();
4750 }
4751
4752 void intel_gpu_ips_teardown(void)
4753 {
4754         spin_lock_irq(&mchdev_lock);
4755         i915_mch_dev = NULL;
4756         spin_unlock_irq(&mchdev_lock);
4757 }
4758 static void intel_init_emon(struct drm_device *dev)
4759 {
4760         struct drm_i915_private *dev_priv = dev->dev_private;
4761         u32 lcfuse;
4762         u8 pxw[16];
4763         int i;
4764
4765         /* Disable to program */
4766         I915_WRITE(ECR, 0);
4767         POSTING_READ(ECR);
4768
4769         /* Program energy weights for various events */
4770         I915_WRITE(SDEW, 0x15040d00);
4771         I915_WRITE(CSIEW0, 0x007f0000);
4772         I915_WRITE(CSIEW1, 0x1e220004);
4773         I915_WRITE(CSIEW2, 0x04000004);
4774
4775         for (i = 0; i < 5; i++)
4776                 I915_WRITE(PEW + (i * 4), 0);
4777         for (i = 0; i < 3; i++)
4778                 I915_WRITE(DEW + (i * 4), 0);
4779
4780         /* Program P-state weights to account for frequency power adjustment */
4781         for (i = 0; i < 16; i++) {
4782                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4783                 unsigned long freq = intel_pxfreq(pxvidfreq);
4784                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4785                         PXVFREQ_PX_SHIFT;
4786                 unsigned long val;
4787
4788                 val = vid * vid;
4789                 val *= (freq / 1000);
4790                 val *= 255;
4791                 val /= (127*127*900);
4792                 if (val > 0xff)
4793                         DRM_ERROR("bad pxval: %ld\n", val);
4794                 pxw[i] = val;
4795         }
4796         /* Render standby states get 0 weight */
4797         pxw[14] = 0;
4798         pxw[15] = 0;
4799
4800         for (i = 0; i < 4; i++) {
4801                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4802                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4803                 I915_WRITE(PXW + (i * 4), val);
4804         }
4805
4806         /* Adjust magic regs to magic values (more experimental results) */
4807         I915_WRITE(OGW0, 0);
4808         I915_WRITE(OGW1, 0);
4809         I915_WRITE(EG0, 0x00007f00);
4810         I915_WRITE(EG1, 0x0000000e);
4811         I915_WRITE(EG2, 0x000e0000);
4812         I915_WRITE(EG3, 0x68000300);
4813         I915_WRITE(EG4, 0x42000000);
4814         I915_WRITE(EG5, 0x00140031);
4815         I915_WRITE(EG6, 0);
4816         I915_WRITE(EG7, 0);
4817
4818         for (i = 0; i < 8; i++)
4819                 I915_WRITE(PXWL + (i * 4), 0);
4820
4821         /* Enable PMON + select events */
4822         I915_WRITE(ECR, 0x80000019);
4823
4824         lcfuse = I915_READ(LCFUSE02);
4825
4826         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4827 }
4828
4829 void intel_disable_gt_powersave(struct drm_device *dev)
4830 {
4831         struct drm_i915_private *dev_priv = dev->dev_private;
4832
4833         /* Interrupts should be disabled already to avoid re-arming. */
4834         WARN_ON(dev->irq_enabled);
4835
4836         if (IS_IRONLAKE_M(dev)) {
4837                 ironlake_disable_drps(dev);
4838                 ironlake_disable_rc6(dev);
4839         } else if (INTEL_INFO(dev)->gen >= 6) {
4840                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4841                 cancel_work_sync(&dev_priv->rps.work);
4842                 mutex_lock(&dev_priv->rps.hw_lock);
4843                 if (IS_VALLEYVIEW(dev))
4844                         valleyview_disable_rps(dev);
4845                 else
4846                         gen6_disable_rps(dev);
4847                 dev_priv->rps.enabled = false;
4848                 mutex_unlock(&dev_priv->rps.hw_lock);
4849         }
4850 }
4851
4852 static void intel_gen6_powersave_work(struct work_struct *work)
4853 {
4854         struct drm_i915_private *dev_priv =
4855                 container_of(work, struct drm_i915_private,
4856                              rps.delayed_resume_work.work);
4857         struct drm_device *dev = dev_priv->dev;
4858
4859         mutex_lock(&dev_priv->rps.hw_lock);
4860
4861         if (IS_VALLEYVIEW(dev)) {
4862                 valleyview_enable_rps(dev);
4863         } else {
4864                 gen6_enable_rps(dev);
4865                 gen6_update_ring_freq(dev);
4866         }
4867         dev_priv->rps.enabled = true;
4868         mutex_unlock(&dev_priv->rps.hw_lock);
4869 }
4870
4871 void intel_enable_gt_powersave(struct drm_device *dev)
4872 {
4873         struct drm_i915_private *dev_priv = dev->dev_private;
4874
4875         if (IS_IRONLAKE_M(dev)) {
4876                 ironlake_enable_drps(dev);
4877                 ironlake_enable_rc6(dev);
4878                 intel_init_emon(dev);
4879         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4880                 /*
4881                  * PCU communication is slow and this doesn't need to be
4882                  * done at any specific time, so do this out of our fast path
4883                  * to make resume and init faster.
4884                  */
4885                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4886                                       round_jiffies_up_relative(HZ));
4887         }
4888 }
4889
4890 static void ibx_init_clock_gating(struct drm_device *dev)
4891 {
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893
4894         /*
4895          * On Ibex Peak and Cougar Point, we need to disable clock
4896          * gating for the panel power sequencer or it will fail to
4897          * start up when no ports are active.
4898          */
4899         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4900 }
4901
4902 static void g4x_disable_trickle_feed(struct drm_device *dev)
4903 {
4904         struct drm_i915_private *dev_priv = dev->dev_private;
4905         int pipe;
4906
4907         for_each_pipe(pipe) {
4908                 I915_WRITE(DSPCNTR(pipe),
4909                            I915_READ(DSPCNTR(pipe)) |
4910                            DISPPLANE_TRICKLE_FEED_DISABLE);
4911                 intel_flush_primary_plane(dev_priv, pipe);
4912         }
4913 }
4914
4915 static void ironlake_init_clock_gating(struct drm_device *dev)
4916 {
4917         struct drm_i915_private *dev_priv = dev->dev_private;
4918         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4919
4920         /*
4921          * Required for FBC
4922          * WaFbcDisableDpfcClockGating:ilk
4923          */
4924         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4925                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4926                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4927
4928         I915_WRITE(PCH_3DCGDIS0,
4929                    MARIUNIT_CLOCK_GATE_DISABLE |
4930                    SVSMUNIT_CLOCK_GATE_DISABLE);
4931         I915_WRITE(PCH_3DCGDIS1,
4932                    VFMUNIT_CLOCK_GATE_DISABLE);
4933
4934         /*
4935          * According to the spec the following bits should be set in
4936          * order to enable memory self-refresh
4937          * The bit 22/21 of 0x42004
4938          * The bit 5 of 0x42020
4939          * The bit 15 of 0x45000
4940          */
4941         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4942                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4943                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4944         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4945         I915_WRITE(DISP_ARB_CTL,
4946                    (I915_READ(DISP_ARB_CTL) |
4947                     DISP_FBC_WM_DIS));
4948         I915_WRITE(WM3_LP_ILK, 0);
4949         I915_WRITE(WM2_LP_ILK, 0);
4950         I915_WRITE(WM1_LP_ILK, 0);
4951
4952         /*
4953          * Based on the document from hardware guys the following bits
4954          * should be set unconditionally in order to enable FBC.
4955          * The bit 22 of 0x42000
4956          * The bit 22 of 0x42004
4957          * The bit 7,8,9 of 0x42020.
4958          */
4959         if (IS_IRONLAKE_M(dev)) {
4960                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4961                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4962                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4963                            ILK_FBCQ_DIS);
4964                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4965                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4966                            ILK_DPARB_GATE);
4967         }
4968
4969         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4970
4971         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4972                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4973                    ILK_ELPIN_409_SELECT);
4974         I915_WRITE(_3D_CHICKEN2,
4975                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4976                    _3D_CHICKEN2_WM_READ_PIPELINED);
4977
4978         /* WaDisableRenderCachePipelinedFlush:ilk */
4979         I915_WRITE(CACHE_MODE_0,
4980                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4981
4982         g4x_disable_trickle_feed(dev);
4983
4984         ibx_init_clock_gating(dev);
4985 }
4986
4987 static void cpt_init_clock_gating(struct drm_device *dev)
4988 {
4989         struct drm_i915_private *dev_priv = dev->dev_private;
4990         int pipe;
4991         uint32_t val;
4992
4993         /*
4994          * On Ibex Peak and Cougar Point, we need to disable clock
4995          * gating for the panel power sequencer or it will fail to
4996          * start up when no ports are active.
4997          */
4998         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4999         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5000                    DPLS_EDP_PPS_FIX_DIS);
5001         /* The below fixes the weird display corruption, a few pixels shifted
5002          * downward, on (only) LVDS of some HP laptops with IVY.
5003          */
5004         for_each_pipe(pipe) {
5005                 val = I915_READ(TRANS_CHICKEN2(pipe));
5006                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5007                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5008                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5009                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5010                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5011                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5012                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5013                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5014         }
5015         /* WADP0ClockGatingDisable */
5016         for_each_pipe(pipe) {
5017                 I915_WRITE(TRANS_CHICKEN1(pipe),
5018                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5019         }
5020 }
5021
5022 static void gen6_check_mch_setup(struct drm_device *dev)
5023 {
5024         struct drm_i915_private *dev_priv = dev->dev_private;
5025         uint32_t tmp;
5026
5027         tmp = I915_READ(MCH_SSKPD);
5028         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5029                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5030                 DRM_INFO("This can cause pipe underruns and display issues.\n");
5031                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5032         }
5033 }
5034
5035 static void gen6_init_clock_gating(struct drm_device *dev)
5036 {
5037         struct drm_i915_private *dev_priv = dev->dev_private;
5038         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5039
5040         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5041
5042         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5043                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5044                    ILK_ELPIN_409_SELECT);
5045
5046         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5047         I915_WRITE(_3D_CHICKEN,
5048                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5049
5050         /* WaSetupGtModeTdRowDispatch:snb */
5051         if (IS_SNB_GT1(dev))
5052                 I915_WRITE(GEN6_GT_MODE,
5053                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5054
5055         I915_WRITE(WM3_LP_ILK, 0);
5056         I915_WRITE(WM2_LP_ILK, 0);
5057         I915_WRITE(WM1_LP_ILK, 0);
5058
5059         I915_WRITE(CACHE_MODE_0,
5060                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5061
5062         I915_WRITE(GEN6_UCGCTL1,
5063                    I915_READ(GEN6_UCGCTL1) |
5064                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5065                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5066
5067         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5068          * gating disable must be set.  Failure to set it results in
5069          * flickering pixels due to Z write ordering failures after
5070          * some amount of runtime in the Mesa "fire" demo, and Unigine
5071          * Sanctuary and Tropics, and apparently anything else with
5072          * alpha test or pixel discard.
5073          *
5074          * According to the spec, bit 11 (RCCUNIT) must also be set,
5075          * but we didn't debug actual testcases to find it out.
5076          *
5077          * Also apply WaDisableVDSUnitClockGating:snb and
5078          * WaDisableRCPBUnitClockGating:snb.
5079          */
5080         I915_WRITE(GEN6_UCGCTL2,
5081                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5082                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5083                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5084
5085         /* Bspec says we need to always set all mask bits. */
5086         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5087                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5088
5089         /*
5090          * According to the spec the following bits should be
5091          * set in order to enable memory self-refresh and fbc:
5092          * The bit21 and bit22 of 0x42000
5093          * The bit21 and bit22 of 0x42004
5094          * The bit5 and bit7 of 0x42020
5095          * The bit14 of 0x70180
5096          * The bit14 of 0x71180
5097          *
5098          * WaFbcAsynchFlipDisableFbcQueue:snb
5099          */
5100         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5101                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5102                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5103         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5104                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5105                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5106         I915_WRITE(ILK_DSPCLK_GATE_D,
5107                    I915_READ(ILK_DSPCLK_GATE_D) |
5108                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5109                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5110
5111         g4x_disable_trickle_feed(dev);
5112
5113         /* The default value should be 0x200 according to docs, but the two
5114          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5115         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5116         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5117
5118         cpt_init_clock_gating(dev);
5119
5120         gen6_check_mch_setup(dev);
5121 }
5122
5123 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5124 {
5125         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5126
5127         reg &= ~GEN7_FF_SCHED_MASK;
5128         reg |= GEN7_FF_TS_SCHED_HW;
5129         reg |= GEN7_FF_VS_SCHED_HW;
5130         reg |= GEN7_FF_DS_SCHED_HW;
5131
5132         if (IS_HASWELL(dev_priv->dev))
5133                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5134
5135         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5136 }
5137
5138 static void lpt_init_clock_gating(struct drm_device *dev)
5139 {
5140         struct drm_i915_private *dev_priv = dev->dev_private;
5141
5142         /*
5143          * TODO: this bit should only be enabled when really needed, then
5144          * disabled when not needed anymore in order to save power.
5145          */
5146         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5147                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5148                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5149                            PCH_LP_PARTITION_LEVEL_DISABLE);
5150
5151         /* WADPOClockGatingDisable:hsw */
5152         I915_WRITE(_TRANSA_CHICKEN1,
5153                    I915_READ(_TRANSA_CHICKEN1) |
5154                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5155 }
5156
5157 static void lpt_suspend_hw(struct drm_device *dev)
5158 {
5159         struct drm_i915_private *dev_priv = dev->dev_private;
5160
5161         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5162                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5163
5164                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5165                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5166         }
5167 }
5168
5169 static void haswell_init_clock_gating(struct drm_device *dev)
5170 {
5171         struct drm_i915_private *dev_priv = dev->dev_private;
5172
5173         I915_WRITE(WM3_LP_ILK, 0);
5174         I915_WRITE(WM2_LP_ILK, 0);
5175         I915_WRITE(WM1_LP_ILK, 0);
5176
5177         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5178          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5179          */
5180         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5181
5182         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5183         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5184                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5185
5186         /* WaApplyL3ControlAndL3ChickenMode:hsw */
5187         I915_WRITE(GEN7_L3CNTLREG1,
5188                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5189         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5190                         GEN7_WA_L3_CHICKEN_MODE);
5191
5192         /* This is required by WaCatErrorRejectionIssue:hsw */
5193         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5194                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5195                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5196
5197         /* WaVSRefCountFullforceMissDisable:hsw */
5198         gen7_setup_fixed_func_scheduler(dev_priv);
5199
5200         /* WaDisable4x2SubspanOptimization:hsw */
5201         I915_WRITE(CACHE_MODE_1,
5202                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5203
5204         /* WaSwitchSolVfFArbitrationPriority:hsw */
5205         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5206
5207         /* WaRsPkgCStateDisplayPMReq:hsw */
5208         I915_WRITE(CHICKEN_PAR1_1,
5209                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5210
5211         lpt_init_clock_gating(dev);
5212 }
5213
5214 static void ivybridge_init_clock_gating(struct drm_device *dev)
5215 {
5216         struct drm_i915_private *dev_priv = dev->dev_private;
5217         uint32_t snpcr;
5218
5219         I915_WRITE(WM3_LP_ILK, 0);
5220         I915_WRITE(WM2_LP_ILK, 0);
5221         I915_WRITE(WM1_LP_ILK, 0);
5222
5223         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5224
5225         /* WaDisableEarlyCull:ivb */
5226         I915_WRITE(_3D_CHICKEN3,
5227                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5228
5229         /* WaDisableBackToBackFlipFix:ivb */
5230         I915_WRITE(IVB_CHICKEN3,
5231                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5232                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5233
5234         /* WaDisablePSDDualDispatchEnable:ivb */
5235         if (IS_IVB_GT1(dev))
5236                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5237                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5238         else
5239                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5240                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5241
5242         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5243         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5244                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5245
5246         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5247         I915_WRITE(GEN7_L3CNTLREG1,
5248                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5249         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5250                    GEN7_WA_L3_CHICKEN_MODE);
5251         if (IS_IVB_GT1(dev))
5252                 I915_WRITE(GEN7_ROW_CHICKEN2,
5253                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5254         else
5255                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5256                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5257
5258
5259         /* WaForceL3Serialization:ivb */
5260         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5261                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5262
5263         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5264          * gating disable must be set.  Failure to set it results in
5265          * flickering pixels due to Z write ordering failures after
5266          * some amount of runtime in the Mesa "fire" demo, and Unigine
5267          * Sanctuary and Tropics, and apparently anything else with
5268          * alpha test or pixel discard.
5269          *
5270          * According to the spec, bit 11 (RCCUNIT) must also be set,
5271          * but we didn't debug actual testcases to find it out.
5272          *
5273          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5274          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5275          */
5276         I915_WRITE(GEN6_UCGCTL2,
5277                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5278                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5279
5280         /* This is required by WaCatErrorRejectionIssue:ivb */
5281         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5282                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5283                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5284
5285         g4x_disable_trickle_feed(dev);
5286
5287         /* WaVSRefCountFullforceMissDisable:ivb */
5288         gen7_setup_fixed_func_scheduler(dev_priv);
5289
5290         /* WaDisable4x2SubspanOptimization:ivb */
5291         I915_WRITE(CACHE_MODE_1,
5292                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5293
5294         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5295         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5296         snpcr |= GEN6_MBC_SNPCR_MED;
5297         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5298
5299         if (!HAS_PCH_NOP(dev))
5300                 cpt_init_clock_gating(dev);
5301
5302         gen6_check_mch_setup(dev);
5303 }
5304
5305 static void valleyview_init_clock_gating(struct drm_device *dev)
5306 {
5307         struct drm_i915_private *dev_priv = dev->dev_private;
5308
5309         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5310
5311         /* WaDisableEarlyCull:vlv */
5312         I915_WRITE(_3D_CHICKEN3,
5313                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5314
5315         /* WaDisableBackToBackFlipFix:vlv */
5316         I915_WRITE(IVB_CHICKEN3,
5317                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5318                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5319
5320         /* WaDisablePSDDualDispatchEnable:vlv */
5321         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5322                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5323                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5324
5325         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5326         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5327                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5328
5329         /* WaApplyL3ControlAndL3ChickenMode:vlv */
5330         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5331         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5332
5333         /* WaForceL3Serialization:vlv */
5334         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5335                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5336
5337         /* WaDisableDopClockGating:vlv */
5338         I915_WRITE(GEN7_ROW_CHICKEN2,
5339                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5340
5341         /* This is required by WaCatErrorRejectionIssue:vlv */
5342         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5343                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5344                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5345
5346         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5347          * gating disable must be set.  Failure to set it results in
5348          * flickering pixels due to Z write ordering failures after
5349          * some amount of runtime in the Mesa "fire" demo, and Unigine
5350          * Sanctuary and Tropics, and apparently anything else with
5351          * alpha test or pixel discard.
5352          *
5353          * According to the spec, bit 11 (RCCUNIT) must also be set,
5354          * but we didn't debug actual testcases to find it out.
5355          *
5356          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5357          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5358          *
5359          * Also apply WaDisableVDSUnitClockGating:vlv and
5360          * WaDisableRCPBUnitClockGating:vlv.
5361          */
5362         I915_WRITE(GEN6_UCGCTL2,
5363                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5364                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5365                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5366                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5367                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5368
5369         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5370
5371         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5372
5373         I915_WRITE(CACHE_MODE_1,
5374                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5375
5376         /*
5377          * WaDisableVLVClockGating_VBIIssue:vlv
5378          * Disable clock gating on th GCFG unit to prevent a delay
5379          * in the reporting of vblank events.
5380          */
5381         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5382
5383         /* Conservative clock gating settings for now */
5384         I915_WRITE(0x9400, 0xffffffff);
5385         I915_WRITE(0x9404, 0xffffffff);
5386         I915_WRITE(0x9408, 0xffffffff);
5387         I915_WRITE(0x940c, 0xffffffff);
5388         I915_WRITE(0x9410, 0xffffffff);
5389         I915_WRITE(0x9414, 0xffffffff);
5390         I915_WRITE(0x9418, 0xffffffff);
5391 }
5392
5393 static void g4x_init_clock_gating(struct drm_device *dev)
5394 {
5395         struct drm_i915_private *dev_priv = dev->dev_private;
5396         uint32_t dspclk_gate;
5397
5398         I915_WRITE(RENCLK_GATE_D1, 0);
5399         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5400                    GS_UNIT_CLOCK_GATE_DISABLE |
5401                    CL_UNIT_CLOCK_GATE_DISABLE);
5402         I915_WRITE(RAMCLK_GATE_D, 0);
5403         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5404                 OVRUNIT_CLOCK_GATE_DISABLE |
5405                 OVCUNIT_CLOCK_GATE_DISABLE;
5406         if (IS_GM45(dev))
5407                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5408         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5409
5410         /* WaDisableRenderCachePipelinedFlush */
5411         I915_WRITE(CACHE_MODE_0,
5412                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5413
5414         g4x_disable_trickle_feed(dev);
5415 }
5416
5417 static void crestline_init_clock_gating(struct drm_device *dev)
5418 {
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420
5421         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5422         I915_WRITE(RENCLK_GATE_D2, 0);
5423         I915_WRITE(DSPCLK_GATE_D, 0);
5424         I915_WRITE(RAMCLK_GATE_D, 0);
5425         I915_WRITE16(DEUC, 0);
5426         I915_WRITE(MI_ARB_STATE,
5427                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5428 }
5429
5430 static void broadwater_init_clock_gating(struct drm_device *dev)
5431 {
5432         struct drm_i915_private *dev_priv = dev->dev_private;
5433
5434         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5435                    I965_RCC_CLOCK_GATE_DISABLE |
5436                    I965_RCPB_CLOCK_GATE_DISABLE |
5437                    I965_ISC_CLOCK_GATE_DISABLE |
5438                    I965_FBC_CLOCK_GATE_DISABLE);
5439         I915_WRITE(RENCLK_GATE_D2, 0);
5440         I915_WRITE(MI_ARB_STATE,
5441                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5442 }
5443
5444 static void gen3_init_clock_gating(struct drm_device *dev)
5445 {
5446         struct drm_i915_private *dev_priv = dev->dev_private;
5447         u32 dstate = I915_READ(D_STATE);
5448
5449         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5450                 DSTATE_DOT_CLOCK_GATING;
5451         I915_WRITE(D_STATE, dstate);
5452
5453         if (IS_PINEVIEW(dev))
5454                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5455
5456         /* IIR "flip pending" means done if this bit is set */
5457         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5458 }
5459
5460 static void i85x_init_clock_gating(struct drm_device *dev)
5461 {
5462         struct drm_i915_private *dev_priv = dev->dev_private;
5463
5464         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5465 }
5466
5467 static void i830_init_clock_gating(struct drm_device *dev)
5468 {
5469         struct drm_i915_private *dev_priv = dev->dev_private;
5470
5471         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5472 }
5473
5474 void intel_init_clock_gating(struct drm_device *dev)
5475 {
5476         struct drm_i915_private *dev_priv = dev->dev_private;
5477
5478         dev_priv->display.init_clock_gating(dev);
5479 }
5480
5481 void intel_suspend_hw(struct drm_device *dev)
5482 {
5483         if (HAS_PCH_LPT(dev))
5484                 lpt_suspend_hw(dev);
5485 }
5486
5487 /**
5488  * We should only use the power well if we explicitly asked the hardware to
5489  * enable it, so check if it's enabled and also check if we've requested it to
5490  * be enabled.
5491  */
5492 bool intel_display_power_enabled(struct drm_device *dev,
5493                                  enum intel_display_power_domain domain)
5494 {
5495         struct drm_i915_private *dev_priv = dev->dev_private;
5496
5497         if (!HAS_POWER_WELL(dev))
5498                 return true;
5499
5500         switch (domain) {
5501         case POWER_DOMAIN_PIPE_A:
5502         case POWER_DOMAIN_TRANSCODER_EDP:
5503                 return true;
5504         case POWER_DOMAIN_VGA:
5505         case POWER_DOMAIN_PIPE_B:
5506         case POWER_DOMAIN_PIPE_C:
5507         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5508         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5509         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5510         case POWER_DOMAIN_TRANSCODER_A:
5511         case POWER_DOMAIN_TRANSCODER_B:
5512         case POWER_DOMAIN_TRANSCODER_C:
5513                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5514                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5515         default:
5516                 BUG();
5517         }
5518 }
5519
5520 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5521 {
5522         struct drm_i915_private *dev_priv = dev->dev_private;
5523         bool is_enabled, enable_requested;
5524         uint32_t tmp;
5525
5526         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5527         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5528         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5529
5530         if (enable) {
5531                 if (!enable_requested)
5532                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5533                                    HSW_PWR_WELL_ENABLE_REQUEST);
5534
5535                 if (!is_enabled) {
5536                         DRM_DEBUG_KMS("Enabling power well\n");
5537                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5538                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5539                                 DRM_ERROR("Timeout enabling power well\n");
5540                 }
5541         } else {
5542                 if (enable_requested) {
5543                         unsigned long irqflags;
5544                         enum pipe p;
5545
5546                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5547                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5548                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5549
5550                         /*
5551                          * After this, the registers on the pipes that are part
5552                          * of the power well will become zero, so we have to
5553                          * adjust our counters according to that.
5554                          *
5555                          * FIXME: Should we do this in general in
5556                          * drm_vblank_post_modeset?
5557                          */
5558                         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5559                         for_each_pipe(p)
5560                                 if (p != PIPE_A)
5561                                         dev->vblank[p].last = 0;
5562                         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5563                 }
5564         }
5565 }
5566
5567 static void __intel_power_well_get(struct i915_power_well *power_well)
5568 {
5569         if (!power_well->count++)
5570                 __intel_set_power_well(power_well->device, true);
5571 }
5572
5573 static void __intel_power_well_put(struct i915_power_well *power_well)
5574 {
5575         WARN_ON(!power_well->count);
5576         if (!--power_well->count)
5577                 __intel_set_power_well(power_well->device, false);
5578 }
5579
5580 void intel_display_power_get(struct drm_device *dev,
5581                              enum intel_display_power_domain domain)
5582 {
5583         struct drm_i915_private *dev_priv = dev->dev_private;
5584         struct i915_power_well *power_well = &dev_priv->power_well;
5585
5586         if (!HAS_POWER_WELL(dev))
5587                 return;
5588
5589         switch (domain) {
5590         case POWER_DOMAIN_PIPE_A:
5591         case POWER_DOMAIN_TRANSCODER_EDP:
5592                 return;
5593         case POWER_DOMAIN_VGA:
5594         case POWER_DOMAIN_PIPE_B:
5595         case POWER_DOMAIN_PIPE_C:
5596         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5597         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5598         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5599         case POWER_DOMAIN_TRANSCODER_A:
5600         case POWER_DOMAIN_TRANSCODER_B:
5601         case POWER_DOMAIN_TRANSCODER_C:
5602                 spin_lock_irq(&power_well->lock);
5603                 __intel_power_well_get(power_well);
5604                 spin_unlock_irq(&power_well->lock);
5605                 return;
5606         default:
5607                 BUG();
5608         }
5609 }
5610
5611 void intel_display_power_put(struct drm_device *dev,
5612                              enum intel_display_power_domain domain)
5613 {
5614         struct drm_i915_private *dev_priv = dev->dev_private;
5615         struct i915_power_well *power_well = &dev_priv->power_well;
5616
5617         if (!HAS_POWER_WELL(dev))
5618                 return;
5619
5620         switch (domain) {
5621         case POWER_DOMAIN_PIPE_A:
5622         case POWER_DOMAIN_TRANSCODER_EDP:
5623                 return;
5624         case POWER_DOMAIN_VGA:
5625         case POWER_DOMAIN_PIPE_B:
5626         case POWER_DOMAIN_PIPE_C:
5627         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5628         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5629         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5630         case POWER_DOMAIN_TRANSCODER_A:
5631         case POWER_DOMAIN_TRANSCODER_B:
5632         case POWER_DOMAIN_TRANSCODER_C:
5633                 spin_lock_irq(&power_well->lock);
5634                 __intel_power_well_put(power_well);
5635                 spin_unlock_irq(&power_well->lock);
5636                 return;
5637         default:
5638                 BUG();
5639         }
5640 }
5641
5642 static struct i915_power_well *hsw_pwr;
5643
5644 /* Display audio driver power well request */
5645 void i915_request_power_well(void)
5646 {
5647         if (WARN_ON(!hsw_pwr))
5648                 return;
5649
5650         spin_lock_irq(&hsw_pwr->lock);
5651         __intel_power_well_get(hsw_pwr);
5652         spin_unlock_irq(&hsw_pwr->lock);
5653 }
5654 EXPORT_SYMBOL_GPL(i915_request_power_well);
5655
5656 /* Display audio driver power well release */
5657 void i915_release_power_well(void)
5658 {
5659         if (WARN_ON(!hsw_pwr))
5660                 return;
5661
5662         spin_lock_irq(&hsw_pwr->lock);
5663         __intel_power_well_put(hsw_pwr);
5664         spin_unlock_irq(&hsw_pwr->lock);
5665 }
5666 EXPORT_SYMBOL_GPL(i915_release_power_well);
5667
5668 int i915_init_power_well(struct drm_device *dev)
5669 {
5670         struct drm_i915_private *dev_priv = dev->dev_private;
5671
5672         hsw_pwr = &dev_priv->power_well;
5673
5674         hsw_pwr->device = dev;
5675         spin_lock_init(&hsw_pwr->lock);
5676         hsw_pwr->count = 0;
5677
5678         return 0;
5679 }
5680
5681 void i915_remove_power_well(struct drm_device *dev)
5682 {
5683         hsw_pwr = NULL;
5684 }
5685
5686 void intel_set_power_well(struct drm_device *dev, bool enable)
5687 {
5688         struct drm_i915_private *dev_priv = dev->dev_private;
5689         struct i915_power_well *power_well = &dev_priv->power_well;
5690
5691         if (!HAS_POWER_WELL(dev))
5692                 return;
5693
5694         if (!i915_disable_power_well && !enable)
5695                 return;
5696
5697         spin_lock_irq(&power_well->lock);
5698
5699         /*
5700          * This function will only ever contribute one
5701          * to the power well reference count. i915_request
5702          * is what tracks whether we have or have not
5703          * added the one to the reference count.
5704          */
5705         if (power_well->i915_request == enable)
5706                 goto out;
5707
5708         power_well->i915_request = enable;
5709
5710         if (enable)
5711                 __intel_power_well_get(power_well);
5712         else
5713                 __intel_power_well_put(power_well);
5714
5715  out:
5716         spin_unlock_irq(&power_well->lock);
5717 }
5718
5719 static void intel_resume_power_well(struct drm_device *dev)
5720 {
5721         struct drm_i915_private *dev_priv = dev->dev_private;
5722         struct i915_power_well *power_well = &dev_priv->power_well;
5723
5724         if (!HAS_POWER_WELL(dev))
5725                 return;
5726
5727         spin_lock_irq(&power_well->lock);
5728         __intel_set_power_well(dev, power_well->count > 0);
5729         spin_unlock_irq(&power_well->lock);
5730 }
5731
5732 /*
5733  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5734  * when not needed anymore. We have 4 registers that can request the power well
5735  * to be enabled, and it will only be disabled if none of the registers is
5736  * requesting it to be enabled.
5737  */
5738 void intel_init_power_well(struct drm_device *dev)
5739 {
5740         struct drm_i915_private *dev_priv = dev->dev_private;
5741
5742         if (!HAS_POWER_WELL(dev))
5743                 return;
5744
5745         /* For now, we need the power well to be always enabled. */
5746         intel_set_power_well(dev, true);
5747         intel_resume_power_well(dev);
5748
5749         /* We're taking over the BIOS, so clear any requests made by it since
5750          * the driver is in charge now. */
5751         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5752                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5753 }
5754
5755 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5756 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5757 {
5758         hsw_disable_package_c8(dev_priv);
5759 }
5760
5761 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5762 {
5763         hsw_enable_package_c8(dev_priv);
5764 }
5765
5766 /* Set up chip specific power management-related functions */
5767 void intel_init_pm(struct drm_device *dev)
5768 {
5769         struct drm_i915_private *dev_priv = dev->dev_private;
5770
5771         if (I915_HAS_FBC(dev)) {
5772                 if (HAS_PCH_SPLIT(dev)) {
5773                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5774                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5775                                 dev_priv->display.enable_fbc =
5776                                         gen7_enable_fbc;
5777                         else
5778                                 dev_priv->display.enable_fbc =
5779                                         ironlake_enable_fbc;
5780                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5781                 } else if (IS_GM45(dev)) {
5782                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5783                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5784                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5785                 } else if (IS_CRESTLINE(dev)) {
5786                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5787                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5788                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5789                 }
5790                 /* 855GM needs testing */
5791         }
5792
5793         /* For cxsr */
5794         if (IS_PINEVIEW(dev))
5795                 i915_pineview_get_mem_freq(dev);
5796         else if (IS_GEN5(dev))
5797                 i915_ironlake_get_mem_freq(dev);
5798
5799         /* For FIFO watermark updates */
5800         if (HAS_PCH_SPLIT(dev)) {
5801                 intel_setup_wm_latency(dev);
5802
5803                 if (IS_GEN5(dev)) {
5804                         if (dev_priv->wm.pri_latency[1] &&
5805                             dev_priv->wm.spr_latency[1] &&
5806                             dev_priv->wm.cur_latency[1])
5807                                 dev_priv->display.update_wm = ironlake_update_wm;
5808                         else {
5809                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5810                                               "Disable CxSR\n");
5811                                 dev_priv->display.update_wm = NULL;
5812                         }
5813                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5814                 } else if (IS_GEN6(dev)) {
5815                         if (dev_priv->wm.pri_latency[0] &&
5816                             dev_priv->wm.spr_latency[0] &&
5817                             dev_priv->wm.cur_latency[0]) {
5818                                 dev_priv->display.update_wm = sandybridge_update_wm;
5819                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5820                         } else {
5821                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5822                                               "Disable CxSR\n");
5823                                 dev_priv->display.update_wm = NULL;
5824                         }
5825                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5826                 } else if (IS_IVYBRIDGE(dev)) {
5827                         if (dev_priv->wm.pri_latency[0] &&
5828                             dev_priv->wm.spr_latency[0] &&
5829                             dev_priv->wm.cur_latency[0]) {
5830                                 dev_priv->display.update_wm = ivybridge_update_wm;
5831                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5832                         } else {
5833                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5834                                               "Disable CxSR\n");
5835                                 dev_priv->display.update_wm = NULL;
5836                         }
5837                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5838                 } else if (IS_HASWELL(dev)) {
5839                         if (dev_priv->wm.pri_latency[0] &&
5840                             dev_priv->wm.spr_latency[0] &&
5841                             dev_priv->wm.cur_latency[0]) {
5842                                 dev_priv->display.update_wm = haswell_update_wm;
5843                                 dev_priv->display.update_sprite_wm =
5844                                         haswell_update_sprite_wm;
5845                         } else {
5846                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5847                                               "Disable CxSR\n");
5848                                 dev_priv->display.update_wm = NULL;
5849                         }
5850                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5851                 } else
5852                         dev_priv->display.update_wm = NULL;
5853         } else if (IS_VALLEYVIEW(dev)) {
5854                 dev_priv->display.update_wm = valleyview_update_wm;
5855                 dev_priv->display.init_clock_gating =
5856                         valleyview_init_clock_gating;
5857         } else if (IS_PINEVIEW(dev)) {
5858                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5859                                             dev_priv->is_ddr3,
5860                                             dev_priv->fsb_freq,
5861                                             dev_priv->mem_freq)) {
5862                         DRM_INFO("failed to find known CxSR latency "
5863                                  "(found ddr%s fsb freq %d, mem freq %d), "
5864                                  "disabling CxSR\n",
5865                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5866                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5867                         /* Disable CxSR and never update its watermark again */
5868                         pineview_disable_cxsr(dev);
5869                         dev_priv->display.update_wm = NULL;
5870                 } else
5871                         dev_priv->display.update_wm = pineview_update_wm;
5872                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5873         } else if (IS_G4X(dev)) {
5874                 dev_priv->display.update_wm = g4x_update_wm;
5875                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5876         } else if (IS_GEN4(dev)) {
5877                 dev_priv->display.update_wm = i965_update_wm;
5878                 if (IS_CRESTLINE(dev))
5879                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5880                 else if (IS_BROADWATER(dev))
5881                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5882         } else if (IS_GEN3(dev)) {
5883                 dev_priv->display.update_wm = i9xx_update_wm;
5884                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5885                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5886         } else if (IS_I865G(dev)) {
5887                 dev_priv->display.update_wm = i830_update_wm;
5888                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5889                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5890         } else if (IS_I85X(dev)) {
5891                 dev_priv->display.update_wm = i9xx_update_wm;
5892                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5893                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5894         } else {
5895                 dev_priv->display.update_wm = i830_update_wm;
5896                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5897                 if (IS_845G(dev))
5898                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5899                 else
5900                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5901         }
5902 }
5903
5904 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5905 {
5906         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5907
5908         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5909                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5910                 return -EAGAIN;
5911         }
5912
5913         I915_WRITE(GEN6_PCODE_DATA, *val);
5914         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5915
5916         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5917                      500)) {
5918                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5919                 return -ETIMEDOUT;
5920         }
5921
5922         *val = I915_READ(GEN6_PCODE_DATA);
5923         I915_WRITE(GEN6_PCODE_DATA, 0);
5924
5925         return 0;
5926 }
5927
5928 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5929 {
5930         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5931
5932         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5933                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5934                 return -EAGAIN;
5935         }
5936
5937         I915_WRITE(GEN6_PCODE_DATA, val);
5938         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5939
5940         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5941                      500)) {
5942                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5943                 return -ETIMEDOUT;
5944         }
5945
5946         I915_WRITE(GEN6_PCODE_DATA, 0);
5947
5948         return 0;
5949 }
5950
5951 int vlv_gpu_freq(int ddr_freq, int val)
5952 {
5953         int mult, base;
5954
5955         switch (ddr_freq) {
5956         case 800:
5957                 mult = 20;
5958                 base = 120;
5959                 break;
5960         case 1066:
5961                 mult = 22;
5962                 base = 133;
5963                 break;
5964         case 1333:
5965                 mult = 21;
5966                 base = 125;
5967                 break;
5968         default:
5969                 return -1;
5970         }
5971
5972         return ((val - 0xbd) * mult) + base;
5973 }
5974
5975 int vlv_freq_opcode(int ddr_freq, int val)
5976 {
5977         int mult, base;
5978
5979         switch (ddr_freq) {
5980         case 800:
5981                 mult = 20;
5982                 base = 120;
5983                 break;
5984         case 1066:
5985                 mult = 22;
5986                 base = 133;
5987                 break;
5988         case 1333:
5989                 mult = 21;
5990                 base = 125;
5991                 break;
5992         default:
5993                 return -1;
5994         }
5995
5996         val /= mult;
5997         val -= base / mult;
5998         val += 0xbd;
5999
6000         if (val > 0xea)
6001                 val = 0xea;
6002
6003         return val;
6004 }
6005
6006 void intel_pm_init(struct drm_device *dev)
6007 {
6008         struct drm_i915_private *dev_priv = dev->dev_private;
6009
6010         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6011                           intel_gen6_powersave_work);
6012 }
6013