2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
47 static bool intel_crtc_active(struct drm_crtc *crtc)
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
55 static void i8xx_disable_fbc(struct drm_device *dev)
57 struct drm_i915_private *dev_priv = dev->dev_private;
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
74 DRM_DEBUG_KMS("disabled FBC\n");
77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
87 u32 fbc_ctl, fbc_ctl2;
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
120 static bool i8xx_fbc_enabled(struct drm_device *dev)
122 struct drm_i915_private *dev_priv = dev->dev_private;
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
154 static void g4x_disable_fbc(struct drm_device *dev)
156 struct drm_i915_private *dev_priv = dev->dev_private;
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
165 DRM_DEBUG_KMS("disabled FBC\n");
169 static bool g4x_fbc_enabled(struct drm_device *dev)
171 struct drm_i915_private *dev_priv = dev->dev_private;
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
178 struct drm_i915_private *dev_priv = dev->dev_private;
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
234 static void ironlake_disable_fbc(struct drm_device *dev)
236 struct drm_i915_private *dev_priv = dev->dev_private;
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
245 if (IS_IVYBRIDGE(dev))
246 /* WaFbcDisableDpfcClockGating:ivb */
247 I915_WRITE(ILK_DSPCLK_GATE_D,
248 I915_READ(ILK_DSPCLK_GATE_D) &
249 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
252 /* WaFbcDisableDpfcClockGating:hsw */
253 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
254 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
255 ~HSW_DPFC_GATING_DISABLE);
257 DRM_DEBUG_KMS("disabled FBC\n");
261 static bool ironlake_fbc_enabled(struct drm_device *dev)
263 struct drm_i915_private *dev_priv = dev->dev_private;
265 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
268 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
270 struct drm_device *dev = crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 struct drm_framebuffer *fb = crtc->fb;
273 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
277 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN |
281 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
283 if (IS_IVYBRIDGE(dev)) {
284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
285 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
286 /* WaFbcDisableDpfcClockGating:ivb */
287 I915_WRITE(ILK_DSPCLK_GATE_D,
288 I915_READ(ILK_DSPCLK_GATE_D) |
289 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
291 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
292 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
293 HSW_BYPASS_FBC_QUEUE);
294 /* WaFbcDisableDpfcClockGating:hsw */
295 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
296 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
297 HSW_DPFC_GATING_DISABLE);
300 I915_WRITE(SNB_DPFC_CTL_SA,
301 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
302 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304 sandybridge_blit_fbc_update(dev);
306 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
309 bool intel_fbc_enabled(struct drm_device *dev)
311 struct drm_i915_private *dev_priv = dev->dev_private;
313 if (!dev_priv->display.fbc_enabled)
316 return dev_priv->display.fbc_enabled(dev);
319 static void intel_fbc_work_fn(struct work_struct *__work)
321 struct intel_fbc_work *work =
322 container_of(to_delayed_work(__work),
323 struct intel_fbc_work, work);
324 struct drm_device *dev = work->crtc->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
327 mutex_lock(&dev->struct_mutex);
328 if (work == dev_priv->fbc_work) {
329 /* Double check that we haven't switched fb without cancelling
332 if (work->crtc->fb == work->fb) {
333 dev_priv->display.enable_fbc(work->crtc,
336 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->cfb_fb = work->crtc->fb->base.id;
338 dev_priv->cfb_y = work->crtc->y;
341 dev_priv->fbc_work = NULL;
343 mutex_unlock(&dev->struct_mutex);
348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
350 if (dev_priv->fbc_work == NULL)
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
359 if (cancel_delayed_work(&dev_priv->fbc_work->work))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv->fbc_work);
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
368 dev_priv->fbc_work = NULL;
371 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
377 if (!dev_priv->display.enable_fbc)
380 intel_cancel_fbc_work(dev_priv);
382 work = kzalloc(sizeof *work, GFP_KERNEL);
384 dev_priv->display.enable_fbc(crtc, interval);
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
393 dev_priv->fbc_work = work;
395 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
397 /* Delay the actual enabling to let pageflipping cease and the
398 * display to settle before starting the compression. Note that
399 * this delay also serves a second purpose: it allows for a
400 * vblank to pass after disabling the FBC before we attempt
401 * to modify the control registers.
403 * A more complicated solution would involve tracking vblanks
404 * following the termination of the page-flipping sequence
405 * and indeed performing the enable as a co-routine and not
406 * waiting synchronously upon the vblank.
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
411 void intel_disable_fbc(struct drm_device *dev)
413 struct drm_i915_private *dev_priv = dev->dev_private;
415 intel_cancel_fbc_work(dev_priv);
417 if (!dev_priv->display.disable_fbc)
420 dev_priv->display.disable_fbc(dev);
421 dev_priv->cfb_plane = -1;
425 * intel_update_fbc - enable/disable FBC as needed
426 * @dev: the drm_device
428 * Set up the framebuffer compression hardware at mode set time. We
429 * enable it if possible:
430 * - plane A only (on pre-965)
431 * - no pixel mulitply/line duplication
432 * - no alpha buffer discard
434 * - framebuffer <= 2048 in width, 1536 in height
436 * We can't assume that any compression will take place (worst case),
437 * so the compressed buffer has to be the same size as the uncompressed
438 * one. It also must reside (along with the line length buffer) in
441 * We need to enable/disable FBC on a global basis.
443 void intel_update_fbc(struct drm_device *dev)
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 struct drm_crtc *crtc = NULL, *tmp_crtc;
447 struct intel_crtc *intel_crtc;
448 struct drm_framebuffer *fb;
449 struct intel_framebuffer *intel_fb;
450 struct drm_i915_gem_object *obj;
456 if (!I915_HAS_FBC(dev))
460 * If FBC is already on, we just have to verify that we can
461 * keep it that way...
462 * Need to disable if:
463 * - more than one pipe is active
464 * - changing FBC params (stride, fence, mode)
465 * - new fb is too large to fit in compressed buffer
466 * - going to an unsupported config (interlace, pixel multiply, etc.)
468 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
469 if (intel_crtc_active(tmp_crtc) &&
470 !to_intel_crtc(tmp_crtc)->primary_disabled) {
472 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
473 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
480 if (!crtc || crtc->fb == NULL) {
481 DRM_DEBUG_KMS("no output, disabling\n");
482 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
486 intel_crtc = to_intel_crtc(crtc);
488 intel_fb = to_intel_framebuffer(fb);
491 enable_fbc = i915_enable_fbc;
492 if (enable_fbc < 0) {
493 DRM_DEBUG_KMS("fbc set to per-chip default\n");
495 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
499 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
503 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
504 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
505 DRM_DEBUG_KMS("mode incompatible with compression, "
507 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
510 if ((crtc->mode.hdisplay > 2048) ||
511 (crtc->mode.vdisplay > 1536)) {
512 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
513 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
516 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
517 intel_crtc->plane != 0) {
518 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
519 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
523 /* The use of a CPU fence is mandatory in order to detect writes
524 * by the CPU to the scanout and trigger updates to the FBC.
526 if (obj->tiling_mode != I915_TILING_X ||
527 obj->fence_reg == I915_FENCE_REG_NONE) {
528 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
529 dev_priv->no_fbc_reason = FBC_NOT_TILED;
533 /* If the kernel debugger is active, always disable compression */
537 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
538 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
539 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
543 /* If the scanout has not changed, don't modify the FBC settings.
544 * Note that we make the fundamental assumption that the fb->obj
545 * cannot be unpinned (and have its GTT offset and fence revoked)
546 * without first being decoupled from the scanout and FBC disabled.
548 if (dev_priv->cfb_plane == intel_crtc->plane &&
549 dev_priv->cfb_fb == fb->base.id &&
550 dev_priv->cfb_y == crtc->y)
553 if (intel_fbc_enabled(dev)) {
554 /* We update FBC along two paths, after changing fb/crtc
555 * configuration (modeswitching) and after page-flipping
556 * finishes. For the latter, we know that not only did
557 * we disable the FBC at the start of the page-flip
558 * sequence, but also more than one vblank has passed.
560 * For the former case of modeswitching, it is possible
561 * to switch between two FBC valid configurations
562 * instantaneously so we do need to disable the FBC
563 * before we can modify its control registers. We also
564 * have to wait for the next vblank for that to take
565 * effect. However, since we delay enabling FBC we can
566 * assume that a vblank has passed since disabling and
567 * that we can safely alter the registers in the deferred
570 * In the scenario that we go from a valid to invalid
571 * and then back to valid FBC configuration we have
572 * no strict enforcement that a vblank occurred since
573 * disabling the FBC. However, along all current pipe
574 * disabling paths we do need to wait for a vblank at
575 * some point. And we wait before enabling FBC anyway.
577 DRM_DEBUG_KMS("disabling active FBC for update\n");
578 intel_disable_fbc(dev);
581 intel_enable_fbc(crtc, 500);
585 /* Multiple disables should be harmless */
586 if (intel_fbc_enabled(dev)) {
587 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
588 intel_disable_fbc(dev);
590 i915_gem_stolen_cleanup_compression(dev);
593 static void i915_pineview_get_mem_freq(struct drm_device *dev)
595 drm_i915_private_t *dev_priv = dev->dev_private;
598 tmp = I915_READ(CLKCFG);
600 switch (tmp & CLKCFG_FSB_MASK) {
602 dev_priv->fsb_freq = 533; /* 133*4 */
605 dev_priv->fsb_freq = 800; /* 200*4 */
608 dev_priv->fsb_freq = 667; /* 167*4 */
611 dev_priv->fsb_freq = 400; /* 100*4 */
615 switch (tmp & CLKCFG_MEM_MASK) {
617 dev_priv->mem_freq = 533;
620 dev_priv->mem_freq = 667;
623 dev_priv->mem_freq = 800;
627 /* detect pineview DDR3 setting */
628 tmp = I915_READ(CSHRDDR3CTL);
629 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
632 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
634 drm_i915_private_t *dev_priv = dev->dev_private;
637 ddrpll = I915_READ16(DDRMPLL1);
638 csipll = I915_READ16(CSIPLL0);
640 switch (ddrpll & 0xff) {
642 dev_priv->mem_freq = 800;
645 dev_priv->mem_freq = 1066;
648 dev_priv->mem_freq = 1333;
651 dev_priv->mem_freq = 1600;
654 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
656 dev_priv->mem_freq = 0;
660 dev_priv->ips.r_t = dev_priv->mem_freq;
662 switch (csipll & 0x3ff) {
664 dev_priv->fsb_freq = 3200;
667 dev_priv->fsb_freq = 3733;
670 dev_priv->fsb_freq = 4266;
673 dev_priv->fsb_freq = 4800;
676 dev_priv->fsb_freq = 5333;
679 dev_priv->fsb_freq = 5866;
682 dev_priv->fsb_freq = 6400;
685 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
687 dev_priv->fsb_freq = 0;
691 if (dev_priv->fsb_freq == 3200) {
692 dev_priv->ips.c_m = 0;
693 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
694 dev_priv->ips.c_m = 1;
696 dev_priv->ips.c_m = 2;
700 static const struct cxsr_latency cxsr_latency_table[] = {
701 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
702 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
703 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
704 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
705 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
707 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
708 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
709 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
710 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
711 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
713 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
714 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
715 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
716 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
717 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
719 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
720 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
721 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
722 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
723 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
725 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
726 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
727 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
728 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
729 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
731 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
732 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
733 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
734 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
735 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
738 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
743 const struct cxsr_latency *latency;
746 if (fsb == 0 || mem == 0)
749 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
750 latency = &cxsr_latency_table[i];
751 if (is_desktop == latency->is_desktop &&
752 is_ddr3 == latency->is_ddr3 &&
753 fsb == latency->fsb_freq && mem == latency->mem_freq)
757 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
762 static void pineview_disable_cxsr(struct drm_device *dev)
764 struct drm_i915_private *dev_priv = dev->dev_private;
766 /* deactivate cxsr */
767 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
771 * Latency for FIFO fetches is dependent on several factors:
772 * - memory configuration (speed, channels)
774 * - current MCH state
775 * It can be fairly high in some situations, so here we assume a fairly
776 * pessimal value. It's a tradeoff between extra memory fetches (if we
777 * set this value too high, the FIFO will fetch frequently to stay full)
778 * and power consumption (set it too low to save power and we might see
779 * FIFO underruns and display "flicker").
781 * A value of 5us seems to be a good balance; safe for very low end
782 * platforms but not overly aggressive on lower latency configs.
784 static const int latency_ns = 5000;
786 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
788 struct drm_i915_private *dev_priv = dev->dev_private;
789 uint32_t dsparb = I915_READ(DSPARB);
792 size = dsparb & 0x7f;
794 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
796 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
797 plane ? "B" : "A", size);
802 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 uint32_t dsparb = I915_READ(DSPARB);
808 size = dsparb & 0x1ff;
810 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
811 size >>= 1; /* Convert to cachelines */
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
819 static int i845_get_fifo_size(struct drm_device *dev, int plane)
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
825 size = dsparb & 0x7f;
826 size >>= 2; /* Convert to cachelines */
828 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
835 static int i830_get_fifo_size(struct drm_device *dev, int plane)
837 struct drm_i915_private *dev_priv = dev->dev_private;
838 uint32_t dsparb = I915_READ(DSPARB);
841 size = dsparb & 0x7f;
842 size >>= 1; /* Convert to cachelines */
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
850 /* Pineview has different values for various configs */
851 static const struct intel_watermark_params pineview_display_wm = {
852 PINEVIEW_DISPLAY_FIFO,
856 PINEVIEW_FIFO_LINE_SIZE
858 static const struct intel_watermark_params pineview_display_hplloff_wm = {
859 PINEVIEW_DISPLAY_FIFO,
861 PINEVIEW_DFT_HPLLOFF_WM,
863 PINEVIEW_FIFO_LINE_SIZE
865 static const struct intel_watermark_params pineview_cursor_wm = {
866 PINEVIEW_CURSOR_FIFO,
867 PINEVIEW_CURSOR_MAX_WM,
868 PINEVIEW_CURSOR_DFT_WM,
869 PINEVIEW_CURSOR_GUARD_WM,
870 PINEVIEW_FIFO_LINE_SIZE,
872 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
873 PINEVIEW_CURSOR_FIFO,
874 PINEVIEW_CURSOR_MAX_WM,
875 PINEVIEW_CURSOR_DFT_WM,
876 PINEVIEW_CURSOR_GUARD_WM,
877 PINEVIEW_FIFO_LINE_SIZE
879 static const struct intel_watermark_params g4x_wm_info = {
886 static const struct intel_watermark_params g4x_cursor_wm_info = {
893 static const struct intel_watermark_params valleyview_wm_info = {
894 VALLEYVIEW_FIFO_SIZE,
900 static const struct intel_watermark_params valleyview_cursor_wm_info = {
902 VALLEYVIEW_CURSOR_MAX_WM,
907 static const struct intel_watermark_params i965_cursor_wm_info = {
914 static const struct intel_watermark_params i945_wm_info = {
921 static const struct intel_watermark_params i915_wm_info = {
928 static const struct intel_watermark_params i855_wm_info = {
935 static const struct intel_watermark_params i830_wm_info = {
943 static const struct intel_watermark_params ironlake_display_wm_info = {
950 static const struct intel_watermark_params ironlake_cursor_wm_info = {
957 static const struct intel_watermark_params ironlake_display_srwm_info = {
959 ILK_DISPLAY_MAX_SRWM,
960 ILK_DISPLAY_DFT_SRWM,
964 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
972 static const struct intel_watermark_params sandybridge_display_wm_info = {
979 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
986 static const struct intel_watermark_params sandybridge_display_srwm_info = {
988 SNB_DISPLAY_MAX_SRWM,
989 SNB_DISPLAY_DFT_SRWM,
993 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1003 * intel_calculate_wm - calculate watermark level
1004 * @clock_in_khz: pixel clock
1005 * @wm: chip FIFO params
1006 * @pixel_size: display pixel size
1007 * @latency_ns: memory latency for the platform
1009 * Calculate the watermark level (the level at which the display plane will
1010 * start fetching from memory again). Each chip has a different display
1011 * FIFO size and allocation, so the caller needs to figure that out and pass
1012 * in the correct intel_watermark_params structure.
1014 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1015 * on the pixel size. When it reaches the watermark level, it'll start
1016 * fetching FIFO line sized based chunks from memory until the FIFO fills
1017 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1018 * will occur, and a display engine hang could result.
1020 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1021 const struct intel_watermark_params *wm,
1024 unsigned long latency_ns)
1026 long entries_required, wm_size;
1029 * Note: we need to make sure we don't overflow for various clock &
1031 * clocks go from a few thousand to several hundred thousand.
1032 * latency is usually a few thousand
1034 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1036 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1038 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1040 wm_size = fifo_size - (entries_required + wm->guard_size);
1042 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1044 /* Don't promote wm_size to unsigned... */
1045 if (wm_size > (long)wm->max_wm)
1046 wm_size = wm->max_wm;
1048 wm_size = wm->default_wm;
1052 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1054 struct drm_crtc *crtc, *enabled = NULL;
1056 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1057 if (intel_crtc_active(crtc)) {
1067 static void pineview_update_wm(struct drm_device *dev)
1069 struct drm_i915_private *dev_priv = dev->dev_private;
1070 struct drm_crtc *crtc;
1071 const struct cxsr_latency *latency;
1075 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1076 dev_priv->fsb_freq, dev_priv->mem_freq);
1078 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1079 pineview_disable_cxsr(dev);
1083 crtc = single_enabled_crtc(dev);
1085 int clock = crtc->mode.clock;
1086 int pixel_size = crtc->fb->bits_per_pixel / 8;
1089 wm = intel_calculate_wm(clock, &pineview_display_wm,
1090 pineview_display_wm.fifo_size,
1091 pixel_size, latency->display_sr);
1092 reg = I915_READ(DSPFW1);
1093 reg &= ~DSPFW_SR_MASK;
1094 reg |= wm << DSPFW_SR_SHIFT;
1095 I915_WRITE(DSPFW1, reg);
1096 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1099 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1100 pineview_display_wm.fifo_size,
1101 pixel_size, latency->cursor_sr);
1102 reg = I915_READ(DSPFW3);
1103 reg &= ~DSPFW_CURSOR_SR_MASK;
1104 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1105 I915_WRITE(DSPFW3, reg);
1107 /* Display HPLL off SR */
1108 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1109 pineview_display_hplloff_wm.fifo_size,
1110 pixel_size, latency->display_hpll_disable);
1111 reg = I915_READ(DSPFW3);
1112 reg &= ~DSPFW_HPLL_SR_MASK;
1113 reg |= wm & DSPFW_HPLL_SR_MASK;
1114 I915_WRITE(DSPFW3, reg);
1116 /* cursor HPLL off SR */
1117 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1118 pineview_display_hplloff_wm.fifo_size,
1119 pixel_size, latency->cursor_hpll_disable);
1120 reg = I915_READ(DSPFW3);
1121 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1122 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1123 I915_WRITE(DSPFW3, reg);
1124 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1128 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1129 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1131 pineview_disable_cxsr(dev);
1132 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1136 static bool g4x_compute_wm0(struct drm_device *dev,
1138 const struct intel_watermark_params *display,
1139 int display_latency_ns,
1140 const struct intel_watermark_params *cursor,
1141 int cursor_latency_ns,
1145 struct drm_crtc *crtc;
1146 int htotal, hdisplay, clock, pixel_size;
1147 int line_time_us, line_count;
1148 int entries, tlb_miss;
1150 crtc = intel_get_crtc_for_plane(dev, plane);
1151 if (!intel_crtc_active(crtc)) {
1152 *cursor_wm = cursor->guard_size;
1153 *plane_wm = display->guard_size;
1157 htotal = crtc->mode.htotal;
1158 hdisplay = crtc->mode.hdisplay;
1159 clock = crtc->mode.clock;
1160 pixel_size = crtc->fb->bits_per_pixel / 8;
1162 /* Use the small buffer method to calculate plane watermark */
1163 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1164 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1166 entries += tlb_miss;
1167 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1168 *plane_wm = entries + display->guard_size;
1169 if (*plane_wm > (int)display->max_wm)
1170 *plane_wm = display->max_wm;
1172 /* Use the large buffer method to calculate cursor watermark */
1173 line_time_us = ((htotal * 1000) / clock);
1174 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1175 entries = line_count * 64 * pixel_size;
1176 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1178 entries += tlb_miss;
1179 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1180 *cursor_wm = entries + cursor->guard_size;
1181 if (*cursor_wm > (int)cursor->max_wm)
1182 *cursor_wm = (int)cursor->max_wm;
1188 * Check the wm result.
1190 * If any calculated watermark values is larger than the maximum value that
1191 * can be programmed into the associated watermark register, that watermark
1194 static bool g4x_check_srwm(struct drm_device *dev,
1195 int display_wm, int cursor_wm,
1196 const struct intel_watermark_params *display,
1197 const struct intel_watermark_params *cursor)
1199 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1200 display_wm, cursor_wm);
1202 if (display_wm > display->max_wm) {
1203 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1204 display_wm, display->max_wm);
1208 if (cursor_wm > cursor->max_wm) {
1209 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1210 cursor_wm, cursor->max_wm);
1214 if (!(display_wm || cursor_wm)) {
1215 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1222 static bool g4x_compute_srwm(struct drm_device *dev,
1225 const struct intel_watermark_params *display,
1226 const struct intel_watermark_params *cursor,
1227 int *display_wm, int *cursor_wm)
1229 struct drm_crtc *crtc;
1230 int hdisplay, htotal, pixel_size, clock;
1231 unsigned long line_time_us;
1232 int line_count, line_size;
1237 *display_wm = *cursor_wm = 0;
1241 crtc = intel_get_crtc_for_plane(dev, plane);
1242 hdisplay = crtc->mode.hdisplay;
1243 htotal = crtc->mode.htotal;
1244 clock = crtc->mode.clock;
1245 pixel_size = crtc->fb->bits_per_pixel / 8;
1247 line_time_us = (htotal * 1000) / clock;
1248 line_count = (latency_ns / line_time_us + 1000) / 1000;
1249 line_size = hdisplay * pixel_size;
1251 /* Use the minimum of the small and large buffer method for primary */
1252 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1253 large = line_count * line_size;
1255 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1256 *display_wm = entries + display->guard_size;
1258 /* calculate the self-refresh watermark for display cursor */
1259 entries = line_count * pixel_size * 64;
1260 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1261 *cursor_wm = entries + cursor->guard_size;
1263 return g4x_check_srwm(dev,
1264 *display_wm, *cursor_wm,
1268 static bool vlv_compute_drain_latency(struct drm_device *dev,
1270 int *plane_prec_mult,
1272 int *cursor_prec_mult,
1275 struct drm_crtc *crtc;
1276 int clock, pixel_size;
1279 crtc = intel_get_crtc_for_plane(dev, plane);
1280 if (!intel_crtc_active(crtc))
1283 clock = crtc->mode.clock; /* VESA DOT Clock */
1284 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1286 entries = (clock / 1000) * pixel_size;
1287 *plane_prec_mult = (entries > 256) ?
1288 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1289 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1292 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1293 *cursor_prec_mult = (entries > 256) ?
1294 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1295 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1301 * Update drain latency registers of memory arbiter
1303 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1304 * to be programmed. Each plane has a drain latency multiplier and a drain
1308 static void vlv_update_drain_latency(struct drm_device *dev)
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1312 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1313 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1316 /* For plane A, Cursor A */
1317 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1318 &cursor_prec_mult, &cursora_dl)) {
1319 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1320 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1321 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1322 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1324 I915_WRITE(VLV_DDL1, cursora_prec |
1325 (cursora_dl << DDL_CURSORA_SHIFT) |
1326 planea_prec | planea_dl);
1329 /* For plane B, Cursor B */
1330 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1331 &cursor_prec_mult, &cursorb_dl)) {
1332 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1333 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1334 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1335 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1337 I915_WRITE(VLV_DDL2, cursorb_prec |
1338 (cursorb_dl << DDL_CURSORB_SHIFT) |
1339 planeb_prec | planeb_dl);
1343 #define single_plane_enabled(mask) is_power_of_2(mask)
1345 static void valleyview_update_wm(struct drm_device *dev)
1347 static const int sr_latency_ns = 12000;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350 int plane_sr, cursor_sr;
1351 int ignore_plane_sr, ignore_cursor_sr;
1352 unsigned int enabled = 0;
1354 vlv_update_drain_latency(dev);
1356 if (g4x_compute_wm0(dev, PIPE_A,
1357 &valleyview_wm_info, latency_ns,
1358 &valleyview_cursor_wm_info, latency_ns,
1359 &planea_wm, &cursora_wm))
1360 enabled |= 1 << PIPE_A;
1362 if (g4x_compute_wm0(dev, PIPE_B,
1363 &valleyview_wm_info, latency_ns,
1364 &valleyview_cursor_wm_info, latency_ns,
1365 &planeb_wm, &cursorb_wm))
1366 enabled |= 1 << PIPE_B;
1368 if (single_plane_enabled(enabled) &&
1369 g4x_compute_srwm(dev, ffs(enabled) - 1,
1371 &valleyview_wm_info,
1372 &valleyview_cursor_wm_info,
1373 &plane_sr, &ignore_cursor_sr) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1376 &valleyview_wm_info,
1377 &valleyview_cursor_wm_info,
1378 &ignore_plane_sr, &cursor_sr)) {
1379 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1381 I915_WRITE(FW_BLC_SELF_VLV,
1382 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1383 plane_sr = cursor_sr = 0;
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387 planea_wm, cursora_wm,
1388 planeb_wm, cursorb_wm,
1389 plane_sr, cursor_sr);
1392 (plane_sr << DSPFW_SR_SHIFT) |
1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1398 (cursora_wm << DSPFW_CURSORA_SHIFT));
1400 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1401 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1404 static void g4x_update_wm(struct drm_device *dev)
1406 static const int sr_latency_ns = 12000;
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1409 int plane_sr, cursor_sr;
1410 unsigned int enabled = 0;
1412 if (g4x_compute_wm0(dev, PIPE_A,
1413 &g4x_wm_info, latency_ns,
1414 &g4x_cursor_wm_info, latency_ns,
1415 &planea_wm, &cursora_wm))
1416 enabled |= 1 << PIPE_A;
1418 if (g4x_compute_wm0(dev, PIPE_B,
1419 &g4x_wm_info, latency_ns,
1420 &g4x_cursor_wm_info, latency_ns,
1421 &planeb_wm, &cursorb_wm))
1422 enabled |= 1 << PIPE_B;
1424 if (single_plane_enabled(enabled) &&
1425 g4x_compute_srwm(dev, ffs(enabled) - 1,
1428 &g4x_cursor_wm_info,
1429 &plane_sr, &cursor_sr)) {
1430 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1432 I915_WRITE(FW_BLC_SELF,
1433 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1434 plane_sr = cursor_sr = 0;
1437 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1438 planea_wm, cursora_wm,
1439 planeb_wm, cursorb_wm,
1440 plane_sr, cursor_sr);
1443 (plane_sr << DSPFW_SR_SHIFT) |
1444 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1445 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1448 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1449 (cursora_wm << DSPFW_CURSORA_SHIFT));
1450 /* HPLL off in SR has some issues on G4x... disable it */
1452 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1453 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1456 static void i965_update_wm(struct drm_device *dev)
1458 struct drm_i915_private *dev_priv = dev->dev_private;
1459 struct drm_crtc *crtc;
1463 /* Calc sr entries for one plane configs */
1464 crtc = single_enabled_crtc(dev);
1466 /* self-refresh has much higher latency */
1467 static const int sr_latency_ns = 12000;
1468 int clock = crtc->mode.clock;
1469 int htotal = crtc->mode.htotal;
1470 int hdisplay = crtc->mode.hdisplay;
1471 int pixel_size = crtc->fb->bits_per_pixel / 8;
1472 unsigned long line_time_us;
1475 line_time_us = ((htotal * 1000) / clock);
1477 /* Use ns/us then divide to preserve precision */
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479 pixel_size * hdisplay;
1480 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1481 srwm = I965_FIFO_SIZE - entries;
1485 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1488 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1490 entries = DIV_ROUND_UP(entries,
1491 i965_cursor_wm_info.cacheline_size);
1492 cursor_sr = i965_cursor_wm_info.fifo_size -
1493 (entries + i965_cursor_wm_info.guard_size);
1495 if (cursor_sr > i965_cursor_wm_info.max_wm)
1496 cursor_sr = i965_cursor_wm_info.max_wm;
1498 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499 "cursor %d\n", srwm, cursor_sr);
1501 if (IS_CRESTLINE(dev))
1502 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1504 /* Turn off self refresh if both pipes are enabled */
1505 if (IS_CRESTLINE(dev))
1506 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1510 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1513 /* 965 has limitations... */
1514 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1515 (8 << 16) | (8 << 8) | (8 << 0));
1516 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1517 /* update cursor SR watermark */
1518 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1521 static void i9xx_update_wm(struct drm_device *dev)
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 const struct intel_watermark_params *wm_info;
1529 int planea_wm, planeb_wm;
1530 struct drm_crtc *crtc, *enabled = NULL;
1533 wm_info = &i945_wm_info;
1534 else if (!IS_GEN2(dev))
1535 wm_info = &i915_wm_info;
1537 wm_info = &i855_wm_info;
1539 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540 crtc = intel_get_crtc_for_plane(dev, 0);
1541 if (intel_crtc_active(crtc)) {
1542 int cpp = crtc->fb->bits_per_pixel / 8;
1546 planea_wm = intel_calculate_wm(crtc->mode.clock,
1547 wm_info, fifo_size, cpp,
1551 planea_wm = fifo_size - wm_info->guard_size;
1553 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554 crtc = intel_get_crtc_for_plane(dev, 1);
1555 if (intel_crtc_active(crtc)) {
1556 int cpp = crtc->fb->bits_per_pixel / 8;
1560 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1561 wm_info, fifo_size, cpp,
1563 if (enabled == NULL)
1568 planeb_wm = fifo_size - wm_info->guard_size;
1570 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1573 * Overlay gets an aggressive default since video jitter is bad.
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
1578 if (IS_I945G(dev) || IS_I945GM(dev))
1579 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1580 else if (IS_I915GM(dev))
1581 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1583 /* Calc sr entries for one plane configs */
1584 if (HAS_FW_BLC(dev) && enabled) {
1585 /* self-refresh has much higher latency */
1586 static const int sr_latency_ns = 6000;
1587 int clock = enabled->mode.clock;
1588 int htotal = enabled->mode.htotal;
1589 int hdisplay = enabled->mode.hdisplay;
1590 int pixel_size = enabled->fb->bits_per_pixel / 8;
1591 unsigned long line_time_us;
1594 line_time_us = (htotal * 1000) / clock;
1596 /* Use ns/us then divide to preserve precision */
1597 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1598 pixel_size * hdisplay;
1599 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1600 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1601 srwm = wm_info->fifo_size - entries;
1605 if (IS_I945G(dev) || IS_I945GM(dev))
1606 I915_WRITE(FW_BLC_SELF,
1607 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1608 else if (IS_I915GM(dev))
1609 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1612 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613 planea_wm, planeb_wm, cwm, srwm);
1615 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1616 fwater_hi = (cwm & 0x1f);
1618 /* Set request length to 8 cachelines per fetch */
1619 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1620 fwater_hi = fwater_hi | (1 << 8);
1622 I915_WRITE(FW_BLC, fwater_lo);
1623 I915_WRITE(FW_BLC2, fwater_hi);
1625 if (HAS_FW_BLC(dev)) {
1627 if (IS_I945G(dev) || IS_I945GM(dev))
1628 I915_WRITE(FW_BLC_SELF,
1629 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1630 else if (IS_I915GM(dev))
1631 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1632 DRM_DEBUG_KMS("memory self refresh enabled\n");
1634 DRM_DEBUG_KMS("memory self refresh disabled\n");
1638 static void i830_update_wm(struct drm_device *dev)
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 struct drm_crtc *crtc;
1645 crtc = single_enabled_crtc(dev);
1649 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1650 dev_priv->display.get_fifo_size(dev, 0),
1652 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1653 fwater_lo |= (3<<8) | planea_wm;
1655 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1657 I915_WRITE(FW_BLC, fwater_lo);
1660 #define ILK_LP0_PLANE_LATENCY 700
1661 #define ILK_LP0_CURSOR_LATENCY 1300
1664 * Check the wm result.
1666 * If any calculated watermark values is larger than the maximum value that
1667 * can be programmed into the associated watermark register, that watermark
1670 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1671 int fbc_wm, int display_wm, int cursor_wm,
1672 const struct intel_watermark_params *display,
1673 const struct intel_watermark_params *cursor)
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1677 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1678 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1680 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1681 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1682 fbc_wm, SNB_FBC_MAX_SRWM, level);
1684 /* fbc has it's own way to disable FBC WM */
1685 I915_WRITE(DISP_ARB_CTL,
1686 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1688 } else if (INTEL_INFO(dev)->gen >= 6) {
1689 /* enable FBC WM (except on ILK, where it must remain off) */
1690 I915_WRITE(DISP_ARB_CTL,
1691 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1694 if (display_wm > display->max_wm) {
1695 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1696 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1700 if (cursor_wm > cursor->max_wm) {
1701 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1702 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1706 if (!(fbc_wm || display_wm || cursor_wm)) {
1707 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1715 * Compute watermark values of WM[1-3],
1717 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1719 const struct intel_watermark_params *display,
1720 const struct intel_watermark_params *cursor,
1721 int *fbc_wm, int *display_wm, int *cursor_wm)
1723 struct drm_crtc *crtc;
1724 unsigned long line_time_us;
1725 int hdisplay, htotal, pixel_size, clock;
1726 int line_count, line_size;
1731 *fbc_wm = *display_wm = *cursor_wm = 0;
1735 crtc = intel_get_crtc_for_plane(dev, plane);
1736 hdisplay = crtc->mode.hdisplay;
1737 htotal = crtc->mode.htotal;
1738 clock = crtc->mode.clock;
1739 pixel_size = crtc->fb->bits_per_pixel / 8;
1741 line_time_us = (htotal * 1000) / clock;
1742 line_count = (latency_ns / line_time_us + 1000) / 1000;
1743 line_size = hdisplay * pixel_size;
1745 /* Use the minimum of the small and large buffer method for primary */
1746 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1747 large = line_count * line_size;
1749 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1750 *display_wm = entries + display->guard_size;
1754 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1756 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1758 /* calculate the self-refresh watermark for display cursor */
1759 entries = line_count * pixel_size * 64;
1760 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1761 *cursor_wm = entries + cursor->guard_size;
1763 return ironlake_check_srwm(dev, level,
1764 *fbc_wm, *display_wm, *cursor_wm,
1768 static void ironlake_update_wm(struct drm_device *dev)
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 int fbc_wm, plane_wm, cursor_wm;
1772 unsigned int enabled;
1775 if (g4x_compute_wm0(dev, PIPE_A,
1776 &ironlake_display_wm_info,
1777 ILK_LP0_PLANE_LATENCY,
1778 &ironlake_cursor_wm_info,
1779 ILK_LP0_CURSOR_LATENCY,
1780 &plane_wm, &cursor_wm)) {
1781 I915_WRITE(WM0_PIPEA_ILK,
1782 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1783 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1784 " plane %d, " "cursor: %d\n",
1785 plane_wm, cursor_wm);
1786 enabled |= 1 << PIPE_A;
1789 if (g4x_compute_wm0(dev, PIPE_B,
1790 &ironlake_display_wm_info,
1791 ILK_LP0_PLANE_LATENCY,
1792 &ironlake_cursor_wm_info,
1793 ILK_LP0_CURSOR_LATENCY,
1794 &plane_wm, &cursor_wm)) {
1795 I915_WRITE(WM0_PIPEB_ILK,
1796 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1797 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1798 " plane %d, cursor: %d\n",
1799 plane_wm, cursor_wm);
1800 enabled |= 1 << PIPE_B;
1804 * Calculate and update the self-refresh watermark only when one
1805 * display plane is used.
1807 I915_WRITE(WM3_LP_ILK, 0);
1808 I915_WRITE(WM2_LP_ILK, 0);
1809 I915_WRITE(WM1_LP_ILK, 0);
1811 if (!single_plane_enabled(enabled))
1813 enabled = ffs(enabled) - 1;
1816 if (!ironlake_compute_srwm(dev, 1, enabled,
1817 ILK_READ_WM1_LATENCY() * 500,
1818 &ironlake_display_srwm_info,
1819 &ironlake_cursor_srwm_info,
1820 &fbc_wm, &plane_wm, &cursor_wm))
1823 I915_WRITE(WM1_LP_ILK,
1825 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1826 (fbc_wm << WM1_LP_FBC_SHIFT) |
1827 (plane_wm << WM1_LP_SR_SHIFT) |
1831 if (!ironlake_compute_srwm(dev, 2, enabled,
1832 ILK_READ_WM2_LATENCY() * 500,
1833 &ironlake_display_srwm_info,
1834 &ironlake_cursor_srwm_info,
1835 &fbc_wm, &plane_wm, &cursor_wm))
1838 I915_WRITE(WM2_LP_ILK,
1840 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1841 (fbc_wm << WM1_LP_FBC_SHIFT) |
1842 (plane_wm << WM1_LP_SR_SHIFT) |
1846 * WM3 is unsupported on ILK, probably because we don't have latency
1847 * data for that power state
1851 static void sandybridge_update_wm(struct drm_device *dev)
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1856 int fbc_wm, plane_wm, cursor_wm;
1857 unsigned int enabled;
1860 if (g4x_compute_wm0(dev, PIPE_A,
1861 &sandybridge_display_wm_info, latency,
1862 &sandybridge_cursor_wm_info, latency,
1863 &plane_wm, &cursor_wm)) {
1864 val = I915_READ(WM0_PIPEA_ILK);
1865 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1866 I915_WRITE(WM0_PIPEA_ILK, val |
1867 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1868 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1869 " plane %d, " "cursor: %d\n",
1870 plane_wm, cursor_wm);
1871 enabled |= 1 << PIPE_A;
1874 if (g4x_compute_wm0(dev, PIPE_B,
1875 &sandybridge_display_wm_info, latency,
1876 &sandybridge_cursor_wm_info, latency,
1877 &plane_wm, &cursor_wm)) {
1878 val = I915_READ(WM0_PIPEB_ILK);
1879 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1880 I915_WRITE(WM0_PIPEB_ILK, val |
1881 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1882 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1883 " plane %d, cursor: %d\n",
1884 plane_wm, cursor_wm);
1885 enabled |= 1 << PIPE_B;
1889 * Calculate and update the self-refresh watermark only when one
1890 * display plane is used.
1892 * SNB support 3 levels of watermark.
1894 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1895 * and disabled in the descending order
1898 I915_WRITE(WM3_LP_ILK, 0);
1899 I915_WRITE(WM2_LP_ILK, 0);
1900 I915_WRITE(WM1_LP_ILK, 0);
1902 if (!single_plane_enabled(enabled) ||
1903 dev_priv->sprite_scaling_enabled)
1905 enabled = ffs(enabled) - 1;
1908 if (!ironlake_compute_srwm(dev, 1, enabled,
1909 SNB_READ_WM1_LATENCY() * 500,
1910 &sandybridge_display_srwm_info,
1911 &sandybridge_cursor_srwm_info,
1912 &fbc_wm, &plane_wm, &cursor_wm))
1915 I915_WRITE(WM1_LP_ILK,
1917 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1918 (fbc_wm << WM1_LP_FBC_SHIFT) |
1919 (plane_wm << WM1_LP_SR_SHIFT) |
1923 if (!ironlake_compute_srwm(dev, 2, enabled,
1924 SNB_READ_WM2_LATENCY() * 500,
1925 &sandybridge_display_srwm_info,
1926 &sandybridge_cursor_srwm_info,
1927 &fbc_wm, &plane_wm, &cursor_wm))
1930 I915_WRITE(WM2_LP_ILK,
1932 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1933 (fbc_wm << WM1_LP_FBC_SHIFT) |
1934 (plane_wm << WM1_LP_SR_SHIFT) |
1938 if (!ironlake_compute_srwm(dev, 3, enabled,
1939 SNB_READ_WM3_LATENCY() * 500,
1940 &sandybridge_display_srwm_info,
1941 &sandybridge_cursor_srwm_info,
1942 &fbc_wm, &plane_wm, &cursor_wm))
1945 I915_WRITE(WM3_LP_ILK,
1947 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1948 (fbc_wm << WM1_LP_FBC_SHIFT) |
1949 (plane_wm << WM1_LP_SR_SHIFT) |
1953 static void ivybridge_update_wm(struct drm_device *dev)
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1958 int fbc_wm, plane_wm, cursor_wm;
1959 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1960 unsigned int enabled;
1963 if (g4x_compute_wm0(dev, PIPE_A,
1964 &sandybridge_display_wm_info, latency,
1965 &sandybridge_cursor_wm_info, latency,
1966 &plane_wm, &cursor_wm)) {
1967 val = I915_READ(WM0_PIPEA_ILK);
1968 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1969 I915_WRITE(WM0_PIPEA_ILK, val |
1970 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1971 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1972 " plane %d, " "cursor: %d\n",
1973 plane_wm, cursor_wm);
1974 enabled |= 1 << PIPE_A;
1977 if (g4x_compute_wm0(dev, PIPE_B,
1978 &sandybridge_display_wm_info, latency,
1979 &sandybridge_cursor_wm_info, latency,
1980 &plane_wm, &cursor_wm)) {
1981 val = I915_READ(WM0_PIPEB_ILK);
1982 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1983 I915_WRITE(WM0_PIPEB_ILK, val |
1984 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1985 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1986 " plane %d, cursor: %d\n",
1987 plane_wm, cursor_wm);
1988 enabled |= 1 << PIPE_B;
1991 if (g4x_compute_wm0(dev, PIPE_C,
1992 &sandybridge_display_wm_info, latency,
1993 &sandybridge_cursor_wm_info, latency,
1994 &plane_wm, &cursor_wm)) {
1995 val = I915_READ(WM0_PIPEC_IVB);
1996 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1997 I915_WRITE(WM0_PIPEC_IVB, val |
1998 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1999 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2000 " plane %d, cursor: %d\n",
2001 plane_wm, cursor_wm);
2002 enabled |= 1 << PIPE_C;
2006 * Calculate and update the self-refresh watermark only when one
2007 * display plane is used.
2009 * SNB support 3 levels of watermark.
2011 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2012 * and disabled in the descending order
2015 I915_WRITE(WM3_LP_ILK, 0);
2016 I915_WRITE(WM2_LP_ILK, 0);
2017 I915_WRITE(WM1_LP_ILK, 0);
2019 if (!single_plane_enabled(enabled) ||
2020 dev_priv->sprite_scaling_enabled)
2022 enabled = ffs(enabled) - 1;
2025 if (!ironlake_compute_srwm(dev, 1, enabled,
2026 SNB_READ_WM1_LATENCY() * 500,
2027 &sandybridge_display_srwm_info,
2028 &sandybridge_cursor_srwm_info,
2029 &fbc_wm, &plane_wm, &cursor_wm))
2032 I915_WRITE(WM1_LP_ILK,
2034 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2035 (fbc_wm << WM1_LP_FBC_SHIFT) |
2036 (plane_wm << WM1_LP_SR_SHIFT) |
2040 if (!ironlake_compute_srwm(dev, 2, enabled,
2041 SNB_READ_WM2_LATENCY() * 500,
2042 &sandybridge_display_srwm_info,
2043 &sandybridge_cursor_srwm_info,
2044 &fbc_wm, &plane_wm, &cursor_wm))
2047 I915_WRITE(WM2_LP_ILK,
2049 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2050 (fbc_wm << WM1_LP_FBC_SHIFT) |
2051 (plane_wm << WM1_LP_SR_SHIFT) |
2054 /* WM3, note we have to correct the cursor latency */
2055 if (!ironlake_compute_srwm(dev, 3, enabled,
2056 SNB_READ_WM3_LATENCY() * 500,
2057 &sandybridge_display_srwm_info,
2058 &sandybridge_cursor_srwm_info,
2059 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2060 !ironlake_compute_srwm(dev, 3, enabled,
2061 2 * SNB_READ_WM3_LATENCY() * 500,
2062 &sandybridge_display_srwm_info,
2063 &sandybridge_cursor_srwm_info,
2064 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2067 I915_WRITE(WM3_LP_ILK,
2069 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2070 (fbc_wm << WM1_LP_FBC_SHIFT) |
2071 (plane_wm << WM1_LP_SR_SHIFT) |
2076 haswell_update_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 enum pipe pipe = intel_crtc->pipe;
2081 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2082 u32 linetime, ips_linetime;
2084 if (!intel_crtc_active(crtc)) {
2085 I915_WRITE(PIPE_WM_LINETIME(pipe), 0);
2089 /* The WM are computed with base on how long it takes to fill a single
2090 * row at the given clock rate, multiplied by 8.
2092 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2093 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2094 intel_ddi_get_cdclk_freq(dev_priv));
2096 I915_WRITE(PIPE_WM_LINETIME(pipe),
2097 PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2098 PIPE_WM_LINETIME_TIME(linetime));
2101 static void haswell_update_wm(struct drm_device *dev)
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 struct drm_crtc *crtc;
2107 /* Disable the LP WMs before changine the linetime registers. This is
2108 * just a temporary code that will be replaced soon. */
2109 I915_WRITE(WM3_LP_ILK, 0);
2110 I915_WRITE(WM2_LP_ILK, 0);
2111 I915_WRITE(WM1_LP_ILK, 0);
2113 for_each_pipe(pipe) {
2114 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2115 haswell_update_linetime_wm(dev, crtc);
2118 sandybridge_update_wm(dev);
2122 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2123 uint32_t sprite_width, int pixel_size,
2124 const struct intel_watermark_params *display,
2125 int display_latency_ns, int *sprite_wm)
2127 struct drm_crtc *crtc;
2129 int entries, tlb_miss;
2131 crtc = intel_get_crtc_for_plane(dev, plane);
2132 if (!intel_crtc_active(crtc)) {
2133 *sprite_wm = display->guard_size;
2137 clock = crtc->mode.clock;
2139 /* Use the small buffer method to calculate the sprite watermark */
2140 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2141 tlb_miss = display->fifo_size*display->cacheline_size -
2144 entries += tlb_miss;
2145 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2146 *sprite_wm = entries + display->guard_size;
2147 if (*sprite_wm > (int)display->max_wm)
2148 *sprite_wm = display->max_wm;
2154 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2155 uint32_t sprite_width, int pixel_size,
2156 const struct intel_watermark_params *display,
2157 int latency_ns, int *sprite_wm)
2159 struct drm_crtc *crtc;
2160 unsigned long line_time_us;
2162 int line_count, line_size;
2171 crtc = intel_get_crtc_for_plane(dev, plane);
2172 clock = crtc->mode.clock;
2178 line_time_us = (sprite_width * 1000) / clock;
2179 if (!line_time_us) {
2184 line_count = (latency_ns / line_time_us + 1000) / 1000;
2185 line_size = sprite_width * pixel_size;
2187 /* Use the minimum of the small and large buffer method for primary */
2188 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2189 large = line_count * line_size;
2191 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2192 *sprite_wm = entries + display->guard_size;
2194 return *sprite_wm > 0x3ff ? false : true;
2197 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2198 uint32_t sprite_width, int pixel_size)
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2208 reg = WM0_PIPEA_ILK;
2211 reg = WM0_PIPEB_ILK;
2214 reg = WM0_PIPEC_IVB;
2217 return; /* bad pipe */
2220 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2221 &sandybridge_display_wm_info,
2222 latency, &sprite_wm);
2224 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2229 val = I915_READ(reg);
2230 val &= ~WM0_PIPE_SPRITE_MASK;
2231 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2232 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2235 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2237 &sandybridge_display_srwm_info,
2238 SNB_READ_WM1_LATENCY() * 500,
2241 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2245 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2247 /* Only IVB has two more LP watermarks for sprite */
2248 if (!IS_IVYBRIDGE(dev))
2251 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2253 &sandybridge_display_srwm_info,
2254 SNB_READ_WM2_LATENCY() * 500,
2257 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2261 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2263 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2265 &sandybridge_display_srwm_info,
2266 SNB_READ_WM3_LATENCY() * 500,
2269 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2273 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2277 * intel_update_watermarks - update FIFO watermark values based on current modes
2279 * Calculate watermark values for the various WM regs based on current mode
2280 * and plane configuration.
2282 * There are several cases to deal with here:
2283 * - normal (i.e. non-self-refresh)
2284 * - self-refresh (SR) mode
2285 * - lines are large relative to FIFO size (buffer can hold up to 2)
2286 * - lines are small relative to FIFO size (buffer can hold more than 2
2287 * lines), so need to account for TLB latency
2289 * The normal calculation is:
2290 * watermark = dotclock * bytes per pixel * latency
2291 * where latency is platform & configuration dependent (we assume pessimal
2294 * The SR calculation is:
2295 * watermark = (trunc(latency/line time)+1) * surface width *
2298 * line time = htotal / dotclock
2299 * surface width = hdisplay for normal plane and 64 for cursor
2300 * and latency is assumed to be high, as above.
2302 * The final value programmed to the register should always be rounded up,
2303 * and include an extra 2 entries to account for clock crossings.
2305 * We don't use the sprite, so we can ignore that. And on Crestline we have
2306 * to set the non-SR watermarks to 8.
2308 void intel_update_watermarks(struct drm_device *dev)
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2312 if (dev_priv->display.update_wm)
2313 dev_priv->display.update_wm(dev);
2316 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2317 uint32_t sprite_width, int pixel_size)
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2321 if (dev_priv->display.update_sprite_wm)
2322 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2326 static struct drm_i915_gem_object *
2327 intel_alloc_context_page(struct drm_device *dev)
2329 struct drm_i915_gem_object *ctx;
2332 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2334 ctx = i915_gem_alloc_object(dev, 4096);
2336 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2340 ret = i915_gem_object_pin(ctx, 4096, true, false);
2342 DRM_ERROR("failed to pin power context: %d\n", ret);
2346 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2348 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2355 i915_gem_object_unpin(ctx);
2357 drm_gem_object_unreference(&ctx->base);
2362 * Lock protecting IPS related data structures
2364 DEFINE_SPINLOCK(mchdev_lock);
2366 /* Global for IPS driver to get at the current i915 device. Protected by
2368 static struct drm_i915_private *i915_mch_dev;
2370 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2372 struct drm_i915_private *dev_priv = dev->dev_private;
2375 assert_spin_locked(&mchdev_lock);
2377 rgvswctl = I915_READ16(MEMSWCTL);
2378 if (rgvswctl & MEMCTL_CMD_STS) {
2379 DRM_DEBUG("gpu busy, RCS change rejected\n");
2380 return false; /* still busy with another command */
2383 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2384 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2385 I915_WRITE16(MEMSWCTL, rgvswctl);
2386 POSTING_READ16(MEMSWCTL);
2388 rgvswctl |= MEMCTL_CMD_STS;
2389 I915_WRITE16(MEMSWCTL, rgvswctl);
2394 static void ironlake_enable_drps(struct drm_device *dev)
2396 struct drm_i915_private *dev_priv = dev->dev_private;
2397 u32 rgvmodectl = I915_READ(MEMMODECTL);
2398 u8 fmax, fmin, fstart, vstart;
2400 spin_lock_irq(&mchdev_lock);
2402 /* Enable temp reporting */
2403 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2404 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2406 /* 100ms RC evaluation intervals */
2407 I915_WRITE(RCUPEI, 100000);
2408 I915_WRITE(RCDNEI, 100000);
2410 /* Set max/min thresholds to 90ms and 80ms respectively */
2411 I915_WRITE(RCBMAXAVG, 90000);
2412 I915_WRITE(RCBMINAVG, 80000);
2414 I915_WRITE(MEMIHYST, 1);
2416 /* Set up min, max, and cur for interrupt handling */
2417 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2418 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2419 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2420 MEMMODE_FSTART_SHIFT;
2422 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2425 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2426 dev_priv->ips.fstart = fstart;
2428 dev_priv->ips.max_delay = fstart;
2429 dev_priv->ips.min_delay = fmin;
2430 dev_priv->ips.cur_delay = fstart;
2432 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2433 fmax, fmin, fstart);
2435 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2438 * Interrupts will be enabled in ironlake_irq_postinstall
2441 I915_WRITE(VIDSTART, vstart);
2442 POSTING_READ(VIDSTART);
2444 rgvmodectl |= MEMMODE_SWMODE_EN;
2445 I915_WRITE(MEMMODECTL, rgvmodectl);
2447 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2448 DRM_ERROR("stuck trying to change perf mode\n");
2451 ironlake_set_drps(dev, fstart);
2453 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2455 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2456 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2457 getrawmonotonic(&dev_priv->ips.last_time2);
2459 spin_unlock_irq(&mchdev_lock);
2462 static void ironlake_disable_drps(struct drm_device *dev)
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2467 spin_lock_irq(&mchdev_lock);
2469 rgvswctl = I915_READ16(MEMSWCTL);
2471 /* Ack interrupts, disable EFC interrupt */
2472 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2473 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2474 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2475 I915_WRITE(DEIIR, DE_PCU_EVENT);
2476 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2478 /* Go back to the starting frequency */
2479 ironlake_set_drps(dev, dev_priv->ips.fstart);
2481 rgvswctl |= MEMCTL_CMD_STS;
2482 I915_WRITE(MEMSWCTL, rgvswctl);
2485 spin_unlock_irq(&mchdev_lock);
2488 /* There's a funny hw issue where the hw returns all 0 when reading from
2489 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2490 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2491 * all limits and the gpu stuck at whatever frequency it is at atm).
2493 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2499 if (*val >= dev_priv->rps.max_delay)
2500 *val = dev_priv->rps.max_delay;
2501 limits |= dev_priv->rps.max_delay << 24;
2503 /* Only set the down limit when we've reached the lowest level to avoid
2504 * getting more interrupts, otherwise leave this clear. This prevents a
2505 * race in the hw when coming out of rc6: There's a tiny window where
2506 * the hw runs at the minimal clock before selecting the desired
2507 * frequency, if the down threshold expires in that window we will not
2508 * receive a down interrupt. */
2509 if (*val <= dev_priv->rps.min_delay) {
2510 *val = dev_priv->rps.min_delay;
2511 limits |= dev_priv->rps.min_delay << 16;
2517 void gen6_set_rps(struct drm_device *dev, u8 val)
2519 struct drm_i915_private *dev_priv = dev->dev_private;
2520 u32 limits = gen6_rps_limits(dev_priv, &val);
2522 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2523 WARN_ON(val > dev_priv->rps.max_delay);
2524 WARN_ON(val < dev_priv->rps.min_delay);
2526 if (val == dev_priv->rps.cur_delay)
2529 if (IS_HASWELL(dev))
2530 I915_WRITE(GEN6_RPNSWREQ,
2531 HSW_FREQUENCY(val));
2533 I915_WRITE(GEN6_RPNSWREQ,
2534 GEN6_FREQUENCY(val) |
2536 GEN6_AGGRESSIVE_TURBO);
2538 /* Make sure we continue to get interrupts
2539 * until we hit the minimum or maximum frequencies.
2541 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2543 POSTING_READ(GEN6_RPNSWREQ);
2545 dev_priv->rps.cur_delay = val;
2547 trace_intel_gpu_freq_change(val * 50);
2550 void valleyview_set_rps(struct drm_device *dev, u8 val)
2552 struct drm_i915_private *dev_priv = dev->dev_private;
2553 unsigned long timeout = jiffies + msecs_to_jiffies(10);
2554 u32 limits = gen6_rps_limits(dev_priv, &val);
2557 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2558 WARN_ON(val > dev_priv->rps.max_delay);
2559 WARN_ON(val < dev_priv->rps.min_delay);
2561 DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2562 vlv_gpu_freq(dev_priv->mem_freq,
2563 dev_priv->rps.cur_delay),
2564 vlv_gpu_freq(dev_priv->mem_freq, val));
2566 if (val == dev_priv->rps.cur_delay)
2569 valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2572 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2573 if (time_after(jiffies, timeout)) {
2574 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2580 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2581 if ((pval >> 8) != val)
2582 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2585 /* Make sure we continue to get interrupts
2586 * until we hit the minimum or maximum frequencies.
2588 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2590 dev_priv->rps.cur_delay = pval >> 8;
2592 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2596 static void gen6_disable_rps(struct drm_device *dev)
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2600 I915_WRITE(GEN6_RC_CONTROL, 0);
2601 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2602 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2603 I915_WRITE(GEN6_PMIER, 0);
2604 /* Complete PM interrupt masking here doesn't race with the rps work
2605 * item again unmasking PM interrupts because that is using a different
2606 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2607 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2609 spin_lock_irq(&dev_priv->rps.lock);
2610 dev_priv->rps.pm_iir = 0;
2611 spin_unlock_irq(&dev_priv->rps.lock);
2613 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2616 static void valleyview_disable_rps(struct drm_device *dev)
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2620 I915_WRITE(GEN6_RC_CONTROL, 0);
2621 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2622 I915_WRITE(GEN6_PMIER, 0);
2623 /* Complete PM interrupt masking here doesn't race with the rps work
2624 * item again unmasking PM interrupts because that is using a different
2625 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2626 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2628 spin_lock_irq(&dev_priv->rps.lock);
2629 dev_priv->rps.pm_iir = 0;
2630 spin_unlock_irq(&dev_priv->rps.lock);
2632 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2634 if (dev_priv->vlv_pctx) {
2635 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2636 dev_priv->vlv_pctx = NULL;
2640 int intel_enable_rc6(const struct drm_device *dev)
2642 /* Respect the kernel parameter if it is set */
2643 if (i915_enable_rc6 >= 0)
2644 return i915_enable_rc6;
2646 /* Disable RC6 on Ironlake */
2647 if (INTEL_INFO(dev)->gen == 5)
2650 if (IS_HASWELL(dev)) {
2651 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2652 return INTEL_RC6_ENABLE;
2655 /* snb/ivb have more than one rc6 state. */
2656 if (INTEL_INFO(dev)->gen == 6) {
2657 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2658 return INTEL_RC6_ENABLE;
2661 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2662 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2665 static void gen6_enable_rps(struct drm_device *dev)
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668 struct intel_ring_buffer *ring;
2671 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2676 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2678 /* Here begins a magic sequence of register writes to enable
2679 * auto-downclocking.
2681 * Perhaps there might be some value in exposing these to
2684 I915_WRITE(GEN6_RC_STATE, 0);
2686 /* Clear the DBG now so we don't confuse earlier errors */
2687 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2688 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2689 I915_WRITE(GTFIFODBG, gtfifodbg);
2692 gen6_gt_force_wake_get(dev_priv);
2694 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2695 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2697 /* In units of 50MHz */
2698 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
2699 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2700 dev_priv->rps.cur_delay = 0;
2702 /* disable the counters and set deterministic thresholds */
2703 I915_WRITE(GEN6_RC_CONTROL, 0);
2705 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2706 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2707 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2708 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2709 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2711 for_each_ring(ring, dev_priv, i)
2712 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2714 I915_WRITE(GEN6_RC_SLEEP, 0);
2715 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2716 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2717 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2718 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2720 /* Check if we are enabling RC6 */
2721 rc6_mode = intel_enable_rc6(dev_priv->dev);
2722 if (rc6_mode & INTEL_RC6_ENABLE)
2723 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2725 /* We don't use those on Haswell */
2726 if (!IS_HASWELL(dev)) {
2727 if (rc6_mode & INTEL_RC6p_ENABLE)
2728 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2730 if (rc6_mode & INTEL_RC6pp_ENABLE)
2731 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2734 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2735 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2736 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2737 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2739 I915_WRITE(GEN6_RC_CONTROL,
2741 GEN6_RC_CTL_EI_MODE(1) |
2742 GEN6_RC_CTL_HW_ENABLE);
2744 if (IS_HASWELL(dev)) {
2745 I915_WRITE(GEN6_RPNSWREQ,
2747 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2750 I915_WRITE(GEN6_RPNSWREQ,
2751 GEN6_FREQUENCY(10) |
2753 GEN6_AGGRESSIVE_TURBO);
2754 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2755 GEN6_FREQUENCY(12));
2758 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2759 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2760 dev_priv->rps.max_delay << 24 |
2761 dev_priv->rps.min_delay << 16);
2763 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2764 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2765 I915_WRITE(GEN6_RP_UP_EI, 66000);
2766 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2768 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2769 I915_WRITE(GEN6_RP_CONTROL,
2770 GEN6_RP_MEDIA_TURBO |
2771 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2772 GEN6_RP_MEDIA_IS_GFX |
2774 GEN6_RP_UP_BUSY_AVG |
2775 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2777 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2780 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2781 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2782 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
2783 (dev_priv->rps.max_delay & 0xff) * 50,
2784 (pcu_mbox & 0xff) * 50);
2785 dev_priv->rps.hw_max = pcu_mbox & 0xff;
2788 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2791 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2793 /* requires MSI enabled */
2794 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2795 spin_lock_irq(&dev_priv->rps.lock);
2796 WARN_ON(dev_priv->rps.pm_iir != 0);
2797 I915_WRITE(GEN6_PMIMR, 0);
2798 spin_unlock_irq(&dev_priv->rps.lock);
2799 /* enable all PM interrupts */
2800 I915_WRITE(GEN6_PMINTRMSK, 0);
2803 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2804 if (IS_GEN6(dev) && ret) {
2805 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2806 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2807 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2808 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2809 rc6vids &= 0xffff00;
2810 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2811 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2813 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2816 gen6_gt_force_wake_put(dev_priv);
2819 static void gen6_update_ring_freq(struct drm_device *dev)
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2823 unsigned int gpu_freq;
2824 unsigned int max_ia_freq, min_ring_freq;
2825 int scaling_factor = 180;
2827 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2829 max_ia_freq = cpufreq_quick_get_max(0);
2831 * Default to measured freq if none found, PCU will ensure we don't go
2835 max_ia_freq = tsc_khz;
2837 /* Convert from kHz to MHz */
2838 max_ia_freq /= 1000;
2840 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2841 /* convert DDR frequency from units of 133.3MHz to bandwidth */
2842 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2845 * For each potential GPU frequency, load a ring frequency we'd like
2846 * to use for memory access. We do this by specifying the IA frequency
2847 * the PCU should use as a reference to determine the ring frequency.
2849 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2851 int diff = dev_priv->rps.max_delay - gpu_freq;
2852 unsigned int ia_freq = 0, ring_freq = 0;
2854 if (IS_HASWELL(dev)) {
2855 ring_freq = (gpu_freq * 5 + 3) / 4;
2856 ring_freq = max(min_ring_freq, ring_freq);
2857 /* leave ia_freq as the default, chosen by cpufreq */
2859 /* On older processors, there is no separate ring
2860 * clock domain, so in order to boost the bandwidth
2861 * of the ring, we need to upclock the CPU (ia_freq).
2863 * For GPU frequencies less than 750MHz,
2864 * just use the lowest ring freq.
2866 if (gpu_freq < min_freq)
2869 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2870 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2873 sandybridge_pcode_write(dev_priv,
2874 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2875 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2876 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2881 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2885 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2887 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2889 rp0 = min_t(u32, rp0, 0xea);
2894 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2898 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2899 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2900 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2901 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2906 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2910 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2915 static void vlv_rps_timer_work(struct work_struct *work)
2917 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
2921 * Timer fired, we must be idle. Drop to min voltage state.
2922 * Note: we use RPe here since it should match the
2923 * Vmin we were shooting for. That should give us better
2924 * perf when we come back out of RC6 than if we used the
2925 * min freq available.
2927 mutex_lock(&dev_priv->rps.hw_lock);
2928 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
2929 mutex_unlock(&dev_priv->rps.hw_lock);
2932 static void valleyview_setup_pctx(struct drm_device *dev)
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935 struct drm_i915_gem_object *pctx;
2936 unsigned long pctx_paddr;
2938 int pctx_size = 24*1024;
2940 pcbr = I915_READ(VLV_PCBR);
2942 /* BIOS set it up already, grab the pre-alloc'd space */
2945 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
2946 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
2954 * From the Gunit register HAS:
2955 * The Gfx driver is expected to program this register and ensure
2956 * proper allocation within Gfx stolen memory. For example, this
2957 * register should be programmed such than the PCBR range does not
2958 * overlap with other ranges, such as the frame buffer, protected
2959 * memory, or any other relevant ranges.
2961 pctx = i915_gem_object_create_stolen(dev, pctx_size);
2963 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
2967 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
2968 I915_WRITE(VLV_PCBR, pctx_paddr);
2971 dev_priv->vlv_pctx = pctx;
2974 static void valleyview_enable_rps(struct drm_device *dev)
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct intel_ring_buffer *ring;
2978 u32 gtfifodbg, val, rpe;
2981 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2983 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2984 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2985 I915_WRITE(GTFIFODBG, gtfifodbg);
2988 valleyview_setup_pctx(dev);
2990 gen6_gt_force_wake_get(dev_priv);
2992 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2993 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2994 I915_WRITE(GEN6_RP_UP_EI, 66000);
2995 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2997 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2999 I915_WRITE(GEN6_RP_CONTROL,
3000 GEN6_RP_MEDIA_TURBO |
3001 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3002 GEN6_RP_MEDIA_IS_GFX |
3004 GEN6_RP_UP_BUSY_AVG |
3005 GEN6_RP_DOWN_IDLE_CONT);
3007 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3008 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3009 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3011 for_each_ring(ring, dev_priv, i)
3012 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3014 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3016 /* allows RC6 residency counter to work */
3017 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3018 I915_WRITE(GEN6_RC_CONTROL,
3019 GEN7_RC_CTL_TO_MODE);
3021 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
3022 switch ((val >> 6) & 3) {
3025 dev_priv->mem_freq = 800;
3028 dev_priv->mem_freq = 1066;
3031 dev_priv->mem_freq = 1333;
3034 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3036 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3037 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3039 DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3040 vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3041 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3043 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3044 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3045 DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3046 dev_priv->rps.max_delay));
3048 rpe = valleyview_rps_rpe_freq(dev_priv);
3049 DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3050 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3051 dev_priv->rps.rpe_delay = rpe;
3053 val = valleyview_rps_min_freq(dev_priv);
3054 DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3056 dev_priv->rps.min_delay = val;
3058 DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3059 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3061 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3063 valleyview_set_rps(dev_priv->dev, rpe);
3065 /* requires MSI enabled */
3066 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3067 spin_lock_irq(&dev_priv->rps.lock);
3068 WARN_ON(dev_priv->rps.pm_iir != 0);
3069 I915_WRITE(GEN6_PMIMR, 0);
3070 spin_unlock_irq(&dev_priv->rps.lock);
3071 /* enable all PM interrupts */
3072 I915_WRITE(GEN6_PMINTRMSK, 0);
3074 gen6_gt_force_wake_put(dev_priv);
3077 void ironlake_teardown_rc6(struct drm_device *dev)
3079 struct drm_i915_private *dev_priv = dev->dev_private;
3081 if (dev_priv->ips.renderctx) {
3082 i915_gem_object_unpin(dev_priv->ips.renderctx);
3083 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3084 dev_priv->ips.renderctx = NULL;
3087 if (dev_priv->ips.pwrctx) {
3088 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3089 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3090 dev_priv->ips.pwrctx = NULL;
3094 static void ironlake_disable_rc6(struct drm_device *dev)
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3098 if (I915_READ(PWRCTXA)) {
3099 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3100 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3101 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3104 I915_WRITE(PWRCTXA, 0);
3105 POSTING_READ(PWRCTXA);
3107 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3108 POSTING_READ(RSTDBYCTL);
3112 static int ironlake_setup_rc6(struct drm_device *dev)
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3116 if (dev_priv->ips.renderctx == NULL)
3117 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3118 if (!dev_priv->ips.renderctx)
3121 if (dev_priv->ips.pwrctx == NULL)
3122 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3123 if (!dev_priv->ips.pwrctx) {
3124 ironlake_teardown_rc6(dev);
3131 static void ironlake_enable_rc6(struct drm_device *dev)
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3135 bool was_interruptible;
3138 /* rc6 disabled by default due to repeated reports of hanging during
3141 if (!intel_enable_rc6(dev))
3144 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3146 ret = ironlake_setup_rc6(dev);
3150 was_interruptible = dev_priv->mm.interruptible;
3151 dev_priv->mm.interruptible = false;
3154 * GPU can automatically power down the render unit if given a page
3157 ret = intel_ring_begin(ring, 6);
3159 ironlake_teardown_rc6(dev);
3160 dev_priv->mm.interruptible = was_interruptible;
3164 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3165 intel_ring_emit(ring, MI_SET_CONTEXT);
3166 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3168 MI_SAVE_EXT_STATE_EN |
3169 MI_RESTORE_EXT_STATE_EN |
3170 MI_RESTORE_INHIBIT);
3171 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3172 intel_ring_emit(ring, MI_NOOP);
3173 intel_ring_emit(ring, MI_FLUSH);
3174 intel_ring_advance(ring);
3177 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3178 * does an implicit flush, combined with MI_FLUSH above, it should be
3179 * safe to assume that renderctx is valid
3181 ret = intel_ring_idle(ring);
3182 dev_priv->mm.interruptible = was_interruptible;
3184 DRM_ERROR("failed to enable ironlake power savings\n");
3185 ironlake_teardown_rc6(dev);
3189 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3190 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3193 static unsigned long intel_pxfreq(u32 vidfreq)
3196 int div = (vidfreq & 0x3f0000) >> 16;
3197 int post = (vidfreq & 0x3000) >> 12;
3198 int pre = (vidfreq & 0x7);
3203 freq = ((div * 133333) / ((1<<post) * pre));
3208 static const struct cparams {
3214 { 1, 1333, 301, 28664 },
3215 { 1, 1066, 294, 24460 },
3216 { 1, 800, 294, 25192 },
3217 { 0, 1333, 276, 27605 },
3218 { 0, 1066, 276, 27605 },
3219 { 0, 800, 231, 23784 },
3222 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3224 u64 total_count, diff, ret;
3225 u32 count1, count2, count3, m = 0, c = 0;
3226 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3229 assert_spin_locked(&mchdev_lock);
3231 diff1 = now - dev_priv->ips.last_time1;
3233 /* Prevent division-by-zero if we are asking too fast.
3234 * Also, we don't get interesting results if we are polling
3235 * faster than once in 10ms, so just return the saved value
3239 return dev_priv->ips.chipset_power;
3241 count1 = I915_READ(DMIEC);
3242 count2 = I915_READ(DDREC);
3243 count3 = I915_READ(CSIEC);
3245 total_count = count1 + count2 + count3;
3247 /* FIXME: handle per-counter overflow */
3248 if (total_count < dev_priv->ips.last_count1) {
3249 diff = ~0UL - dev_priv->ips.last_count1;
3250 diff += total_count;
3252 diff = total_count - dev_priv->ips.last_count1;
3255 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3256 if (cparams[i].i == dev_priv->ips.c_m &&
3257 cparams[i].t == dev_priv->ips.r_t) {
3264 diff = div_u64(diff, diff1);
3265 ret = ((m * diff) + c);
3266 ret = div_u64(ret, 10);
3268 dev_priv->ips.last_count1 = total_count;
3269 dev_priv->ips.last_time1 = now;
3271 dev_priv->ips.chipset_power = ret;
3276 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3280 if (dev_priv->info->gen != 5)
3283 spin_lock_irq(&mchdev_lock);
3285 val = __i915_chipset_val(dev_priv);
3287 spin_unlock_irq(&mchdev_lock);
3292 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3294 unsigned long m, x, b;
3297 tsfs = I915_READ(TSFS);
3299 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3300 x = I915_READ8(TR1);
3302 b = tsfs & TSFS_INTR_MASK;
3304 return ((m * x) / 127) - b;
3307 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3309 static const struct v_table {
3310 u16 vd; /* in .1 mil */
3311 u16 vm; /* in .1 mil */
3442 if (dev_priv->info->is_mobile)
3443 return v_table[pxvid].vm;
3445 return v_table[pxvid].vd;
3448 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3450 struct timespec now, diff1;
3452 unsigned long diffms;
3455 assert_spin_locked(&mchdev_lock);
3457 getrawmonotonic(&now);
3458 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3460 /* Don't divide by 0 */
3461 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3465 count = I915_READ(GFXEC);
3467 if (count < dev_priv->ips.last_count2) {
3468 diff = ~0UL - dev_priv->ips.last_count2;
3471 diff = count - dev_priv->ips.last_count2;
3474 dev_priv->ips.last_count2 = count;
3475 dev_priv->ips.last_time2 = now;
3477 /* More magic constants... */
3479 diff = div_u64(diff, diffms * 10);
3480 dev_priv->ips.gfx_power = diff;
3483 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3485 if (dev_priv->info->gen != 5)
3488 spin_lock_irq(&mchdev_lock);
3490 __i915_update_gfx_val(dev_priv);
3492 spin_unlock_irq(&mchdev_lock);
3495 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3497 unsigned long t, corr, state1, corr2, state2;
3500 assert_spin_locked(&mchdev_lock);
3502 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3503 pxvid = (pxvid >> 24) & 0x7f;
3504 ext_v = pvid_to_extvid(dev_priv, pxvid);
3508 t = i915_mch_val(dev_priv);
3510 /* Revel in the empirically derived constants */
3512 /* Correction factor in 1/100000 units */
3514 corr = ((t * 2349) + 135940);
3516 corr = ((t * 964) + 29317);
3518 corr = ((t * 301) + 1004);
3520 corr = corr * ((150142 * state1) / 10000 - 78642);
3522 corr2 = (corr * dev_priv->ips.corr);
3524 state2 = (corr2 * state1) / 10000;
3525 state2 /= 100; /* convert to mW */
3527 __i915_update_gfx_val(dev_priv);
3529 return dev_priv->ips.gfx_power + state2;
3532 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3536 if (dev_priv->info->gen != 5)
3539 spin_lock_irq(&mchdev_lock);
3541 val = __i915_gfx_val(dev_priv);
3543 spin_unlock_irq(&mchdev_lock);
3549 * i915_read_mch_val - return value for IPS use
3551 * Calculate and return a value for the IPS driver to use when deciding whether
3552 * we have thermal and power headroom to increase CPU or GPU power budget.
3554 unsigned long i915_read_mch_val(void)
3556 struct drm_i915_private *dev_priv;
3557 unsigned long chipset_val, graphics_val, ret = 0;
3559 spin_lock_irq(&mchdev_lock);
3562 dev_priv = i915_mch_dev;
3564 chipset_val = __i915_chipset_val(dev_priv);
3565 graphics_val = __i915_gfx_val(dev_priv);
3567 ret = chipset_val + graphics_val;
3570 spin_unlock_irq(&mchdev_lock);
3574 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3577 * i915_gpu_raise - raise GPU frequency limit
3579 * Raise the limit; IPS indicates we have thermal headroom.
3581 bool i915_gpu_raise(void)
3583 struct drm_i915_private *dev_priv;
3586 spin_lock_irq(&mchdev_lock);
3587 if (!i915_mch_dev) {
3591 dev_priv = i915_mch_dev;
3593 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3594 dev_priv->ips.max_delay--;
3597 spin_unlock_irq(&mchdev_lock);
3601 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3604 * i915_gpu_lower - lower GPU frequency limit
3606 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3607 * frequency maximum.
3609 bool i915_gpu_lower(void)
3611 struct drm_i915_private *dev_priv;
3614 spin_lock_irq(&mchdev_lock);
3615 if (!i915_mch_dev) {
3619 dev_priv = i915_mch_dev;
3621 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3622 dev_priv->ips.max_delay++;
3625 spin_unlock_irq(&mchdev_lock);
3629 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3632 * i915_gpu_busy - indicate GPU business to IPS
3634 * Tell the IPS driver whether or not the GPU is busy.
3636 bool i915_gpu_busy(void)
3638 struct drm_i915_private *dev_priv;
3639 struct intel_ring_buffer *ring;
3643 spin_lock_irq(&mchdev_lock);
3646 dev_priv = i915_mch_dev;
3648 for_each_ring(ring, dev_priv, i)
3649 ret |= !list_empty(&ring->request_list);
3652 spin_unlock_irq(&mchdev_lock);
3656 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3659 * i915_gpu_turbo_disable - disable graphics turbo
3661 * Disable graphics turbo by resetting the max frequency and setting the
3662 * current frequency to the default.
3664 bool i915_gpu_turbo_disable(void)
3666 struct drm_i915_private *dev_priv;
3669 spin_lock_irq(&mchdev_lock);
3670 if (!i915_mch_dev) {
3674 dev_priv = i915_mch_dev;
3676 dev_priv->ips.max_delay = dev_priv->ips.fstart;
3678 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3682 spin_unlock_irq(&mchdev_lock);
3686 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3689 * Tells the intel_ips driver that the i915 driver is now loaded, if
3690 * IPS got loaded first.
3692 * This awkward dance is so that neither module has to depend on the
3693 * other in order for IPS to do the appropriate communication of
3694 * GPU turbo limits to i915.
3697 ips_ping_for_i915_load(void)
3701 link = symbol_get(ips_link_to_i915_driver);
3704 symbol_put(ips_link_to_i915_driver);
3708 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3710 /* We only register the i915 ips part with intel-ips once everything is
3711 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3712 spin_lock_irq(&mchdev_lock);
3713 i915_mch_dev = dev_priv;
3714 spin_unlock_irq(&mchdev_lock);
3716 ips_ping_for_i915_load();
3719 void intel_gpu_ips_teardown(void)
3721 spin_lock_irq(&mchdev_lock);
3722 i915_mch_dev = NULL;
3723 spin_unlock_irq(&mchdev_lock);
3725 static void intel_init_emon(struct drm_device *dev)
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3732 /* Disable to program */
3736 /* Program energy weights for various events */
3737 I915_WRITE(SDEW, 0x15040d00);
3738 I915_WRITE(CSIEW0, 0x007f0000);
3739 I915_WRITE(CSIEW1, 0x1e220004);
3740 I915_WRITE(CSIEW2, 0x04000004);
3742 for (i = 0; i < 5; i++)
3743 I915_WRITE(PEW + (i * 4), 0);
3744 for (i = 0; i < 3; i++)
3745 I915_WRITE(DEW + (i * 4), 0);
3747 /* Program P-state weights to account for frequency power adjustment */
3748 for (i = 0; i < 16; i++) {
3749 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3750 unsigned long freq = intel_pxfreq(pxvidfreq);
3751 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3756 val *= (freq / 1000);
3758 val /= (127*127*900);
3760 DRM_ERROR("bad pxval: %ld\n", val);
3763 /* Render standby states get 0 weight */
3767 for (i = 0; i < 4; i++) {
3768 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3769 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3770 I915_WRITE(PXW + (i * 4), val);
3773 /* Adjust magic regs to magic values (more experimental results) */
3774 I915_WRITE(OGW0, 0);
3775 I915_WRITE(OGW1, 0);
3776 I915_WRITE(EG0, 0x00007f00);
3777 I915_WRITE(EG1, 0x0000000e);
3778 I915_WRITE(EG2, 0x000e0000);
3779 I915_WRITE(EG3, 0x68000300);
3780 I915_WRITE(EG4, 0x42000000);
3781 I915_WRITE(EG5, 0x00140031);
3785 for (i = 0; i < 8; i++)
3786 I915_WRITE(PXWL + (i * 4), 0);
3788 /* Enable PMON + select events */
3789 I915_WRITE(ECR, 0x80000019);
3791 lcfuse = I915_READ(LCFUSE02);
3793 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3796 void intel_disable_gt_powersave(struct drm_device *dev)
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3800 /* Interrupts should be disabled already to avoid re-arming. */
3801 WARN_ON(dev->irq_enabled);
3803 if (IS_IRONLAKE_M(dev)) {
3804 ironlake_disable_drps(dev);
3805 ironlake_disable_rc6(dev);
3806 } else if (INTEL_INFO(dev)->gen >= 6) {
3807 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3808 cancel_work_sync(&dev_priv->rps.work);
3809 if (IS_VALLEYVIEW(dev))
3810 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
3811 mutex_lock(&dev_priv->rps.hw_lock);
3812 if (IS_VALLEYVIEW(dev))
3813 valleyview_disable_rps(dev);
3815 gen6_disable_rps(dev);
3816 mutex_unlock(&dev_priv->rps.hw_lock);
3820 static void intel_gen6_powersave_work(struct work_struct *work)
3822 struct drm_i915_private *dev_priv =
3823 container_of(work, struct drm_i915_private,
3824 rps.delayed_resume_work.work);
3825 struct drm_device *dev = dev_priv->dev;
3827 mutex_lock(&dev_priv->rps.hw_lock);
3829 if (IS_VALLEYVIEW(dev)) {
3830 valleyview_enable_rps(dev);
3832 gen6_enable_rps(dev);
3833 gen6_update_ring_freq(dev);
3835 mutex_unlock(&dev_priv->rps.hw_lock);
3838 void intel_enable_gt_powersave(struct drm_device *dev)
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3842 if (IS_IRONLAKE_M(dev)) {
3843 ironlake_enable_drps(dev);
3844 ironlake_enable_rc6(dev);
3845 intel_init_emon(dev);
3846 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3848 * PCU communication is slow and this doesn't need to be
3849 * done at any specific time, so do this out of our fast path
3850 * to make resume and init faster.
3852 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3853 round_jiffies_up_relative(HZ));
3857 static void ibx_init_clock_gating(struct drm_device *dev)
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3862 * On Ibex Peak and Cougar Point, we need to disable clock
3863 * gating for the panel power sequencer or it will fail to
3864 * start up when no ports are active.
3866 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3869 static void ironlake_init_clock_gating(struct drm_device *dev)
3871 struct drm_i915_private *dev_priv = dev->dev_private;
3872 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3874 /* Required for FBC */
3875 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3876 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3877 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3879 I915_WRITE(PCH_3DCGDIS0,
3880 MARIUNIT_CLOCK_GATE_DISABLE |
3881 SVSMUNIT_CLOCK_GATE_DISABLE);
3882 I915_WRITE(PCH_3DCGDIS1,
3883 VFMUNIT_CLOCK_GATE_DISABLE);
3886 * According to the spec the following bits should be set in
3887 * order to enable memory self-refresh
3888 * The bit 22/21 of 0x42004
3889 * The bit 5 of 0x42020
3890 * The bit 15 of 0x45000
3892 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3893 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3894 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3895 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3896 I915_WRITE(DISP_ARB_CTL,
3897 (I915_READ(DISP_ARB_CTL) |
3899 I915_WRITE(WM3_LP_ILK, 0);
3900 I915_WRITE(WM2_LP_ILK, 0);
3901 I915_WRITE(WM1_LP_ILK, 0);
3904 * Based on the document from hardware guys the following bits
3905 * should be set unconditionally in order to enable FBC.
3906 * The bit 22 of 0x42000
3907 * The bit 22 of 0x42004
3908 * The bit 7,8,9 of 0x42020.
3910 if (IS_IRONLAKE_M(dev)) {
3911 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3912 I915_READ(ILK_DISPLAY_CHICKEN1) |
3914 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3915 I915_READ(ILK_DISPLAY_CHICKEN2) |
3919 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3921 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3922 I915_READ(ILK_DISPLAY_CHICKEN2) |
3923 ILK_ELPIN_409_SELECT);
3924 I915_WRITE(_3D_CHICKEN2,
3925 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3926 _3D_CHICKEN2_WM_READ_PIPELINED);
3928 /* WaDisableRenderCachePipelinedFlush:ilk */
3929 I915_WRITE(CACHE_MODE_0,
3930 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3932 ibx_init_clock_gating(dev);
3935 static void cpt_init_clock_gating(struct drm_device *dev)
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3942 * On Ibex Peak and Cougar Point, we need to disable clock
3943 * gating for the panel power sequencer or it will fail to
3944 * start up when no ports are active.
3946 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3947 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3948 DPLS_EDP_PPS_FIX_DIS);
3949 /* The below fixes the weird display corruption, a few pixels shifted
3950 * downward, on (only) LVDS of some HP laptops with IVY.
3952 for_each_pipe(pipe) {
3953 val = I915_READ(TRANS_CHICKEN2(pipe));
3954 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3955 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3956 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3957 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3958 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3959 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3960 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3961 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3963 /* WADP0ClockGatingDisable */
3964 for_each_pipe(pipe) {
3965 I915_WRITE(TRANS_CHICKEN1(pipe),
3966 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3970 static void gen6_check_mch_setup(struct drm_device *dev)
3972 struct drm_i915_private *dev_priv = dev->dev_private;
3975 tmp = I915_READ(MCH_SSKPD);
3976 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3977 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3978 DRM_INFO("This can cause pipe underruns and display issues.\n");
3979 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3983 static void gen6_init_clock_gating(struct drm_device *dev)
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3987 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3989 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3991 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3992 I915_READ(ILK_DISPLAY_CHICKEN2) |
3993 ILK_ELPIN_409_SELECT);
3995 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
3996 I915_WRITE(_3D_CHICKEN,
3997 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3999 /* WaSetupGtModeTdRowDispatch:snb */
4000 if (IS_SNB_GT1(dev))
4001 I915_WRITE(GEN6_GT_MODE,
4002 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4004 I915_WRITE(WM3_LP_ILK, 0);
4005 I915_WRITE(WM2_LP_ILK, 0);
4006 I915_WRITE(WM1_LP_ILK, 0);
4008 I915_WRITE(CACHE_MODE_0,
4009 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4011 I915_WRITE(GEN6_UCGCTL1,
4012 I915_READ(GEN6_UCGCTL1) |
4013 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4014 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4016 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4017 * gating disable must be set. Failure to set it results in
4018 * flickering pixels due to Z write ordering failures after
4019 * some amount of runtime in the Mesa "fire" demo, and Unigine
4020 * Sanctuary and Tropics, and apparently anything else with
4021 * alpha test or pixel discard.
4023 * According to the spec, bit 11 (RCCUNIT) must also be set,
4024 * but we didn't debug actual testcases to find it out.
4026 * Also apply WaDisableVDSUnitClockGating:snb and
4027 * WaDisableRCPBUnitClockGating:snb.
4029 I915_WRITE(GEN6_UCGCTL2,
4030 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4031 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4032 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4034 /* Bspec says we need to always set all mask bits. */
4035 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4036 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4039 * According to the spec the following bits should be
4040 * set in order to enable memory self-refresh and fbc:
4041 * The bit21 and bit22 of 0x42000
4042 * The bit21 and bit22 of 0x42004
4043 * The bit5 and bit7 of 0x42020
4044 * The bit14 of 0x70180
4045 * The bit14 of 0x71180
4047 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4048 I915_READ(ILK_DISPLAY_CHICKEN1) |
4049 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4050 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4051 I915_READ(ILK_DISPLAY_CHICKEN2) |
4052 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4053 I915_WRITE(ILK_DSPCLK_GATE_D,
4054 I915_READ(ILK_DSPCLK_GATE_D) |
4055 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4056 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4058 /* WaMbcDriverBootEnable:snb */
4059 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4060 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4062 for_each_pipe(pipe) {
4063 I915_WRITE(DSPCNTR(pipe),
4064 I915_READ(DSPCNTR(pipe)) |
4065 DISPPLANE_TRICKLE_FEED_DISABLE);
4066 intel_flush_display_plane(dev_priv, pipe);
4069 /* The default value should be 0x200 according to docs, but the two
4070 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4071 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4072 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4074 cpt_init_clock_gating(dev);
4076 gen6_check_mch_setup(dev);
4079 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4081 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4083 reg &= ~GEN7_FF_SCHED_MASK;
4084 reg |= GEN7_FF_TS_SCHED_HW;
4085 reg |= GEN7_FF_VS_SCHED_HW;
4086 reg |= GEN7_FF_DS_SCHED_HW;
4088 if (IS_HASWELL(dev_priv->dev))
4089 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4091 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4094 static void lpt_init_clock_gating(struct drm_device *dev)
4096 struct drm_i915_private *dev_priv = dev->dev_private;
4099 * TODO: this bit should only be enabled when really needed, then
4100 * disabled when not needed anymore in order to save power.
4102 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4103 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4104 I915_READ(SOUTH_DSPCLK_GATE_D) |
4105 PCH_LP_PARTITION_LEVEL_DISABLE);
4107 /* WADPOClockGatingDisable:hsw */
4108 I915_WRITE(_TRANSA_CHICKEN1,
4109 I915_READ(_TRANSA_CHICKEN1) |
4110 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4113 static void lpt_suspend_hw(struct drm_device *dev)
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4117 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4118 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4120 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4121 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4125 static void haswell_init_clock_gating(struct drm_device *dev)
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4130 I915_WRITE(WM3_LP_ILK, 0);
4131 I915_WRITE(WM2_LP_ILK, 0);
4132 I915_WRITE(WM1_LP_ILK, 0);
4134 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4135 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4137 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4139 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4140 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4141 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4143 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4144 I915_WRITE(GEN7_L3CNTLREG1,
4145 GEN7_WA_FOR_GEN7_L3_CONTROL);
4146 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4147 GEN7_WA_L3_CHICKEN_MODE);
4149 /* This is required by WaCatErrorRejectionIssue:hsw */
4150 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4151 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4152 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4154 for_each_pipe(pipe) {
4155 I915_WRITE(DSPCNTR(pipe),
4156 I915_READ(DSPCNTR(pipe)) |
4157 DISPPLANE_TRICKLE_FEED_DISABLE);
4158 intel_flush_display_plane(dev_priv, pipe);
4161 /* WaVSRefCountFullforceMissDisable:hsw */
4162 gen7_setup_fixed_func_scheduler(dev_priv);
4164 /* WaDisable4x2SubspanOptimization:hsw */
4165 I915_WRITE(CACHE_MODE_1,
4166 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4168 /* WaMbcDriverBootEnable:hsw */
4169 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4170 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4172 /* WaSwitchSolVfFArbitrationPriority:hsw */
4173 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4175 /* WaRsPkgCStateDisplayPMReq:hsw */
4176 I915_WRITE(CHICKEN_PAR1_1,
4177 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4179 lpt_init_clock_gating(dev);
4182 static void ivybridge_init_clock_gating(struct drm_device *dev)
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4188 I915_WRITE(WM3_LP_ILK, 0);
4189 I915_WRITE(WM2_LP_ILK, 0);
4190 I915_WRITE(WM1_LP_ILK, 0);
4192 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4194 /* WaDisableEarlyCull:ivb */
4195 I915_WRITE(_3D_CHICKEN3,
4196 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4198 /* WaDisableBackToBackFlipFix:ivb */
4199 I915_WRITE(IVB_CHICKEN3,
4200 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4201 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4203 /* WaDisablePSDDualDispatchEnable:ivb */
4204 if (IS_IVB_GT1(dev))
4205 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4206 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4208 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4209 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4211 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4212 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4213 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4215 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4216 I915_WRITE(GEN7_L3CNTLREG1,
4217 GEN7_WA_FOR_GEN7_L3_CONTROL);
4218 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4219 GEN7_WA_L3_CHICKEN_MODE);
4220 if (IS_IVB_GT1(dev))
4221 I915_WRITE(GEN7_ROW_CHICKEN2,
4222 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4224 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4225 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4228 /* WaForceL3Serialization:ivb */
4229 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4230 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4232 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4233 * gating disable must be set. Failure to set it results in
4234 * flickering pixels due to Z write ordering failures after
4235 * some amount of runtime in the Mesa "fire" demo, and Unigine
4236 * Sanctuary and Tropics, and apparently anything else with
4237 * alpha test or pixel discard.
4239 * According to the spec, bit 11 (RCCUNIT) must also be set,
4240 * but we didn't debug actual testcases to find it out.
4242 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4243 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4245 I915_WRITE(GEN6_UCGCTL2,
4246 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4247 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4249 /* This is required by WaCatErrorRejectionIssue:ivb */
4250 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4251 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4252 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4254 for_each_pipe(pipe) {
4255 I915_WRITE(DSPCNTR(pipe),
4256 I915_READ(DSPCNTR(pipe)) |
4257 DISPPLANE_TRICKLE_FEED_DISABLE);
4258 intel_flush_display_plane(dev_priv, pipe);
4261 /* WaMbcDriverBootEnable:ivb */
4262 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4263 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4265 /* WaVSRefCountFullforceMissDisable:ivb */
4266 gen7_setup_fixed_func_scheduler(dev_priv);
4268 /* WaDisable4x2SubspanOptimization:ivb */
4269 I915_WRITE(CACHE_MODE_1,
4270 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4272 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4273 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4274 snpcr |= GEN6_MBC_SNPCR_MED;
4275 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4277 if (!HAS_PCH_NOP(dev))
4278 cpt_init_clock_gating(dev);
4280 gen6_check_mch_setup(dev);
4283 static void valleyview_init_clock_gating(struct drm_device *dev)
4285 struct drm_i915_private *dev_priv = dev->dev_private;
4288 I915_WRITE(WM3_LP_ILK, 0);
4289 I915_WRITE(WM2_LP_ILK, 0);
4290 I915_WRITE(WM1_LP_ILK, 0);
4292 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4294 /* WaDisableEarlyCull:vlv */
4295 I915_WRITE(_3D_CHICKEN3,
4296 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4298 /* WaDisableBackToBackFlipFix:vlv */
4299 I915_WRITE(IVB_CHICKEN3,
4300 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4301 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4303 /* WaDisablePSDDualDispatchEnable:vlv */
4304 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4305 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4306 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4308 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4309 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4310 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4312 /* WaApplyL3ControlAndL3ChickenMode:vlv */
4313 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4314 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4316 /* WaForceL3Serialization:vlv */
4317 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4318 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4320 /* WaDisableDopClockGating:vlv */
4321 I915_WRITE(GEN7_ROW_CHICKEN2,
4322 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4324 /* WaForceL3Serialization:vlv */
4325 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4326 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4328 /* This is required by WaCatErrorRejectionIssue:vlv */
4329 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4330 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4331 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4333 /* WaMbcDriverBootEnable:vlv */
4334 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4335 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4338 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4339 * gating disable must be set. Failure to set it results in
4340 * flickering pixels due to Z write ordering failures after
4341 * some amount of runtime in the Mesa "fire" demo, and Unigine
4342 * Sanctuary and Tropics, and apparently anything else with
4343 * alpha test or pixel discard.
4345 * According to the spec, bit 11 (RCCUNIT) must also be set,
4346 * but we didn't debug actual testcases to find it out.
4348 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4349 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4351 * Also apply WaDisableVDSUnitClockGating:vlv and
4352 * WaDisableRCPBUnitClockGating:vlv.
4354 I915_WRITE(GEN6_UCGCTL2,
4355 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4356 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4357 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4358 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4359 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4361 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4363 for_each_pipe(pipe) {
4364 I915_WRITE(DSPCNTR(pipe),
4365 I915_READ(DSPCNTR(pipe)) |
4366 DISPPLANE_TRICKLE_FEED_DISABLE);
4367 intel_flush_display_plane(dev_priv, pipe);
4370 I915_WRITE(CACHE_MODE_1,
4371 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4374 * WaDisableVLVClockGating_VBIIssue:vlv
4375 * Disable clock gating on th GCFG unit to prevent a delay
4376 * in the reporting of vblank events.
4378 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4380 /* Conservative clock gating settings for now */
4381 I915_WRITE(0x9400, 0xffffffff);
4382 I915_WRITE(0x9404, 0xffffffff);
4383 I915_WRITE(0x9408, 0xffffffff);
4384 I915_WRITE(0x940c, 0xffffffff);
4385 I915_WRITE(0x9410, 0xffffffff);
4386 I915_WRITE(0x9414, 0xffffffff);
4387 I915_WRITE(0x9418, 0xffffffff);
4390 static void g4x_init_clock_gating(struct drm_device *dev)
4392 struct drm_i915_private *dev_priv = dev->dev_private;
4393 uint32_t dspclk_gate;
4395 I915_WRITE(RENCLK_GATE_D1, 0);
4396 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4397 GS_UNIT_CLOCK_GATE_DISABLE |
4398 CL_UNIT_CLOCK_GATE_DISABLE);
4399 I915_WRITE(RAMCLK_GATE_D, 0);
4400 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4401 OVRUNIT_CLOCK_GATE_DISABLE |
4402 OVCUNIT_CLOCK_GATE_DISABLE;
4404 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4405 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4407 /* WaDisableRenderCachePipelinedFlush */
4408 I915_WRITE(CACHE_MODE_0,
4409 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4412 static void crestline_init_clock_gating(struct drm_device *dev)
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4416 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4417 I915_WRITE(RENCLK_GATE_D2, 0);
4418 I915_WRITE(DSPCLK_GATE_D, 0);
4419 I915_WRITE(RAMCLK_GATE_D, 0);
4420 I915_WRITE16(DEUC, 0);
4423 static void broadwater_init_clock_gating(struct drm_device *dev)
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4427 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4428 I965_RCC_CLOCK_GATE_DISABLE |
4429 I965_RCPB_CLOCK_GATE_DISABLE |
4430 I965_ISC_CLOCK_GATE_DISABLE |
4431 I965_FBC_CLOCK_GATE_DISABLE);
4432 I915_WRITE(RENCLK_GATE_D2, 0);
4435 static void gen3_init_clock_gating(struct drm_device *dev)
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4438 u32 dstate = I915_READ(D_STATE);
4440 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4441 DSTATE_DOT_CLOCK_GATING;
4442 I915_WRITE(D_STATE, dstate);
4444 if (IS_PINEVIEW(dev))
4445 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4447 /* IIR "flip pending" means done if this bit is set */
4448 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4451 static void i85x_init_clock_gating(struct drm_device *dev)
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4455 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4458 static void i830_init_clock_gating(struct drm_device *dev)
4460 struct drm_i915_private *dev_priv = dev->dev_private;
4462 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4465 void intel_init_clock_gating(struct drm_device *dev)
4467 struct drm_i915_private *dev_priv = dev->dev_private;
4469 dev_priv->display.init_clock_gating(dev);
4472 void intel_suspend_hw(struct drm_device *dev)
4474 if (HAS_PCH_LPT(dev))
4475 lpt_suspend_hw(dev);
4479 * We should only use the power well if we explicitly asked the hardware to
4480 * enable it, so check if it's enabled and also check if we've requested it to
4483 bool intel_display_power_enabled(struct drm_device *dev,
4484 enum intel_display_power_domain domain)
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4488 if (!HAS_POWER_WELL(dev))
4492 case POWER_DOMAIN_PIPE_A:
4493 case POWER_DOMAIN_TRANSCODER_EDP:
4495 case POWER_DOMAIN_PIPE_B:
4496 case POWER_DOMAIN_PIPE_C:
4497 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4498 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4499 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4500 case POWER_DOMAIN_TRANSCODER_A:
4501 case POWER_DOMAIN_TRANSCODER_B:
4502 case POWER_DOMAIN_TRANSCODER_C:
4503 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4504 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4510 void intel_set_power_well(struct drm_device *dev, bool enable)
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 bool is_enabled, enable_requested;
4516 if (!HAS_POWER_WELL(dev))
4519 if (!i915_disable_power_well && !enable)
4522 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4523 is_enabled = tmp & HSW_PWR_WELL_STATE;
4524 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4527 if (!enable_requested)
4528 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4531 DRM_DEBUG_KMS("Enabling power well\n");
4532 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4533 HSW_PWR_WELL_STATE), 20))
4534 DRM_ERROR("Timeout enabling power well\n");
4537 if (enable_requested) {
4538 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4539 DRM_DEBUG_KMS("Requesting to disable the power well\n");
4545 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4546 * when not needed anymore. We have 4 registers that can request the power well
4547 * to be enabled, and it will only be disabled if none of the registers is
4548 * requesting it to be enabled.
4550 void intel_init_power_well(struct drm_device *dev)
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4554 if (!HAS_POWER_WELL(dev))
4557 /* For now, we need the power well to be always enabled. */
4558 intel_set_power_well(dev, true);
4560 /* We're taking over the BIOS, so clear any requests made by it since
4561 * the driver is in charge now. */
4562 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4563 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4566 /* Set up chip specific power management-related functions */
4567 void intel_init_pm(struct drm_device *dev)
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4571 if (I915_HAS_FBC(dev)) {
4572 if (HAS_PCH_SPLIT(dev)) {
4573 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4574 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4575 dev_priv->display.enable_fbc =
4578 dev_priv->display.enable_fbc =
4579 ironlake_enable_fbc;
4580 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4581 } else if (IS_GM45(dev)) {
4582 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4583 dev_priv->display.enable_fbc = g4x_enable_fbc;
4584 dev_priv->display.disable_fbc = g4x_disable_fbc;
4585 } else if (IS_CRESTLINE(dev)) {
4586 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4587 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4588 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4590 /* 855GM needs testing */
4594 if (IS_PINEVIEW(dev))
4595 i915_pineview_get_mem_freq(dev);
4596 else if (IS_GEN5(dev))
4597 i915_ironlake_get_mem_freq(dev);
4599 /* For FIFO watermark updates */
4600 if (HAS_PCH_SPLIT(dev)) {
4602 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4603 dev_priv->display.update_wm = ironlake_update_wm;
4605 DRM_DEBUG_KMS("Failed to get proper latency. "
4607 dev_priv->display.update_wm = NULL;
4609 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4610 } else if (IS_GEN6(dev)) {
4611 if (SNB_READ_WM0_LATENCY()) {
4612 dev_priv->display.update_wm = sandybridge_update_wm;
4613 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4615 DRM_DEBUG_KMS("Failed to read display plane latency. "
4617 dev_priv->display.update_wm = NULL;
4619 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4620 } else if (IS_IVYBRIDGE(dev)) {
4621 if (SNB_READ_WM0_LATENCY()) {
4622 dev_priv->display.update_wm = ivybridge_update_wm;
4623 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4625 DRM_DEBUG_KMS("Failed to read display plane latency. "
4627 dev_priv->display.update_wm = NULL;
4629 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4630 } else if (IS_HASWELL(dev)) {
4631 if (I915_READ64(MCH_SSKPD)) {
4632 dev_priv->display.update_wm = haswell_update_wm;
4633 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4635 DRM_DEBUG_KMS("Failed to read display plane latency. "
4637 dev_priv->display.update_wm = NULL;
4639 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4641 dev_priv->display.update_wm = NULL;
4642 } else if (IS_VALLEYVIEW(dev)) {
4643 dev_priv->display.update_wm = valleyview_update_wm;
4644 dev_priv->display.init_clock_gating =
4645 valleyview_init_clock_gating;
4646 } else if (IS_PINEVIEW(dev)) {
4647 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4650 dev_priv->mem_freq)) {
4651 DRM_INFO("failed to find known CxSR latency "
4652 "(found ddr%s fsb freq %d, mem freq %d), "
4654 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4655 dev_priv->fsb_freq, dev_priv->mem_freq);
4656 /* Disable CxSR and never update its watermark again */
4657 pineview_disable_cxsr(dev);
4658 dev_priv->display.update_wm = NULL;
4660 dev_priv->display.update_wm = pineview_update_wm;
4661 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4662 } else if (IS_G4X(dev)) {
4663 dev_priv->display.update_wm = g4x_update_wm;
4664 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4665 } else if (IS_GEN4(dev)) {
4666 dev_priv->display.update_wm = i965_update_wm;
4667 if (IS_CRESTLINE(dev))
4668 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4669 else if (IS_BROADWATER(dev))
4670 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4671 } else if (IS_GEN3(dev)) {
4672 dev_priv->display.update_wm = i9xx_update_wm;
4673 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4674 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4675 } else if (IS_I865G(dev)) {
4676 dev_priv->display.update_wm = i830_update_wm;
4677 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4678 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4679 } else if (IS_I85X(dev)) {
4680 dev_priv->display.update_wm = i9xx_update_wm;
4681 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4682 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4684 dev_priv->display.update_wm = i830_update_wm;
4685 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4687 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4689 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4693 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4695 u32 gt_thread_status_mask;
4697 if (IS_HASWELL(dev_priv->dev))
4698 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4700 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4702 /* w/a for a sporadic read returning 0 by waiting for the GT
4703 * thread to wake up.
4705 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4706 DRM_ERROR("GT thread status wait timed out\n");
4709 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4711 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4712 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4715 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4717 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
4718 FORCEWAKE_ACK_TIMEOUT_MS))
4719 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4721 I915_WRITE_NOTRACE(FORCEWAKE, 1);
4722 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4724 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
4725 FORCEWAKE_ACK_TIMEOUT_MS))
4726 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4728 /* WaRsForcewakeWaitTC0:snb */
4729 __gen6_gt_wait_for_thread_c0(dev_priv);
4732 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4734 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4735 /* something from same cacheline, but !FORCEWAKE_MT */
4736 POSTING_READ(ECOBUS);
4739 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4743 if (IS_HASWELL(dev_priv->dev))
4744 forcewake_ack = FORCEWAKE_ACK_HSW;
4746 forcewake_ack = FORCEWAKE_MT_ACK;
4748 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
4749 FORCEWAKE_ACK_TIMEOUT_MS))
4750 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4752 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4753 /* something from same cacheline, but !FORCEWAKE_MT */
4754 POSTING_READ(ECOBUS);
4756 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
4757 FORCEWAKE_ACK_TIMEOUT_MS))
4758 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4760 /* WaRsForcewakeWaitTC0:ivb,hsw */
4761 __gen6_gt_wait_for_thread_c0(dev_priv);
4765 * Generally this is called implicitly by the register read function. However,
4766 * if some sequence requires the GT to not power down then this function should
4767 * be called at the beginning of the sequence followed by a call to
4768 * gen6_gt_force_wake_put() at the end of the sequence.
4770 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4772 unsigned long irqflags;
4774 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4775 if (dev_priv->forcewake_count++ == 0)
4776 dev_priv->gt.force_wake_get(dev_priv);
4777 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4780 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4783 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4784 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4785 "MMIO read or write has been dropped %x\n", gtfifodbg))
4786 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4789 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4791 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4792 /* something from same cacheline, but !FORCEWAKE */
4793 POSTING_READ(ECOBUS);
4794 gen6_gt_check_fifodbg(dev_priv);
4797 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4799 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4800 /* something from same cacheline, but !FORCEWAKE_MT */
4801 POSTING_READ(ECOBUS);
4802 gen6_gt_check_fifodbg(dev_priv);
4806 * see gen6_gt_force_wake_get()
4808 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4810 unsigned long irqflags;
4812 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4813 if (--dev_priv->forcewake_count == 0)
4814 dev_priv->gt.force_wake_put(dev_priv);
4815 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4818 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4822 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4824 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4825 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4827 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4829 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4831 dev_priv->gt_fifo_count = fifo;
4833 dev_priv->gt_fifo_count--;
4838 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4840 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4841 /* something from same cacheline, but !FORCEWAKE_VLV */
4842 POSTING_READ(FORCEWAKE_ACK_VLV);
4845 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4847 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
4848 FORCEWAKE_ACK_TIMEOUT_MS))
4849 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4851 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4852 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4853 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4855 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
4856 FORCEWAKE_ACK_TIMEOUT_MS))
4857 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4859 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4861 FORCEWAKE_ACK_TIMEOUT_MS))
4862 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
4864 /* WaRsForcewakeWaitTC0:vlv */
4865 __gen6_gt_wait_for_thread_c0(dev_priv);
4868 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4870 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4871 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4872 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4873 /* The below doubles as a POSTING_READ */
4874 gen6_gt_check_fifodbg(dev_priv);
4877 void intel_gt_reset(struct drm_device *dev)
4879 struct drm_i915_private *dev_priv = dev->dev_private;
4881 if (IS_VALLEYVIEW(dev)) {
4882 vlv_force_wake_reset(dev_priv);
4883 } else if (INTEL_INFO(dev)->gen >= 6) {
4884 __gen6_gt_force_wake_reset(dev_priv);
4885 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4886 __gen6_gt_force_wake_mt_reset(dev_priv);
4890 void intel_gt_init(struct drm_device *dev)
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4894 spin_lock_init(&dev_priv->gt_lock);
4896 intel_gt_reset(dev);
4898 if (IS_VALLEYVIEW(dev)) {
4899 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4900 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4901 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4902 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4903 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4904 } else if (IS_GEN6(dev)) {
4905 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4906 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4908 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4909 intel_gen6_powersave_work);
4912 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4914 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4916 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4917 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4921 I915_WRITE(GEN6_PCODE_DATA, *val);
4922 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4924 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4926 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4930 *val = I915_READ(GEN6_PCODE_DATA);
4931 I915_WRITE(GEN6_PCODE_DATA, 0);
4936 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4938 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4940 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4941 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4945 I915_WRITE(GEN6_PCODE_DATA, val);
4946 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4948 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4950 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4954 I915_WRITE(GEN6_PCODE_DATA, 0);
4959 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
4962 u32 cmd, devfn, be, bar;
4966 devfn = PCI_DEVFN(2, 0);
4968 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4969 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4970 (bar << IOSF_BAR_SHIFT);
4972 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4974 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4975 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4976 opcode == PUNIT_OPCODE_REG_READ ?
4981 I915_WRITE(VLV_IOSF_ADDR, addr);
4982 if (opcode == PUNIT_OPCODE_REG_WRITE)
4983 I915_WRITE(VLV_IOSF_DATA, *val);
4984 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4986 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4988 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4989 opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4994 if (opcode == PUNIT_OPCODE_REG_READ)
4995 *val = I915_READ(VLV_IOSF_DATA);
4996 I915_WRITE(VLV_IOSF_DATA, 0);
5001 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
5003 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
5007 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
5009 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
5013 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
5015 return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
5019 int vlv_gpu_freq(int ddr_freq, int val)
5040 return ((val - 0xbd) * mult) + base;
5043 int vlv_freq_opcode(int ddr_freq, int val)