drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int plane, i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 113
 114         /* Clear old tags */
 115         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 116                 I915_WRITE(FBC_TAG + (i * 4), 0);
 117
 118         if (IS_GEN4(dev)) {
 119                 u32 fbc_ctl2;
 120
 121                 /* Set it up... */
 122                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 123                 fbc_ctl2 |= plane;
 124                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 125                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 126         }
 127
 128         /* enable it... */
 129         fbc_ctl = I915_READ(FBC_CONTROL);
 130         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 131         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 132         if (IS_I945GM(dev))
 133                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 134         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 135         fbc_ctl |= obj->fence_reg;
 136         I915_WRITE(FBC_CONTROL, fbc_ctl);
 137
 138         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 139                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 140 }
 141
 142 static bool i8xx_fbc_enabled(struct drm_device *dev)
 143 {
 144         struct drm_i915_private *dev_priv = dev->dev_private;
 145
 146         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 147 }
 148
 149 static void g4x_enable_fbc(struct drm_crtc *crtc)
 150 {
 151         struct drm_device *dev = crtc->dev;
 152         struct drm_i915_private *dev_priv = dev->dev_private;
 153         struct drm_framebuffer *fb = crtc->fb;
 154         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 155         struct drm_i915_gem_object *obj = intel_fb->obj;
 156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 157         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 158         u32 dpfc_ctl;
 159
 160         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 161         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 162         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 163
 164         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 165
 166         /* enable it... */
 167         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 168
 169         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 170 }
 171
 172 static void g4x_disable_fbc(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         u32 dpfc_ctl;
 176
 177         /* Disable compression */
 178         dpfc_ctl = I915_READ(DPFC_CONTROL);
 179         if (dpfc_ctl & DPFC_CTL_EN) {
 180                 dpfc_ctl &= ~DPFC_CTL_EN;
 181                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 182
 183                 DRM_DEBUG_KMS("disabled FBC\n");
 184         }
 185 }
 186
 187 static bool g4x_fbc_enabled(struct drm_device *dev)
 188 {
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190
 191         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 192 }
 193
 194 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 195 {
 196         struct drm_i915_private *dev_priv = dev->dev_private;
 197         u32 blt_ecoskpd;
 198
 199         /* Make sure blitter notifies FBC of writes */
 200
 201         /* Blitter is part of Media powerwell on VLV. No impact of
 202          * his param in other platforms for now */
 203         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 204
 205         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 206         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 207                 GEN6_BLITTER_LOCK_SHIFT;
 208         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 209         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 210         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 211         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 212                          GEN6_BLITTER_LOCK_SHIFT);
 213         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 214         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 215
 216         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 217 }
 218
 219 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 220 {
 221         struct drm_device *dev = crtc->dev;
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         struct drm_framebuffer *fb = crtc->fb;
 224         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 225         struct drm_i915_gem_object *obj = intel_fb->obj;
 226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 227         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 231         dpfc_ctl &= DPFC_RESERVED;
 232         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 233         /* Set persistent mode for front-buffer rendering, ala X. */
 234         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 239
 240         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 241         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 242         /* enable it... */
 243         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 244
 245         if (IS_GEN6(dev)) {
 246                 I915_WRITE(SNB_DPFC_CTL_SA,
 247                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 248                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 249                 sandybridge_blit_fbc_update(dev);
 250         }
 251
 252         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 253 }
 254
 255 static void ironlake_disable_fbc(struct drm_device *dev)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         u32 dpfc_ctl;
 259
 260         /* Disable compression */
 261         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 262         if (dpfc_ctl & DPFC_CTL_EN) {
 263                 dpfc_ctl &= ~DPFC_CTL_EN;
 264                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 265
 266                 DRM_DEBUG_KMS("disabled FBC\n");
 267         }
 268 }
 269
 270 static bool ironlake_fbc_enabled(struct drm_device *dev)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 275 }
 276
 277 static void gen7_enable_fbc(struct drm_crtc *crtc)
 278 {
 279         struct drm_device *dev = crtc->dev;
 280         struct drm_i915_private *dev_priv = dev->dev_private;
 281         struct drm_framebuffer *fb = crtc->fb;
 282         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 283         struct drm_i915_gem_object *obj = intel_fb->obj;
 284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 285
 286         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 287
 288         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 289                    IVB_DPFC_CTL_FENCE_EN |
 290                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 291
 292         if (IS_IVYBRIDGE(dev)) {
 293                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 294                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 295         } else {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 297                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 298                            HSW_BYPASS_FBC_QUEUE);
 299         }
 300
 301         I915_WRITE(SNB_DPFC_CTL_SA,
 302                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 303         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 304
 305         sandybridge_blit_fbc_update(dev);
 306
 307         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 308 }
 309
 310 bool intel_fbc_enabled(struct drm_device *dev)
 311 {
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313
 314         if (!dev_priv->display.fbc_enabled)
 315                 return false;
 316
 317         return dev_priv->display.fbc_enabled(dev);
 318 }
 319
 320 static void intel_fbc_work_fn(struct work_struct *__work)
 321 {
 322         struct intel_fbc_work *work =
 323                 container_of(to_delayed_work(__work),
 324                              struct intel_fbc_work, work);
 325         struct drm_device *dev = work->crtc->dev;
 326         struct drm_i915_private *dev_priv = dev->dev_private;
 327
 328         mutex_lock(&dev->struct_mutex);
 329         if (work == dev_priv->fbc.fbc_work) {
 330                 /* Double check that we haven't switched fb without cancelling
 331                  * the prior work.
 332                  */
 333                 if (work->crtc->fb == work->fb) {
 334                         dev_priv->display.enable_fbc(work->crtc);
 335
 336                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 337                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 338                         dev_priv->fbc.y = work->crtc->y;
 339                 }
 340
 341                 dev_priv->fbc.fbc_work = NULL;
 342         }
 343         mutex_unlock(&dev->struct_mutex);
 344
 345         kfree(work);
 346 }
 347
 348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 349 {
 350         if (dev_priv->fbc.fbc_work == NULL)
 351                 return;
 352
 353         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 354
 355         /* Synchronisation is provided by struct_mutex and checking of
 356          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 357          * entirely asynchronously.
 358          */
 359         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 360                 /* tasklet was killed before being run, clean up */
 361                 kfree(dev_priv->fbc.fbc_work);
 362
 363         /* Mark the work as no longer wanted so that if it does
 364          * wake-up (because the work was already running and waiting
 365          * for our mutex), it will discover that is no longer
 366          * necessary to run.
 367          */
 368         dev_priv->fbc.fbc_work = NULL;
 369 }
 370
 371 static void intel_enable_fbc(struct drm_crtc *crtc)
 372 {
 373         struct intel_fbc_work *work;
 374         struct drm_device *dev = crtc->dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         if (!dev_priv->display.enable_fbc)
 378                 return;
 379
 380         intel_cancel_fbc_work(dev_priv);
 381
 382         work = kzalloc(sizeof(*work), GFP_KERNEL);
 383         if (work == NULL) {
 384                 DRM_ERROR("Failed to allocate FBC work structure\n");
 385                 dev_priv->display.enable_fbc(crtc);
 386                 return;
 387         }
 388
 389         work->crtc = crtc;
 390         work->fb = crtc->fb;
 391         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 392
 393         dev_priv->fbc.fbc_work = work;
 394
 395         /* Delay the actual enabling to let pageflipping cease and the
 396          * display to settle before starting the compression. Note that
 397          * this delay also serves a second purpose: it allows for a
 398          * vblank to pass after disabling the FBC before we attempt
 399          * to modify the control registers.
 400          *
 401          * A more complicated solution would involve tracking vblanks
 402          * following the termination of the page-flipping sequence
 403          * and indeed performing the enable as a co-routine and not
 404          * waiting synchronously upon the vblank.
 405          *
 406          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 407          */
 408         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 409 }
 410
 411 void intel_disable_fbc(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         intel_cancel_fbc_work(dev_priv);
 416
 417         if (!dev_priv->display.disable_fbc)
 418                 return;
 419
 420         dev_priv->display.disable_fbc(dev);
 421         dev_priv->fbc.plane = -1;
 422 }
 423
 424 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 425                               enum no_fbc_reason reason)
 426 {
 427         if (dev_priv->fbc.no_fbc_reason == reason)
 428                 return false;
 429
 430         dev_priv->fbc.no_fbc_reason = reason;
 431         return true;
 432 }
 433
 434 /**
 435  * intel_update_fbc - enable/disable FBC as needed
 436  * @dev: the drm_device
 437  *
 438  * Set up the framebuffer compression hardware at mode set time.  We
 439  * enable it if possible:
 440  *   - plane A only (on pre-965)
 441  *   - no pixel mulitply/line duplication
 442  *   - no alpha buffer discard
 443  *   - no dual wide
 444  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 445  *
 446  * We can't assume that any compression will take place (worst case),
 447  * so the compressed buffer has to be the same size as the uncompressed
 448  * one.  It also must reside (along with the line length buffer) in
 449  * stolen memory.
 450  *
 451  * We need to enable/disable FBC on a global basis.
 452  */
 453 void intel_update_fbc(struct drm_device *dev)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         struct drm_crtc *crtc = NULL, *tmp_crtc;
 457         struct intel_crtc *intel_crtc;
 458         struct drm_framebuffer *fb;
 459         struct intel_framebuffer *intel_fb;
 460         struct drm_i915_gem_object *obj;
 461         const struct drm_display_mode *adjusted_mode;
 462         unsigned int max_width, max_height;
 463
 464         if (!I915_HAS_FBC(dev)) {
 465                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 466                 return;
 467         }
 468
 469         if (!i915_powersave) {
 470                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 471                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 472                 return;
 473         }
 474
 475         /*
 476          * If FBC is already on, we just have to verify that we can
 477          * keep it that way...
 478          * Need to disable if:
 479          *   - more than one pipe is active
 480          *   - changing FBC params (stride, fence, mode)
 481          *   - new fb is too large to fit in compressed buffer
 482          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 483          */
 484         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 485                 if (intel_crtc_active(tmp_crtc) &&
 486                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 487                         if (crtc) {
 488                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 489                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 490                                 goto out_disable;
 491                         }
 492                         crtc = tmp_crtc;
 493                 }
 494         }
 495
 496         if (!crtc || crtc->fb == NULL) {
 497                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 498                         DRM_DEBUG_KMS("no output, disabling\n");
 499                 goto out_disable;
 500         }
 501
 502         intel_crtc = to_intel_crtc(crtc);
 503         fb = crtc->fb;
 504         intel_fb = to_intel_framebuffer(fb);
 505         obj = intel_fb->obj;
 506         adjusted_mode = &intel_crtc->config.adjusted_mode;
 507
 508         if (i915_enable_fbc < 0 &&
 509             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 510                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 511                         DRM_DEBUG_KMS("disabled per chip default\n");
 512                 goto out_disable;
 513         }
 514         if (!i915_enable_fbc) {
 515                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 516                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 517                 goto out_disable;
 518         }
 519         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 520             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 522                         DRM_DEBUG_KMS("mode incompatible with compression, "
 523                                       "disabling\n");
 524                 goto out_disable;
 525         }
 526
 527         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 528                 max_width = 4096;
 529                 max_height = 2048;
 530         } else {
 531                 max_width = 2048;
 532                 max_height = 1536;
 533         }
 534         if (intel_crtc->config.pipe_src_w > max_width ||
 535             intel_crtc->config.pipe_src_h > max_height) {
 536                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 537                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 538                 goto out_disable;
 539         }
 540         if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
 541             intel_crtc->plane != PLANE_A) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 543                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 544                 goto out_disable;
 545         }
 546
 547         /* The use of a CPU fence is mandatory in order to detect writes
 548          * by the CPU to the scanout and trigger updates to the FBC.
 549          */
 550         if (obj->tiling_mode != I915_TILING_X ||
 551             obj->fence_reg == I915_FENCE_REG_NONE) {
 552                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 553                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 554                 goto out_disable;
 555         }
 556
 557         /* If the kernel debugger is active, always disable compression */
 558         if (in_dbg_master())
 559                 goto out_disable;
 560
 561         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 562                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 563                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 564                 goto out_disable;
 565         }
 566
 567         /* If the scanout has not changed, don't modify the FBC settings.
 568          * Note that we make the fundamental assumption that the fb->obj
 569          * cannot be unpinned (and have its GTT offset and fence revoked)
 570          * without first being decoupled from the scanout and FBC disabled.
 571          */
 572         if (dev_priv->fbc.plane == intel_crtc->plane &&
 573             dev_priv->fbc.fb_id == fb->base.id &&
 574             dev_priv->fbc.y == crtc->y)
 575                 return;
 576
 577         if (intel_fbc_enabled(dev)) {
 578                 /* We update FBC along two paths, after changing fb/crtc
 579                  * configuration (modeswitching) and after page-flipping
 580                  * finishes. For the latter, we know that not only did
 581                  * we disable the FBC at the start of the page-flip
 582                  * sequence, but also more than one vblank has passed.
 583                  *
 584                  * For the former case of modeswitching, it is possible
 585                  * to switch between two FBC valid configurations
 586                  * instantaneously so we do need to disable the FBC
 587                  * before we can modify its control registers. We also
 588                  * have to wait for the next vblank for that to take
 589                  * effect. However, since we delay enabling FBC we can
 590                  * assume that a vblank has passed since disabling and
 591                  * that we can safely alter the registers in the deferred
 592                  * callback.
 593                  *
 594                  * In the scenario that we go from a valid to invalid
 595                  * and then back to valid FBC configuration we have
 596                  * no strict enforcement that a vblank occurred since
 597                  * disabling the FBC. However, along all current pipe
 598                  * disabling paths we do need to wait for a vblank at
 599                  * some point. And we wait before enabling FBC anyway.
 600                  */
 601                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 602                 intel_disable_fbc(dev);
 603         }
 604
 605         intel_enable_fbc(crtc);
 606         dev_priv->fbc.no_fbc_reason = FBC_OK;
 607         return;
 608
 609 out_disable:
 610         /* Multiple disables should be harmless */
 611         if (intel_fbc_enabled(dev)) {
 612                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 613                 intel_disable_fbc(dev);
 614         }
 615         i915_gem_stolen_cleanup_compression(dev);
 616 }
 617
 618 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 619 {
 620         drm_i915_private_t *dev_priv = dev->dev_private;
 621         u32 tmp;
 622
 623         tmp = I915_READ(CLKCFG);
 624
 625         switch (tmp & CLKCFG_FSB_MASK) {
 626         case CLKCFG_FSB_533:
 627                 dev_priv->fsb_freq = 533; /* 133*4 */
 628                 break;
 629         case CLKCFG_FSB_800:
 630                 dev_priv->fsb_freq = 800; /* 200*4 */
 631                 break;
 632         case CLKCFG_FSB_667:
 633                 dev_priv->fsb_freq =  667; /* 167*4 */
 634                 break;
 635         case CLKCFG_FSB_400:
 636                 dev_priv->fsb_freq = 400; /* 100*4 */
 637                 break;
 638         }
 639
 640         switch (tmp & CLKCFG_MEM_MASK) {
 641         case CLKCFG_MEM_533:
 642                 dev_priv->mem_freq = 533;
 643                 break;
 644         case CLKCFG_MEM_667:
 645                 dev_priv->mem_freq = 667;
 646                 break;
 647         case CLKCFG_MEM_800:
 648                 dev_priv->mem_freq = 800;
 649                 break;
 650         }
 651
 652         /* detect pineview DDR3 setting */
 653         tmp = I915_READ(CSHRDDR3CTL);
 654         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 655 }
 656
 657 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 658 {
 659         drm_i915_private_t *dev_priv = dev->dev_private;
 660         u16 ddrpll, csipll;
 661
 662         ddrpll = I915_READ16(DDRMPLL1);
 663         csipll = I915_READ16(CSIPLL0);
 664
 665         switch (ddrpll & 0xff) {
 666         case 0xc:
 667                 dev_priv->mem_freq = 800;
 668                 break;
 669         case 0x10:
 670                 dev_priv->mem_freq = 1066;
 671                 break;
 672         case 0x14:
 673                 dev_priv->mem_freq = 1333;
 674                 break;
 675         case 0x18:
 676                 dev_priv->mem_freq = 1600;
 677                 break;
 678         default:
 679                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 680                                  ddrpll & 0xff);
 681                 dev_priv->mem_freq = 0;
 682                 break;
 683         }
 684
 685         dev_priv->ips.r_t = dev_priv->mem_freq;
 686
 687         switch (csipll & 0x3ff) {
 688         case 0x00c:
 689                 dev_priv->fsb_freq = 3200;
 690                 break;
 691         case 0x00e:
 692                 dev_priv->fsb_freq = 3733;
 693                 break;
 694         case 0x010:
 695                 dev_priv->fsb_freq = 4266;
 696                 break;
 697         case 0x012:
 698                 dev_priv->fsb_freq = 4800;
 699                 break;
 700         case 0x014:
 701                 dev_priv->fsb_freq = 5333;
 702                 break;
 703         case 0x016:
 704                 dev_priv->fsb_freq = 5866;
 705                 break;
 706         case 0x018:
 707                 dev_priv->fsb_freq = 6400;
 708                 break;
 709         default:
 710                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 711                                  csipll & 0x3ff);
 712                 dev_priv->fsb_freq = 0;
 713                 break;
 714         }
 715
 716         if (dev_priv->fsb_freq == 3200) {
 717                 dev_priv->ips.c_m = 0;
 718         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 719                 dev_priv->ips.c_m = 1;
 720         } else {
 721                 dev_priv->ips.c_m = 2;
 722         }
 723 }
 724
 725 static const struct cxsr_latency cxsr_latency_table[] = {
 726         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 727         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 728         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 729         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 730         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 731
 732         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 733         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 734         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 735         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 736         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 737
 738         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 739         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 740         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 741         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 742         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 743
 744         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 745         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 746         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 747         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 748         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 749
 750         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 751         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 752         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 753         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 754         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 755
 756         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 757         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 758         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 759         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 760         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 761 };
 762
 763 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 764                                                          int is_ddr3,
 765                                                          int fsb,
 766                                                          int mem)
 767 {
 768         const struct cxsr_latency *latency;
 769         int i;
 770
 771         if (fsb == 0 || mem == 0)
 772                 return NULL;
 773
 774         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 775                 latency = &cxsr_latency_table[i];
 776                 if (is_desktop == latency->is_desktop &&
 777                     is_ddr3 == latency->is_ddr3 &&
 778                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 779                         return latency;
 780         }
 781
 782         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 783
 784         return NULL;
 785 }
 786
 787 static void pineview_disable_cxsr(struct drm_device *dev)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790
 791         /* deactivate cxsr */
 792         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 793 }
 794
 795 /*
 796  * Latency for FIFO fetches is dependent on several factors:
 797  *   - memory configuration (speed, channels)
 798  *   - chipset
 799  *   - current MCH state
 800  * It can be fairly high in some situations, so here we assume a fairly
 801  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 802  * set this value too high, the FIFO will fetch frequently to stay full)
 803  * and power consumption (set it too low to save power and we might see
 804  * FIFO underruns and display "flicker").
 805  *
 806  * A value of 5us seems to be a good balance; safe for very low end
 807  * platforms but not overly aggressive on lower latency configs.
 808  */
 809 static const int latency_ns = 5000;
 810
 811 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 812 {
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         uint32_t dsparb = I915_READ(DSPARB);
 815         int size;
 816
 817         size = dsparb & 0x7f;
 818         if (plane)
 819                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 820
 821         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 822                       plane ? "B" : "A", size);
 823
 824         return size;
 825 }
 826
 827 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 828 {
 829         struct drm_i915_private *dev_priv = dev->dev_private;
 830         uint32_t dsparb = I915_READ(DSPARB);
 831         int size;
 832
 833         size = dsparb & 0x1ff;
 834         if (plane)
 835                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 836         size >>= 1; /* Convert to cachelines */
 837
 838         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 839                       plane ? "B" : "A", size);
 840
 841         return size;
 842 }
 843
 844 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         uint32_t dsparb = I915_READ(DSPARB);
 848         int size;
 849
 850         size = dsparb & 0x7f;
 851         size >>= 2; /* Convert to cachelines */
 852
 853         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 854                       plane ? "B" : "A",
 855                       size);
 856
 857         return size;
 858 }
 859
 860 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 861 {
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863         uint32_t dsparb = I915_READ(DSPARB);
 864         int size;
 865
 866         size = dsparb & 0x7f;
 867         size >>= 1; /* Convert to cachelines */
 868
 869         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 870                       plane ? "B" : "A", size);
 871
 872         return size;
 873 }
 874
 875 /* Pineview has different values for various configs */
 876 static const struct intel_watermark_params pineview_display_wm = {
 877         PINEVIEW_DISPLAY_FIFO,
 878         PINEVIEW_MAX_WM,
 879         PINEVIEW_DFT_WM,
 880         PINEVIEW_GUARD_WM,
 881         PINEVIEW_FIFO_LINE_SIZE
 882 };
 883 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 884         PINEVIEW_DISPLAY_FIFO,
 885         PINEVIEW_MAX_WM,
 886         PINEVIEW_DFT_HPLLOFF_WM,
 887         PINEVIEW_GUARD_WM,
 888         PINEVIEW_FIFO_LINE_SIZE
 889 };
 890 static const struct intel_watermark_params pineview_cursor_wm = {
 891         PINEVIEW_CURSOR_FIFO,
 892         PINEVIEW_CURSOR_MAX_WM,
 893         PINEVIEW_CURSOR_DFT_WM,
 894         PINEVIEW_CURSOR_GUARD_WM,
 895         PINEVIEW_FIFO_LINE_SIZE,
 896 };
 897 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 898         PINEVIEW_CURSOR_FIFO,
 899         PINEVIEW_CURSOR_MAX_WM,
 900         PINEVIEW_CURSOR_DFT_WM,
 901         PINEVIEW_CURSOR_GUARD_WM,
 902         PINEVIEW_FIFO_LINE_SIZE
 903 };
 904 static const struct intel_watermark_params g4x_wm_info = {
 905         G4X_FIFO_SIZE,
 906         G4X_MAX_WM,
 907         G4X_MAX_WM,
 908         2,
 909         G4X_FIFO_LINE_SIZE,
 910 };
 911 static const struct intel_watermark_params g4x_cursor_wm_info = {
 912         I965_CURSOR_FIFO,
 913         I965_CURSOR_MAX_WM,
 914         I965_CURSOR_DFT_WM,
 915         2,
 916         G4X_FIFO_LINE_SIZE,
 917 };
 918 static const struct intel_watermark_params valleyview_wm_info = {
 919         VALLEYVIEW_FIFO_SIZE,
 920         VALLEYVIEW_MAX_WM,
 921         VALLEYVIEW_MAX_WM,
 922         2,
 923         G4X_FIFO_LINE_SIZE,
 924 };
 925 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 926         I965_CURSOR_FIFO,
 927         VALLEYVIEW_CURSOR_MAX_WM,
 928         I965_CURSOR_DFT_WM,
 929         2,
 930         G4X_FIFO_LINE_SIZE,
 931 };
 932 static const struct intel_watermark_params i965_cursor_wm_info = {
 933         I965_CURSOR_FIFO,
 934         I965_CURSOR_MAX_WM,
 935         I965_CURSOR_DFT_WM,
 936         2,
 937         I915_FIFO_LINE_SIZE,
 938 };
 939 static const struct intel_watermark_params i945_wm_info = {
 940         I945_FIFO_SIZE,
 941         I915_MAX_WM,
 942         1,
 943         2,
 944         I915_FIFO_LINE_SIZE
 945 };
 946 static const struct intel_watermark_params i915_wm_info = {
 947         I915_FIFO_SIZE,
 948         I915_MAX_WM,
 949         1,
 950         2,
 951         I915_FIFO_LINE_SIZE
 952 };
 953 static const struct intel_watermark_params i855_wm_info = {
 954         I855GM_FIFO_SIZE,
 955         I915_MAX_WM,
 956         1,
 957         2,
 958         I830_FIFO_LINE_SIZE
 959 };
 960 static const struct intel_watermark_params i830_wm_info = {
 961         I830_FIFO_SIZE,
 962         I915_MAX_WM,
 963         1,
 964         2,
 965         I830_FIFO_LINE_SIZE
 966 };
 967
 968 static const struct intel_watermark_params ironlake_display_wm_info = {
 969         ILK_DISPLAY_FIFO,
 970         ILK_DISPLAY_MAXWM,
 971         ILK_DISPLAY_DFTWM,
 972         2,
 973         ILK_FIFO_LINE_SIZE
 974 };
 975 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 976         ILK_CURSOR_FIFO,
 977         ILK_CURSOR_MAXWM,
 978         ILK_CURSOR_DFTWM,
 979         2,
 980         ILK_FIFO_LINE_SIZE
 981 };
 982 static const struct intel_watermark_params ironlake_display_srwm_info = {
 983         ILK_DISPLAY_SR_FIFO,
 984         ILK_DISPLAY_MAX_SRWM,
 985         ILK_DISPLAY_DFT_SRWM,
 986         2,
 987         ILK_FIFO_LINE_SIZE
 988 };
 989 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 990         ILK_CURSOR_SR_FIFO,
 991         ILK_CURSOR_MAX_SRWM,
 992         ILK_CURSOR_DFT_SRWM,
 993         2,
 994         ILK_FIFO_LINE_SIZE
 995 };
 996
 997 static const struct intel_watermark_params sandybridge_display_wm_info = {
 998         SNB_DISPLAY_FIFO,
 999         SNB_DISPLAY_MAXWM,
1000         SNB_DISPLAY_DFTWM,
1001         2,
1002         SNB_FIFO_LINE_SIZE
1003 };
1004 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1005         SNB_CURSOR_FIFO,
1006         SNB_CURSOR_MAXWM,
1007         SNB_CURSOR_DFTWM,
1008         2,
1009         SNB_FIFO_LINE_SIZE
1010 };
1011 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1012         SNB_DISPLAY_SR_FIFO,
1013         SNB_DISPLAY_MAX_SRWM,
1014         SNB_DISPLAY_DFT_SRWM,
1015         2,
1016         SNB_FIFO_LINE_SIZE
1017 };
1018 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1019         SNB_CURSOR_SR_FIFO,
1020         SNB_CURSOR_MAX_SRWM,
1021         SNB_CURSOR_DFT_SRWM,
1022         2,
1023         SNB_FIFO_LINE_SIZE
1024 };
1025
1026
1027 /**
1028  * intel_calculate_wm - calculate watermark level
1029  * @clock_in_khz: pixel clock
1030  * @wm: chip FIFO params
1031  * @pixel_size: display pixel size
1032  * @latency_ns: memory latency for the platform
1033  *
1034  * Calculate the watermark level (the level at which the display plane will
1035  * start fetching from memory again).  Each chip has a different display
1036  * FIFO size and allocation, so the caller needs to figure that out and pass
1037  * in the correct intel_watermark_params structure.
1038  *
1039  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1040  * on the pixel size.  When it reaches the watermark level, it'll start
1041  * fetching FIFO line sized based chunks from memory until the FIFO fills
1042  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1043  * will occur, and a display engine hang could result.
1044  */
1045 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1046                                         const struct intel_watermark_params *wm,
1047                                         int fifo_size,
1048                                         int pixel_size,
1049                                         unsigned long latency_ns)
1050 {
1051         long entries_required, wm_size;
1052
1053         /*
1054          * Note: we need to make sure we don't overflow for various clock &
1055          * latency values.
1056          * clocks go from a few thousand to several hundred thousand.
1057          * latency is usually a few thousand
1058          */
1059         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1060                 1000;
1061         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1062
1063         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1064
1065         wm_size = fifo_size - (entries_required + wm->guard_size);
1066
1067         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1068
1069         /* Don't promote wm_size to unsigned... */
1070         if (wm_size > (long)wm->max_wm)
1071                 wm_size = wm->max_wm;
1072         if (wm_size <= 0)
1073                 wm_size = wm->default_wm;
1074         return wm_size;
1075 }
1076
1077 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1078 {
1079         struct drm_crtc *crtc, *enabled = NULL;
1080
1081         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1082                 if (intel_crtc_active(crtc)) {
1083                         if (enabled)
1084                                 return NULL;
1085                         enabled = crtc;
1086                 }
1087         }
1088
1089         return enabled;
1090 }
1091
1092 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1093 {
1094         struct drm_device *dev = unused_crtc->dev;
1095         struct drm_i915_private *dev_priv = dev->dev_private;
1096         struct drm_crtc *crtc;
1097         const struct cxsr_latency *latency;
1098         u32 reg;
1099         unsigned long wm;
1100
1101         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1102                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1103         if (!latency) {
1104                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1105                 pineview_disable_cxsr(dev);
1106                 return;
1107         }
1108
1109         crtc = single_enabled_crtc(dev);
1110         if (crtc) {
1111                 const struct drm_display_mode *adjusted_mode;
1112                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1113                 int clock;
1114
1115                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1116                 clock = adjusted_mode->crtc_clock;
1117
1118                 /* Display SR */
1119                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1120                                         pineview_display_wm.fifo_size,
1121                                         pixel_size, latency->display_sr);
1122                 reg = I915_READ(DSPFW1);
1123                 reg &= ~DSPFW_SR_MASK;
1124                 reg |= wm << DSPFW_SR_SHIFT;
1125                 I915_WRITE(DSPFW1, reg);
1126                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1127
1128                 /* cursor SR */
1129                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1130                                         pineview_display_wm.fifo_size,
1131                                         pixel_size, latency->cursor_sr);
1132                 reg = I915_READ(DSPFW3);
1133                 reg &= ~DSPFW_CURSOR_SR_MASK;
1134                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1135                 I915_WRITE(DSPFW3, reg);
1136
1137                 /* Display HPLL off SR */
1138                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1139                                         pineview_display_hplloff_wm.fifo_size,
1140                                         pixel_size, latency->display_hpll_disable);
1141                 reg = I915_READ(DSPFW3);
1142                 reg &= ~DSPFW_HPLL_SR_MASK;
1143                 reg |= wm & DSPFW_HPLL_SR_MASK;
1144                 I915_WRITE(DSPFW3, reg);
1145
1146                 /* cursor HPLL off SR */
1147                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1148                                         pineview_display_hplloff_wm.fifo_size,
1149                                         pixel_size, latency->cursor_hpll_disable);
1150                 reg = I915_READ(DSPFW3);
1151                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1152                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1153                 I915_WRITE(DSPFW3, reg);
1154                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1155
1156                 /* activate cxsr */
1157                 I915_WRITE(DSPFW3,
1158                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1159                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1160         } else {
1161                 pineview_disable_cxsr(dev);
1162                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1163         }
1164 }
1165
1166 static bool g4x_compute_wm0(struct drm_device *dev,
1167                             int plane,
1168                             const struct intel_watermark_params *display,
1169                             int display_latency_ns,
1170                             const struct intel_watermark_params *cursor,
1171                             int cursor_latency_ns,
1172                             int *plane_wm,
1173                             int *cursor_wm)
1174 {
1175         struct drm_crtc *crtc;
1176         const struct drm_display_mode *adjusted_mode;
1177         int htotal, hdisplay, clock, pixel_size;
1178         int line_time_us, line_count;
1179         int entries, tlb_miss;
1180
1181         crtc = intel_get_crtc_for_plane(dev, plane);
1182         if (!intel_crtc_active(crtc)) {
1183                 *cursor_wm = cursor->guard_size;
1184                 *plane_wm = display->guard_size;
1185                 return false;
1186         }
1187
1188         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1189         clock = adjusted_mode->crtc_clock;
1190         htotal = adjusted_mode->htotal;
1191         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1192         pixel_size = crtc->fb->bits_per_pixel / 8;
1193
1194         /* Use the small buffer method to calculate plane watermark */
1195         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1196         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1197         if (tlb_miss > 0)
1198                 entries += tlb_miss;
1199         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1200         *plane_wm = entries + display->guard_size;
1201         if (*plane_wm > (int)display->max_wm)
1202                 *plane_wm = display->max_wm;
1203
1204         /* Use the large buffer method to calculate cursor watermark */
1205         line_time_us = ((htotal * 1000) / clock);
1206         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1207         entries = line_count * 64 * pixel_size;
1208         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1209         if (tlb_miss > 0)
1210                 entries += tlb_miss;
1211         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1212         *cursor_wm = entries + cursor->guard_size;
1213         if (*cursor_wm > (int)cursor->max_wm)
1214                 *cursor_wm = (int)cursor->max_wm;
1215
1216         return true;
1217 }
1218
1219 /*
1220  * Check the wm result.
1221  *
1222  * If any calculated watermark values is larger than the maximum value that
1223  * can be programmed into the associated watermark register, that watermark
1224  * must be disabled.
1225  */
1226 static bool g4x_check_srwm(struct drm_device *dev,
1227                            int display_wm, int cursor_wm,
1228                            const struct intel_watermark_params *display,
1229                            const struct intel_watermark_params *cursor)
1230 {
1231         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1232                       display_wm, cursor_wm);
1233
1234         if (display_wm > display->max_wm) {
1235                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1236                               display_wm, display->max_wm);
1237                 return false;
1238         }
1239
1240         if (cursor_wm > cursor->max_wm) {
1241                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1242                               cursor_wm, cursor->max_wm);
1243                 return false;
1244         }
1245
1246         if (!(display_wm || cursor_wm)) {
1247                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1248                 return false;
1249         }
1250
1251         return true;
1252 }
1253
1254 static bool g4x_compute_srwm(struct drm_device *dev,
1255                              int plane,
1256                              int latency_ns,
1257                              const struct intel_watermark_params *display,
1258                              const struct intel_watermark_params *cursor,
1259                              int *display_wm, int *cursor_wm)
1260 {
1261         struct drm_crtc *crtc;
1262         const struct drm_display_mode *adjusted_mode;
1263         int hdisplay, htotal, pixel_size, clock;
1264         unsigned long line_time_us;
1265         int line_count, line_size;
1266         int small, large;
1267         int entries;
1268
1269         if (!latency_ns) {
1270                 *display_wm = *cursor_wm = 0;
1271                 return false;
1272         }
1273
1274         crtc = intel_get_crtc_for_plane(dev, plane);
1275         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1276         clock = adjusted_mode->crtc_clock;
1277         htotal = adjusted_mode->htotal;
1278         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1279         pixel_size = crtc->fb->bits_per_pixel / 8;
1280
1281         line_time_us = (htotal * 1000) / clock;
1282         line_count = (latency_ns / line_time_us + 1000) / 1000;
1283         line_size = hdisplay * pixel_size;
1284
1285         /* Use the minimum of the small and large buffer method for primary */
1286         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1287         large = line_count * line_size;
1288
1289         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1290         *display_wm = entries + display->guard_size;
1291
1292         /* calculate the self-refresh watermark for display cursor */
1293         entries = line_count * pixel_size * 64;
1294         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1295         *cursor_wm = entries + cursor->guard_size;
1296
1297         return g4x_check_srwm(dev,
1298                               *display_wm, *cursor_wm,
1299                               display, cursor);
1300 }
1301
1302 static bool vlv_compute_drain_latency(struct drm_device *dev,
1303                                      int plane,
1304                                      int *plane_prec_mult,
1305                                      int *plane_dl,
1306                                      int *cursor_prec_mult,
1307                                      int *cursor_dl)
1308 {
1309         struct drm_crtc *crtc;
1310         int clock, pixel_size;
1311         int entries;
1312
1313         crtc = intel_get_crtc_for_plane(dev, plane);
1314         if (!intel_crtc_active(crtc))
1315                 return false;
1316
1317         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1318         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1319
1320         entries = (clock / 1000) * pixel_size;
1321         *plane_prec_mult = (entries > 256) ?
1322                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1323         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1324                                                      pixel_size);
1325
1326         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1327         *cursor_prec_mult = (entries > 256) ?
1328                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1329         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1330
1331         return true;
1332 }
1333
1334 /*
1335  * Update drain latency registers of memory arbiter
1336  *
1337  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1338  * to be programmed. Each plane has a drain latency multiplier and a drain
1339  * latency value.
1340  */
1341
1342 static void vlv_update_drain_latency(struct drm_device *dev)
1343 {
1344         struct drm_i915_private *dev_priv = dev->dev_private;
1345         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1346         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1347         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1348                                                         either 16 or 32 */
1349
1350         /* For plane A, Cursor A */
1351         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1352                                       &cursor_prec_mult, &cursora_dl)) {
1353                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1354                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1355                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1357
1358                 I915_WRITE(VLV_DDL1, cursora_prec |
1359                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1360                                 planea_prec | planea_dl);
1361         }
1362
1363         /* For plane B, Cursor B */
1364         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1365                                       &cursor_prec_mult, &cursorb_dl)) {
1366                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1367                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1368                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1369                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1370
1371                 I915_WRITE(VLV_DDL2, cursorb_prec |
1372                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1373                                 planeb_prec | planeb_dl);
1374         }
1375 }
1376
1377 #define single_plane_enabled(mask) is_power_of_2(mask)
1378
1379 static void valleyview_update_wm(struct drm_crtc *crtc)
1380 {
1381         struct drm_device *dev = crtc->dev;
1382         static const int sr_latency_ns = 12000;
1383         struct drm_i915_private *dev_priv = dev->dev_private;
1384         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1385         int plane_sr, cursor_sr;
1386         int ignore_plane_sr, ignore_cursor_sr;
1387         unsigned int enabled = 0;
1388
1389         vlv_update_drain_latency(dev);
1390
1391         if (g4x_compute_wm0(dev, PIPE_A,
1392                             &valleyview_wm_info, latency_ns,
1393                             &valleyview_cursor_wm_info, latency_ns,
1394                             &planea_wm, &cursora_wm))
1395                 enabled |= 1 << PIPE_A;
1396
1397         if (g4x_compute_wm0(dev, PIPE_B,
1398                             &valleyview_wm_info, latency_ns,
1399                             &valleyview_cursor_wm_info, latency_ns,
1400                             &planeb_wm, &cursorb_wm))
1401                 enabled |= 1 << PIPE_B;
1402
1403         if (single_plane_enabled(enabled) &&
1404             g4x_compute_srwm(dev, ffs(enabled) - 1,
1405                              sr_latency_ns,
1406                              &valleyview_wm_info,
1407                              &valleyview_cursor_wm_info,
1408                              &plane_sr, &ignore_cursor_sr) &&
1409             g4x_compute_srwm(dev, ffs(enabled) - 1,
1410                              2*sr_latency_ns,
1411                              &valleyview_wm_info,
1412                              &valleyview_cursor_wm_info,
1413                              &ignore_plane_sr, &cursor_sr)) {
1414                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1415         } else {
1416                 I915_WRITE(FW_BLC_SELF_VLV,
1417                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1418                 plane_sr = cursor_sr = 0;
1419         }
1420
1421         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422                       planea_wm, cursora_wm,
1423                       planeb_wm, cursorb_wm,
1424                       plane_sr, cursor_sr);
1425
1426         I915_WRITE(DSPFW1,
1427                    (plane_sr << DSPFW_SR_SHIFT) |
1428                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1429                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1430                    planea_wm);
1431         I915_WRITE(DSPFW2,
1432                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1433                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1434         I915_WRITE(DSPFW3,
1435                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1436                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1437 }
1438
1439 static void g4x_update_wm(struct drm_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->dev;
1442         static const int sr_latency_ns = 12000;
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1445         int plane_sr, cursor_sr;
1446         unsigned int enabled = 0;
1447
1448         if (g4x_compute_wm0(dev, PIPE_A,
1449                             &g4x_wm_info, latency_ns,
1450                             &g4x_cursor_wm_info, latency_ns,
1451                             &planea_wm, &cursora_wm))
1452                 enabled |= 1 << PIPE_A;
1453
1454         if (g4x_compute_wm0(dev, PIPE_B,
1455                             &g4x_wm_info, latency_ns,
1456                             &g4x_cursor_wm_info, latency_ns,
1457                             &planeb_wm, &cursorb_wm))
1458                 enabled |= 1 << PIPE_B;
1459
1460         if (single_plane_enabled(enabled) &&
1461             g4x_compute_srwm(dev, ffs(enabled) - 1,
1462                              sr_latency_ns,
1463                              &g4x_wm_info,
1464                              &g4x_cursor_wm_info,
1465                              &plane_sr, &cursor_sr)) {
1466                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1467         } else {
1468                 I915_WRITE(FW_BLC_SELF,
1469                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1470                 plane_sr = cursor_sr = 0;
1471         }
1472
1473         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1474                       planea_wm, cursora_wm,
1475                       planeb_wm, cursorb_wm,
1476                       plane_sr, cursor_sr);
1477
1478         I915_WRITE(DSPFW1,
1479                    (plane_sr << DSPFW_SR_SHIFT) |
1480                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1481                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1482                    planea_wm);
1483         I915_WRITE(DSPFW2,
1484                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1485                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1486         /* HPLL off in SR has some issues on G4x... disable it */
1487         I915_WRITE(DSPFW3,
1488                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1489                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490 }
1491
1492 static void i965_update_wm(struct drm_crtc *unused_crtc)
1493 {
1494         struct drm_device *dev = unused_crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         struct drm_crtc *crtc;
1497         int srwm = 1;
1498         int cursor_sr = 16;
1499
1500         /* Calc sr entries for one plane configs */
1501         crtc = single_enabled_crtc(dev);
1502         if (crtc) {
1503                 /* self-refresh has much higher latency */
1504                 static const int sr_latency_ns = 12000;
1505                 const struct drm_display_mode *adjusted_mode =
1506                         &to_intel_crtc(crtc)->config.adjusted_mode;
1507                 int clock = adjusted_mode->crtc_clock;
1508                 int htotal = adjusted_mode->htotal;
1509                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1510                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1511                 unsigned long line_time_us;
1512                 int entries;
1513
1514                 line_time_us = ((htotal * 1000) / clock);
1515
1516                 /* Use ns/us then divide to preserve precision */
1517                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1518                         pixel_size * hdisplay;
1519                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1520                 srwm = I965_FIFO_SIZE - entries;
1521                 if (srwm < 0)
1522                         srwm = 1;
1523                 srwm &= 0x1ff;
1524                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1525                               entries, srwm);
1526
1527                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1528                         pixel_size * 64;
1529                 entries = DIV_ROUND_UP(entries,
1530                                           i965_cursor_wm_info.cacheline_size);
1531                 cursor_sr = i965_cursor_wm_info.fifo_size -
1532                         (entries + i965_cursor_wm_info.guard_size);
1533
1534                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1535                         cursor_sr = i965_cursor_wm_info.max_wm;
1536
1537                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1538                               "cursor %d\n", srwm, cursor_sr);
1539
1540                 if (IS_CRESTLINE(dev))
1541                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1542         } else {
1543                 /* Turn off self refresh if both pipes are enabled */
1544                 if (IS_CRESTLINE(dev))
1545                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1546                                    & ~FW_BLC_SELF_EN);
1547         }
1548
1549         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1550                       srwm);
1551
1552         /* 965 has limitations... */
1553         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1554                    (8 << 16) | (8 << 8) | (8 << 0));
1555         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1556         /* update cursor SR watermark */
1557         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1558 }
1559
1560 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1561 {
1562         struct drm_device *dev = unused_crtc->dev;
1563         struct drm_i915_private *dev_priv = dev->dev_private;
1564         const struct intel_watermark_params *wm_info;
1565         uint32_t fwater_lo;
1566         uint32_t fwater_hi;
1567         int cwm, srwm = 1;
1568         int fifo_size;
1569         int planea_wm, planeb_wm;
1570         struct drm_crtc *crtc, *enabled = NULL;
1571
1572         if (IS_I945GM(dev))
1573                 wm_info = &i945_wm_info;
1574         else if (!IS_GEN2(dev))
1575                 wm_info = &i915_wm_info;
1576         else
1577                 wm_info = &i855_wm_info;
1578
1579         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1580         crtc = intel_get_crtc_for_plane(dev, 0);
1581         if (intel_crtc_active(crtc)) {
1582                 const struct drm_display_mode *adjusted_mode;
1583                 int cpp = crtc->fb->bits_per_pixel / 8;
1584                 if (IS_GEN2(dev))
1585                         cpp = 4;
1586
1587                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1588                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1589                                                wm_info, fifo_size, cpp,
1590                                                latency_ns);
1591                 enabled = crtc;
1592         } else
1593                 planea_wm = fifo_size - wm_info->guard_size;
1594
1595         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1596         crtc = intel_get_crtc_for_plane(dev, 1);
1597         if (intel_crtc_active(crtc)) {
1598                 const struct drm_display_mode *adjusted_mode;
1599                 int cpp = crtc->fb->bits_per_pixel / 8;
1600                 if (IS_GEN2(dev))
1601                         cpp = 4;
1602
1603                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1604                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1605                                                wm_info, fifo_size, cpp,
1606                                                latency_ns);
1607                 if (enabled == NULL)
1608                         enabled = crtc;
1609                 else
1610                         enabled = NULL;
1611         } else
1612                 planeb_wm = fifo_size - wm_info->guard_size;
1613
1614         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1615
1616         /*
1617          * Overlay gets an aggressive default since video jitter is bad.
1618          */
1619         cwm = 2;
1620
1621         /* Play safe and disable self-refresh before adjusting watermarks. */
1622         if (IS_I945G(dev) || IS_I945GM(dev))
1623                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1624         else if (IS_I915GM(dev))
1625                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1626
1627         /* Calc sr entries for one plane configs */
1628         if (HAS_FW_BLC(dev) && enabled) {
1629                 /* self-refresh has much higher latency */
1630                 static const int sr_latency_ns = 6000;
1631                 const struct drm_display_mode *adjusted_mode =
1632                         &to_intel_crtc(enabled)->config.adjusted_mode;
1633                 int clock = adjusted_mode->crtc_clock;
1634                 int htotal = adjusted_mode->htotal;
1635                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1636                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1637                 unsigned long line_time_us;
1638                 int entries;
1639
1640                 line_time_us = (htotal * 1000) / clock;
1641
1642                 /* Use ns/us then divide to preserve precision */
1643                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644                         pixel_size * hdisplay;
1645                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647                 srwm = wm_info->fifo_size - entries;
1648                 if (srwm < 0)
1649                         srwm = 1;
1650
1651                 if (IS_I945G(dev) || IS_I945GM(dev))
1652                         I915_WRITE(FW_BLC_SELF,
1653                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654                 else if (IS_I915GM(dev))
1655                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656         }
1657
1658         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659                       planea_wm, planeb_wm, cwm, srwm);
1660
1661         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662         fwater_hi = (cwm & 0x1f);
1663
1664         /* Set request length to 8 cachelines per fetch */
1665         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666         fwater_hi = fwater_hi | (1 << 8);
1667
1668         I915_WRITE(FW_BLC, fwater_lo);
1669         I915_WRITE(FW_BLC2, fwater_hi);
1670
1671         if (HAS_FW_BLC(dev)) {
1672                 if (enabled) {
1673                         if (IS_I945G(dev) || IS_I945GM(dev))
1674                                 I915_WRITE(FW_BLC_SELF,
1675                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1676                         else if (IS_I915GM(dev))
1677                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1678                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1679                 } else
1680                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1681         }
1682 }
1683
1684 static void i830_update_wm(struct drm_crtc *unused_crtc)
1685 {
1686         struct drm_device *dev = unused_crtc->dev;
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         struct drm_crtc *crtc;
1689         const struct drm_display_mode *adjusted_mode;
1690         uint32_t fwater_lo;
1691         int planea_wm;
1692
1693         crtc = single_enabled_crtc(dev);
1694         if (crtc == NULL)
1695                 return;
1696
1697         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1698         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1699                                        &i830_wm_info,
1700                                        dev_priv->display.get_fifo_size(dev, 0),
1701                                        4, latency_ns);
1702         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1703         fwater_lo |= (3<<8) | planea_wm;
1704
1705         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1706
1707         I915_WRITE(FW_BLC, fwater_lo);
1708 }
1709
1710 /*
1711  * Check the wm result.
1712  *
1713  * If any calculated watermark values is larger than the maximum value that
1714  * can be programmed into the associated watermark register, that watermark
1715  * must be disabled.
1716  */
1717 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1718                                 int fbc_wm, int display_wm, int cursor_wm,
1719                                 const struct intel_watermark_params *display,
1720                                 const struct intel_watermark_params *cursor)
1721 {
1722         struct drm_i915_private *dev_priv = dev->dev_private;
1723
1724         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1725                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1726
1727         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1728                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1729                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1730
1731                 /* fbc has it's own way to disable FBC WM */
1732                 I915_WRITE(DISP_ARB_CTL,
1733                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1734                 return false;
1735         } else if (INTEL_INFO(dev)->gen >= 6) {
1736                 /* enable FBC WM (except on ILK, where it must remain off) */
1737                 I915_WRITE(DISP_ARB_CTL,
1738                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1739         }
1740
1741         if (display_wm > display->max_wm) {
1742                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1743                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1744                 return false;
1745         }
1746
1747         if (cursor_wm > cursor->max_wm) {
1748                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1749                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1750                 return false;
1751         }
1752
1753         if (!(fbc_wm || display_wm || cursor_wm)) {
1754                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1755                 return false;
1756         }
1757
1758         return true;
1759 }
1760
1761 /*
1762  * Compute watermark values of WM[1-3],
1763  */
1764 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1765                                   int latency_ns,
1766                                   const struct intel_watermark_params *display,
1767                                   const struct intel_watermark_params *cursor,
1768                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1769 {
1770         struct drm_crtc *crtc;
1771         const struct drm_display_mode *adjusted_mode;
1772         unsigned long line_time_us;
1773         int hdisplay, htotal, pixel_size, clock;
1774         int line_count, line_size;
1775         int small, large;
1776         int entries;
1777
1778         if (!latency_ns) {
1779                 *fbc_wm = *display_wm = *cursor_wm = 0;
1780                 return false;
1781         }
1782
1783         crtc = intel_get_crtc_for_plane(dev, plane);
1784         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1785         clock = adjusted_mode->crtc_clock;
1786         htotal = adjusted_mode->htotal;
1787         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1788         pixel_size = crtc->fb->bits_per_pixel / 8;
1789
1790         line_time_us = (htotal * 1000) / clock;
1791         line_count = (latency_ns / line_time_us + 1000) / 1000;
1792         line_size = hdisplay * pixel_size;
1793
1794         /* Use the minimum of the small and large buffer method for primary */
1795         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1796         large = line_count * line_size;
1797
1798         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1799         *display_wm = entries + display->guard_size;
1800
1801         /*
1802          * Spec says:
1803          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1804          */
1805         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1806
1807         /* calculate the self-refresh watermark for display cursor */
1808         entries = line_count * pixel_size * 64;
1809         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1810         *cursor_wm = entries + cursor->guard_size;
1811
1812         return ironlake_check_srwm(dev, level,
1813                                    *fbc_wm, *display_wm, *cursor_wm,
1814                                    display, cursor);
1815 }
1816
1817 static void ironlake_update_wm(struct drm_crtc *crtc)
1818 {
1819         struct drm_device *dev = crtc->dev;
1820         struct drm_i915_private *dev_priv = dev->dev_private;
1821         int fbc_wm, plane_wm, cursor_wm;
1822         unsigned int enabled;
1823
1824         enabled = 0;
1825         if (g4x_compute_wm0(dev, PIPE_A,
1826                             &ironlake_display_wm_info,
1827                             dev_priv->wm.pri_latency[0] * 100,
1828                             &ironlake_cursor_wm_info,
1829                             dev_priv->wm.cur_latency[0] * 100,
1830                             &plane_wm, &cursor_wm)) {
1831                 I915_WRITE(WM0_PIPEA_ILK,
1832                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1833                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1834                               " plane %d, " "cursor: %d\n",
1835                               plane_wm, cursor_wm);
1836                 enabled |= 1 << PIPE_A;
1837         }
1838
1839         if (g4x_compute_wm0(dev, PIPE_B,
1840                             &ironlake_display_wm_info,
1841                             dev_priv->wm.pri_latency[0] * 100,
1842                             &ironlake_cursor_wm_info,
1843                             dev_priv->wm.cur_latency[0] * 100,
1844                             &plane_wm, &cursor_wm)) {
1845                 I915_WRITE(WM0_PIPEB_ILK,
1846                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1847                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1848                               " plane %d, cursor: %d\n",
1849                               plane_wm, cursor_wm);
1850                 enabled |= 1 << PIPE_B;
1851         }
1852
1853         /*
1854          * Calculate and update the self-refresh watermark only when one
1855          * display plane is used.
1856          */
1857         I915_WRITE(WM3_LP_ILK, 0);
1858         I915_WRITE(WM2_LP_ILK, 0);
1859         I915_WRITE(WM1_LP_ILK, 0);
1860
1861         if (!single_plane_enabled(enabled))
1862                 return;
1863         enabled = ffs(enabled) - 1;
1864
1865         /* WM1 */
1866         if (!ironlake_compute_srwm(dev, 1, enabled,
1867                                    dev_priv->wm.pri_latency[1] * 500,
1868                                    &ironlake_display_srwm_info,
1869                                    &ironlake_cursor_srwm_info,
1870                                    &fbc_wm, &plane_wm, &cursor_wm))
1871                 return;
1872
1873         I915_WRITE(WM1_LP_ILK,
1874                    WM1_LP_SR_EN |
1875                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1876                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1877                    (plane_wm << WM1_LP_SR_SHIFT) |
1878                    cursor_wm);
1879
1880         /* WM2 */
1881         if (!ironlake_compute_srwm(dev, 2, enabled,
1882                                    dev_priv->wm.pri_latency[2] * 500,
1883                                    &ironlake_display_srwm_info,
1884                                    &ironlake_cursor_srwm_info,
1885                                    &fbc_wm, &plane_wm, &cursor_wm))
1886                 return;
1887
1888         I915_WRITE(WM2_LP_ILK,
1889                    WM2_LP_EN |
1890                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1891                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1892                    (plane_wm << WM1_LP_SR_SHIFT) |
1893                    cursor_wm);
1894
1895         /*
1896          * WM3 is unsupported on ILK, probably because we don't have latency
1897          * data for that power state
1898          */
1899 }
1900
1901 static void sandybridge_update_wm(struct drm_crtc *crtc)
1902 {
1903         struct drm_device *dev = crtc->dev;
1904         struct drm_i915_private *dev_priv = dev->dev_private;
1905         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1906         u32 val;
1907         int fbc_wm, plane_wm, cursor_wm;
1908         unsigned int enabled;
1909
1910         enabled = 0;
1911         if (g4x_compute_wm0(dev, PIPE_A,
1912                             &sandybridge_display_wm_info, latency,
1913                             &sandybridge_cursor_wm_info, latency,
1914                             &plane_wm, &cursor_wm)) {
1915                 val = I915_READ(WM0_PIPEA_ILK);
1916                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1917                 I915_WRITE(WM0_PIPEA_ILK, val |
1918                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1919                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1920                               " plane %d, " "cursor: %d\n",
1921                               plane_wm, cursor_wm);
1922                 enabled |= 1 << PIPE_A;
1923         }
1924
1925         if (g4x_compute_wm0(dev, PIPE_B,
1926                             &sandybridge_display_wm_info, latency,
1927                             &sandybridge_cursor_wm_info, latency,
1928                             &plane_wm, &cursor_wm)) {
1929                 val = I915_READ(WM0_PIPEB_ILK);
1930                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1931                 I915_WRITE(WM0_PIPEB_ILK, val |
1932                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1933                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1934                               " plane %d, cursor: %d\n",
1935                               plane_wm, cursor_wm);
1936                 enabled |= 1 << PIPE_B;
1937         }
1938
1939         /*
1940          * Calculate and update the self-refresh watermark only when one
1941          * display plane is used.
1942          *
1943          * SNB support 3 levels of watermark.
1944          *
1945          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1946          * and disabled in the descending order
1947          *
1948          */
1949         I915_WRITE(WM3_LP_ILK, 0);
1950         I915_WRITE(WM2_LP_ILK, 0);
1951         I915_WRITE(WM1_LP_ILK, 0);
1952
1953         if (!single_plane_enabled(enabled) ||
1954             dev_priv->sprite_scaling_enabled)
1955                 return;
1956         enabled = ffs(enabled) - 1;
1957
1958         /* WM1 */
1959         if (!ironlake_compute_srwm(dev, 1, enabled,
1960                                    dev_priv->wm.pri_latency[1] * 500,
1961                                    &sandybridge_display_srwm_info,
1962                                    &sandybridge_cursor_srwm_info,
1963                                    &fbc_wm, &plane_wm, &cursor_wm))
1964                 return;
1965
1966         I915_WRITE(WM1_LP_ILK,
1967                    WM1_LP_SR_EN |
1968                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1969                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1970                    (plane_wm << WM1_LP_SR_SHIFT) |
1971                    cursor_wm);
1972
1973         /* WM2 */
1974         if (!ironlake_compute_srwm(dev, 2, enabled,
1975                                    dev_priv->wm.pri_latency[2] * 500,
1976                                    &sandybridge_display_srwm_info,
1977                                    &sandybridge_cursor_srwm_info,
1978                                    &fbc_wm, &plane_wm, &cursor_wm))
1979                 return;
1980
1981         I915_WRITE(WM2_LP_ILK,
1982                    WM2_LP_EN |
1983                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1984                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1985                    (plane_wm << WM1_LP_SR_SHIFT) |
1986                    cursor_wm);
1987
1988         /* WM3 */
1989         if (!ironlake_compute_srwm(dev, 3, enabled,
1990                                    dev_priv->wm.pri_latency[3] * 500,
1991                                    &sandybridge_display_srwm_info,
1992                                    &sandybridge_cursor_srwm_info,
1993                                    &fbc_wm, &plane_wm, &cursor_wm))
1994                 return;
1995
1996         I915_WRITE(WM3_LP_ILK,
1997                    WM3_LP_EN |
1998                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1999                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2000                    (plane_wm << WM1_LP_SR_SHIFT) |
2001                    cursor_wm);
2002 }
2003
2004 static void ivybridge_update_wm(struct drm_crtc *crtc)
2005 {
2006         struct drm_device *dev = crtc->dev;
2007         struct drm_i915_private *dev_priv = dev->dev_private;
2008         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
2009         u32 val;
2010         int fbc_wm, plane_wm, cursor_wm;
2011         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2012         unsigned int enabled;
2013
2014         enabled = 0;
2015         if (g4x_compute_wm0(dev, PIPE_A,
2016                             &sandybridge_display_wm_info, latency,
2017                             &sandybridge_cursor_wm_info, latency,
2018                             &plane_wm, &cursor_wm)) {
2019                 val = I915_READ(WM0_PIPEA_ILK);
2020                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2021                 I915_WRITE(WM0_PIPEA_ILK, val |
2022                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2023                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2024                               " plane %d, " "cursor: %d\n",
2025                               plane_wm, cursor_wm);
2026                 enabled |= 1 << PIPE_A;
2027         }
2028
2029         if (g4x_compute_wm0(dev, PIPE_B,
2030                             &sandybridge_display_wm_info, latency,
2031                             &sandybridge_cursor_wm_info, latency,
2032                             &plane_wm, &cursor_wm)) {
2033                 val = I915_READ(WM0_PIPEB_ILK);
2034                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2035                 I915_WRITE(WM0_PIPEB_ILK, val |
2036                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2037                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2038                               " plane %d, cursor: %d\n",
2039                               plane_wm, cursor_wm);
2040                 enabled |= 1 << PIPE_B;
2041         }
2042
2043         if (g4x_compute_wm0(dev, PIPE_C,
2044                             &sandybridge_display_wm_info, latency,
2045                             &sandybridge_cursor_wm_info, latency,
2046                             &plane_wm, &cursor_wm)) {
2047                 val = I915_READ(WM0_PIPEC_IVB);
2048                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2049                 I915_WRITE(WM0_PIPEC_IVB, val |
2050                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2051                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2052                               " plane %d, cursor: %d\n",
2053                               plane_wm, cursor_wm);
2054                 enabled |= 1 << PIPE_C;
2055         }
2056
2057         /*
2058          * Calculate and update the self-refresh watermark only when one
2059          * display plane is used.
2060          *
2061          * SNB support 3 levels of watermark.
2062          *
2063          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2064          * and disabled in the descending order
2065          *
2066          */
2067         I915_WRITE(WM3_LP_ILK, 0);
2068         I915_WRITE(WM2_LP_ILK, 0);
2069         I915_WRITE(WM1_LP_ILK, 0);
2070
2071         if (!single_plane_enabled(enabled) ||
2072             dev_priv->sprite_scaling_enabled)
2073                 return;
2074         enabled = ffs(enabled) - 1;
2075
2076         /* WM1 */
2077         if (!ironlake_compute_srwm(dev, 1, enabled,
2078                                    dev_priv->wm.pri_latency[1] * 500,
2079                                    &sandybridge_display_srwm_info,
2080                                    &sandybridge_cursor_srwm_info,
2081                                    &fbc_wm, &plane_wm, &cursor_wm))
2082                 return;
2083
2084         I915_WRITE(WM1_LP_ILK,
2085                    WM1_LP_SR_EN |
2086                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2087                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2088                    (plane_wm << WM1_LP_SR_SHIFT) |
2089                    cursor_wm);
2090
2091         /* WM2 */
2092         if (!ironlake_compute_srwm(dev, 2, enabled,
2093                                    dev_priv->wm.pri_latency[2] * 500,
2094                                    &sandybridge_display_srwm_info,
2095                                    &sandybridge_cursor_srwm_info,
2096                                    &fbc_wm, &plane_wm, &cursor_wm))
2097                 return;
2098
2099         I915_WRITE(WM2_LP_ILK,
2100                    WM2_LP_EN |
2101                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2102                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2103                    (plane_wm << WM1_LP_SR_SHIFT) |
2104                    cursor_wm);
2105
2106         /* WM3, note we have to correct the cursor latency */
2107         if (!ironlake_compute_srwm(dev, 3, enabled,
2108                                    dev_priv->wm.pri_latency[3] * 500,
2109                                    &sandybridge_display_srwm_info,
2110                                    &sandybridge_cursor_srwm_info,
2111                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2112             !ironlake_compute_srwm(dev, 3, enabled,
2113                                    dev_priv->wm.cur_latency[3] * 500,
2114                                    &sandybridge_display_srwm_info,
2115                                    &sandybridge_cursor_srwm_info,
2116                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2117                 return;
2118
2119         I915_WRITE(WM3_LP_ILK,
2120                    WM3_LP_EN |
2121                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2122                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2123                    (plane_wm << WM1_LP_SR_SHIFT) |
2124                    cursor_wm);
2125 }
2126
2127 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2128                                     struct drm_crtc *crtc)
2129 {
2130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131         uint32_t pixel_rate;
2132
2133         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2134
2135         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2136          * adjust the pixel_rate here. */
2137
2138         if (intel_crtc->config.pch_pfit.enabled) {
2139                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2140                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2141
2142                 pipe_w = intel_crtc->config.pipe_src_w;
2143                 pipe_h = intel_crtc->config.pipe_src_h;
2144                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2145                 pfit_h = pfit_size & 0xFFFF;
2146                 if (pipe_w < pfit_w)
2147                         pipe_w = pfit_w;
2148                 if (pipe_h < pfit_h)
2149                         pipe_h = pfit_h;
2150
2151                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2152                                      pfit_w * pfit_h);
2153         }
2154
2155         return pixel_rate;
2156 }
2157
2158 /* latency must be in 0.1us units. */
2159 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2160                                uint32_t latency)
2161 {
2162         uint64_t ret;
2163
2164         if (WARN(latency == 0, "Latency value missing\n"))
2165                 return UINT_MAX;
2166
2167         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2168         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2169
2170         return ret;
2171 }
2172
2173 /* latency must be in 0.1us units. */
2174 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2175                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2176                                uint32_t latency)
2177 {
2178         uint32_t ret;
2179
2180         if (WARN(latency == 0, "Latency value missing\n"))
2181                 return UINT_MAX;
2182
2183         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2184         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2185         ret = DIV_ROUND_UP(ret, 64) + 2;
2186         return ret;
2187 }
2188
2189 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2190                            uint8_t bytes_per_pixel)
2191 {
2192         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2193 }
2194
2195 struct hsw_pipe_wm_parameters {
2196         bool active;
2197         uint32_t pipe_htotal;
2198         uint32_t pixel_rate;
2199         struct intel_plane_wm_parameters pri;
2200         struct intel_plane_wm_parameters spr;
2201         struct intel_plane_wm_parameters cur;
2202 };
2203
2204 struct hsw_wm_maximums {
2205         uint16_t pri;
2206         uint16_t spr;
2207         uint16_t cur;
2208         uint16_t fbc;
2209 };
2210
2211 /* used in computing the new watermarks state */
2212 struct intel_wm_config {
2213         unsigned int num_pipes_active;
2214         bool sprites_enabled;
2215         bool sprites_scaled;
2216 };
2217
2218 /*
2219  * For both WM_PIPE and WM_LP.
2220  * mem_value must be in 0.1us units.
2221  */
2222 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2223                                    uint32_t mem_value,
2224                                    bool is_lp)
2225 {
2226         uint32_t method1, method2;
2227
2228         if (!params->active || !params->pri.enabled)
2229                 return 0;
2230
2231         method1 = ilk_wm_method1(params->pixel_rate,
2232                                  params->pri.bytes_per_pixel,
2233                                  mem_value);
2234
2235         if (!is_lp)
2236                 return method1;
2237
2238         method2 = ilk_wm_method2(params->pixel_rate,
2239                                  params->pipe_htotal,
2240                                  params->pri.horiz_pixels,
2241                                  params->pri.bytes_per_pixel,
2242                                  mem_value);
2243
2244         return min(method1, method2);
2245 }
2246
2247 /*
2248  * For both WM_PIPE and WM_LP.
2249  * mem_value must be in 0.1us units.
2250  */
2251 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2252                                    uint32_t mem_value)
2253 {
2254         uint32_t method1, method2;
2255
2256         if (!params->active || !params->spr.enabled)
2257                 return 0;
2258
2259         method1 = ilk_wm_method1(params->pixel_rate,
2260                                  params->spr.bytes_per_pixel,
2261                                  mem_value);
2262         method2 = ilk_wm_method2(params->pixel_rate,
2263                                  params->pipe_htotal,
2264                                  params->spr.horiz_pixels,
2265                                  params->spr.bytes_per_pixel,
2266                                  mem_value);
2267         return min(method1, method2);
2268 }
2269
2270 /*
2271  * For both WM_PIPE and WM_LP.
2272  * mem_value must be in 0.1us units.
2273  */
2274 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2275                                    uint32_t mem_value)
2276 {
2277         if (!params->active || !params->cur.enabled)
2278                 return 0;
2279
2280         return ilk_wm_method2(params->pixel_rate,
2281                               params->pipe_htotal,
2282                               params->cur.horiz_pixels,
2283                               params->cur.bytes_per_pixel,
2284                               mem_value);
2285 }
2286
2287 /* Only for WM_LP. */
2288 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2289                                    uint32_t pri_val)
2290 {
2291         if (!params->active || !params->pri.enabled)
2292                 return 0;
2293
2294         return ilk_wm_fbc(pri_val,
2295                           params->pri.horiz_pixels,
2296                           params->pri.bytes_per_pixel);
2297 }
2298
2299 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2300 {
2301         if (INTEL_INFO(dev)->gen >= 8)
2302                 return 3072;
2303         else if (INTEL_INFO(dev)->gen >= 7)
2304                 return 768;
2305         else
2306                 return 512;
2307 }
2308
2309 /* Calculate the maximum primary/sprite plane watermark */
2310 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2311                                      int level,
2312                                      const struct intel_wm_config *config,
2313                                      enum intel_ddb_partitioning ddb_partitioning,
2314                                      bool is_sprite)
2315 {
2316         unsigned int fifo_size = ilk_display_fifo_size(dev);
2317         unsigned int max;
2318
2319         /* if sprites aren't enabled, sprites get nothing */
2320         if (is_sprite && !config->sprites_enabled)
2321                 return 0;
2322
2323         /* HSW allows LP1+ watermarks even with multiple pipes */
2324         if (level == 0 || config->num_pipes_active > 1) {
2325                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2326
2327                 /*
2328                  * For some reason the non self refresh
2329                  * FIFO size is only half of the self
2330                  * refresh FIFO size on ILK/SNB.
2331                  */
2332                 if (INTEL_INFO(dev)->gen <= 6)
2333                         fifo_size /= 2;
2334         }
2335
2336         if (config->sprites_enabled) {
2337                 /* level 0 is always calculated with 1:1 split */
2338                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2339                         if (is_sprite)
2340                                 fifo_size *= 5;
2341                         fifo_size /= 6;
2342                 } else {
2343                         fifo_size /= 2;
2344                 }
2345         }
2346
2347         /* clamp to max that the registers can hold */
2348         if (INTEL_INFO(dev)->gen >= 8)
2349                 max = level == 0 ? 255 : 2047;
2350         else if (INTEL_INFO(dev)->gen >= 7)
2351                 /* IVB/HSW primary/sprite plane watermarks */
2352                 max = level == 0 ? 127 : 1023;
2353         else if (!is_sprite)
2354                 /* ILK/SNB primary plane watermarks */
2355                 max = level == 0 ? 127 : 511;
2356         else
2357                 /* ILK/SNB sprite plane watermarks */
2358                 max = level == 0 ? 63 : 255;
2359
2360         return min(fifo_size, max);
2361 }
2362
2363 /* Calculate the maximum cursor plane watermark */
2364 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2365                                       int level,
2366                                       const struct intel_wm_config *config)
2367 {
2368         /* HSW LP1+ watermarks w/ multiple pipes */
2369         if (level > 0 && config->num_pipes_active > 1)
2370                 return 64;
2371
2372         /* otherwise just report max that registers can hold */
2373         if (INTEL_INFO(dev)->gen >= 7)
2374                 return level == 0 ? 63 : 255;
2375         else
2376                 return level == 0 ? 31 : 63;
2377 }
2378
2379 /* Calculate the maximum FBC watermark */
2380 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
2381 {
2382         /* max that registers can hold */
2383         if (INTEL_INFO(dev)->gen >= 8)
2384                 return 31;
2385         else
2386                 return 15;
2387 }
2388
2389 static void ilk_compute_wm_maximums(struct drm_device *dev,
2390                                     int level,
2391                                     const struct intel_wm_config *config,
2392                                     enum intel_ddb_partitioning ddb_partitioning,
2393                                     struct hsw_wm_maximums *max)
2394 {
2395         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2396         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2397         max->cur = ilk_cursor_wm_max(dev, level, config);
2398         max->fbc = ilk_fbc_wm_max(dev);
2399 }
2400
2401 static bool ilk_validate_wm_level(int level,
2402                                   const struct hsw_wm_maximums *max,
2403                                   struct intel_wm_level *result)
2404 {
2405         bool ret;
2406
2407         /* already determined to be invalid? */
2408         if (!result->enable)
2409                 return false;
2410
2411         result->enable = result->pri_val <= max->pri &&
2412                          result->spr_val <= max->spr &&
2413                          result->cur_val <= max->cur;
2414
2415         ret = result->enable;
2416
2417         /*
2418          * HACK until we can pre-compute everything,
2419          * and thus fail gracefully if LP0 watermarks
2420          * are exceeded...
2421          */
2422         if (level == 0 && !result->enable) {
2423                 if (result->pri_val > max->pri)
2424                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2425                                       level, result->pri_val, max->pri);
2426                 if (result->spr_val > max->spr)
2427                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2428                                       level, result->spr_val, max->spr);
2429                 if (result->cur_val > max->cur)
2430                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2431                                       level, result->cur_val, max->cur);
2432
2433                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2434                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2435                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2436                 result->enable = true;
2437         }
2438
2439         return ret;
2440 }
2441
2442 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2443                                  int level,
2444                                  const struct hsw_pipe_wm_parameters *p,
2445                                  struct intel_wm_level *result)
2446 {
2447         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2448         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2449         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2450
2451         /* WM1+ latency values stored in 0.5us units */
2452         if (level > 0) {
2453                 pri_latency *= 5;
2454                 spr_latency *= 5;
2455                 cur_latency *= 5;
2456         }
2457
2458         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2459         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2460         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2461         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2462         result->enable = true;
2463 }
2464
2465 static uint32_t
2466 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2467 {
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2471         u32 linetime, ips_linetime;
2472
2473         if (!intel_crtc_active(crtc))
2474                 return 0;
2475
2476         /* The WM are computed with base on how long it takes to fill a single
2477          * row at the given clock rate, multiplied by 8.
2478          * */
2479         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2480         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2481                                          intel_ddi_get_cdclk_freq(dev_priv));
2482
2483         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2484                PIPE_WM_LINETIME_TIME(linetime);
2485 }
2486
2487 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2488 {
2489         struct drm_i915_private *dev_priv = dev->dev_private;
2490
2491         if (IS_HASWELL(dev)) {
2492                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2493
2494                 wm[0] = (sskpd >> 56) & 0xFF;
2495                 if (wm[0] == 0)
2496                         wm[0] = sskpd & 0xF;
2497                 wm[1] = (sskpd >> 4) & 0xFF;
2498                 wm[2] = (sskpd >> 12) & 0xFF;
2499                 wm[3] = (sskpd >> 20) & 0x1FF;
2500                 wm[4] = (sskpd >> 32) & 0x1FF;
2501         } else if (INTEL_INFO(dev)->gen >= 6) {
2502                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2503
2504                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2505                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2506                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2507                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2508         } else if (INTEL_INFO(dev)->gen >= 5) {
2509                 uint32_t mltr = I915_READ(MLTR_ILK);
2510
2511                 /* ILK primary LP0 latency is 700 ns */
2512                 wm[0] = 7;
2513                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2514                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2515         }
2516 }
2517
2518 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2519 {
2520         /* ILK sprite LP0 latency is 1300 ns */
2521         if (INTEL_INFO(dev)->gen == 5)
2522                 wm[0] = 13;
2523 }
2524
2525 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2526 {
2527         /* ILK cursor LP0 latency is 1300 ns */
2528         if (INTEL_INFO(dev)->gen == 5)
2529                 wm[0] = 13;
2530
2531         /* WaDoubleCursorLP3Latency:ivb */
2532         if (IS_IVYBRIDGE(dev))
2533                 wm[3] *= 2;
2534 }
2535
2536 static int ilk_wm_max_level(const struct drm_device *dev)
2537 {
2538         /* how many WM levels are we expecting */
2539         if (IS_HASWELL(dev))
2540                 return 4;
2541         else if (INTEL_INFO(dev)->gen >= 6)
2542                 return 3;
2543         else
2544                 return 2;
2545 }
2546
2547 static void intel_print_wm_latency(struct drm_device *dev,
2548                                    const char *name,
2549                                    const uint16_t wm[5])
2550 {
2551         int level, max_level = ilk_wm_max_level(dev);
2552
2553         for (level = 0; level <= max_level; level++) {
2554                 unsigned int latency = wm[level];
2555
2556                 if (latency == 0) {
2557                         DRM_ERROR("%s WM%d latency not provided\n",
2558                                   name, level);
2559                         continue;
2560                 }
2561
2562                 /* WM1+ latency values in 0.5us units */
2563                 if (level > 0)
2564                         latency *= 5;
2565
2566                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2567                               name, level, wm[level],
2568                               latency / 10, latency % 10);
2569         }
2570 }
2571
2572 static void intel_setup_wm_latency(struct drm_device *dev)
2573 {
2574         struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2577
2578         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2579                sizeof(dev_priv->wm.pri_latency));
2580         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2581                sizeof(dev_priv->wm.pri_latency));
2582
2583         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2584         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2585
2586         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2587         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2588         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2589 }
2590
2591 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2592                                       struct hsw_pipe_wm_parameters *p,
2593                                       struct intel_wm_config *config)
2594 {
2595         struct drm_device *dev = crtc->dev;
2596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597         enum pipe pipe = intel_crtc->pipe;
2598         struct drm_plane *plane;
2599
2600         p->active = intel_crtc_active(crtc);
2601         if (p->active) {
2602                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2603                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2604                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2605                 p->cur.bytes_per_pixel = 4;
2606                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2607                 p->cur.horiz_pixels = 64;
2608                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2609                 p->pri.enabled = true;
2610                 p->cur.enabled = true;
2611         }
2612
2613         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2614                 config->num_pipes_active += intel_crtc_active(crtc);
2615
2616         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2617                 struct intel_plane *intel_plane = to_intel_plane(plane);
2618
2619                 if (intel_plane->pipe == pipe)
2620                         p->spr = intel_plane->wm;
2621
2622                 config->sprites_enabled |= intel_plane->wm.enabled;
2623                 config->sprites_scaled |= intel_plane->wm.scaled;
2624         }
2625 }
2626
2627 /* Compute new watermarks for the pipe */
2628 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2629                                   const struct hsw_pipe_wm_parameters *params,
2630                                   struct intel_pipe_wm *pipe_wm)
2631 {
2632         struct drm_device *dev = crtc->dev;
2633         struct drm_i915_private *dev_priv = dev->dev_private;
2634         int level, max_level = ilk_wm_max_level(dev);
2635         /* LP0 watermark maximums depend on this pipe alone */
2636         struct intel_wm_config config = {
2637                 .num_pipes_active = 1,
2638                 .sprites_enabled = params->spr.enabled,
2639                 .sprites_scaled = params->spr.scaled,
2640         };
2641         struct hsw_wm_maximums max;
2642
2643         /* LP0 watermarks always use 1/2 DDB partitioning */
2644         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2645
2646         for (level = 0; level <= max_level; level++)
2647                 ilk_compute_wm_level(dev_priv, level, params,
2648                                      &pipe_wm->wm[level]);
2649
2650         pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2651
2652         /* At least LP0 must be valid */
2653         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2654 }
2655
2656 /*
2657  * Merge the watermarks from all active pipes for a specific level.
2658  */
2659 static void ilk_merge_wm_level(struct drm_device *dev,
2660                                int level,
2661                                struct intel_wm_level *ret_wm)
2662 {
2663         const struct intel_crtc *intel_crtc;
2664
2665         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2666                 const struct intel_wm_level *wm =
2667                         &intel_crtc->wm.active.wm[level];
2668
2669                 if (!wm->enable)
2670                         return;
2671
2672                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2673                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2674                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2675                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2676         }
2677
2678         ret_wm->enable = true;
2679 }
2680
2681 /*
2682  * Merge all low power watermarks for all active pipes.
2683  */
2684 static void ilk_wm_merge(struct drm_device *dev,
2685                          const struct hsw_wm_maximums *max,
2686                          struct intel_pipe_wm *merged)
2687 {
2688         int level, max_level = ilk_wm_max_level(dev);
2689
2690         merged->fbc_wm_enabled = true;
2691
2692         /* merge each WM1+ level */
2693         for (level = 1; level <= max_level; level++) {
2694                 struct intel_wm_level *wm = &merged->wm[level];
2695
2696                 ilk_merge_wm_level(dev, level, wm);
2697
2698                 if (!ilk_validate_wm_level(level, max, wm))
2699                         break;
2700
2701                 /*
2702                  * The spec says it is preferred to disable
2703                  * FBC WMs instead of disabling a WM level.
2704                  */
2705                 if (wm->fbc_val > max->fbc) {
2706                         merged->fbc_wm_enabled = false;
2707                         wm->fbc_val = 0;
2708                 }
2709         }
2710 }
2711
2712 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2713 {
2714         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2715         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2716 }
2717
2718 /* The value we need to program into the WM_LPx latency field */
2719 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2720 {
2721         struct drm_i915_private *dev_priv = dev->dev_private;
2722
2723         if (IS_HASWELL(dev))
2724                 return 2 * level;
2725         else
2726                 return dev_priv->wm.pri_latency[level];
2727 }
2728
2729 static void hsw_compute_wm_results(struct drm_device *dev,
2730                                    const struct intel_pipe_wm *merged,
2731                                    enum intel_ddb_partitioning partitioning,
2732                                    struct hsw_wm_values *results)
2733 {
2734         struct intel_crtc *intel_crtc;
2735         int level, wm_lp;
2736
2737         results->enable_fbc_wm = merged->fbc_wm_enabled;
2738         results->partitioning = partitioning;
2739
2740         /* LP1+ register values */
2741         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2742                 const struct intel_wm_level *r;
2743
2744                 level = ilk_wm_lp_to_level(wm_lp, merged);
2745
2746                 r = &merged->wm[level];
2747                 if (!r->enable)
2748                         break;
2749
2750                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2751                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2752                         (r->pri_val << WM1_LP_SR_SHIFT) |
2753                         r->cur_val;
2754
2755                 if (INTEL_INFO(dev)->gen >= 8)
2756                         results->wm_lp[wm_lp - 1] |=
2757                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2758                 else
2759                         results->wm_lp[wm_lp - 1] |=
2760                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2761
2762                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2763         }
2764
2765         /* LP0 register values */
2766         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2767                 enum pipe pipe = intel_crtc->pipe;
2768                 const struct intel_wm_level *r =
2769                         &intel_crtc->wm.active.wm[0];
2770
2771                 if (WARN_ON(!r->enable))
2772                         continue;
2773
2774                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2775
2776                 results->wm_pipe[pipe] =
2777                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2778                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2779                         r->cur_val;
2780         }
2781 }
2782
2783 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2784  * case both are at the same level. Prefer r1 in case they're the same. */
2785 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2786                                                   struct intel_pipe_wm *r1,
2787                                                   struct intel_pipe_wm *r2)
2788 {
2789         int level, max_level = ilk_wm_max_level(dev);
2790         int level1 = 0, level2 = 0;
2791
2792         for (level = 1; level <= max_level; level++) {
2793                 if (r1->wm[level].enable)
2794                         level1 = level;
2795                 if (r2->wm[level].enable)
2796                         level2 = level;
2797         }
2798
2799         if (level1 == level2) {
2800                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2801                         return r2;
2802                 else
2803                         return r1;
2804         } else if (level1 > level2) {
2805                 return r1;
2806         } else {
2807                 return r2;
2808         }
2809 }
2810
2811 /* dirty bits used to track which watermarks need changes */
2812 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2813 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2814 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2815 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2816 #define WM_DIRTY_FBC (1 << 24)
2817 #define WM_DIRTY_DDB (1 << 25)
2818
2819 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2820                                          const struct hsw_wm_values *old,
2821                                          const struct hsw_wm_values *new)
2822 {
2823         unsigned int dirty = 0;
2824         enum pipe pipe;
2825         int wm_lp;
2826
2827         for_each_pipe(pipe) {
2828                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2829                         dirty |= WM_DIRTY_LINETIME(pipe);
2830                         /* Must disable LP1+ watermarks too */
2831                         dirty |= WM_DIRTY_LP_ALL;
2832                 }
2833
2834                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2835                         dirty |= WM_DIRTY_PIPE(pipe);
2836                         /* Must disable LP1+ watermarks too */
2837                         dirty |= WM_DIRTY_LP_ALL;
2838                 }
2839         }
2840
2841         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2842                 dirty |= WM_DIRTY_FBC;
2843                 /* Must disable LP1+ watermarks too */
2844                 dirty |= WM_DIRTY_LP_ALL;
2845         }
2846
2847         if (old->partitioning != new->partitioning) {
2848                 dirty |= WM_DIRTY_DDB;
2849                 /* Must disable LP1+ watermarks too */
2850                 dirty |= WM_DIRTY_LP_ALL;
2851         }
2852
2853         /* LP1+ watermarks already deemed dirty, no need to continue */
2854         if (dirty & WM_DIRTY_LP_ALL)
2855                 return dirty;
2856
2857         /* Find the lowest numbered LP1+ watermark in need of an update... */
2858         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2859                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2860                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2861                         break;
2862         }
2863
2864         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2865         for (; wm_lp <= 3; wm_lp++)
2866                 dirty |= WM_DIRTY_LP(wm_lp);
2867
2868         return dirty;
2869 }
2870
2871 /*
2872  * The spec says we shouldn't write when we don't need, because every write
2873  * causes WMs to be re-evaluated, expending some power.
2874  */
2875 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2876                                 struct hsw_wm_values *results)
2877 {
2878         struct drm_device *dev = dev_priv->dev;
2879         struct hsw_wm_values *previous = &dev_priv->wm.hw;
2880         unsigned int dirty;
2881         uint32_t val;
2882
2883         dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2884         if (!dirty)
2885                 return;
2886
2887         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2888                 I915_WRITE(WM3_LP_ILK, 0);
2889         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2890                 I915_WRITE(WM2_LP_ILK, 0);
2891         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2892                 I915_WRITE(WM1_LP_ILK, 0);
2893
2894         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2895                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2896         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2897                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2898         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2899                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2900
2901         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2902                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2903         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2904                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2905         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2906                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2907
2908         if (dirty & WM_DIRTY_DDB) {
2909                 if (IS_HASWELL(dev)) {
2910                         val = I915_READ(WM_MISC);
2911                         if (results->partitioning == INTEL_DDB_PART_1_2)
2912                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2913                         else
2914                                 val |= WM_MISC_DATA_PARTITION_5_6;
2915                         I915_WRITE(WM_MISC, val);
2916                 } else {
2917                         val = I915_READ(DISP_ARB_CTL2);
2918                         if (results->partitioning == INTEL_DDB_PART_1_2)
2919                                 val &= ~DISP_DATA_PARTITION_5_6;
2920                         else
2921                                 val |= DISP_DATA_PARTITION_5_6;
2922                         I915_WRITE(DISP_ARB_CTL2, val);
2923                 }
2924         }
2925
2926         if (dirty & WM_DIRTY_FBC) {
2927                 val = I915_READ(DISP_ARB_CTL);
2928                 if (results->enable_fbc_wm)
2929                         val &= ~DISP_FBC_WM_DIS;
2930                 else
2931                         val |= DISP_FBC_WM_DIS;
2932                 I915_WRITE(DISP_ARB_CTL, val);
2933         }
2934
2935         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2936                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2937         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2938                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2939         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2940                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2941
2942         if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2943                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2944         if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2945                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2946         if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2947                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2948
2949         dev_priv->wm.hw = *results;
2950 }
2951
2952 static void haswell_update_wm(struct drm_crtc *crtc)
2953 {
2954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2955         struct drm_device *dev = crtc->dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         struct hsw_wm_maximums max;
2958         struct hsw_pipe_wm_parameters params = {};
2959         struct hsw_wm_values results = {};
2960         enum intel_ddb_partitioning partitioning;
2961         struct intel_pipe_wm pipe_wm = {};
2962         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2963         struct intel_wm_config config = {};
2964
2965         hsw_compute_wm_parameters(crtc, &params, &config);
2966
2967         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2968
2969         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2970                 return;
2971
2972         intel_crtc->wm.active = pipe_wm;
2973
2974         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2975         ilk_wm_merge(dev, &max, &lp_wm_1_2);
2976
2977         /* 5/6 split only in single pipe config on IVB+ */
2978         if (INTEL_INFO(dev)->gen >= 7 &&
2979             config.num_pipes_active == 1 && config.sprites_enabled) {
2980                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2981                 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2982
2983                 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2984         } else {
2985                 best_lp_wm = &lp_wm_1_2;
2986         }
2987
2988         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2989                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2990
2991         hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2992
2993         hsw_write_wm_values(dev_priv, &results);
2994 }
2995
2996 static void haswell_update_sprite_wm(struct drm_plane *plane,
2997                                      struct drm_crtc *crtc,
2998                                      uint32_t sprite_width, int pixel_size,
2999                                      bool enabled, bool scaled)
3000 {
3001         struct intel_plane *intel_plane = to_intel_plane(plane);
3002
3003         intel_plane->wm.enabled = enabled;
3004         intel_plane->wm.scaled = scaled;
3005         intel_plane->wm.horiz_pixels = sprite_width;
3006         intel_plane->wm.bytes_per_pixel = pixel_size;
3007
3008         haswell_update_wm(crtc);
3009 }
3010
3011 static bool
3012 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
3013                               uint32_t sprite_width, int pixel_size,
3014                               const struct intel_watermark_params *display,
3015                               int display_latency_ns, int *sprite_wm)
3016 {
3017         struct drm_crtc *crtc;
3018         int clock;
3019         int entries, tlb_miss;
3020
3021         crtc = intel_get_crtc_for_plane(dev, plane);
3022         if (!intel_crtc_active(crtc)) {
3023                 *sprite_wm = display->guard_size;
3024                 return false;
3025         }
3026
3027         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3028
3029         /* Use the small buffer method to calculate the sprite watermark */
3030         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3031         tlb_miss = display->fifo_size*display->cacheline_size -
3032                 sprite_width * 8;
3033         if (tlb_miss > 0)
3034                 entries += tlb_miss;
3035         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3036         *sprite_wm = entries + display->guard_size;
3037         if (*sprite_wm > (int)display->max_wm)
3038                 *sprite_wm = display->max_wm;
3039
3040         return true;
3041 }
3042
3043 static bool
3044 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3045                                 uint32_t sprite_width, int pixel_size,
3046                                 const struct intel_watermark_params *display,
3047                                 int latency_ns, int *sprite_wm)
3048 {
3049         struct drm_crtc *crtc;
3050         unsigned long line_time_us;
3051         int clock;
3052         int line_count, line_size;
3053         int small, large;
3054         int entries;
3055
3056         if (!latency_ns) {
3057                 *sprite_wm = 0;
3058                 return false;
3059         }
3060
3061         crtc = intel_get_crtc_for_plane(dev, plane);
3062         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3063         if (!clock) {
3064                 *sprite_wm = 0;
3065                 return false;
3066         }
3067
3068         line_time_us = (sprite_width * 1000) / clock;
3069         if (!line_time_us) {
3070                 *sprite_wm = 0;
3071                 return false;
3072         }
3073
3074         line_count = (latency_ns / line_time_us + 1000) / 1000;
3075         line_size = sprite_width * pixel_size;
3076
3077         /* Use the minimum of the small and large buffer method for primary */
3078         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3079         large = line_count * line_size;
3080
3081         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3082         *sprite_wm = entries + display->guard_size;
3083
3084         return *sprite_wm > 0x3ff ? false : true;
3085 }
3086
3087 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3088                                          struct drm_crtc *crtc,
3089                                          uint32_t sprite_width, int pixel_size,
3090                                          bool enabled, bool scaled)
3091 {
3092         struct drm_device *dev = plane->dev;
3093         struct drm_i915_private *dev_priv = dev->dev_private;
3094         int pipe = to_intel_plane(plane)->pipe;
3095         int latency = dev_priv->wm.spr_latency[0] * 100;        /* In unit 0.1us */
3096         u32 val;
3097         int sprite_wm, reg;
3098         int ret;
3099
3100         if (!enabled)
3101                 return;
3102
3103         switch (pipe) {
3104         case 0:
3105                 reg = WM0_PIPEA_ILK;
3106                 break;
3107         case 1:
3108                 reg = WM0_PIPEB_ILK;
3109                 break;
3110         case 2:
3111                 reg = WM0_PIPEC_IVB;
3112                 break;
3113         default:
3114                 return; /* bad pipe */
3115         }
3116
3117         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3118                                             &sandybridge_display_wm_info,
3119                                             latency, &sprite_wm);
3120         if (!ret) {
3121                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3122                               pipe_name(pipe));
3123                 return;
3124         }
3125
3126         val = I915_READ(reg);
3127         val &= ~WM0_PIPE_SPRITE_MASK;
3128         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3129         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3130
3131
3132         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3133                                               pixel_size,
3134                                               &sandybridge_display_srwm_info,
3135                                               dev_priv->wm.spr_latency[1] * 500,
3136                                               &sprite_wm);
3137         if (!ret) {
3138                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3139                               pipe_name(pipe));
3140                 return;
3141         }
3142         I915_WRITE(WM1S_LP_ILK, sprite_wm);
3143
3144         /* Only IVB has two more LP watermarks for sprite */
3145         if (!IS_IVYBRIDGE(dev))
3146                 return;
3147
3148         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3149                                               pixel_size,
3150                                               &sandybridge_display_srwm_info,
3151                                               dev_priv->wm.spr_latency[2] * 500,
3152                                               &sprite_wm);
3153         if (!ret) {
3154                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3155                               pipe_name(pipe));
3156                 return;
3157         }
3158         I915_WRITE(WM2S_LP_IVB, sprite_wm);
3159
3160         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3161                                               pixel_size,
3162                                               &sandybridge_display_srwm_info,
3163                                               dev_priv->wm.spr_latency[3] * 500,
3164                                               &sprite_wm);
3165         if (!ret) {
3166                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3167                               pipe_name(pipe));
3168                 return;
3169         }
3170         I915_WRITE(WM3S_LP_IVB, sprite_wm);
3171 }
3172
3173 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3174 {
3175         struct drm_device *dev = crtc->dev;
3176         struct drm_i915_private *dev_priv = dev->dev_private;
3177         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3180         enum pipe pipe = intel_crtc->pipe;
3181         static const unsigned int wm0_pipe_reg[] = {
3182                 [PIPE_A] = WM0_PIPEA_ILK,
3183                 [PIPE_B] = WM0_PIPEB_ILK,
3184                 [PIPE_C] = WM0_PIPEC_IVB,
3185         };
3186
3187         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3188         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3189
3190         if (intel_crtc_active(crtc)) {
3191                 u32 tmp = hw->wm_pipe[pipe];
3192
3193                 /*
3194                  * For active pipes LP0 watermark is marked as
3195                  * enabled, and LP1+ watermaks as disabled since
3196                  * we can't really reverse compute them in case
3197                  * multiple pipes are active.
3198                  */
3199                 active->wm[0].enable = true;
3200                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3201                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3202                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3203                 active->linetime = hw->wm_linetime[pipe];
3204         } else {
3205                 int level, max_level = ilk_wm_max_level(dev);
3206
3207                 /*
3208                  * For inactive pipes, all watermark levels
3209                  * should be marked as enabled but zeroed,
3210                  * which is what we'd compute them to.
3211                  */
3212                 for (level = 0; level <= max_level; level++)
3213                         active->wm[level].enable = true;
3214         }
3215 }
3216
3217 void ilk_wm_get_hw_state(struct drm_device *dev)
3218 {
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3221         struct drm_crtc *crtc;
3222
3223         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3224                 ilk_pipe_wm_get_hw_state(crtc);
3225
3226         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3227         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3228         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3229
3230         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3231         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3232         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3233
3234         if (IS_HASWELL(dev))
3235                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3236                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3237         else if (IS_IVYBRIDGE(dev))
3238                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3239                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3240
3241         hw->enable_fbc_wm =
3242                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3243 }
3244
3245 /**
3246  * intel_update_watermarks - update FIFO watermark values based on current modes
3247  *
3248  * Calculate watermark values for the various WM regs based on current mode
3249  * and plane configuration.
3250  *
3251  * There are several cases to deal with here:
3252  *   - normal (i.e. non-self-refresh)
3253  *   - self-refresh (SR) mode
3254  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3255  *   - lines are small relative to FIFO size (buffer can hold more than 2
3256  *     lines), so need to account for TLB latency
3257  *
3258  *   The normal calculation is:
3259  *     watermark = dotclock * bytes per pixel * latency
3260  *   where latency is platform & configuration dependent (we assume pessimal
3261  *   values here).
3262  *
3263  *   The SR calculation is:
3264  *     watermark = (trunc(latency/line time)+1) * surface width *
3265  *       bytes per pixel
3266  *   where
3267  *     line time = htotal / dotclock
3268  *     surface width = hdisplay for normal plane and 64 for cursor
3269  *   and latency is assumed to be high, as above.
3270  *
3271  * The final value programmed to the register should always be rounded up,
3272  * and include an extra 2 entries to account for clock crossings.
3273  *
3274  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3275  * to set the non-SR watermarks to 8.
3276  */
3277 void intel_update_watermarks(struct drm_crtc *crtc)
3278 {
3279         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3280
3281         if (dev_priv->display.update_wm)
3282                 dev_priv->display.update_wm(crtc);
3283 }
3284
3285 void intel_update_sprite_watermarks(struct drm_plane *plane,
3286                                     struct drm_crtc *crtc,
3287                                     uint32_t sprite_width, int pixel_size,
3288                                     bool enabled, bool scaled)
3289 {
3290         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3291
3292         if (dev_priv->display.update_sprite_wm)
3293                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3294                                                    pixel_size, enabled, scaled);
3295 }
3296
3297 static struct drm_i915_gem_object *
3298 intel_alloc_context_page(struct drm_device *dev)
3299 {
3300         struct drm_i915_gem_object *ctx;
3301         int ret;
3302
3303         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3304
3305         ctx = i915_gem_alloc_object(dev, 4096);
3306         if (!ctx) {
3307                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3308                 return NULL;
3309         }
3310
3311         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3312         if (ret) {
3313                 DRM_ERROR("failed to pin power context: %d\n", ret);
3314                 goto err_unref;
3315         }
3316
3317         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3318         if (ret) {
3319                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3320                 goto err_unpin;
3321         }
3322
3323         return ctx;
3324
3325 err_unpin:
3326         i915_gem_object_unpin(ctx);
3327 err_unref:
3328         drm_gem_object_unreference(&ctx->base);
3329         return NULL;
3330 }
3331
3332 /**
3333  * Lock protecting IPS related data structures
3334  */
3335 DEFINE_SPINLOCK(mchdev_lock);
3336
3337 /* Global for IPS driver to get at the current i915 device. Protected by
3338  * mchdev_lock. */
3339 static struct drm_i915_private *i915_mch_dev;
3340
3341 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3342 {
3343         struct drm_i915_private *dev_priv = dev->dev_private;
3344         u16 rgvswctl;
3345
3346         assert_spin_locked(&mchdev_lock);
3347
3348         rgvswctl = I915_READ16(MEMSWCTL);
3349         if (rgvswctl & MEMCTL_CMD_STS) {
3350                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3351                 return false; /* still busy with another command */
3352         }
3353
3354         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3355                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3356         I915_WRITE16(MEMSWCTL, rgvswctl);
3357         POSTING_READ16(MEMSWCTL);
3358
3359         rgvswctl |= MEMCTL_CMD_STS;
3360         I915_WRITE16(MEMSWCTL, rgvswctl);
3361
3362         return true;
3363 }
3364
3365 static void ironlake_enable_drps(struct drm_device *dev)
3366 {
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         u32 rgvmodectl = I915_READ(MEMMODECTL);
3369         u8 fmax, fmin, fstart, vstart;
3370
3371         spin_lock_irq(&mchdev_lock);
3372
3373         /* Enable temp reporting */
3374         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3375         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3376
3377         /* 100ms RC evaluation intervals */
3378         I915_WRITE(RCUPEI, 100000);
3379         I915_WRITE(RCDNEI, 100000);
3380
3381         /* Set max/min thresholds to 90ms and 80ms respectively */
3382         I915_WRITE(RCBMAXAVG, 90000);
3383         I915_WRITE(RCBMINAVG, 80000);
3384
3385         I915_WRITE(MEMIHYST, 1);
3386
3387         /* Set up min, max, and cur for interrupt handling */
3388         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3389         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3390         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3391                 MEMMODE_FSTART_SHIFT;
3392
3393         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3394                 PXVFREQ_PX_SHIFT;
3395
3396         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3397         dev_priv->ips.fstart = fstart;
3398
3399         dev_priv->ips.max_delay = fstart;
3400         dev_priv->ips.min_delay = fmin;
3401         dev_priv->ips.cur_delay = fstart;
3402
3403         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3404                          fmax, fmin, fstart);
3405
3406         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3407
3408         /*
3409          * Interrupts will be enabled in ironlake_irq_postinstall
3410          */
3411
3412         I915_WRITE(VIDSTART, vstart);
3413         POSTING_READ(VIDSTART);
3414
3415         rgvmodectl |= MEMMODE_SWMODE_EN;
3416         I915_WRITE(MEMMODECTL, rgvmodectl);
3417
3418         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3419                 DRM_ERROR("stuck trying to change perf mode\n");
3420         mdelay(1);
3421
3422         ironlake_set_drps(dev, fstart);
3423
3424         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3425                 I915_READ(0x112e0);
3426         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3427         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3428         getrawmonotonic(&dev_priv->ips.last_time2);
3429
3430         spin_unlock_irq(&mchdev_lock);
3431 }
3432
3433 static void ironlake_disable_drps(struct drm_device *dev)
3434 {
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         u16 rgvswctl;
3437
3438         spin_lock_irq(&mchdev_lock);
3439
3440         rgvswctl = I915_READ16(MEMSWCTL);
3441
3442         /* Ack interrupts, disable EFC interrupt */
3443         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3444         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3445         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3446         I915_WRITE(DEIIR, DE_PCU_EVENT);
3447         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3448
3449         /* Go back to the starting frequency */
3450         ironlake_set_drps(dev, dev_priv->ips.fstart);
3451         mdelay(1);
3452         rgvswctl |= MEMCTL_CMD_STS;
3453         I915_WRITE(MEMSWCTL, rgvswctl);
3454         mdelay(1);
3455
3456         spin_unlock_irq(&mchdev_lock);
3457 }
3458
3459 /* There's a funny hw issue where the hw returns all 0 when reading from
3460  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3461  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3462  * all limits and the gpu stuck at whatever frequency it is at atm).
3463  */
3464 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3465 {
3466         u32 limits;
3467
3468         /* Only set the down limit when we've reached the lowest level to avoid
3469          * getting more interrupts, otherwise leave this clear. This prevents a
3470          * race in the hw when coming out of rc6: There's a tiny window where
3471          * the hw runs at the minimal clock before selecting the desired
3472          * frequency, if the down threshold expires in that window we will not
3473          * receive a down interrupt. */
3474         limits = dev_priv->rps.max_delay << 24;
3475         if (val <= dev_priv->rps.min_delay)
3476                 limits |= dev_priv->rps.min_delay << 16;
3477
3478         return limits;
3479 }
3480
3481 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3482 {
3483         int new_power;
3484
3485         new_power = dev_priv->rps.power;
3486         switch (dev_priv->rps.power) {
3487         case LOW_POWER:
3488                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3489                         new_power = BETWEEN;
3490                 break;
3491
3492         case BETWEEN:
3493                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3494                         new_power = LOW_POWER;
3495                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3496                         new_power = HIGH_POWER;
3497                 break;
3498
3499         case HIGH_POWER:
3500                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3501                         new_power = BETWEEN;
3502                 break;
3503         }
3504         /* Max/min bins are special */
3505         if (val == dev_priv->rps.min_delay)
3506                 new_power = LOW_POWER;
3507         if (val == dev_priv->rps.max_delay)
3508                 new_power = HIGH_POWER;
3509         if (new_power == dev_priv->rps.power)
3510                 return;
3511
3512         /* Note the units here are not exactly 1us, but 1280ns. */
3513         switch (new_power) {
3514         case LOW_POWER:
3515                 /* Upclock if more than 95% busy over 16ms */
3516                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3517                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3518
3519                 /* Downclock if less than 85% busy over 32ms */
3520                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3521                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3522
3523                 I915_WRITE(GEN6_RP_CONTROL,
3524                            GEN6_RP_MEDIA_TURBO |
3525                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3526                            GEN6_RP_MEDIA_IS_GFX |
3527                            GEN6_RP_ENABLE |
3528                            GEN6_RP_UP_BUSY_AVG |
3529                            GEN6_RP_DOWN_IDLE_AVG);
3530                 break;
3531
3532         case BETWEEN:
3533                 /* Upclock if more than 90% busy over 13ms */
3534                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3535                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3536
3537                 /* Downclock if less than 75% busy over 32ms */
3538                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3539                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3540
3541                 I915_WRITE(GEN6_RP_CONTROL,
3542                            GEN6_RP_MEDIA_TURBO |
3543                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3544                            GEN6_RP_MEDIA_IS_GFX |
3545                            GEN6_RP_ENABLE |
3546                            GEN6_RP_UP_BUSY_AVG |
3547                            GEN6_RP_DOWN_IDLE_AVG);
3548                 break;
3549
3550         case HIGH_POWER:
3551                 /* Upclock if more than 85% busy over 10ms */
3552                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3553                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3554
3555                 /* Downclock if less than 60% busy over 32ms */
3556                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3557                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3558
3559                 I915_WRITE(GEN6_RP_CONTROL,
3560                            GEN6_RP_MEDIA_TURBO |
3561                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3562                            GEN6_RP_MEDIA_IS_GFX |
3563                            GEN6_RP_ENABLE |
3564                            GEN6_RP_UP_BUSY_AVG |
3565                            GEN6_RP_DOWN_IDLE_AVG);
3566                 break;
3567         }
3568
3569         dev_priv->rps.power = new_power;
3570         dev_priv->rps.last_adj = 0;
3571 }
3572
3573 void gen6_set_rps(struct drm_device *dev, u8 val)
3574 {
3575         struct drm_i915_private *dev_priv = dev->dev_private;
3576
3577         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3578         WARN_ON(val > dev_priv->rps.max_delay);
3579         WARN_ON(val < dev_priv->rps.min_delay);
3580
3581         if (val == dev_priv->rps.cur_delay)
3582                 return;
3583
3584         gen6_set_rps_thresholds(dev_priv, val);
3585
3586         if (IS_HASWELL(dev))
3587                 I915_WRITE(GEN6_RPNSWREQ,
3588                            HSW_FREQUENCY(val));
3589         else
3590                 I915_WRITE(GEN6_RPNSWREQ,
3591                            GEN6_FREQUENCY(val) |
3592                            GEN6_OFFSET(0) |
3593                            GEN6_AGGRESSIVE_TURBO);
3594
3595         /* Make sure we continue to get interrupts
3596          * until we hit the minimum or maximum frequencies.
3597          */
3598         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3599                    gen6_rps_limits(dev_priv, val));
3600
3601         POSTING_READ(GEN6_RPNSWREQ);
3602
3603         dev_priv->rps.cur_delay = val;
3604
3605         trace_intel_gpu_freq_change(val * 50);
3606 }
3607
3608 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3609 {
3610         struct drm_device *dev = dev_priv->dev;
3611
3612         mutex_lock(&dev_priv->rps.hw_lock);
3613         if (dev_priv->rps.enabled) {
3614                 if (IS_VALLEYVIEW(dev))
3615                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3616                 else
3617                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3618                 dev_priv->rps.last_adj = 0;
3619         }
3620         mutex_unlock(&dev_priv->rps.hw_lock);
3621 }
3622
3623 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3624 {
3625         struct drm_device *dev = dev_priv->dev;
3626
3627         mutex_lock(&dev_priv->rps.hw_lock);
3628         if (dev_priv->rps.enabled) {
3629                 if (IS_VALLEYVIEW(dev))
3630                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3631                 else
3632                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3633                 dev_priv->rps.last_adj = 0;
3634         }
3635         mutex_unlock(&dev_priv->rps.hw_lock);
3636 }
3637
3638 void valleyview_set_rps(struct drm_device *dev, u8 val)
3639 {
3640         struct drm_i915_private *dev_priv = dev->dev_private;
3641
3642         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3643         WARN_ON(val > dev_priv->rps.max_delay);
3644         WARN_ON(val < dev_priv->rps.min_delay);
3645
3646         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3647                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3648                          dev_priv->rps.cur_delay,
3649                          vlv_gpu_freq(dev_priv, val), val);
3650
3651         if (val == dev_priv->rps.cur_delay)
3652                 return;
3653
3654         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3655
3656         dev_priv->rps.cur_delay = val;
3657
3658         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3659 }
3660
3661 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3662 {
3663         struct drm_i915_private *dev_priv = dev->dev_private;
3664
3665         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3666         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3667         /* Complete PM interrupt masking here doesn't race with the rps work
3668          * item again unmasking PM interrupts because that is using a different
3669          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3670          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3671
3672         spin_lock_irq(&dev_priv->irq_lock);
3673         dev_priv->rps.pm_iir = 0;
3674         spin_unlock_irq(&dev_priv->irq_lock);
3675
3676         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3677 }
3678
3679 static void gen6_disable_rps(struct drm_device *dev)
3680 {
3681         struct drm_i915_private *dev_priv = dev->dev_private;
3682
3683         I915_WRITE(GEN6_RC_CONTROL, 0);
3684         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3685
3686         gen6_disable_rps_interrupts(dev);
3687 }
3688
3689 static void valleyview_disable_rps(struct drm_device *dev)
3690 {
3691         struct drm_i915_private *dev_priv = dev->dev_private;
3692
3693         I915_WRITE(GEN6_RC_CONTROL, 0);
3694
3695         gen6_disable_rps_interrupts(dev);
3696
3697         if (dev_priv->vlv_pctx) {
3698                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3699                 dev_priv->vlv_pctx = NULL;
3700         }
3701 }
3702
3703 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3704 {
3705         if (IS_GEN6(dev))
3706                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3707
3708         if (IS_HASWELL(dev))
3709                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3710
3711         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3712                         (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3713                         (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3714                         (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3715 }
3716
3717 int intel_enable_rc6(const struct drm_device *dev)
3718 {
3719         /* No RC6 before Ironlake */
3720         if (INTEL_INFO(dev)->gen < 5)
3721                 return 0;
3722
3723         /* Respect the kernel parameter if it is set */
3724         if (i915_enable_rc6 >= 0)
3725                 return i915_enable_rc6;
3726
3727         /* Disable RC6 on Ironlake */
3728         if (INTEL_INFO(dev)->gen == 5)
3729                 return 0;
3730
3731         if (IS_HASWELL(dev))
3732                 return INTEL_RC6_ENABLE;
3733
3734         /* snb/ivb have more than one rc6 state. */
3735         if (INTEL_INFO(dev)->gen == 6)
3736                 return INTEL_RC6_ENABLE;
3737
3738         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3739 }
3740
3741 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3742 {
3743         struct drm_i915_private *dev_priv = dev->dev_private;
3744         u32 enabled_intrs;
3745
3746         spin_lock_irq(&dev_priv->irq_lock);
3747         WARN_ON(dev_priv->rps.pm_iir);
3748         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3749         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3750         spin_unlock_irq(&dev_priv->irq_lock);
3751
3752         /* only unmask PM interrupts we need. Mask all others. */
3753         enabled_intrs = GEN6_PM_RPS_EVENTS;
3754
3755         /* IVB and SNB hard hangs on looping batchbuffer
3756          * if GEN6_PM_UP_EI_EXPIRED is masked.
3757          */
3758         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3759                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3760
3761         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3762 }
3763
3764 static void gen8_enable_rps(struct drm_device *dev)
3765 {
3766         struct drm_i915_private *dev_priv = dev->dev_private;
3767         struct intel_ring_buffer *ring;
3768         uint32_t rc6_mask = 0, rp_state_cap;
3769         int unused;
3770
3771         /* 1a: Software RC state - RC0 */
3772         I915_WRITE(GEN6_RC_STATE, 0);
3773
3774         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3775          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3776         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3777
3778         /* 2a: Disable RC states. */
3779         I915_WRITE(GEN6_RC_CONTROL, 0);
3780
3781         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3782
3783         /* 2b: Program RC6 thresholds.*/
3784         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3785         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3786         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3787         for_each_ring(ring, dev_priv, unused)
3788                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3789         I915_WRITE(GEN6_RC_SLEEP, 0);
3790         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3791
3792         /* 3: Enable RC6 */
3793         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3794                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3795         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3796         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3797                         GEN6_RC_CTL_EI_MODE(1) |
3798                         rc6_mask);
3799
3800         /* 4 Program defaults and thresholds for RPS*/
3801         I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3802         I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3803         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3804         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3805
3806         /* Docs recommend 900MHz, and 300 MHz respectively */
3807         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3808                    dev_priv->rps.max_delay << 24 |
3809                    dev_priv->rps.min_delay << 16);
3810
3811         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3812         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3813         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3814         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3815
3816         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3817
3818         /* 5: Enable RPS */
3819         I915_WRITE(GEN6_RP_CONTROL,
3820                    GEN6_RP_MEDIA_TURBO |
3821                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3822                    GEN6_RP_MEDIA_IS_GFX |
3823                    GEN6_RP_ENABLE |
3824                    GEN6_RP_UP_BUSY_AVG |
3825                    GEN6_RP_DOWN_IDLE_AVG);
3826
3827         /* 6: Ring frequency + overclocking (our driver does this later */
3828
3829         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3830
3831         gen6_enable_rps_interrupts(dev);
3832
3833         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3834 }
3835
3836 static void gen6_enable_rps(struct drm_device *dev)
3837 {
3838         struct drm_i915_private *dev_priv = dev->dev_private;
3839         struct intel_ring_buffer *ring;
3840         u32 rp_state_cap;
3841         u32 gt_perf_status;
3842         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3843         u32 gtfifodbg;
3844         int rc6_mode;
3845         int i, ret;
3846
3847         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3848
3849         /* Here begins a magic sequence of register writes to enable
3850          * auto-downclocking.
3851          *
3852          * Perhaps there might be some value in exposing these to
3853          * userspace...
3854          */
3855         I915_WRITE(GEN6_RC_STATE, 0);
3856
3857         /* Clear the DBG now so we don't confuse earlier errors */
3858         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3859                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3860                 I915_WRITE(GTFIFODBG, gtfifodbg);
3861         }
3862
3863         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3864
3865         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3866         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3867
3868         /* In units of 50MHz */
3869         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3870         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3871         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3872         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3873         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3874         dev_priv->rps.cur_delay = 0;
3875
3876         /* disable the counters and set deterministic thresholds */
3877         I915_WRITE(GEN6_RC_CONTROL, 0);
3878
3879         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3880         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3881         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3882         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3883         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3884
3885         for_each_ring(ring, dev_priv, i)
3886                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3887
3888         I915_WRITE(GEN6_RC_SLEEP, 0);
3889         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3890         if (IS_IVYBRIDGE(dev))
3891                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3892         else
3893                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3894         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3895         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3896
3897         /* Check if we are enabling RC6 */
3898         rc6_mode = intel_enable_rc6(dev_priv->dev);
3899         if (rc6_mode & INTEL_RC6_ENABLE)
3900                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3901
3902         /* We don't use those on Haswell */
3903         if (!IS_HASWELL(dev)) {
3904                 if (rc6_mode & INTEL_RC6p_ENABLE)
3905                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3906
3907                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3908                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3909         }
3910
3911         intel_print_rc6_info(dev, rc6_mask);
3912
3913         I915_WRITE(GEN6_RC_CONTROL,
3914                    rc6_mask |
3915                    GEN6_RC_CTL_EI_MODE(1) |
3916                    GEN6_RC_CTL_HW_ENABLE);
3917
3918         /* Power down if completely idle for over 50ms */
3919         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3920         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3921
3922         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3923         if (!ret) {
3924                 pcu_mbox = 0;
3925                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3926                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3927                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3928                                          (dev_priv->rps.max_delay & 0xff) * 50,
3929                                          (pcu_mbox & 0xff) * 50);
3930                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3931                 }
3932         } else {
3933                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3934         }
3935
3936         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3937         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3938
3939         gen6_enable_rps_interrupts(dev);
3940
3941         rc6vids = 0;
3942         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3943         if (IS_GEN6(dev) && ret) {
3944                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3945         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3946                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3947                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3948                 rc6vids &= 0xffff00;
3949                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3950                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3951                 if (ret)
3952                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3953         }
3954
3955         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3956 }
3957
3958 void gen6_update_ring_freq(struct drm_device *dev)
3959 {
3960         struct drm_i915_private *dev_priv = dev->dev_private;
3961         int min_freq = 15;
3962         unsigned int gpu_freq;
3963         unsigned int max_ia_freq, min_ring_freq;
3964         int scaling_factor = 180;
3965         struct cpufreq_policy *policy;
3966
3967         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3968
3969         policy = cpufreq_cpu_get(0);
3970         if (policy) {
3971                 max_ia_freq = policy->cpuinfo.max_freq;
3972                 cpufreq_cpu_put(policy);
3973         } else {
3974                 /*
3975                  * Default to measured freq if none found, PCU will ensure we
3976                  * don't go over
3977                  */
3978                 max_ia_freq = tsc_khz;
3979         }
3980
3981         /* Convert from kHz to MHz */
3982         max_ia_freq /= 1000;
3983
3984         min_ring_freq = I915_READ(DCLK) & 0xf;
3985         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3986         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3987
3988         /*
3989          * For each potential GPU frequency, load a ring frequency we'd like
3990          * to use for memory access.  We do this by specifying the IA frequency
3991          * the PCU should use as a reference to determine the ring frequency.
3992          */
3993         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3994              gpu_freq--) {
3995                 int diff = dev_priv->rps.max_delay - gpu_freq;
3996                 unsigned int ia_freq = 0, ring_freq = 0;
3997
3998                 if (INTEL_INFO(dev)->gen >= 8) {
3999                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
4000                         ring_freq = max(min_ring_freq, gpu_freq);
4001                 } else if (IS_HASWELL(dev)) {
4002                         ring_freq = mult_frac(gpu_freq, 5, 4);
4003                         ring_freq = max(min_ring_freq, ring_freq);
4004                         /* leave ia_freq as the default, chosen by cpufreq */
4005                 } else {
4006                         /* On older processors, there is no separate ring
4007                          * clock domain, so in order to boost the bandwidth
4008                          * of the ring, we need to upclock the CPU (ia_freq).
4009                          *
4010                          * For GPU frequencies less than 750MHz,
4011                          * just use the lowest ring freq.
4012                          */
4013                         if (gpu_freq < min_freq)
4014                                 ia_freq = 800;
4015                         else
4016                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4017                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4018                 }
4019
4020                 sandybridge_pcode_write(dev_priv,
4021                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4022                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4023                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4024                                         gpu_freq);
4025         }
4026 }
4027
4028 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4029 {
4030         u32 val, rp0;
4031
4032         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4033
4034         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4035         /* Clamp to max */
4036         rp0 = min_t(u32, rp0, 0xea);
4037
4038         return rp0;
4039 }
4040
4041 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4042 {
4043         u32 val, rpe;
4044
4045         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4046         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4047         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4048         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4049
4050         return rpe;
4051 }
4052
4053 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4054 {
4055         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4056 }
4057
4058 static void valleyview_setup_pctx(struct drm_device *dev)
4059 {
4060         struct drm_i915_private *dev_priv = dev->dev_private;
4061         struct drm_i915_gem_object *pctx;
4062         unsigned long pctx_paddr;
4063         u32 pcbr;
4064         int pctx_size = 24*1024;
4065
4066         pcbr = I915_READ(VLV_PCBR);
4067         if (pcbr) {
4068                 /* BIOS set it up already, grab the pre-alloc'd space */
4069                 int pcbr_offset;
4070
4071                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4072                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4073                                                                       pcbr_offset,
4074                                                                       I915_GTT_OFFSET_NONE,
4075                                                                       pctx_size);
4076                 goto out;
4077         }
4078
4079         /*
4080          * From the Gunit register HAS:
4081          * The Gfx driver is expected to program this register and ensure
4082          * proper allocation within Gfx stolen memory.  For example, this
4083          * register should be programmed such than the PCBR range does not
4084          * overlap with other ranges, such as the frame buffer, protected
4085          * memory, or any other relevant ranges.
4086          */
4087         pctx = i915_gem_object_create_stolen(dev, pctx_size);
4088         if (!pctx) {
4089                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4090                 return;
4091         }
4092
4093         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4094         I915_WRITE(VLV_PCBR, pctx_paddr);
4095
4096 out:
4097         dev_priv->vlv_pctx = pctx;
4098 }
4099
4100 static void valleyview_enable_rps(struct drm_device *dev)
4101 {
4102         struct drm_i915_private *dev_priv = dev->dev_private;
4103         struct intel_ring_buffer *ring;
4104         u32 gtfifodbg, val, rc6_mode = 0;
4105         int i;
4106
4107         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4108
4109         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4110                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4111                                  gtfifodbg);
4112                 I915_WRITE(GTFIFODBG, gtfifodbg);
4113         }
4114
4115         valleyview_setup_pctx(dev);
4116
4117         /* If VLV, Forcewake all wells, else re-direct to regular path */
4118         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4119
4120         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4121         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4122         I915_WRITE(GEN6_RP_UP_EI, 66000);
4123         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4124
4125         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4126
4127         I915_WRITE(GEN6_RP_CONTROL,
4128                    GEN6_RP_MEDIA_TURBO |
4129                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4130                    GEN6_RP_MEDIA_IS_GFX |
4131                    GEN6_RP_ENABLE |
4132                    GEN6_RP_UP_BUSY_AVG |
4133                    GEN6_RP_DOWN_IDLE_CONT);
4134
4135         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4136         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4137         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4138
4139         for_each_ring(ring, dev_priv, i)
4140                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4141
4142         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4143
4144         /* allows RC6 residency counter to work */
4145         I915_WRITE(VLV_COUNTER_CONTROL,
4146                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4147                                       VLV_MEDIA_RC6_COUNT_EN |
4148                                       VLV_RENDER_RC6_COUNT_EN));
4149         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4150                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4151
4152         intel_print_rc6_info(dev, rc6_mode);
4153
4154         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4155
4156         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4157
4158         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4159         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4160
4161         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4162         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4163                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
4164                          dev_priv->rps.cur_delay);
4165
4166         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4167         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4168         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4169                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
4170                          dev_priv->rps.max_delay);
4171
4172         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4173         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4174                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4175                          dev_priv->rps.rpe_delay);
4176
4177         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4178         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4179                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
4180                          dev_priv->rps.min_delay);
4181
4182         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4183                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4184                          dev_priv->rps.rpe_delay);
4185
4186         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4187
4188         gen6_enable_rps_interrupts(dev);
4189
4190         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4191 }
4192
4193 void ironlake_teardown_rc6(struct drm_device *dev)
4194 {
4195         struct drm_i915_private *dev_priv = dev->dev_private;
4196
4197         if (dev_priv->ips.renderctx) {
4198                 i915_gem_object_unpin(dev_priv->ips.renderctx);
4199                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4200                 dev_priv->ips.renderctx = NULL;
4201         }
4202
4203         if (dev_priv->ips.pwrctx) {
4204                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4205                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4206                 dev_priv->ips.pwrctx = NULL;
4207         }
4208 }
4209
4210 static void ironlake_disable_rc6(struct drm_device *dev)
4211 {
4212         struct drm_i915_private *dev_priv = dev->dev_private;
4213
4214         if (I915_READ(PWRCTXA)) {
4215                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4216                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4217                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4218                          50);
4219
4220                 I915_WRITE(PWRCTXA, 0);
4221                 POSTING_READ(PWRCTXA);
4222
4223                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4224                 POSTING_READ(RSTDBYCTL);
4225         }
4226 }
4227
4228 static int ironlake_setup_rc6(struct drm_device *dev)
4229 {
4230         struct drm_i915_private *dev_priv = dev->dev_private;
4231
4232         if (dev_priv->ips.renderctx == NULL)
4233                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4234         if (!dev_priv->ips.renderctx)
4235                 return -ENOMEM;
4236
4237         if (dev_priv->ips.pwrctx == NULL)
4238                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4239         if (!dev_priv->ips.pwrctx) {
4240                 ironlake_teardown_rc6(dev);
4241                 return -ENOMEM;
4242         }
4243
4244         return 0;
4245 }
4246
4247 static void ironlake_enable_rc6(struct drm_device *dev)
4248 {
4249         struct drm_i915_private *dev_priv = dev->dev_private;
4250         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4251         bool was_interruptible;
4252         int ret;
4253
4254         /* rc6 disabled by default due to repeated reports of hanging during
4255          * boot and resume.
4256          */
4257         if (!intel_enable_rc6(dev))
4258                 return;
4259
4260         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4261
4262         ret = ironlake_setup_rc6(dev);
4263         if (ret)
4264                 return;
4265
4266         was_interruptible = dev_priv->mm.interruptible;
4267         dev_priv->mm.interruptible = false;
4268
4269         /*
4270          * GPU can automatically power down the render unit if given a page
4271          * to save state.
4272          */
4273         ret = intel_ring_begin(ring, 6);
4274         if (ret) {
4275                 ironlake_teardown_rc6(dev);
4276                 dev_priv->mm.interruptible = was_interruptible;
4277                 return;
4278         }
4279
4280         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4281         intel_ring_emit(ring, MI_SET_CONTEXT);
4282         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4283                         MI_MM_SPACE_GTT |
4284                         MI_SAVE_EXT_STATE_EN |
4285                         MI_RESTORE_EXT_STATE_EN |
4286                         MI_RESTORE_INHIBIT);
4287         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4288         intel_ring_emit(ring, MI_NOOP);
4289         intel_ring_emit(ring, MI_FLUSH);
4290         intel_ring_advance(ring);
4291
4292         /*
4293          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4294          * does an implicit flush, combined with MI_FLUSH above, it should be
4295          * safe to assume that renderctx is valid
4296          */
4297         ret = intel_ring_idle(ring);
4298         dev_priv->mm.interruptible = was_interruptible;
4299         if (ret) {
4300                 DRM_ERROR("failed to enable ironlake power savings\n");
4301                 ironlake_teardown_rc6(dev);
4302                 return;
4303         }
4304
4305         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4306         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4307
4308         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4309 }
4310
4311 static unsigned long intel_pxfreq(u32 vidfreq)
4312 {
4313         unsigned long freq;
4314         int div = (vidfreq & 0x3f0000) >> 16;
4315         int post = (vidfreq & 0x3000) >> 12;
4316         int pre = (vidfreq & 0x7);
4317
4318         if (!pre)
4319                 return 0;
4320
4321         freq = ((div * 133333) / ((1<<post) * pre));
4322
4323         return freq;
4324 }
4325
4326 static const struct cparams {
4327         u16 i;
4328         u16 t;
4329         u16 m;
4330         u16 c;
4331 } cparams[] = {
4332         { 1, 1333, 301, 28664 },
4333         { 1, 1066, 294, 24460 },
4334         { 1, 800, 294, 25192 },
4335         { 0, 1333, 276, 27605 },
4336         { 0, 1066, 276, 27605 },
4337         { 0, 800, 231, 23784 },
4338 };
4339
4340 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4341 {
4342         u64 total_count, diff, ret;
4343         u32 count1, count2, count3, m = 0, c = 0;
4344         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4345         int i;
4346
4347         assert_spin_locked(&mchdev_lock);
4348
4349         diff1 = now - dev_priv->ips.last_time1;
4350
4351         /* Prevent division-by-zero if we are asking too fast.
4352          * Also, we don't get interesting results if we are polling
4353          * faster than once in 10ms, so just return the saved value
4354          * in such cases.
4355          */
4356         if (diff1 <= 10)
4357                 return dev_priv->ips.chipset_power;
4358
4359         count1 = I915_READ(DMIEC);
4360         count2 = I915_READ(DDREC);
4361         count3 = I915_READ(CSIEC);
4362
4363         total_count = count1 + count2 + count3;
4364
4365         /* FIXME: handle per-counter overflow */
4366         if (total_count < dev_priv->ips.last_count1) {
4367                 diff = ~0UL - dev_priv->ips.last_count1;
4368                 diff += total_count;
4369         } else {
4370                 diff = total_count - dev_priv->ips.last_count1;
4371         }
4372
4373         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4374                 if (cparams[i].i == dev_priv->ips.c_m &&
4375                     cparams[i].t == dev_priv->ips.r_t) {
4376                         m = cparams[i].m;
4377                         c = cparams[i].c;
4378                         break;
4379                 }
4380         }
4381
4382         diff = div_u64(diff, diff1);
4383         ret = ((m * diff) + c);
4384         ret = div_u64(ret, 10);
4385
4386         dev_priv->ips.last_count1 = total_count;
4387         dev_priv->ips.last_time1 = now;
4388
4389         dev_priv->ips.chipset_power = ret;
4390
4391         return ret;
4392 }
4393
4394 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4395 {
4396         unsigned long val;
4397
4398         if (dev_priv->info->gen != 5)
4399                 return 0;
4400
4401         spin_lock_irq(&mchdev_lock);
4402
4403         val = __i915_chipset_val(dev_priv);
4404
4405         spin_unlock_irq(&mchdev_lock);
4406
4407         return val;
4408 }
4409
4410 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4411 {
4412         unsigned long m, x, b;
4413         u32 tsfs;
4414
4415         tsfs = I915_READ(TSFS);
4416
4417         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4418         x = I915_READ8(TR1);
4419
4420         b = tsfs & TSFS_INTR_MASK;
4421
4422         return ((m * x) / 127) - b;
4423 }
4424
4425 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4426 {
4427         static const struct v_table {
4428                 u16 vd; /* in .1 mil */
4429                 u16 vm; /* in .1 mil */
4430         } v_table[] = {
4431                 { 0, 0, },
4432                 { 375, 0, },
4433                 { 500, 0, },
4434                 { 625, 0, },
4435                 { 750, 0, },
4436                 { 875, 0, },
4437                 { 1000, 0, },
4438                 { 1125, 0, },
4439                 { 4125, 3000, },
4440                 { 4125, 3000, },
4441                 { 4125, 3000, },
4442                 { 4125, 3000, },
4443                 { 4125, 3000, },
4444                 { 4125, 3000, },
4445                 { 4125, 3000, },
4446                 { 4125, 3000, },
4447                 { 4125, 3000, },
4448                 { 4125, 3000, },
4449                 { 4125, 3000, },
4450                 { 4125, 3000, },
4451                 { 4125, 3000, },
4452                 { 4125, 3000, },
4453                 { 4125, 3000, },
4454                 { 4125, 3000, },
4455                 { 4125, 3000, },
4456                 { 4125, 3000, },
4457                 { 4125, 3000, },
4458                 { 4125, 3000, },
4459                 { 4125, 3000, },
4460                 { 4125, 3000, },
4461                 { 4125, 3000, },
4462                 { 4125, 3000, },
4463                 { 4250, 3125, },
4464                 { 4375, 3250, },
4465                 { 4500, 3375, },
4466                 { 4625, 3500, },
4467                 { 4750, 3625, },
4468                 { 4875, 3750, },
4469                 { 5000, 3875, },
4470                 { 5125, 4000, },
4471                 { 5250, 4125, },
4472                 { 5375, 4250, },
4473                 { 5500, 4375, },
4474                 { 5625, 4500, },
4475                 { 5750, 4625, },
4476                 { 5875, 4750, },
4477                 { 6000, 4875, },
4478                 { 6125, 5000, },
4479                 { 6250, 5125, },
4480                 { 6375, 5250, },
4481                 { 6500, 5375, },
4482                 { 6625, 5500, },
4483                 { 6750, 5625, },
4484                 { 6875, 5750, },
4485                 { 7000, 5875, },
4486                 { 7125, 6000, },
4487                 { 7250, 6125, },
4488                 { 7375, 6250, },
4489                 { 7500, 6375, },
4490                 { 7625, 6500, },
4491                 { 7750, 6625, },
4492                 { 7875, 6750, },
4493                 { 8000, 6875, },
4494                 { 8125, 7000, },
4495                 { 8250, 7125, },
4496                 { 8375, 7250, },
4497                 { 8500, 7375, },
4498                 { 8625, 7500, },
4499                 { 8750, 7625, },
4500                 { 8875, 7750, },
4501                 { 9000, 7875, },
4502                 { 9125, 8000, },
4503                 { 9250, 8125, },
4504                 { 9375, 8250, },
4505                 { 9500, 8375, },
4506                 { 9625, 8500, },
4507                 { 9750, 8625, },
4508                 { 9875, 8750, },
4509                 { 10000, 8875, },
4510                 { 10125, 9000, },
4511                 { 10250, 9125, },
4512                 { 10375, 9250, },
4513                 { 10500, 9375, },
4514                 { 10625, 9500, },
4515                 { 10750, 9625, },
4516                 { 10875, 9750, },
4517                 { 11000, 9875, },
4518                 { 11125, 10000, },
4519                 { 11250, 10125, },
4520                 { 11375, 10250, },
4521                 { 11500, 10375, },
4522                 { 11625, 10500, },
4523                 { 11750, 10625, },
4524                 { 11875, 10750, },
4525                 { 12000, 10875, },
4526                 { 12125, 11000, },
4527                 { 12250, 11125, },
4528                 { 12375, 11250, },
4529                 { 12500, 11375, },
4530                 { 12625, 11500, },
4531                 { 12750, 11625, },
4532                 { 12875, 11750, },
4533                 { 13000, 11875, },
4534                 { 13125, 12000, },
4535                 { 13250, 12125, },
4536                 { 13375, 12250, },
4537                 { 13500, 12375, },
4538                 { 13625, 12500, },
4539                 { 13750, 12625, },
4540                 { 13875, 12750, },
4541                 { 14000, 12875, },
4542                 { 14125, 13000, },
4543                 { 14250, 13125, },
4544                 { 14375, 13250, },
4545                 { 14500, 13375, },
4546                 { 14625, 13500, },
4547                 { 14750, 13625, },
4548                 { 14875, 13750, },
4549                 { 15000, 13875, },
4550                 { 15125, 14000, },
4551                 { 15250, 14125, },
4552                 { 15375, 14250, },
4553                 { 15500, 14375, },
4554                 { 15625, 14500, },
4555                 { 15750, 14625, },
4556                 { 15875, 14750, },
4557                 { 16000, 14875, },
4558                 { 16125, 15000, },
4559         };
4560         if (dev_priv->info->is_mobile)
4561                 return v_table[pxvid].vm;
4562         else
4563                 return v_table[pxvid].vd;
4564 }
4565
4566 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4567 {
4568         struct timespec now, diff1;
4569         u64 diff;
4570         unsigned long diffms;
4571         u32 count;
4572
4573         assert_spin_locked(&mchdev_lock);
4574
4575         getrawmonotonic(&now);
4576         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4577
4578         /* Don't divide by 0 */
4579         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4580         if (!diffms)
4581                 return;
4582
4583         count = I915_READ(GFXEC);
4584
4585         if (count < dev_priv->ips.last_count2) {
4586                 diff = ~0UL - dev_priv->ips.last_count2;
4587                 diff += count;
4588         } else {
4589                 diff = count - dev_priv->ips.last_count2;
4590         }
4591
4592         dev_priv->ips.last_count2 = count;
4593         dev_priv->ips.last_time2 = now;
4594
4595         /* More magic constants... */
4596         diff = diff * 1181;
4597         diff = div_u64(diff, diffms * 10);
4598         dev_priv->ips.gfx_power = diff;
4599 }
4600
4601 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4602 {
4603         if (dev_priv->info->gen != 5)
4604                 return;
4605
4606         spin_lock_irq(&mchdev_lock);
4607
4608         __i915_update_gfx_val(dev_priv);
4609
4610         spin_unlock_irq(&mchdev_lock);
4611 }
4612
4613 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4614 {
4615         unsigned long t, corr, state1, corr2, state2;
4616         u32 pxvid, ext_v;
4617
4618         assert_spin_locked(&mchdev_lock);
4619
4620         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4621         pxvid = (pxvid >> 24) & 0x7f;
4622         ext_v = pvid_to_extvid(dev_priv, pxvid);
4623
4624         state1 = ext_v;
4625
4626         t = i915_mch_val(dev_priv);
4627
4628         /* Revel in the empirically derived constants */
4629
4630         /* Correction factor in 1/100000 units */
4631         if (t > 80)
4632                 corr = ((t * 2349) + 135940);
4633         else if (t >= 50)
4634                 corr = ((t * 964) + 29317);
4635         else /* < 50 */
4636                 corr = ((t * 301) + 1004);
4637
4638         corr = corr * ((150142 * state1) / 10000 - 78642);
4639         corr /= 100000;
4640         corr2 = (corr * dev_priv->ips.corr);
4641
4642         state2 = (corr2 * state1) / 10000;
4643         state2 /= 100; /* convert to mW */
4644
4645         __i915_update_gfx_val(dev_priv);
4646
4647         return dev_priv->ips.gfx_power + state2;
4648 }
4649
4650 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4651 {
4652         unsigned long val;
4653
4654         if (dev_priv->info->gen != 5)
4655                 return 0;
4656
4657         spin_lock_irq(&mchdev_lock);
4658
4659         val = __i915_gfx_val(dev_priv);
4660
4661         spin_unlock_irq(&mchdev_lock);
4662
4663         return val;
4664 }
4665
4666 /**
4667  * i915_read_mch_val - return value for IPS use
4668  *
4669  * Calculate and return a value for the IPS driver to use when deciding whether
4670  * we have thermal and power headroom to increase CPU or GPU power budget.
4671  */
4672 unsigned long i915_read_mch_val(void)
4673 {
4674         struct drm_i915_private *dev_priv;
4675         unsigned long chipset_val, graphics_val, ret = 0;
4676
4677         spin_lock_irq(&mchdev_lock);
4678         if (!i915_mch_dev)
4679                 goto out_unlock;
4680         dev_priv = i915_mch_dev;
4681
4682         chipset_val = __i915_chipset_val(dev_priv);
4683         graphics_val = __i915_gfx_val(dev_priv);
4684
4685         ret = chipset_val + graphics_val;
4686
4687 out_unlock:
4688         spin_unlock_irq(&mchdev_lock);
4689
4690         return ret;
4691 }
4692 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4693
4694 /**
4695  * i915_gpu_raise - raise GPU frequency limit
4696  *
4697  * Raise the limit; IPS indicates we have thermal headroom.
4698  */
4699 bool i915_gpu_raise(void)
4700 {
4701         struct drm_i915_private *dev_priv;
4702         bool ret = true;
4703
4704         spin_lock_irq(&mchdev_lock);
4705         if (!i915_mch_dev) {
4706                 ret = false;
4707                 goto out_unlock;
4708         }
4709         dev_priv = i915_mch_dev;
4710
4711         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4712                 dev_priv->ips.max_delay--;
4713
4714 out_unlock:
4715         spin_unlock_irq(&mchdev_lock);
4716
4717         return ret;
4718 }
4719 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4720
4721 /**
4722  * i915_gpu_lower - lower GPU frequency limit
4723  *
4724  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4725  * frequency maximum.
4726  */
4727 bool i915_gpu_lower(void)
4728 {
4729         struct drm_i915_private *dev_priv;
4730         bool ret = true;
4731
4732         spin_lock_irq(&mchdev_lock);
4733         if (!i915_mch_dev) {
4734                 ret = false;
4735                 goto out_unlock;
4736         }
4737         dev_priv = i915_mch_dev;
4738
4739         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4740                 dev_priv->ips.max_delay++;
4741
4742 out_unlock:
4743         spin_unlock_irq(&mchdev_lock);
4744
4745         return ret;
4746 }
4747 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4748
4749 /**
4750  * i915_gpu_busy - indicate GPU business to IPS
4751  *
4752  * Tell the IPS driver whether or not the GPU is busy.
4753  */
4754 bool i915_gpu_busy(void)
4755 {
4756         struct drm_i915_private *dev_priv;
4757         struct intel_ring_buffer *ring;
4758         bool ret = false;
4759         int i;
4760
4761         spin_lock_irq(&mchdev_lock);
4762         if (!i915_mch_dev)
4763                 goto out_unlock;
4764         dev_priv = i915_mch_dev;
4765
4766         for_each_ring(ring, dev_priv, i)
4767                 ret |= !list_empty(&ring->request_list);
4768
4769 out_unlock:
4770         spin_unlock_irq(&mchdev_lock);
4771
4772         return ret;
4773 }
4774 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4775
4776 /**
4777  * i915_gpu_turbo_disable - disable graphics turbo
4778  *
4779  * Disable graphics turbo by resetting the max frequency and setting the
4780  * current frequency to the default.
4781  */
4782 bool i915_gpu_turbo_disable(void)
4783 {
4784         struct drm_i915_private *dev_priv;
4785         bool ret = true;
4786
4787         spin_lock_irq(&mchdev_lock);
4788         if (!i915_mch_dev) {
4789                 ret = false;
4790                 goto out_unlock;
4791         }
4792         dev_priv = i915_mch_dev;
4793
4794         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4795
4796         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4797                 ret = false;
4798
4799 out_unlock:
4800         spin_unlock_irq(&mchdev_lock);
4801
4802         return ret;
4803 }
4804 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4805
4806 /**
4807  * Tells the intel_ips driver that the i915 driver is now loaded, if
4808  * IPS got loaded first.
4809  *
4810  * This awkward dance is so that neither module has to depend on the
4811  * other in order for IPS to do the appropriate communication of
4812  * GPU turbo limits to i915.
4813  */
4814 static void
4815 ips_ping_for_i915_load(void)
4816 {
4817         void (*link)(void);
4818
4819         link = symbol_get(ips_link_to_i915_driver);
4820         if (link) {
4821                 link();
4822                 symbol_put(ips_link_to_i915_driver);
4823         }
4824 }
4825
4826 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4827 {
4828         /* We only register the i915 ips part with intel-ips once everything is
4829          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4830         spin_lock_irq(&mchdev_lock);
4831         i915_mch_dev = dev_priv;
4832         spin_unlock_irq(&mchdev_lock);
4833
4834         ips_ping_for_i915_load();
4835 }
4836
4837 void intel_gpu_ips_teardown(void)
4838 {
4839         spin_lock_irq(&mchdev_lock);
4840         i915_mch_dev = NULL;
4841         spin_unlock_irq(&mchdev_lock);
4842 }
4843 static void intel_init_emon(struct drm_device *dev)
4844 {
4845         struct drm_i915_private *dev_priv = dev->dev_private;
4846         u32 lcfuse;
4847         u8 pxw[16];
4848         int i;
4849
4850         /* Disable to program */
4851         I915_WRITE(ECR, 0);
4852         POSTING_READ(ECR);
4853
4854         /* Program energy weights for various events */
4855         I915_WRITE(SDEW, 0x15040d00);
4856         I915_WRITE(CSIEW0, 0x007f0000);
4857         I915_WRITE(CSIEW1, 0x1e220004);
4858         I915_WRITE(CSIEW2, 0x04000004);
4859
4860         for (i = 0; i < 5; i++)
4861                 I915_WRITE(PEW + (i * 4), 0);
4862         for (i = 0; i < 3; i++)
4863                 I915_WRITE(DEW + (i * 4), 0);
4864
4865         /* Program P-state weights to account for frequency power adjustment */
4866         for (i = 0; i < 16; i++) {
4867                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4868                 unsigned long freq = intel_pxfreq(pxvidfreq);
4869                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4870                         PXVFREQ_PX_SHIFT;
4871                 unsigned long val;
4872
4873                 val = vid * vid;
4874                 val *= (freq / 1000);
4875                 val *= 255;
4876                 val /= (127*127*900);
4877                 if (val > 0xff)
4878                         DRM_ERROR("bad pxval: %ld\n", val);
4879                 pxw[i] = val;
4880         }
4881         /* Render standby states get 0 weight */
4882         pxw[14] = 0;
4883         pxw[15] = 0;
4884
4885         for (i = 0; i < 4; i++) {
4886                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4887                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4888                 I915_WRITE(PXW + (i * 4), val);
4889         }
4890
4891         /* Adjust magic regs to magic values (more experimental results) */
4892         I915_WRITE(OGW0, 0);
4893         I915_WRITE(OGW1, 0);
4894         I915_WRITE(EG0, 0x00007f00);
4895         I915_WRITE(EG1, 0x0000000e);
4896         I915_WRITE(EG2, 0x000e0000);
4897         I915_WRITE(EG3, 0x68000300);
4898         I915_WRITE(EG4, 0x42000000);
4899         I915_WRITE(EG5, 0x00140031);
4900         I915_WRITE(EG6, 0);
4901         I915_WRITE(EG7, 0);
4902
4903         for (i = 0; i < 8; i++)
4904                 I915_WRITE(PXWL + (i * 4), 0);
4905
4906         /* Enable PMON + select events */
4907         I915_WRITE(ECR, 0x80000019);
4908
4909         lcfuse = I915_READ(LCFUSE02);
4910
4911         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4912 }
4913
4914 void intel_disable_gt_powersave(struct drm_device *dev)
4915 {
4916         struct drm_i915_private *dev_priv = dev->dev_private;
4917
4918         /* Interrupts should be disabled already to avoid re-arming. */
4919         WARN_ON(dev->irq_enabled);
4920
4921         if (IS_IRONLAKE_M(dev)) {
4922                 ironlake_disable_drps(dev);
4923                 ironlake_disable_rc6(dev);
4924         } else if (INTEL_INFO(dev)->gen >= 6) {
4925                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4926                 cancel_work_sync(&dev_priv->rps.work);
4927                 mutex_lock(&dev_priv->rps.hw_lock);
4928                 if (IS_VALLEYVIEW(dev))
4929                         valleyview_disable_rps(dev);
4930                 else
4931                         gen6_disable_rps(dev);
4932                 dev_priv->rps.enabled = false;
4933                 mutex_unlock(&dev_priv->rps.hw_lock);
4934         }
4935 }
4936
4937 static void intel_gen6_powersave_work(struct work_struct *work)
4938 {
4939         struct drm_i915_private *dev_priv =
4940                 container_of(work, struct drm_i915_private,
4941                              rps.delayed_resume_work.work);
4942         struct drm_device *dev = dev_priv->dev;
4943
4944         mutex_lock(&dev_priv->rps.hw_lock);
4945
4946         if (IS_VALLEYVIEW(dev)) {
4947                 valleyview_enable_rps(dev);
4948         } else if (IS_BROADWELL(dev)) {
4949                 gen8_enable_rps(dev);
4950                 gen6_update_ring_freq(dev);
4951         } else {
4952                 gen6_enable_rps(dev);
4953                 gen6_update_ring_freq(dev);
4954         }
4955         dev_priv->rps.enabled = true;
4956         mutex_unlock(&dev_priv->rps.hw_lock);
4957 }
4958
4959 void intel_enable_gt_powersave(struct drm_device *dev)
4960 {
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962
4963         if (IS_IRONLAKE_M(dev)) {
4964                 ironlake_enable_drps(dev);
4965                 ironlake_enable_rc6(dev);
4966                 intel_init_emon(dev);
4967         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4968                 /*
4969                  * PCU communication is slow and this doesn't need to be
4970                  * done at any specific time, so do this out of our fast path
4971                  * to make resume and init faster.
4972                  */
4973                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4974                                       round_jiffies_up_relative(HZ));
4975         }
4976 }
4977
4978 static void ibx_init_clock_gating(struct drm_device *dev)
4979 {
4980         struct drm_i915_private *dev_priv = dev->dev_private;
4981
4982         /*
4983          * On Ibex Peak and Cougar Point, we need to disable clock
4984          * gating for the panel power sequencer or it will fail to
4985          * start up when no ports are active.
4986          */
4987         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4988 }
4989
4990 static void g4x_disable_trickle_feed(struct drm_device *dev)
4991 {
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         int pipe;
4994
4995         for_each_pipe(pipe) {
4996                 I915_WRITE(DSPCNTR(pipe),
4997                            I915_READ(DSPCNTR(pipe)) |
4998                            DISPPLANE_TRICKLE_FEED_DISABLE);
4999                 intel_flush_primary_plane(dev_priv, pipe);
5000         }
5001 }
5002
5003 static void ironlake_init_clock_gating(struct drm_device *dev)
5004 {
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5007
5008         /*
5009          * Required for FBC
5010          * WaFbcDisableDpfcClockGating:ilk
5011          */
5012         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5013                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5014                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5015
5016         I915_WRITE(PCH_3DCGDIS0,
5017                    MARIUNIT_CLOCK_GATE_DISABLE |
5018                    SVSMUNIT_CLOCK_GATE_DISABLE);
5019         I915_WRITE(PCH_3DCGDIS1,
5020                    VFMUNIT_CLOCK_GATE_DISABLE);
5021
5022         /*
5023          * According to the spec the following bits should be set in
5024          * order to enable memory self-refresh
5025          * The bit 22/21 of 0x42004
5026          * The bit 5 of 0x42020
5027          * The bit 15 of 0x45000
5028          */
5029         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5030                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
5031                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5032         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5033         I915_WRITE(DISP_ARB_CTL,
5034                    (I915_READ(DISP_ARB_CTL) |
5035                     DISP_FBC_WM_DIS));
5036         I915_WRITE(WM3_LP_ILK, 0);
5037         I915_WRITE(WM2_LP_ILK, 0);
5038         I915_WRITE(WM1_LP_ILK, 0);
5039
5040         /*
5041          * Based on the document from hardware guys the following bits
5042          * should be set unconditionally in order to enable FBC.
5043          * The bit 22 of 0x42000
5044          * The bit 22 of 0x42004
5045          * The bit 7,8,9 of 0x42020.
5046          */
5047         if (IS_IRONLAKE_M(dev)) {
5048                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5049                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5050                            I915_READ(ILK_DISPLAY_CHICKEN1) |
5051                            ILK_FBCQ_DIS);
5052                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5053                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5054                            ILK_DPARB_GATE);
5055         }
5056
5057         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5058
5059         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5060                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5061                    ILK_ELPIN_409_SELECT);
5062         I915_WRITE(_3D_CHICKEN2,
5063                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5064                    _3D_CHICKEN2_WM_READ_PIPELINED);
5065
5066         /* WaDisableRenderCachePipelinedFlush:ilk */
5067         I915_WRITE(CACHE_MODE_0,
5068                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5069
5070         g4x_disable_trickle_feed(dev);
5071
5072         ibx_init_clock_gating(dev);
5073 }
5074
5075 static void cpt_init_clock_gating(struct drm_device *dev)
5076 {
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         int pipe;
5079         uint32_t val;
5080
5081         /*
5082          * On Ibex Peak and Cougar Point, we need to disable clock
5083          * gating for the panel power sequencer or it will fail to
5084          * start up when no ports are active.
5085          */
5086         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5087                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5088                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
5089         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5090                    DPLS_EDP_PPS_FIX_DIS);
5091         /* The below fixes the weird display corruption, a few pixels shifted
5092          * downward, on (only) LVDS of some HP laptops with IVY.
5093          */
5094         for_each_pipe(pipe) {
5095                 val = I915_READ(TRANS_CHICKEN2(pipe));
5096                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5097                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5098                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5099                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5100                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5101                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5102                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5103                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5104         }
5105         /* WADP0ClockGatingDisable */
5106         for_each_pipe(pipe) {
5107                 I915_WRITE(TRANS_CHICKEN1(pipe),
5108                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5109         }
5110 }
5111
5112 static void gen6_check_mch_setup(struct drm_device *dev)
5113 {
5114         struct drm_i915_private *dev_priv = dev->dev_private;
5115         uint32_t tmp;
5116
5117         tmp = I915_READ(MCH_SSKPD);
5118         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5119                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5120                 DRM_INFO("This can cause pipe underruns and display issues.\n");
5121                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5122         }
5123 }
5124
5125 static void gen6_init_clock_gating(struct drm_device *dev)
5126 {
5127         struct drm_i915_private *dev_priv = dev->dev_private;
5128         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5129
5130         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5131
5132         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5133                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5134                    ILK_ELPIN_409_SELECT);
5135
5136         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5137         I915_WRITE(_3D_CHICKEN,
5138                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5139
5140         /* WaSetupGtModeTdRowDispatch:snb */
5141         if (IS_SNB_GT1(dev))
5142                 I915_WRITE(GEN6_GT_MODE,
5143                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5144
5145         I915_WRITE(WM3_LP_ILK, 0);
5146         I915_WRITE(WM2_LP_ILK, 0);
5147         I915_WRITE(WM1_LP_ILK, 0);
5148
5149         I915_WRITE(CACHE_MODE_0,
5150                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5151
5152         I915_WRITE(GEN6_UCGCTL1,
5153                    I915_READ(GEN6_UCGCTL1) |
5154                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5155                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5156
5157         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5158          * gating disable must be set.  Failure to set it results in
5159          * flickering pixels due to Z write ordering failures after
5160          * some amount of runtime in the Mesa "fire" demo, and Unigine
5161          * Sanctuary and Tropics, and apparently anything else with
5162          * alpha test or pixel discard.
5163          *
5164          * According to the spec, bit 11 (RCCUNIT) must also be set,
5165          * but we didn't debug actual testcases to find it out.
5166          *
5167          * Also apply WaDisableVDSUnitClockGating:snb and
5168          * WaDisableRCPBUnitClockGating:snb.
5169          */
5170         I915_WRITE(GEN6_UCGCTL2,
5171                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5172                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5173                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5174
5175         /* Bspec says we need to always set all mask bits. */
5176         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5177                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5178
5179         /*
5180          * According to the spec the following bits should be
5181          * set in order to enable memory self-refresh and fbc:
5182          * The bit21 and bit22 of 0x42000
5183          * The bit21 and bit22 of 0x42004
5184          * The bit5 and bit7 of 0x42020
5185          * The bit14 of 0x70180
5186          * The bit14 of 0x71180
5187          *
5188          * WaFbcAsynchFlipDisableFbcQueue:snb
5189          */
5190         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5191                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5192                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5193         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5194                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5195                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5196         I915_WRITE(ILK_DSPCLK_GATE_D,
5197                    I915_READ(ILK_DSPCLK_GATE_D) |
5198                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5199                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5200
5201         g4x_disable_trickle_feed(dev);
5202
5203         /* The default value should be 0x200 according to docs, but the two
5204          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5205         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5206         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5207
5208         cpt_init_clock_gating(dev);
5209
5210         gen6_check_mch_setup(dev);
5211 }
5212
5213 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5214 {
5215         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5216
5217         reg &= ~GEN7_FF_SCHED_MASK;
5218         reg |= GEN7_FF_TS_SCHED_HW;
5219         reg |= GEN7_FF_VS_SCHED_HW;
5220         reg |= GEN7_FF_DS_SCHED_HW;
5221
5222         if (IS_HASWELL(dev_priv->dev))
5223                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5224
5225         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5226 }
5227
5228 static void lpt_init_clock_gating(struct drm_device *dev)
5229 {
5230         struct drm_i915_private *dev_priv = dev->dev_private;
5231
5232         /*
5233          * TODO: this bit should only be enabled when really needed, then
5234          * disabled when not needed anymore in order to save power.
5235          */
5236         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5237                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5238                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5239                            PCH_LP_PARTITION_LEVEL_DISABLE);
5240
5241         /* WADPOClockGatingDisable:hsw */
5242         I915_WRITE(_TRANSA_CHICKEN1,
5243                    I915_READ(_TRANSA_CHICKEN1) |
5244                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5245 }
5246
5247 static void lpt_suspend_hw(struct drm_device *dev)
5248 {
5249         struct drm_i915_private *dev_priv = dev->dev_private;
5250
5251         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5252                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5253
5254                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5255                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5256         }
5257 }
5258
5259 static void gen8_init_clock_gating(struct drm_device *dev)
5260 {
5261         struct drm_i915_private *dev_priv = dev->dev_private;
5262         enum pipe i;
5263
5264         I915_WRITE(WM3_LP_ILK, 0);
5265         I915_WRITE(WM2_LP_ILK, 0);
5266         I915_WRITE(WM1_LP_ILK, 0);
5267
5268         /* FIXME(BDW): Check all the w/a, some might only apply to
5269          * pre-production hw. */
5270
5271         WARN(!i915_preliminary_hw_support,
5272              "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5273         I915_WRITE(HALF_SLICE_CHICKEN3,
5274                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5275         I915_WRITE(HALF_SLICE_CHICKEN3,
5276                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5277         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5278
5279         I915_WRITE(_3D_CHICKEN3,
5280                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5281
5282         I915_WRITE(COMMON_SLICE_CHICKEN2,
5283                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5284
5285         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5286                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5287
5288         /* WaSwitchSolVfFArbitrationPriority:bdw */
5289         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5290
5291         /* WaPsrDPAMaskVBlankInSRD:bdw */
5292         I915_WRITE(CHICKEN_PAR1_1,
5293                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5294
5295         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5296         for_each_pipe(i) {
5297                 I915_WRITE(CHICKEN_PIPESL_1(i),
5298                            I915_READ(CHICKEN_PIPESL_1(i) |
5299                                      DPRS_MASK_VBLANK_SRD));
5300         }
5301
5302         /* Use Force Non-Coherent whenever executing a 3D context. This is a
5303          * workaround for for a possible hang in the unlikely event a TLB
5304          * invalidation occurs during a PSD flush.
5305          */
5306         I915_WRITE(HDC_CHICKEN0,
5307                    I915_READ(HDC_CHICKEN0) |
5308                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5309
5310         /* WaVSRefCountFullforceMissDisable:bdw */
5311         /* WaDSRefCountFullforceMissDisable:bdw */
5312         I915_WRITE(GEN7_FF_THREAD_MODE,
5313                    I915_READ(GEN7_FF_THREAD_MODE) &
5314                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5315 }
5316
5317 static void haswell_init_clock_gating(struct drm_device *dev)
5318 {
5319         struct drm_i915_private *dev_priv = dev->dev_private;
5320
5321         I915_WRITE(WM3_LP_ILK, 0);
5322         I915_WRITE(WM2_LP_ILK, 0);
5323         I915_WRITE(WM1_LP_ILK, 0);
5324
5325         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5326          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5327          */
5328         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5329
5330         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5331         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5332                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5333
5334         /* WaApplyL3ControlAndL3ChickenMode:hsw */
5335         I915_WRITE(GEN7_L3CNTLREG1,
5336                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5337         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5338                         GEN7_WA_L3_CHICKEN_MODE);
5339
5340         /* L3 caching of data atomics doesn't work -- disable it. */
5341         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5342         I915_WRITE(HSW_ROW_CHICKEN3,
5343                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5344
5345         /* This is required by WaCatErrorRejectionIssue:hsw */
5346         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5347                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5348                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5349
5350         /* WaVSRefCountFullforceMissDisable:hsw */
5351         gen7_setup_fixed_func_scheduler(dev_priv);
5352
5353         /* WaDisable4x2SubspanOptimization:hsw */
5354         I915_WRITE(CACHE_MODE_1,
5355                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5356
5357         /* WaSwitchSolVfFArbitrationPriority:hsw */
5358         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5359
5360         /* WaRsPkgCStateDisplayPMReq:hsw */
5361         I915_WRITE(CHICKEN_PAR1_1,
5362                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5363
5364         lpt_init_clock_gating(dev);
5365 }
5366
5367 static void ivybridge_init_clock_gating(struct drm_device *dev)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         uint32_t snpcr;
5371
5372         I915_WRITE(WM3_LP_ILK, 0);
5373         I915_WRITE(WM2_LP_ILK, 0);
5374         I915_WRITE(WM1_LP_ILK, 0);
5375
5376         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5377
5378         /* WaDisableEarlyCull:ivb */
5379         I915_WRITE(_3D_CHICKEN3,
5380                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5381
5382         /* WaDisableBackToBackFlipFix:ivb */
5383         I915_WRITE(IVB_CHICKEN3,
5384                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5385                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5386
5387         /* WaDisablePSDDualDispatchEnable:ivb */
5388         if (IS_IVB_GT1(dev))
5389                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5390                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5391         else
5392                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5393                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5394
5395         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5396         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5397                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5398
5399         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5400         I915_WRITE(GEN7_L3CNTLREG1,
5401                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5402         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5403                    GEN7_WA_L3_CHICKEN_MODE);
5404         if (IS_IVB_GT1(dev))
5405                 I915_WRITE(GEN7_ROW_CHICKEN2,
5406                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5407         else
5408                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5409                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5410
5411
5412         /* WaForceL3Serialization:ivb */
5413         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5414                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5415
5416         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5417          * gating disable must be set.  Failure to set it results in
5418          * flickering pixels due to Z write ordering failures after
5419          * some amount of runtime in the Mesa "fire" demo, and Unigine
5420          * Sanctuary and Tropics, and apparently anything else with
5421          * alpha test or pixel discard.
5422          *
5423          * According to the spec, bit 11 (RCCUNIT) must also be set,
5424          * but we didn't debug actual testcases to find it out.
5425          *
5426          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5427          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5428          */
5429         I915_WRITE(GEN6_UCGCTL2,
5430                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5431                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5432
5433         /* This is required by WaCatErrorRejectionIssue:ivb */
5434         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5435                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5436                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5437
5438         g4x_disable_trickle_feed(dev);
5439
5440         /* WaVSRefCountFullforceMissDisable:ivb */
5441         gen7_setup_fixed_func_scheduler(dev_priv);
5442
5443         /* WaDisable4x2SubspanOptimization:ivb */
5444         I915_WRITE(CACHE_MODE_1,
5445                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5446
5447         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5448         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5449         snpcr |= GEN6_MBC_SNPCR_MED;
5450         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5451
5452         if (!HAS_PCH_NOP(dev))
5453                 cpt_init_clock_gating(dev);
5454
5455         gen6_check_mch_setup(dev);
5456 }
5457
5458 static void valleyview_init_clock_gating(struct drm_device *dev)
5459 {
5460         struct drm_i915_private *dev_priv = dev->dev_private;
5461         u32 val;
5462
5463         mutex_lock(&dev_priv->rps.hw_lock);
5464         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5465         mutex_unlock(&dev_priv->rps.hw_lock);
5466         switch ((val >> 6) & 3) {
5467         case 0:
5468                 dev_priv->mem_freq = 800;
5469                 break;
5470         case 1:
5471                 dev_priv->mem_freq = 1066;
5472                 break;
5473         case 2:
5474                 dev_priv->mem_freq = 1333;
5475                 break;
5476         case 3:
5477                 dev_priv->mem_freq = 1333;
5478                 break;
5479         }
5480         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5481
5482         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5483
5484         /* WaDisableEarlyCull:vlv */
5485         I915_WRITE(_3D_CHICKEN3,
5486                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5487
5488         /* WaDisableBackToBackFlipFix:vlv */
5489         I915_WRITE(IVB_CHICKEN3,
5490                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5491                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5492
5493         /* WaDisablePSDDualDispatchEnable:vlv */
5494         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5495                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5496                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5497
5498         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5499         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5500                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5501
5502         /* WaApplyL3ControlAndL3ChickenMode:vlv */
5503         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5504         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5505
5506         /* WaForceL3Serialization:vlv */
5507         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5508                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5509
5510         /* WaDisableDopClockGating:vlv */
5511         I915_WRITE(GEN7_ROW_CHICKEN2,
5512                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5513
5514         /* This is required by WaCatErrorRejectionIssue:vlv */
5515         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5516                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5517                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5518
5519         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5520          * gating disable must be set.  Failure to set it results in
5521          * flickering pixels due to Z write ordering failures after
5522          * some amount of runtime in the Mesa "fire" demo, and Unigine
5523          * Sanctuary and Tropics, and apparently anything else with
5524          * alpha test or pixel discard.
5525          *
5526          * According to the spec, bit 11 (RCCUNIT) must also be set,
5527          * but we didn't debug actual testcases to find it out.
5528          *
5529          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5530          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5531          *
5532          * Also apply WaDisableVDSUnitClockGating:vlv and
5533          * WaDisableRCPBUnitClockGating:vlv.
5534          */
5535         I915_WRITE(GEN6_UCGCTL2,
5536                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5537                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5538                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5539                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5540                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5541
5542         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5543
5544         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5545
5546         I915_WRITE(CACHE_MODE_1,
5547                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5548
5549         /*
5550          * WaDisableVLVClockGating_VBIIssue:vlv
5551          * Disable clock gating on th GCFG unit to prevent a delay
5552          * in the reporting of vblank events.
5553          */
5554         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5555
5556         /* Conservative clock gating settings for now */
5557         I915_WRITE(0x9400, 0xffffffff);
5558         I915_WRITE(0x9404, 0xffffffff);
5559         I915_WRITE(0x9408, 0xffffffff);
5560         I915_WRITE(0x940c, 0xffffffff);
5561         I915_WRITE(0x9410, 0xffffffff);
5562         I915_WRITE(0x9414, 0xffffffff);
5563         I915_WRITE(0x9418, 0xffffffff);
5564 }
5565
5566 static void g4x_init_clock_gating(struct drm_device *dev)
5567 {
5568         struct drm_i915_private *dev_priv = dev->dev_private;
5569         uint32_t dspclk_gate;
5570
5571         I915_WRITE(RENCLK_GATE_D1, 0);
5572         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5573                    GS_UNIT_CLOCK_GATE_DISABLE |
5574                    CL_UNIT_CLOCK_GATE_DISABLE);
5575         I915_WRITE(RAMCLK_GATE_D, 0);
5576         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5577                 OVRUNIT_CLOCK_GATE_DISABLE |
5578                 OVCUNIT_CLOCK_GATE_DISABLE;
5579         if (IS_GM45(dev))
5580                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5581         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5582
5583         /* WaDisableRenderCachePipelinedFlush */
5584         I915_WRITE(CACHE_MODE_0,
5585                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5586
5587         g4x_disable_trickle_feed(dev);
5588 }
5589
5590 static void crestline_init_clock_gating(struct drm_device *dev)
5591 {
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593
5594         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5595         I915_WRITE(RENCLK_GATE_D2, 0);
5596         I915_WRITE(DSPCLK_GATE_D, 0);
5597         I915_WRITE(RAMCLK_GATE_D, 0);
5598         I915_WRITE16(DEUC, 0);
5599         I915_WRITE(MI_ARB_STATE,
5600                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5601 }
5602
5603 static void broadwater_init_clock_gating(struct drm_device *dev)
5604 {
5605         struct drm_i915_private *dev_priv = dev->dev_private;
5606
5607         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5608                    I965_RCC_CLOCK_GATE_DISABLE |
5609                    I965_RCPB_CLOCK_GATE_DISABLE |
5610                    I965_ISC_CLOCK_GATE_DISABLE |
5611                    I965_FBC_CLOCK_GATE_DISABLE);
5612         I915_WRITE(RENCLK_GATE_D2, 0);
5613         I915_WRITE(MI_ARB_STATE,
5614                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5615 }
5616
5617 static void gen3_init_clock_gating(struct drm_device *dev)
5618 {
5619         struct drm_i915_private *dev_priv = dev->dev_private;
5620         u32 dstate = I915_READ(D_STATE);
5621
5622         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5623                 DSTATE_DOT_CLOCK_GATING;
5624         I915_WRITE(D_STATE, dstate);
5625
5626         if (IS_PINEVIEW(dev))
5627                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5628
5629         /* IIR "flip pending" means done if this bit is set */
5630         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5631 }
5632
5633 static void i85x_init_clock_gating(struct drm_device *dev)
5634 {
5635         struct drm_i915_private *dev_priv = dev->dev_private;
5636
5637         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5638 }
5639
5640 static void i830_init_clock_gating(struct drm_device *dev)
5641 {
5642         struct drm_i915_private *dev_priv = dev->dev_private;
5643
5644         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5645 }
5646
5647 void intel_init_clock_gating(struct drm_device *dev)
5648 {
5649         struct drm_i915_private *dev_priv = dev->dev_private;
5650
5651         dev_priv->display.init_clock_gating(dev);
5652 }
5653
5654 void intel_suspend_hw(struct drm_device *dev)
5655 {
5656         if (HAS_PCH_LPT(dev))
5657                 lpt_suspend_hw(dev);
5658 }
5659
5660 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5661         for (i = 0;                                                     \
5662              i < (power_domains)->power_well_count &&                   \
5663                  ((power_well) = &(power_domains)->power_wells[i]);     \
5664              i++)                                                       \
5665                 if ((power_well)->domains & (domain_mask))
5666
5667 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5668         for (i = (power_domains)->power_well_count - 1;                  \
5669              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5670              i--)                                                        \
5671                 if ((power_well)->domains & (domain_mask))
5672
5673 /**
5674  * We should only use the power well if we explicitly asked the hardware to
5675  * enable it, so check if it's enabled and also check if we've requested it to
5676  * be enabled.
5677  */
5678 static bool hsw_power_well_enabled(struct drm_device *dev,
5679                                    struct i915_power_well *power_well)
5680 {
5681         struct drm_i915_private *dev_priv = dev->dev_private;
5682
5683         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5684                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5685 }
5686
5687 bool intel_display_power_enabled_sw(struct drm_device *dev,
5688                                     enum intel_display_power_domain domain)
5689 {
5690         struct drm_i915_private *dev_priv = dev->dev_private;
5691         struct i915_power_domains *power_domains;
5692
5693         power_domains = &dev_priv->power_domains;
5694
5695         return power_domains->domain_use_count[domain];
5696 }
5697
5698 bool intel_display_power_enabled(struct drm_device *dev,
5699                                  enum intel_display_power_domain domain)
5700 {
5701         struct drm_i915_private *dev_priv = dev->dev_private;
5702         struct i915_power_domains *power_domains;
5703         struct i915_power_well *power_well;
5704         bool is_enabled;
5705         int i;
5706
5707         power_domains = &dev_priv->power_domains;
5708
5709         is_enabled = true;
5710
5711         mutex_lock(&power_domains->lock);
5712         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5713                 if (power_well->always_on)
5714                         continue;
5715
5716                 if (!power_well->is_enabled(dev, power_well)) {
5717                         is_enabled = false;
5718                         break;
5719                 }
5720         }
5721         mutex_unlock(&power_domains->lock);
5722
5723         return is_enabled;
5724 }
5725
5726 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5727 {
5728         struct drm_device *dev = dev_priv->dev;
5729         unsigned long irqflags;
5730
5731         /*
5732          * After we re-enable the power well, if we touch VGA register 0x3d5
5733          * we'll get unclaimed register interrupts. This stops after we write
5734          * anything to the VGA MSR register. The vgacon module uses this
5735          * register all the time, so if we unbind our driver and, as a
5736          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5737          * console_unlock(). So make here we touch the VGA MSR register, making
5738          * sure vgacon can keep working normally without triggering interrupts
5739          * and error messages.
5740          */
5741         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5742         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5743         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5744
5745         if (IS_BROADWELL(dev)) {
5746                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5747                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5748                            dev_priv->de_irq_mask[PIPE_B]);
5749                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5750                            ~dev_priv->de_irq_mask[PIPE_B] |
5751                            GEN8_PIPE_VBLANK);
5752                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5753                            dev_priv->de_irq_mask[PIPE_C]);
5754                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5755                            ~dev_priv->de_irq_mask[PIPE_C] |
5756                            GEN8_PIPE_VBLANK);
5757                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5758                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5759         }
5760 }
5761
5762 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5763 {
5764         struct drm_device *dev = dev_priv->dev;
5765         enum pipe p;
5766         unsigned long irqflags;
5767
5768         /*
5769          * After this, the registers on the pipes that are part of the power
5770          * well will become zero, so we have to adjust our counters according to
5771          * that.
5772          *
5773          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5774          */
5775         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5776         for_each_pipe(p)
5777                 if (p != PIPE_A)
5778                         dev->vblank[p].last = 0;
5779         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5780 }
5781
5782 static void hsw_set_power_well(struct drm_device *dev,
5783                                struct i915_power_well *power_well, bool enable)
5784 {
5785         struct drm_i915_private *dev_priv = dev->dev_private;
5786         bool is_enabled, enable_requested;
5787         uint32_t tmp;
5788
5789         WARN_ON(dev_priv->pc8.enabled);
5790
5791         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5792         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5793         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5794
5795         if (enable) {
5796                 if (!enable_requested)
5797                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5798                                    HSW_PWR_WELL_ENABLE_REQUEST);
5799
5800                 if (!is_enabled) {
5801                         DRM_DEBUG_KMS("Enabling power well\n");
5802                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5803                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5804                                 DRM_ERROR("Timeout enabling power well\n");
5805                 }
5806
5807                 hsw_power_well_post_enable(dev_priv);
5808         } else {
5809                 if (enable_requested) {
5810                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5811                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5812                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5813
5814                         hsw_power_well_post_disable(dev_priv);
5815                 }
5816         }
5817 }
5818
5819 static void __intel_power_well_get(struct drm_device *dev,
5820                                    struct i915_power_well *power_well)
5821 {
5822         struct drm_i915_private *dev_priv = dev->dev_private;
5823
5824         if (!power_well->count++ && power_well->set) {
5825                 hsw_disable_package_c8(dev_priv);
5826                 power_well->set(dev, power_well, true);
5827         }
5828 }
5829
5830 static void __intel_power_well_put(struct drm_device *dev,
5831                                    struct i915_power_well *power_well)
5832 {
5833         struct drm_i915_private *dev_priv = dev->dev_private;
5834
5835         WARN_ON(!power_well->count);
5836
5837         if (!--power_well->count && power_well->set &&
5838             i915_disable_power_well) {
5839                 power_well->set(dev, power_well, false);
5840                 hsw_enable_package_c8(dev_priv);
5841         }
5842 }
5843
5844 void intel_display_power_get(struct drm_device *dev,
5845                              enum intel_display_power_domain domain)
5846 {
5847         struct drm_i915_private *dev_priv = dev->dev_private;
5848         struct i915_power_domains *power_domains;
5849         struct i915_power_well *power_well;
5850         int i;
5851
5852         power_domains = &dev_priv->power_domains;
5853
5854         mutex_lock(&power_domains->lock);
5855
5856         for_each_power_well(i, power_well, BIT(domain), power_domains)
5857                 __intel_power_well_get(dev, power_well);
5858
5859         power_domains->domain_use_count[domain]++;
5860
5861         mutex_unlock(&power_domains->lock);
5862 }
5863
5864 void intel_display_power_put(struct drm_device *dev,
5865                              enum intel_display_power_domain domain)
5866 {
5867         struct drm_i915_private *dev_priv = dev->dev_private;
5868         struct i915_power_domains *power_domains;
5869         struct i915_power_well *power_well;
5870         int i;
5871
5872         power_domains = &dev_priv->power_domains;
5873
5874         mutex_lock(&power_domains->lock);
5875
5876         WARN_ON(!power_domains->domain_use_count[domain]);
5877         power_domains->domain_use_count[domain]--;
5878
5879         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5880                 __intel_power_well_put(dev, power_well);
5881
5882         mutex_unlock(&power_domains->lock);
5883 }
5884
5885 static struct i915_power_domains *hsw_pwr;
5886
5887 /* Display audio driver power well request */
5888 void i915_request_power_well(void)
5889 {
5890         struct drm_i915_private *dev_priv;
5891
5892         if (WARN_ON(!hsw_pwr))
5893                 return;
5894
5895         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5896                                 power_domains);
5897         intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5898 }
5899 EXPORT_SYMBOL_GPL(i915_request_power_well);
5900
5901 /* Display audio driver power well release */
5902 void i915_release_power_well(void)
5903 {
5904         struct drm_i915_private *dev_priv;
5905
5906         if (WARN_ON(!hsw_pwr))
5907                 return;
5908
5909         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5910                                 power_domains);
5911         intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5912 }
5913 EXPORT_SYMBOL_GPL(i915_release_power_well);
5914
5915 static struct i915_power_well i9xx_always_on_power_well[] = {
5916         {
5917                 .name = "always-on",
5918                 .always_on = 1,
5919                 .domains = POWER_DOMAIN_MASK,
5920         },
5921 };
5922
5923 static struct i915_power_well hsw_power_wells[] = {
5924         {
5925                 .name = "always-on",
5926                 .always_on = 1,
5927                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5928         },
5929         {
5930                 .name = "display",
5931                 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5932                 .is_enabled = hsw_power_well_enabled,
5933                 .set = hsw_set_power_well,
5934         },
5935 };
5936
5937 static struct i915_power_well bdw_power_wells[] = {
5938         {
5939                 .name = "always-on",
5940                 .always_on = 1,
5941                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5942         },
5943         {
5944                 .name = "display",
5945                 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5946                 .is_enabled = hsw_power_well_enabled,
5947                 .set = hsw_set_power_well,
5948         },
5949 };
5950
5951 #define set_power_wells(power_domains, __power_wells) ({                \
5952         (power_domains)->power_wells = (__power_wells);                 \
5953         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
5954 })
5955
5956 int intel_power_domains_init(struct drm_device *dev)
5957 {
5958         struct drm_i915_private *dev_priv = dev->dev_private;
5959         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5960
5961         mutex_init(&power_domains->lock);
5962
5963         /*
5964          * The enabling order will be from lower to higher indexed wells,
5965          * the disabling order is reversed.
5966          */
5967         if (IS_HASWELL(dev)) {
5968                 set_power_wells(power_domains, hsw_power_wells);
5969                 hsw_pwr = power_domains;
5970         } else if (IS_BROADWELL(dev)) {
5971                 set_power_wells(power_domains, bdw_power_wells);
5972                 hsw_pwr = power_domains;
5973         } else {
5974                 set_power_wells(power_domains, i9xx_always_on_power_well);
5975         }
5976
5977         return 0;
5978 }
5979
5980 void intel_power_domains_remove(struct drm_device *dev)
5981 {
5982         hsw_pwr = NULL;
5983 }
5984
5985 static void intel_power_domains_resume(struct drm_device *dev)
5986 {
5987         struct drm_i915_private *dev_priv = dev->dev_private;
5988         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5989         struct i915_power_well *power_well;
5990         int i;
5991
5992         mutex_lock(&power_domains->lock);
5993         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5994                 if (power_well->set)
5995                         power_well->set(dev, power_well, power_well->count > 0);
5996         }
5997         mutex_unlock(&power_domains->lock);
5998 }
5999
6000 /*
6001  * Starting with Haswell, we have a "Power Down Well" that can be turned off
6002  * when not needed anymore. We have 4 registers that can request the power well
6003  * to be enabled, and it will only be disabled if none of the registers is
6004  * requesting it to be enabled.
6005  */
6006 void intel_power_domains_init_hw(struct drm_device *dev)
6007 {
6008         struct drm_i915_private *dev_priv = dev->dev_private;
6009
6010         /* For now, we need the power well to be always enabled. */
6011         intel_display_set_init_power(dev, true);
6012         intel_power_domains_resume(dev);
6013
6014         if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
6015                 return;
6016
6017         /* We're taking over the BIOS, so clear any requests made by it since
6018          * the driver is in charge now. */
6019         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6020                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6021 }
6022
6023 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
6024 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6025 {
6026         hsw_disable_package_c8(dev_priv);
6027 }
6028
6029 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6030 {
6031         hsw_enable_package_c8(dev_priv);
6032 }
6033
6034 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6035 {
6036         struct drm_device *dev = dev_priv->dev;
6037         struct device *device = &dev->pdev->dev;
6038
6039         if (!HAS_RUNTIME_PM(dev))
6040                 return;
6041
6042         pm_runtime_get_sync(device);
6043         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6044 }
6045
6046 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6047 {
6048         struct drm_device *dev = dev_priv->dev;
6049         struct device *device = &dev->pdev->dev;
6050
6051         if (!HAS_RUNTIME_PM(dev))
6052                 return;
6053
6054         pm_runtime_mark_last_busy(device);
6055         pm_runtime_put_autosuspend(device);
6056 }
6057
6058 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6059 {
6060         struct drm_device *dev = dev_priv->dev;
6061         struct device *device = &dev->pdev->dev;
6062
6063         dev_priv->pm.suspended = false;
6064
6065         if (!HAS_RUNTIME_PM(dev))
6066                 return;
6067
6068         pm_runtime_set_active(device);
6069
6070         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6071         pm_runtime_mark_last_busy(device);
6072         pm_runtime_use_autosuspend(device);
6073 }
6074
6075 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6076 {
6077         struct drm_device *dev = dev_priv->dev;
6078         struct device *device = &dev->pdev->dev;
6079
6080         if (!HAS_RUNTIME_PM(dev))
6081                 return;
6082
6083         /* Make sure we're not suspended first. */
6084         pm_runtime_get_sync(device);
6085         pm_runtime_disable(device);
6086 }
6087
6088 /* Set up chip specific power management-related functions */
6089 void intel_init_pm(struct drm_device *dev)
6090 {
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092
6093         if (I915_HAS_FBC(dev)) {
6094                 if (INTEL_INFO(dev)->gen >= 7) {
6095                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6096                         dev_priv->display.enable_fbc = gen7_enable_fbc;
6097                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6098                 } else if (INTEL_INFO(dev)->gen >= 5) {
6099                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6100                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6101                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6102                 } else if (IS_GM45(dev)) {
6103                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6104                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6105                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6106                 } else {
6107                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6108                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6109                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6110
6111                         /* This value was pulled out of someone's hat */
6112                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6113                 }
6114         }
6115
6116         /* For cxsr */
6117         if (IS_PINEVIEW(dev))
6118                 i915_pineview_get_mem_freq(dev);
6119         else if (IS_GEN5(dev))
6120                 i915_ironlake_get_mem_freq(dev);
6121
6122         /* For FIFO watermark updates */
6123         if (HAS_PCH_SPLIT(dev)) {
6124                 intel_setup_wm_latency(dev);
6125
6126                 if (IS_GEN5(dev)) {
6127                         if (dev_priv->wm.pri_latency[1] &&
6128                             dev_priv->wm.spr_latency[1] &&
6129                             dev_priv->wm.cur_latency[1])
6130                                 dev_priv->display.update_wm = ironlake_update_wm;
6131                         else {
6132                                 DRM_DEBUG_KMS("Failed to get proper latency. "
6133                                               "Disable CxSR\n");
6134                                 dev_priv->display.update_wm = NULL;
6135                         }
6136                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6137                 } else if (IS_GEN6(dev)) {
6138                         if (dev_priv->wm.pri_latency[0] &&
6139                             dev_priv->wm.spr_latency[0] &&
6140                             dev_priv->wm.cur_latency[0]) {
6141                                 dev_priv->display.update_wm = sandybridge_update_wm;
6142                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6143                         } else {
6144                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6145                                               "Disable CxSR\n");
6146                                 dev_priv->display.update_wm = NULL;
6147                         }
6148                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6149                 } else if (IS_IVYBRIDGE(dev)) {
6150                         if (dev_priv->wm.pri_latency[0] &&
6151                             dev_priv->wm.spr_latency[0] &&
6152                             dev_priv->wm.cur_latency[0]) {
6153                                 dev_priv->display.update_wm = ivybridge_update_wm;
6154                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6155                         } else {
6156                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6157                                               "Disable CxSR\n");
6158                                 dev_priv->display.update_wm = NULL;
6159                         }
6160                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6161                 } else if (IS_HASWELL(dev)) {
6162                         if (dev_priv->wm.pri_latency[0] &&
6163                             dev_priv->wm.spr_latency[0] &&
6164                             dev_priv->wm.cur_latency[0]) {
6165                                 dev_priv->display.update_wm = haswell_update_wm;
6166                                 dev_priv->display.update_sprite_wm =
6167                                         haswell_update_sprite_wm;
6168                         } else {
6169                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6170                                               "Disable CxSR\n");
6171                                 dev_priv->display.update_wm = NULL;
6172                         }
6173                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6174                 } else if (INTEL_INFO(dev)->gen == 8) {
6175                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6176                 } else
6177                         dev_priv->display.update_wm = NULL;
6178         } else if (IS_VALLEYVIEW(dev)) {
6179                 dev_priv->display.update_wm = valleyview_update_wm;
6180                 dev_priv->display.init_clock_gating =
6181                         valleyview_init_clock_gating;
6182         } else if (IS_PINEVIEW(dev)) {
6183                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6184                                             dev_priv->is_ddr3,
6185                                             dev_priv->fsb_freq,
6186                                             dev_priv->mem_freq)) {
6187                         DRM_INFO("failed to find known CxSR latency "
6188                                  "(found ddr%s fsb freq %d, mem freq %d), "
6189                                  "disabling CxSR\n",
6190                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6191                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6192                         /* Disable CxSR and never update its watermark again */
6193                         pineview_disable_cxsr(dev);
6194                         dev_priv->display.update_wm = NULL;
6195                 } else
6196                         dev_priv->display.update_wm = pineview_update_wm;
6197                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6198         } else if (IS_G4X(dev)) {
6199                 dev_priv->display.update_wm = g4x_update_wm;
6200                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6201         } else if (IS_GEN4(dev)) {
6202                 dev_priv->display.update_wm = i965_update_wm;
6203                 if (IS_CRESTLINE(dev))
6204                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6205                 else if (IS_BROADWATER(dev))
6206                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6207         } else if (IS_GEN3(dev)) {
6208                 dev_priv->display.update_wm = i9xx_update_wm;
6209                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6210                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6211         } else if (IS_I865G(dev)) {
6212                 dev_priv->display.update_wm = i830_update_wm;
6213                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6214                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6215         } else if (IS_I85X(dev)) {
6216                 dev_priv->display.update_wm = i9xx_update_wm;
6217                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6218                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6219         } else {
6220                 dev_priv->display.update_wm = i830_update_wm;
6221                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6222                 if (IS_845G(dev))
6223                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6224                 else
6225                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6226         }
6227 }
6228
6229 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6230 {
6231         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6232
6233         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6234                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6235                 return -EAGAIN;
6236         }
6237
6238         I915_WRITE(GEN6_PCODE_DATA, *val);
6239         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6240
6241         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6242                      500)) {
6243                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6244                 return -ETIMEDOUT;
6245         }
6246
6247         *val = I915_READ(GEN6_PCODE_DATA);
6248         I915_WRITE(GEN6_PCODE_DATA, 0);
6249
6250         return 0;
6251 }
6252
6253 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6254 {
6255         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6256
6257         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6258                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6259                 return -EAGAIN;
6260         }
6261
6262         I915_WRITE(GEN6_PCODE_DATA, val);
6263         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6264
6265         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6266                      500)) {
6267                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6268                 return -ETIMEDOUT;
6269         }
6270
6271         I915_WRITE(GEN6_PCODE_DATA, 0);
6272
6273         return 0;
6274 }
6275
6276 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6277 {
6278         int div;
6279
6280         /* 4 x czclk */
6281         switch (dev_priv->mem_freq) {
6282         case 800:
6283                 div = 10;
6284                 break;
6285         case 1066:
6286                 div = 12;
6287                 break;
6288         case 1333:
6289                 div = 16;
6290                 break;
6291         default:
6292                 return -1;
6293         }
6294
6295         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6296 }
6297
6298 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6299 {
6300         int mul;
6301
6302         /* 4 x czclk */
6303         switch (dev_priv->mem_freq) {
6304         case 800:
6305                 mul = 10;
6306                 break;
6307         case 1066:
6308                 mul = 12;
6309                 break;
6310         case 1333:
6311                 mul = 16;
6312                 break;
6313         default:
6314                 return -1;
6315         }
6316
6317         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6318 }
6319
6320 void intel_pm_init(struct drm_device *dev)
6321 {
6322         struct drm_i915_private *dev_priv = dev->dev_private;
6323
6324         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6325                           intel_gen6_powersave_work);
6326 }