drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int plane, i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 113
 114         /* Clear old tags */
 115         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 116                 I915_WRITE(FBC_TAG + (i * 4), 0);
 117
 118         if (IS_GEN4(dev)) {
 119                 u32 fbc_ctl2;
 120
 121                 /* Set it up... */
 122                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 123                 fbc_ctl2 |= plane;
 124                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 125                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 126         }
 127
 128         /* enable it... */
 129         fbc_ctl = I915_READ(FBC_CONTROL);
 130         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 131         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 132         if (IS_I945GM(dev))
 133                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 134         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 135         fbc_ctl |= obj->fence_reg;
 136         I915_WRITE(FBC_CONTROL, fbc_ctl);
 137
 138         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 139                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 140 }
 141
 142 static bool i8xx_fbc_enabled(struct drm_device *dev)
 143 {
 144         struct drm_i915_private *dev_priv = dev->dev_private;
 145
 146         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 147 }
 148
 149 static void g4x_enable_fbc(struct drm_crtc *crtc)
 150 {
 151         struct drm_device *dev = crtc->dev;
 152         struct drm_i915_private *dev_priv = dev->dev_private;
 153         struct drm_framebuffer *fb = crtc->fb;
 154         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 155         struct drm_i915_gem_object *obj = intel_fb->obj;
 156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 157         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 158         u32 dpfc_ctl;
 159
 160         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 161         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 162         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 163
 164         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 165
 166         /* enable it... */
 167         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 168
 169         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 170 }
 171
 172 static void g4x_disable_fbc(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         u32 dpfc_ctl;
 176
 177         /* Disable compression */
 178         dpfc_ctl = I915_READ(DPFC_CONTROL);
 179         if (dpfc_ctl & DPFC_CTL_EN) {
 180                 dpfc_ctl &= ~DPFC_CTL_EN;
 181                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 182
 183                 DRM_DEBUG_KMS("disabled FBC\n");
 184         }
 185 }
 186
 187 static bool g4x_fbc_enabled(struct drm_device *dev)
 188 {
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190
 191         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 192 }
 193
 194 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 195 {
 196         struct drm_i915_private *dev_priv = dev->dev_private;
 197         u32 blt_ecoskpd;
 198
 199         /* Make sure blitter notifies FBC of writes */
 200
 201         /* Blitter is part of Media powerwell on VLV. No impact of
 202          * his param in other platforms for now */
 203         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 204
 205         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 206         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 207                 GEN6_BLITTER_LOCK_SHIFT;
 208         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 209         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 210         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 211         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 212                          GEN6_BLITTER_LOCK_SHIFT);
 213         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 214         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 215
 216         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 217 }
 218
 219 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 220 {
 221         struct drm_device *dev = crtc->dev;
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         struct drm_framebuffer *fb = crtc->fb;
 224         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 225         struct drm_i915_gem_object *obj = intel_fb->obj;
 226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 227         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 231         dpfc_ctl &= DPFC_RESERVED;
 232         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 233         /* Set persistent mode for front-buffer rendering, ala X. */
 234         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 239
 240         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 241         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 242         /* enable it... */
 243         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 244
 245         if (IS_GEN6(dev)) {
 246                 I915_WRITE(SNB_DPFC_CTL_SA,
 247                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 248                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 249                 sandybridge_blit_fbc_update(dev);
 250         }
 251
 252         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 253 }
 254
 255 static void ironlake_disable_fbc(struct drm_device *dev)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         u32 dpfc_ctl;
 259
 260         /* Disable compression */
 261         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 262         if (dpfc_ctl & DPFC_CTL_EN) {
 263                 dpfc_ctl &= ~DPFC_CTL_EN;
 264                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 265
 266                 DRM_DEBUG_KMS("disabled FBC\n");
 267         }
 268 }
 269
 270 static bool ironlake_fbc_enabled(struct drm_device *dev)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 275 }
 276
 277 static void gen7_enable_fbc(struct drm_crtc *crtc)
 278 {
 279         struct drm_device *dev = crtc->dev;
 280         struct drm_i915_private *dev_priv = dev->dev_private;
 281         struct drm_framebuffer *fb = crtc->fb;
 282         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 283         struct drm_i915_gem_object *obj = intel_fb->obj;
 284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 285
 286         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 287
 288         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 289                    IVB_DPFC_CTL_FENCE_EN |
 290                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 291
 292         if (IS_IVYBRIDGE(dev)) {
 293                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 294                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 295         } else {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 297                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 298                            HSW_BYPASS_FBC_QUEUE);
 299         }
 300
 301         I915_WRITE(SNB_DPFC_CTL_SA,
 302                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 303         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 304
 305         sandybridge_blit_fbc_update(dev);
 306
 307         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 308 }
 309
 310 bool intel_fbc_enabled(struct drm_device *dev)
 311 {
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313
 314         if (!dev_priv->display.fbc_enabled)
 315                 return false;
 316
 317         return dev_priv->display.fbc_enabled(dev);
 318 }
 319
 320 static void intel_fbc_work_fn(struct work_struct *__work)
 321 {
 322         struct intel_fbc_work *work =
 323                 container_of(to_delayed_work(__work),
 324                              struct intel_fbc_work, work);
 325         struct drm_device *dev = work->crtc->dev;
 326         struct drm_i915_private *dev_priv = dev->dev_private;
 327
 328         mutex_lock(&dev->struct_mutex);
 329         if (work == dev_priv->fbc.fbc_work) {
 330                 /* Double check that we haven't switched fb without cancelling
 331                  * the prior work.
 332                  */
 333                 if (work->crtc->fb == work->fb) {
 334                         dev_priv->display.enable_fbc(work->crtc);
 335
 336                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 337                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 338                         dev_priv->fbc.y = work->crtc->y;
 339                 }
 340
 341                 dev_priv->fbc.fbc_work = NULL;
 342         }
 343         mutex_unlock(&dev->struct_mutex);
 344
 345         kfree(work);
 346 }
 347
 348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 349 {
 350         if (dev_priv->fbc.fbc_work == NULL)
 351                 return;
 352
 353         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 354
 355         /* Synchronisation is provided by struct_mutex and checking of
 356          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 357          * entirely asynchronously.
 358          */
 359         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 360                 /* tasklet was killed before being run, clean up */
 361                 kfree(dev_priv->fbc.fbc_work);
 362
 363         /* Mark the work as no longer wanted so that if it does
 364          * wake-up (because the work was already running and waiting
 365          * for our mutex), it will discover that is no longer
 366          * necessary to run.
 367          */
 368         dev_priv->fbc.fbc_work = NULL;
 369 }
 370
 371 static void intel_enable_fbc(struct drm_crtc *crtc)
 372 {
 373         struct intel_fbc_work *work;
 374         struct drm_device *dev = crtc->dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         if (!dev_priv->display.enable_fbc)
 378                 return;
 379
 380         intel_cancel_fbc_work(dev_priv);
 381
 382         work = kzalloc(sizeof(*work), GFP_KERNEL);
 383         if (work == NULL) {
 384                 DRM_ERROR("Failed to allocate FBC work structure\n");
 385                 dev_priv->display.enable_fbc(crtc);
 386                 return;
 387         }
 388
 389         work->crtc = crtc;
 390         work->fb = crtc->fb;
 391         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 392
 393         dev_priv->fbc.fbc_work = work;
 394
 395         /* Delay the actual enabling to let pageflipping cease and the
 396          * display to settle before starting the compression. Note that
 397          * this delay also serves a second purpose: it allows for a
 398          * vblank to pass after disabling the FBC before we attempt
 399          * to modify the control registers.
 400          *
 401          * A more complicated solution would involve tracking vblanks
 402          * following the termination of the page-flipping sequence
 403          * and indeed performing the enable as a co-routine and not
 404          * waiting synchronously upon the vblank.
 405          *
 406          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 407          */
 408         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 409 }
 410
 411 void intel_disable_fbc(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         intel_cancel_fbc_work(dev_priv);
 416
 417         if (!dev_priv->display.disable_fbc)
 418                 return;
 419
 420         dev_priv->display.disable_fbc(dev);
 421         dev_priv->fbc.plane = -1;
 422 }
 423
 424 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 425                               enum no_fbc_reason reason)
 426 {
 427         if (dev_priv->fbc.no_fbc_reason == reason)
 428                 return false;
 429
 430         dev_priv->fbc.no_fbc_reason = reason;
 431         return true;
 432 }
 433
 434 /**
 435  * intel_update_fbc - enable/disable FBC as needed
 436  * @dev: the drm_device
 437  *
 438  * Set up the framebuffer compression hardware at mode set time.  We
 439  * enable it if possible:
 440  *   - plane A only (on pre-965)
 441  *   - no pixel mulitply/line duplication
 442  *   - no alpha buffer discard
 443  *   - no dual wide
 444  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 445  *
 446  * We can't assume that any compression will take place (worst case),
 447  * so the compressed buffer has to be the same size as the uncompressed
 448  * one.  It also must reside (along with the line length buffer) in
 449  * stolen memory.
 450  *
 451  * We need to enable/disable FBC on a global basis.
 452  */
 453 void intel_update_fbc(struct drm_device *dev)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         struct drm_crtc *crtc = NULL, *tmp_crtc;
 457         struct intel_crtc *intel_crtc;
 458         struct drm_framebuffer *fb;
 459         struct intel_framebuffer *intel_fb;
 460         struct drm_i915_gem_object *obj;
 461         const struct drm_display_mode *adjusted_mode;
 462         unsigned int max_width, max_height;
 463
 464         if (!HAS_FBC(dev)) {
 465                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 466                 return;
 467         }
 468
 469         if (!i915_powersave) {
 470                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 471                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 472                 return;
 473         }
 474
 475         /*
 476          * If FBC is already on, we just have to verify that we can
 477          * keep it that way...
 478          * Need to disable if:
 479          *   - more than one pipe is active
 480          *   - changing FBC params (stride, fence, mode)
 481          *   - new fb is too large to fit in compressed buffer
 482          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 483          */
 484         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 485                 if (intel_crtc_active(tmp_crtc) &&
 486                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 487                         if (crtc) {
 488                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 489                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 490                                 goto out_disable;
 491                         }
 492                         crtc = tmp_crtc;
 493                 }
 494         }
 495
 496         if (!crtc || crtc->fb == NULL) {
 497                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 498                         DRM_DEBUG_KMS("no output, disabling\n");
 499                 goto out_disable;
 500         }
 501
 502         intel_crtc = to_intel_crtc(crtc);
 503         fb = crtc->fb;
 504         intel_fb = to_intel_framebuffer(fb);
 505         obj = intel_fb->obj;
 506         adjusted_mode = &intel_crtc->config.adjusted_mode;
 507
 508         if (i915_enable_fbc < 0 &&
 509             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 510                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 511                         DRM_DEBUG_KMS("disabled per chip default\n");
 512                 goto out_disable;
 513         }
 514         if (!i915_enable_fbc) {
 515                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 516                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 517                 goto out_disable;
 518         }
 519         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 520             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 522                         DRM_DEBUG_KMS("mode incompatible with compression, "
 523                                       "disabling\n");
 524                 goto out_disable;
 525         }
 526
 527         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 528                 max_width = 4096;
 529                 max_height = 2048;
 530         } else {
 531                 max_width = 2048;
 532                 max_height = 1536;
 533         }
 534         if (intel_crtc->config.pipe_src_w > max_width ||
 535             intel_crtc->config.pipe_src_h > max_height) {
 536                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 537                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 538                 goto out_disable;
 539         }
 540         if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
 541             intel_crtc->plane != PLANE_A) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 543                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 544                 goto out_disable;
 545         }
 546
 547         /* The use of a CPU fence is mandatory in order to detect writes
 548          * by the CPU to the scanout and trigger updates to the FBC.
 549          */
 550         if (obj->tiling_mode != I915_TILING_X ||
 551             obj->fence_reg == I915_FENCE_REG_NONE) {
 552                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 553                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 554                 goto out_disable;
 555         }
 556
 557         /* If the kernel debugger is active, always disable compression */
 558         if (in_dbg_master())
 559                 goto out_disable;
 560
 561         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 562                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 563                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 564                 goto out_disable;
 565         }
 566
 567         /* If the scanout has not changed, don't modify the FBC settings.
 568          * Note that we make the fundamental assumption that the fb->obj
 569          * cannot be unpinned (and have its GTT offset and fence revoked)
 570          * without first being decoupled from the scanout and FBC disabled.
 571          */
 572         if (dev_priv->fbc.plane == intel_crtc->plane &&
 573             dev_priv->fbc.fb_id == fb->base.id &&
 574             dev_priv->fbc.y == crtc->y)
 575                 return;
 576
 577         if (intel_fbc_enabled(dev)) {
 578                 /* We update FBC along two paths, after changing fb/crtc
 579                  * configuration (modeswitching) and after page-flipping
 580                  * finishes. For the latter, we know that not only did
 581                  * we disable the FBC at the start of the page-flip
 582                  * sequence, but also more than one vblank has passed.
 583                  *
 584                  * For the former case of modeswitching, it is possible
 585                  * to switch between two FBC valid configurations
 586                  * instantaneously so we do need to disable the FBC
 587                  * before we can modify its control registers. We also
 588                  * have to wait for the next vblank for that to take
 589                  * effect. However, since we delay enabling FBC we can
 590                  * assume that a vblank has passed since disabling and
 591                  * that we can safely alter the registers in the deferred
 592                  * callback.
 593                  *
 594                  * In the scenario that we go from a valid to invalid
 595                  * and then back to valid FBC configuration we have
 596                  * no strict enforcement that a vblank occurred since
 597                  * disabling the FBC. However, along all current pipe
 598                  * disabling paths we do need to wait for a vblank at
 599                  * some point. And we wait before enabling FBC anyway.
 600                  */
 601                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 602                 intel_disable_fbc(dev);
 603         }
 604
 605         intel_enable_fbc(crtc);
 606         dev_priv->fbc.no_fbc_reason = FBC_OK;
 607         return;
 608
 609 out_disable:
 610         /* Multiple disables should be harmless */
 611         if (intel_fbc_enabled(dev)) {
 612                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 613                 intel_disable_fbc(dev);
 614         }
 615         i915_gem_stolen_cleanup_compression(dev);
 616 }
 617
 618 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 619 {
 620         drm_i915_private_t *dev_priv = dev->dev_private;
 621         u32 tmp;
 622
 623         tmp = I915_READ(CLKCFG);
 624
 625         switch (tmp & CLKCFG_FSB_MASK) {
 626         case CLKCFG_FSB_533:
 627                 dev_priv->fsb_freq = 533; /* 133*4 */
 628                 break;
 629         case CLKCFG_FSB_800:
 630                 dev_priv->fsb_freq = 800; /* 200*4 */
 631                 break;
 632         case CLKCFG_FSB_667:
 633                 dev_priv->fsb_freq =  667; /* 167*4 */
 634                 break;
 635         case CLKCFG_FSB_400:
 636                 dev_priv->fsb_freq = 400; /* 100*4 */
 637                 break;
 638         }
 639
 640         switch (tmp & CLKCFG_MEM_MASK) {
 641         case CLKCFG_MEM_533:
 642                 dev_priv->mem_freq = 533;
 643                 break;
 644         case CLKCFG_MEM_667:
 645                 dev_priv->mem_freq = 667;
 646                 break;
 647         case CLKCFG_MEM_800:
 648                 dev_priv->mem_freq = 800;
 649                 break;
 650         }
 651
 652         /* detect pineview DDR3 setting */
 653         tmp = I915_READ(CSHRDDR3CTL);
 654         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 655 }
 656
 657 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 658 {
 659         drm_i915_private_t *dev_priv = dev->dev_private;
 660         u16 ddrpll, csipll;
 661
 662         ddrpll = I915_READ16(DDRMPLL1);
 663         csipll = I915_READ16(CSIPLL0);
 664
 665         switch (ddrpll & 0xff) {
 666         case 0xc:
 667                 dev_priv->mem_freq = 800;
 668                 break;
 669         case 0x10:
 670                 dev_priv->mem_freq = 1066;
 671                 break;
 672         case 0x14:
 673                 dev_priv->mem_freq = 1333;
 674                 break;
 675         case 0x18:
 676                 dev_priv->mem_freq = 1600;
 677                 break;
 678         default:
 679                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 680                                  ddrpll & 0xff);
 681                 dev_priv->mem_freq = 0;
 682                 break;
 683         }
 684
 685         dev_priv->ips.r_t = dev_priv->mem_freq;
 686
 687         switch (csipll & 0x3ff) {
 688         case 0x00c:
 689                 dev_priv->fsb_freq = 3200;
 690                 break;
 691         case 0x00e:
 692                 dev_priv->fsb_freq = 3733;
 693                 break;
 694         case 0x010:
 695                 dev_priv->fsb_freq = 4266;
 696                 break;
 697         case 0x012:
 698                 dev_priv->fsb_freq = 4800;
 699                 break;
 700         case 0x014:
 701                 dev_priv->fsb_freq = 5333;
 702                 break;
 703         case 0x016:
 704                 dev_priv->fsb_freq = 5866;
 705                 break;
 706         case 0x018:
 707                 dev_priv->fsb_freq = 6400;
 708                 break;
 709         default:
 710                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 711                                  csipll & 0x3ff);
 712                 dev_priv->fsb_freq = 0;
 713                 break;
 714         }
 715
 716         if (dev_priv->fsb_freq == 3200) {
 717                 dev_priv->ips.c_m = 0;
 718         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 719                 dev_priv->ips.c_m = 1;
 720         } else {
 721                 dev_priv->ips.c_m = 2;
 722         }
 723 }
 724
 725 static const struct cxsr_latency cxsr_latency_table[] = {
 726         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 727         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 728         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 729         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 730         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 731
 732         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 733         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 734         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 735         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 736         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 737
 738         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 739         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 740         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 741         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 742         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 743
 744         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 745         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 746         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 747         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 748         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 749
 750         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 751         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 752         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 753         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 754         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 755
 756         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 757         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 758         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 759         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 760         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 761 };
 762
 763 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 764                                                          int is_ddr3,
 765                                                          int fsb,
 766                                                          int mem)
 767 {
 768         const struct cxsr_latency *latency;
 769         int i;
 770
 771         if (fsb == 0 || mem == 0)
 772                 return NULL;
 773
 774         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 775                 latency = &cxsr_latency_table[i];
 776                 if (is_desktop == latency->is_desktop &&
 777                     is_ddr3 == latency->is_ddr3 &&
 778                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 779                         return latency;
 780         }
 781
 782         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 783
 784         return NULL;
 785 }
 786
 787 static void pineview_disable_cxsr(struct drm_device *dev)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790
 791         /* deactivate cxsr */
 792         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 793 }
 794
 795 /*
 796  * Latency for FIFO fetches is dependent on several factors:
 797  *   - memory configuration (speed, channels)
 798  *   - chipset
 799  *   - current MCH state
 800  * It can be fairly high in some situations, so here we assume a fairly
 801  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 802  * set this value too high, the FIFO will fetch frequently to stay full)
 803  * and power consumption (set it too low to save power and we might see
 804  * FIFO underruns and display "flicker").
 805  *
 806  * A value of 5us seems to be a good balance; safe for very low end
 807  * platforms but not overly aggressive on lower latency configs.
 808  */
 809 static const int latency_ns = 5000;
 810
 811 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 812 {
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         uint32_t dsparb = I915_READ(DSPARB);
 815         int size;
 816
 817         size = dsparb & 0x7f;
 818         if (plane)
 819                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 820
 821         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 822                       plane ? "B" : "A", size);
 823
 824         return size;
 825 }
 826
 827 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 828 {
 829         struct drm_i915_private *dev_priv = dev->dev_private;
 830         uint32_t dsparb = I915_READ(DSPARB);
 831         int size;
 832
 833         size = dsparb & 0x1ff;
 834         if (plane)
 835                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 836         size >>= 1; /* Convert to cachelines */
 837
 838         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 839                       plane ? "B" : "A", size);
 840
 841         return size;
 842 }
 843
 844 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         uint32_t dsparb = I915_READ(DSPARB);
 848         int size;
 849
 850         size = dsparb & 0x7f;
 851         size >>= 2; /* Convert to cachelines */
 852
 853         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 854                       plane ? "B" : "A",
 855                       size);
 856
 857         return size;
 858 }
 859
 860 /* Pineview has different values for various configs */
 861 static const struct intel_watermark_params pineview_display_wm = {
 862         PINEVIEW_DISPLAY_FIFO,
 863         PINEVIEW_MAX_WM,
 864         PINEVIEW_DFT_WM,
 865         PINEVIEW_GUARD_WM,
 866         PINEVIEW_FIFO_LINE_SIZE
 867 };
 868 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 869         PINEVIEW_DISPLAY_FIFO,
 870         PINEVIEW_MAX_WM,
 871         PINEVIEW_DFT_HPLLOFF_WM,
 872         PINEVIEW_GUARD_WM,
 873         PINEVIEW_FIFO_LINE_SIZE
 874 };
 875 static const struct intel_watermark_params pineview_cursor_wm = {
 876         PINEVIEW_CURSOR_FIFO,
 877         PINEVIEW_CURSOR_MAX_WM,
 878         PINEVIEW_CURSOR_DFT_WM,
 879         PINEVIEW_CURSOR_GUARD_WM,
 880         PINEVIEW_FIFO_LINE_SIZE,
 881 };
 882 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 883         PINEVIEW_CURSOR_FIFO,
 884         PINEVIEW_CURSOR_MAX_WM,
 885         PINEVIEW_CURSOR_DFT_WM,
 886         PINEVIEW_CURSOR_GUARD_WM,
 887         PINEVIEW_FIFO_LINE_SIZE
 888 };
 889 static const struct intel_watermark_params g4x_wm_info = {
 890         G4X_FIFO_SIZE,
 891         G4X_MAX_WM,
 892         G4X_MAX_WM,
 893         2,
 894         G4X_FIFO_LINE_SIZE,
 895 };
 896 static const struct intel_watermark_params g4x_cursor_wm_info = {
 897         I965_CURSOR_FIFO,
 898         I965_CURSOR_MAX_WM,
 899         I965_CURSOR_DFT_WM,
 900         2,
 901         G4X_FIFO_LINE_SIZE,
 902 };
 903 static const struct intel_watermark_params valleyview_wm_info = {
 904         VALLEYVIEW_FIFO_SIZE,
 905         VALLEYVIEW_MAX_WM,
 906         VALLEYVIEW_MAX_WM,
 907         2,
 908         G4X_FIFO_LINE_SIZE,
 909 };
 910 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 911         I965_CURSOR_FIFO,
 912         VALLEYVIEW_CURSOR_MAX_WM,
 913         I965_CURSOR_DFT_WM,
 914         2,
 915         G4X_FIFO_LINE_SIZE,
 916 };
 917 static const struct intel_watermark_params i965_cursor_wm_info = {
 918         I965_CURSOR_FIFO,
 919         I965_CURSOR_MAX_WM,
 920         I965_CURSOR_DFT_WM,
 921         2,
 922         I915_FIFO_LINE_SIZE,
 923 };
 924 static const struct intel_watermark_params i945_wm_info = {
 925         I945_FIFO_SIZE,
 926         I915_MAX_WM,
 927         1,
 928         2,
 929         I915_FIFO_LINE_SIZE
 930 };
 931 static const struct intel_watermark_params i915_wm_info = {
 932         I915_FIFO_SIZE,
 933         I915_MAX_WM,
 934         1,
 935         2,
 936         I915_FIFO_LINE_SIZE
 937 };
 938 static const struct intel_watermark_params i830_wm_info = {
 939         I855GM_FIFO_SIZE,
 940         I915_MAX_WM,
 941         1,
 942         2,
 943         I830_FIFO_LINE_SIZE
 944 };
 945 static const struct intel_watermark_params i845_wm_info = {
 946         I830_FIFO_SIZE,
 947         I915_MAX_WM,
 948         1,
 949         2,
 950         I830_FIFO_LINE_SIZE
 951 };
 952
 953 /**
 954  * intel_calculate_wm - calculate watermark level
 955  * @clock_in_khz: pixel clock
 956  * @wm: chip FIFO params
 957  * @pixel_size: display pixel size
 958  * @latency_ns: memory latency for the platform
 959  *
 960  * Calculate the watermark level (the level at which the display plane will
 961  * start fetching from memory again).  Each chip has a different display
 962  * FIFO size and allocation, so the caller needs to figure that out and pass
 963  * in the correct intel_watermark_params structure.
 964  *
 965  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 966  * on the pixel size.  When it reaches the watermark level, it'll start
 967  * fetching FIFO line sized based chunks from memory until the FIFO fills
 968  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 969  * will occur, and a display engine hang could result.
 970  */
 971 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 972                                         const struct intel_watermark_params *wm,
 973                                         int fifo_size,
 974                                         int pixel_size,
 975                                         unsigned long latency_ns)
 976 {
 977         long entries_required, wm_size;
 978
 979         /*
 980          * Note: we need to make sure we don't overflow for various clock &
 981          * latency values.
 982          * clocks go from a few thousand to several hundred thousand.
 983          * latency is usually a few thousand
 984          */
 985         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 986                 1000;
 987         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 988
 989         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 990
 991         wm_size = fifo_size - (entries_required + wm->guard_size);
 992
 993         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 994
 995         /* Don't promote wm_size to unsigned... */
 996         if (wm_size > (long)wm->max_wm)
 997                 wm_size = wm->max_wm;
 998         if (wm_size <= 0)
 999                 wm_size = wm->default_wm;
1000         return wm_size;
1001 }
1002
1003 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1004 {
1005         struct drm_crtc *crtc, *enabled = NULL;
1006
1007         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1008                 if (intel_crtc_active(crtc)) {
1009                         if (enabled)
1010                                 return NULL;
1011                         enabled = crtc;
1012                 }
1013         }
1014
1015         return enabled;
1016 }
1017
1018 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1019 {
1020         struct drm_device *dev = unused_crtc->dev;
1021         struct drm_i915_private *dev_priv = dev->dev_private;
1022         struct drm_crtc *crtc;
1023         const struct cxsr_latency *latency;
1024         u32 reg;
1025         unsigned long wm;
1026
1027         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1028                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1029         if (!latency) {
1030                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1031                 pineview_disable_cxsr(dev);
1032                 return;
1033         }
1034
1035         crtc = single_enabled_crtc(dev);
1036         if (crtc) {
1037                 const struct drm_display_mode *adjusted_mode;
1038                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1039                 int clock;
1040
1041                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1042                 clock = adjusted_mode->crtc_clock;
1043
1044                 /* Display SR */
1045                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1046                                         pineview_display_wm.fifo_size,
1047                                         pixel_size, latency->display_sr);
1048                 reg = I915_READ(DSPFW1);
1049                 reg &= ~DSPFW_SR_MASK;
1050                 reg |= wm << DSPFW_SR_SHIFT;
1051                 I915_WRITE(DSPFW1, reg);
1052                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1053
1054                 /* cursor SR */
1055                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1056                                         pineview_display_wm.fifo_size,
1057                                         pixel_size, latency->cursor_sr);
1058                 reg = I915_READ(DSPFW3);
1059                 reg &= ~DSPFW_CURSOR_SR_MASK;
1060                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1061                 I915_WRITE(DSPFW3, reg);
1062
1063                 /* Display HPLL off SR */
1064                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1065                                         pineview_display_hplloff_wm.fifo_size,
1066                                         pixel_size, latency->display_hpll_disable);
1067                 reg = I915_READ(DSPFW3);
1068                 reg &= ~DSPFW_HPLL_SR_MASK;
1069                 reg |= wm & DSPFW_HPLL_SR_MASK;
1070                 I915_WRITE(DSPFW3, reg);
1071
1072                 /* cursor HPLL off SR */
1073                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1074                                         pineview_display_hplloff_wm.fifo_size,
1075                                         pixel_size, latency->cursor_hpll_disable);
1076                 reg = I915_READ(DSPFW3);
1077                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1078                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1079                 I915_WRITE(DSPFW3, reg);
1080                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1081
1082                 /* activate cxsr */
1083                 I915_WRITE(DSPFW3,
1084                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1085                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1086         } else {
1087                 pineview_disable_cxsr(dev);
1088                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1089         }
1090 }
1091
1092 static bool g4x_compute_wm0(struct drm_device *dev,
1093                             int plane,
1094                             const struct intel_watermark_params *display,
1095                             int display_latency_ns,
1096                             const struct intel_watermark_params *cursor,
1097                             int cursor_latency_ns,
1098                             int *plane_wm,
1099                             int *cursor_wm)
1100 {
1101         struct drm_crtc *crtc;
1102         const struct drm_display_mode *adjusted_mode;
1103         int htotal, hdisplay, clock, pixel_size;
1104         int line_time_us, line_count;
1105         int entries, tlb_miss;
1106
1107         crtc = intel_get_crtc_for_plane(dev, plane);
1108         if (!intel_crtc_active(crtc)) {
1109                 *cursor_wm = cursor->guard_size;
1110                 *plane_wm = display->guard_size;
1111                 return false;
1112         }
1113
1114         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1115         clock = adjusted_mode->crtc_clock;
1116         htotal = adjusted_mode->crtc_htotal;
1117         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1118         pixel_size = crtc->fb->bits_per_pixel / 8;
1119
1120         /* Use the small buffer method to calculate plane watermark */
1121         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1122         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1123         if (tlb_miss > 0)
1124                 entries += tlb_miss;
1125         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1126         *plane_wm = entries + display->guard_size;
1127         if (*plane_wm > (int)display->max_wm)
1128                 *plane_wm = display->max_wm;
1129
1130         /* Use the large buffer method to calculate cursor watermark */
1131         line_time_us = ((htotal * 1000) / clock);
1132         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1133         entries = line_count * 64 * pixel_size;
1134         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1135         if (tlb_miss > 0)
1136                 entries += tlb_miss;
1137         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1138         *cursor_wm = entries + cursor->guard_size;
1139         if (*cursor_wm > (int)cursor->max_wm)
1140                 *cursor_wm = (int)cursor->max_wm;
1141
1142         return true;
1143 }
1144
1145 /*
1146  * Check the wm result.
1147  *
1148  * If any calculated watermark values is larger than the maximum value that
1149  * can be programmed into the associated watermark register, that watermark
1150  * must be disabled.
1151  */
1152 static bool g4x_check_srwm(struct drm_device *dev,
1153                            int display_wm, int cursor_wm,
1154                            const struct intel_watermark_params *display,
1155                            const struct intel_watermark_params *cursor)
1156 {
1157         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1158                       display_wm, cursor_wm);
1159
1160         if (display_wm > display->max_wm) {
1161                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1162                               display_wm, display->max_wm);
1163                 return false;
1164         }
1165
1166         if (cursor_wm > cursor->max_wm) {
1167                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1168                               cursor_wm, cursor->max_wm);
1169                 return false;
1170         }
1171
1172         if (!(display_wm || cursor_wm)) {
1173                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1174                 return false;
1175         }
1176
1177         return true;
1178 }
1179
1180 static bool g4x_compute_srwm(struct drm_device *dev,
1181                              int plane,
1182                              int latency_ns,
1183                              const struct intel_watermark_params *display,
1184                              const struct intel_watermark_params *cursor,
1185                              int *display_wm, int *cursor_wm)
1186 {
1187         struct drm_crtc *crtc;
1188         const struct drm_display_mode *adjusted_mode;
1189         int hdisplay, htotal, pixel_size, clock;
1190         unsigned long line_time_us;
1191         int line_count, line_size;
1192         int small, large;
1193         int entries;
1194
1195         if (!latency_ns) {
1196                 *display_wm = *cursor_wm = 0;
1197                 return false;
1198         }
1199
1200         crtc = intel_get_crtc_for_plane(dev, plane);
1201         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1202         clock = adjusted_mode->crtc_clock;
1203         htotal = adjusted_mode->crtc_htotal;
1204         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1205         pixel_size = crtc->fb->bits_per_pixel / 8;
1206
1207         line_time_us = (htotal * 1000) / clock;
1208         line_count = (latency_ns / line_time_us + 1000) / 1000;
1209         line_size = hdisplay * pixel_size;
1210
1211         /* Use the minimum of the small and large buffer method for primary */
1212         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1213         large = line_count * line_size;
1214
1215         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1216         *display_wm = entries + display->guard_size;
1217
1218         /* calculate the self-refresh watermark for display cursor */
1219         entries = line_count * pixel_size * 64;
1220         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1221         *cursor_wm = entries + cursor->guard_size;
1222
1223         return g4x_check_srwm(dev,
1224                               *display_wm, *cursor_wm,
1225                               display, cursor);
1226 }
1227
1228 static bool vlv_compute_drain_latency(struct drm_device *dev,
1229                                      int plane,
1230                                      int *plane_prec_mult,
1231                                      int *plane_dl,
1232                                      int *cursor_prec_mult,
1233                                      int *cursor_dl)
1234 {
1235         struct drm_crtc *crtc;
1236         int clock, pixel_size;
1237         int entries;
1238
1239         crtc = intel_get_crtc_for_plane(dev, plane);
1240         if (!intel_crtc_active(crtc))
1241                 return false;
1242
1243         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1244         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1245
1246         entries = (clock / 1000) * pixel_size;
1247         *plane_prec_mult = (entries > 256) ?
1248                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1249         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1250                                                      pixel_size);
1251
1252         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1253         *cursor_prec_mult = (entries > 256) ?
1254                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1256
1257         return true;
1258 }
1259
1260 /*
1261  * Update drain latency registers of memory arbiter
1262  *
1263  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1264  * to be programmed. Each plane has a drain latency multiplier and a drain
1265  * latency value.
1266  */
1267
1268 static void vlv_update_drain_latency(struct drm_device *dev)
1269 {
1270         struct drm_i915_private *dev_priv = dev->dev_private;
1271         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1272         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1273         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1274                                                         either 16 or 32 */
1275
1276         /* For plane A, Cursor A */
1277         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1278                                       &cursor_prec_mult, &cursora_dl)) {
1279                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1280                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1281                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1282                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1283
1284                 I915_WRITE(VLV_DDL1, cursora_prec |
1285                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1286                                 planea_prec | planea_dl);
1287         }
1288
1289         /* For plane B, Cursor B */
1290         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1291                                       &cursor_prec_mult, &cursorb_dl)) {
1292                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1293                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1294                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1295                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1296
1297                 I915_WRITE(VLV_DDL2, cursorb_prec |
1298                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1299                                 planeb_prec | planeb_dl);
1300         }
1301 }
1302
1303 #define single_plane_enabled(mask) is_power_of_2(mask)
1304
1305 static void valleyview_update_wm(struct drm_crtc *crtc)
1306 {
1307         struct drm_device *dev = crtc->dev;
1308         static const int sr_latency_ns = 12000;
1309         struct drm_i915_private *dev_priv = dev->dev_private;
1310         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1311         int plane_sr, cursor_sr;
1312         int ignore_plane_sr, ignore_cursor_sr;
1313         unsigned int enabled = 0;
1314
1315         vlv_update_drain_latency(dev);
1316
1317         if (g4x_compute_wm0(dev, PIPE_A,
1318                             &valleyview_wm_info, latency_ns,
1319                             &valleyview_cursor_wm_info, latency_ns,
1320                             &planea_wm, &cursora_wm))
1321                 enabled |= 1 << PIPE_A;
1322
1323         if (g4x_compute_wm0(dev, PIPE_B,
1324                             &valleyview_wm_info, latency_ns,
1325                             &valleyview_cursor_wm_info, latency_ns,
1326                             &planeb_wm, &cursorb_wm))
1327                 enabled |= 1 << PIPE_B;
1328
1329         if (single_plane_enabled(enabled) &&
1330             g4x_compute_srwm(dev, ffs(enabled) - 1,
1331                              sr_latency_ns,
1332                              &valleyview_wm_info,
1333                              &valleyview_cursor_wm_info,
1334                              &plane_sr, &ignore_cursor_sr) &&
1335             g4x_compute_srwm(dev, ffs(enabled) - 1,
1336                              2*sr_latency_ns,
1337                              &valleyview_wm_info,
1338                              &valleyview_cursor_wm_info,
1339                              &ignore_plane_sr, &cursor_sr)) {
1340                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1341         } else {
1342                 I915_WRITE(FW_BLC_SELF_VLV,
1343                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1344                 plane_sr = cursor_sr = 0;
1345         }
1346
1347         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1348                       planea_wm, cursora_wm,
1349                       planeb_wm, cursorb_wm,
1350                       plane_sr, cursor_sr);
1351
1352         I915_WRITE(DSPFW1,
1353                    (plane_sr << DSPFW_SR_SHIFT) |
1354                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1355                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1356                    planea_wm);
1357         I915_WRITE(DSPFW2,
1358                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1359                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1360         I915_WRITE(DSPFW3,
1361                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1362                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1363 }
1364
1365 static void g4x_update_wm(struct drm_crtc *crtc)
1366 {
1367         struct drm_device *dev = crtc->dev;
1368         static const int sr_latency_ns = 12000;
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371         int plane_sr, cursor_sr;
1372         unsigned int enabled = 0;
1373
1374         if (g4x_compute_wm0(dev, PIPE_A,
1375                             &g4x_wm_info, latency_ns,
1376                             &g4x_cursor_wm_info, latency_ns,
1377                             &planea_wm, &cursora_wm))
1378                 enabled |= 1 << PIPE_A;
1379
1380         if (g4x_compute_wm0(dev, PIPE_B,
1381                             &g4x_wm_info, latency_ns,
1382                             &g4x_cursor_wm_info, latency_ns,
1383                             &planeb_wm, &cursorb_wm))
1384                 enabled |= 1 << PIPE_B;
1385
1386         if (single_plane_enabled(enabled) &&
1387             g4x_compute_srwm(dev, ffs(enabled) - 1,
1388                              sr_latency_ns,
1389                              &g4x_wm_info,
1390                              &g4x_cursor_wm_info,
1391                              &plane_sr, &cursor_sr)) {
1392                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1393         } else {
1394                 I915_WRITE(FW_BLC_SELF,
1395                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1396                 plane_sr = cursor_sr = 0;
1397         }
1398
1399         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1400                       planea_wm, cursora_wm,
1401                       planeb_wm, cursorb_wm,
1402                       plane_sr, cursor_sr);
1403
1404         I915_WRITE(DSPFW1,
1405                    (plane_sr << DSPFW_SR_SHIFT) |
1406                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1407                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1408                    planea_wm);
1409         I915_WRITE(DSPFW2,
1410                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1411                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1412         /* HPLL off in SR has some issues on G4x... disable it */
1413         I915_WRITE(DSPFW3,
1414                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1415                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1416 }
1417
1418 static void i965_update_wm(struct drm_crtc *unused_crtc)
1419 {
1420         struct drm_device *dev = unused_crtc->dev;
1421         struct drm_i915_private *dev_priv = dev->dev_private;
1422         struct drm_crtc *crtc;
1423         int srwm = 1;
1424         int cursor_sr = 16;
1425
1426         /* Calc sr entries for one plane configs */
1427         crtc = single_enabled_crtc(dev);
1428         if (crtc) {
1429                 /* self-refresh has much higher latency */
1430                 static const int sr_latency_ns = 12000;
1431                 const struct drm_display_mode *adjusted_mode =
1432                         &to_intel_crtc(crtc)->config.adjusted_mode;
1433                 int clock = adjusted_mode->crtc_clock;
1434                 int htotal = adjusted_mode->crtc_htotal;
1435                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1436                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1437                 unsigned long line_time_us;
1438                 int entries;
1439
1440                 line_time_us = ((htotal * 1000) / clock);
1441
1442                 /* Use ns/us then divide to preserve precision */
1443                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1444                         pixel_size * hdisplay;
1445                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1446                 srwm = I965_FIFO_SIZE - entries;
1447                 if (srwm < 0)
1448                         srwm = 1;
1449                 srwm &= 0x1ff;
1450                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1451                               entries, srwm);
1452
1453                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1454                         pixel_size * 64;
1455                 entries = DIV_ROUND_UP(entries,
1456                                           i965_cursor_wm_info.cacheline_size);
1457                 cursor_sr = i965_cursor_wm_info.fifo_size -
1458                         (entries + i965_cursor_wm_info.guard_size);
1459
1460                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1461                         cursor_sr = i965_cursor_wm_info.max_wm;
1462
1463                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1464                               "cursor %d\n", srwm, cursor_sr);
1465
1466                 if (IS_CRESTLINE(dev))
1467                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1468         } else {
1469                 /* Turn off self refresh if both pipes are enabled */
1470                 if (IS_CRESTLINE(dev))
1471                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1472                                    & ~FW_BLC_SELF_EN);
1473         }
1474
1475         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1476                       srwm);
1477
1478         /* 965 has limitations... */
1479         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1480                    (8 << 16) | (8 << 8) | (8 << 0));
1481         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1482         /* update cursor SR watermark */
1483         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1484 }
1485
1486 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1487 {
1488         struct drm_device *dev = unused_crtc->dev;
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         const struct intel_watermark_params *wm_info;
1491         uint32_t fwater_lo;
1492         uint32_t fwater_hi;
1493         int cwm, srwm = 1;
1494         int fifo_size;
1495         int planea_wm, planeb_wm;
1496         struct drm_crtc *crtc, *enabled = NULL;
1497
1498         if (IS_I945GM(dev))
1499                 wm_info = &i945_wm_info;
1500         else if (!IS_GEN2(dev))
1501                 wm_info = &i915_wm_info;
1502         else
1503                 wm_info = &i830_wm_info;
1504
1505         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1506         crtc = intel_get_crtc_for_plane(dev, 0);
1507         if (intel_crtc_active(crtc)) {
1508                 const struct drm_display_mode *adjusted_mode;
1509                 int cpp = crtc->fb->bits_per_pixel / 8;
1510                 if (IS_GEN2(dev))
1511                         cpp = 4;
1512
1513                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1514                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1515                                                wm_info, fifo_size, cpp,
1516                                                latency_ns);
1517                 enabled = crtc;
1518         } else
1519                 planea_wm = fifo_size - wm_info->guard_size;
1520
1521         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1522         crtc = intel_get_crtc_for_plane(dev, 1);
1523         if (intel_crtc_active(crtc)) {
1524                 const struct drm_display_mode *adjusted_mode;
1525                 int cpp = crtc->fb->bits_per_pixel / 8;
1526                 if (IS_GEN2(dev))
1527                         cpp = 4;
1528
1529                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1530                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1531                                                wm_info, fifo_size, cpp,
1532                                                latency_ns);
1533                 if (enabled == NULL)
1534                         enabled = crtc;
1535                 else
1536                         enabled = NULL;
1537         } else
1538                 planeb_wm = fifo_size - wm_info->guard_size;
1539
1540         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1541
1542         if (IS_I915GM(dev) && enabled) {
1543                 struct intel_framebuffer *fb;
1544
1545                 fb = to_intel_framebuffer(enabled->fb);
1546
1547                 /* self-refresh seems busted with untiled */
1548                 if (fb->obj->tiling_mode == I915_TILING_NONE)
1549                         enabled = NULL;
1550         }
1551
1552         /*
1553          * Overlay gets an aggressive default since video jitter is bad.
1554          */
1555         cwm = 2;
1556
1557         /* Play safe and disable self-refresh before adjusting watermarks. */
1558         if (IS_I945G(dev) || IS_I945GM(dev))
1559                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1560         else if (IS_I915GM(dev))
1561                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1562
1563         /* Calc sr entries for one plane configs */
1564         if (HAS_FW_BLC(dev) && enabled) {
1565                 /* self-refresh has much higher latency */
1566                 static const int sr_latency_ns = 6000;
1567                 const struct drm_display_mode *adjusted_mode =
1568                         &to_intel_crtc(enabled)->config.adjusted_mode;
1569                 int clock = adjusted_mode->crtc_clock;
1570                 int htotal = adjusted_mode->crtc_htotal;
1571                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1572                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1573                 unsigned long line_time_us;
1574                 int entries;
1575
1576                 line_time_us = (htotal * 1000) / clock;
1577
1578                 /* Use ns/us then divide to preserve precision */
1579                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1580                         pixel_size * hdisplay;
1581                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1582                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1583                 srwm = wm_info->fifo_size - entries;
1584                 if (srwm < 0)
1585                         srwm = 1;
1586
1587                 if (IS_I945G(dev) || IS_I945GM(dev))
1588                         I915_WRITE(FW_BLC_SELF,
1589                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1590                 else if (IS_I915GM(dev))
1591                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1592         }
1593
1594         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1595                       planea_wm, planeb_wm, cwm, srwm);
1596
1597         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1598         fwater_hi = (cwm & 0x1f);
1599
1600         /* Set request length to 8 cachelines per fetch */
1601         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1602         fwater_hi = fwater_hi | (1 << 8);
1603
1604         I915_WRITE(FW_BLC, fwater_lo);
1605         I915_WRITE(FW_BLC2, fwater_hi);
1606
1607         if (HAS_FW_BLC(dev)) {
1608                 if (enabled) {
1609                         if (IS_I945G(dev) || IS_I945GM(dev))
1610                                 I915_WRITE(FW_BLC_SELF,
1611                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1612                         else if (IS_I915GM(dev))
1613                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1614                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1615                 } else
1616                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1617         }
1618 }
1619
1620 static void i845_update_wm(struct drm_crtc *unused_crtc)
1621 {
1622         struct drm_device *dev = unused_crtc->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         struct drm_crtc *crtc;
1625         const struct drm_display_mode *adjusted_mode;
1626         uint32_t fwater_lo;
1627         int planea_wm;
1628
1629         crtc = single_enabled_crtc(dev);
1630         if (crtc == NULL)
1631                 return;
1632
1633         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1634         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1635                                        &i845_wm_info,
1636                                        dev_priv->display.get_fifo_size(dev, 0),
1637                                        4, latency_ns);
1638         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1639         fwater_lo |= (3<<8) | planea_wm;
1640
1641         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1642
1643         I915_WRITE(FW_BLC, fwater_lo);
1644 }
1645
1646 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1647                                     struct drm_crtc *crtc)
1648 {
1649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1650         uint32_t pixel_rate;
1651
1652         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1653
1654         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1655          * adjust the pixel_rate here. */
1656
1657         if (intel_crtc->config.pch_pfit.enabled) {
1658                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1659                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1660
1661                 pipe_w = intel_crtc->config.pipe_src_w;
1662                 pipe_h = intel_crtc->config.pipe_src_h;
1663                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1664                 pfit_h = pfit_size & 0xFFFF;
1665                 if (pipe_w < pfit_w)
1666                         pipe_w = pfit_w;
1667                 if (pipe_h < pfit_h)
1668                         pipe_h = pfit_h;
1669
1670                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1671                                      pfit_w * pfit_h);
1672         }
1673
1674         return pixel_rate;
1675 }
1676
1677 /* latency must be in 0.1us units. */
1678 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1679                                uint32_t latency)
1680 {
1681         uint64_t ret;
1682
1683         if (WARN(latency == 0, "Latency value missing\n"))
1684                 return UINT_MAX;
1685
1686         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1687         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1688
1689         return ret;
1690 }
1691
1692 /* latency must be in 0.1us units. */
1693 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1694                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1695                                uint32_t latency)
1696 {
1697         uint32_t ret;
1698
1699         if (WARN(latency == 0, "Latency value missing\n"))
1700                 return UINT_MAX;
1701
1702         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1703         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1704         ret = DIV_ROUND_UP(ret, 64) + 2;
1705         return ret;
1706 }
1707
1708 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1709                            uint8_t bytes_per_pixel)
1710 {
1711         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1712 }
1713
1714 struct ilk_pipe_wm_parameters {
1715         bool active;
1716         uint32_t pipe_htotal;
1717         uint32_t pixel_rate;
1718         struct intel_plane_wm_parameters pri;
1719         struct intel_plane_wm_parameters spr;
1720         struct intel_plane_wm_parameters cur;
1721 };
1722
1723 struct ilk_wm_maximums {
1724         uint16_t pri;
1725         uint16_t spr;
1726         uint16_t cur;
1727         uint16_t fbc;
1728 };
1729
1730 /* used in computing the new watermarks state */
1731 struct intel_wm_config {
1732         unsigned int num_pipes_active;
1733         bool sprites_enabled;
1734         bool sprites_scaled;
1735 };
1736
1737 /*
1738  * For both WM_PIPE and WM_LP.
1739  * mem_value must be in 0.1us units.
1740  */
1741 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1742                                    uint32_t mem_value,
1743                                    bool is_lp)
1744 {
1745         uint32_t method1, method2;
1746
1747         if (!params->active || !params->pri.enabled)
1748                 return 0;
1749
1750         method1 = ilk_wm_method1(params->pixel_rate,
1751                                  params->pri.bytes_per_pixel,
1752                                  mem_value);
1753
1754         if (!is_lp)
1755                 return method1;
1756
1757         method2 = ilk_wm_method2(params->pixel_rate,
1758                                  params->pipe_htotal,
1759                                  params->pri.horiz_pixels,
1760                                  params->pri.bytes_per_pixel,
1761                                  mem_value);
1762
1763         return min(method1, method2);
1764 }
1765
1766 /*
1767  * For both WM_PIPE and WM_LP.
1768  * mem_value must be in 0.1us units.
1769  */
1770 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1771                                    uint32_t mem_value)
1772 {
1773         uint32_t method1, method2;
1774
1775         if (!params->active || !params->spr.enabled)
1776                 return 0;
1777
1778         method1 = ilk_wm_method1(params->pixel_rate,
1779                                  params->spr.bytes_per_pixel,
1780                                  mem_value);
1781         method2 = ilk_wm_method2(params->pixel_rate,
1782                                  params->pipe_htotal,
1783                                  params->spr.horiz_pixels,
1784                                  params->spr.bytes_per_pixel,
1785                                  mem_value);
1786         return min(method1, method2);
1787 }
1788
1789 /*
1790  * For both WM_PIPE and WM_LP.
1791  * mem_value must be in 0.1us units.
1792  */
1793 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1794                                    uint32_t mem_value)
1795 {
1796         if (!params->active || !params->cur.enabled)
1797                 return 0;
1798
1799         return ilk_wm_method2(params->pixel_rate,
1800                               params->pipe_htotal,
1801                               params->cur.horiz_pixels,
1802                               params->cur.bytes_per_pixel,
1803                               mem_value);
1804 }
1805
1806 /* Only for WM_LP. */
1807 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1808                                    uint32_t pri_val)
1809 {
1810         if (!params->active || !params->pri.enabled)
1811                 return 0;
1812
1813         return ilk_wm_fbc(pri_val,
1814                           params->pri.horiz_pixels,
1815                           params->pri.bytes_per_pixel);
1816 }
1817
1818 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 {
1820         if (INTEL_INFO(dev)->gen >= 8)
1821                 return 3072;
1822         else if (INTEL_INFO(dev)->gen >= 7)
1823                 return 768;
1824         else
1825                 return 512;
1826 }
1827
1828 /* Calculate the maximum primary/sprite plane watermark */
1829 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1830                                      int level,
1831                                      const struct intel_wm_config *config,
1832                                      enum intel_ddb_partitioning ddb_partitioning,
1833                                      bool is_sprite)
1834 {
1835         unsigned int fifo_size = ilk_display_fifo_size(dev);
1836         unsigned int max;
1837
1838         /* if sprites aren't enabled, sprites get nothing */
1839         if (is_sprite && !config->sprites_enabled)
1840                 return 0;
1841
1842         /* HSW allows LP1+ watermarks even with multiple pipes */
1843         if (level == 0 || config->num_pipes_active > 1) {
1844                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1845
1846                 /*
1847                  * For some reason the non self refresh
1848                  * FIFO size is only half of the self
1849                  * refresh FIFO size on ILK/SNB.
1850                  */
1851                 if (INTEL_INFO(dev)->gen <= 6)
1852                         fifo_size /= 2;
1853         }
1854
1855         if (config->sprites_enabled) {
1856                 /* level 0 is always calculated with 1:1 split */
1857                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1858                         if (is_sprite)
1859                                 fifo_size *= 5;
1860                         fifo_size /= 6;
1861                 } else {
1862                         fifo_size /= 2;
1863                 }
1864         }
1865
1866         /* clamp to max that the registers can hold */
1867         if (INTEL_INFO(dev)->gen >= 8)
1868                 max = level == 0 ? 255 : 2047;
1869         else if (INTEL_INFO(dev)->gen >= 7)
1870                 /* IVB/HSW primary/sprite plane watermarks */
1871                 max = level == 0 ? 127 : 1023;
1872         else if (!is_sprite)
1873                 /* ILK/SNB primary plane watermarks */
1874                 max = level == 0 ? 127 : 511;
1875         else
1876                 /* ILK/SNB sprite plane watermarks */
1877                 max = level == 0 ? 63 : 255;
1878
1879         return min(fifo_size, max);
1880 }
1881
1882 /* Calculate the maximum cursor plane watermark */
1883 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1884                                       int level,
1885                                       const struct intel_wm_config *config)
1886 {
1887         /* HSW LP1+ watermarks w/ multiple pipes */
1888         if (level > 0 && config->num_pipes_active > 1)
1889                 return 64;
1890
1891         /* otherwise just report max that registers can hold */
1892         if (INTEL_INFO(dev)->gen >= 7)
1893                 return level == 0 ? 63 : 255;
1894         else
1895                 return level == 0 ? 31 : 63;
1896 }
1897
1898 /* Calculate the maximum FBC watermark */
1899 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
1900 {
1901         /* max that registers can hold */
1902         if (INTEL_INFO(dev)->gen >= 8)
1903                 return 31;
1904         else
1905                 return 15;
1906 }
1907
1908 static void ilk_compute_wm_maximums(struct drm_device *dev,
1909                                     int level,
1910                                     const struct intel_wm_config *config,
1911                                     enum intel_ddb_partitioning ddb_partitioning,
1912                                     struct ilk_wm_maximums *max)
1913 {
1914         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1915         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1916         max->cur = ilk_cursor_wm_max(dev, level, config);
1917         max->fbc = ilk_fbc_wm_max(dev);
1918 }
1919
1920 static bool ilk_validate_wm_level(int level,
1921                                   const struct ilk_wm_maximums *max,
1922                                   struct intel_wm_level *result)
1923 {
1924         bool ret;
1925
1926         /* already determined to be invalid? */
1927         if (!result->enable)
1928                 return false;
1929
1930         result->enable = result->pri_val <= max->pri &&
1931                          result->spr_val <= max->spr &&
1932                          result->cur_val <= max->cur;
1933
1934         ret = result->enable;
1935
1936         /*
1937          * HACK until we can pre-compute everything,
1938          * and thus fail gracefully if LP0 watermarks
1939          * are exceeded...
1940          */
1941         if (level == 0 && !result->enable) {
1942                 if (result->pri_val > max->pri)
1943                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1944                                       level, result->pri_val, max->pri);
1945                 if (result->spr_val > max->spr)
1946                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1947                                       level, result->spr_val, max->spr);
1948                 if (result->cur_val > max->cur)
1949                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1950                                       level, result->cur_val, max->cur);
1951
1952                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1953                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1954                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1955                 result->enable = true;
1956         }
1957
1958         return ret;
1959 }
1960
1961 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
1962                                  int level,
1963                                  const struct ilk_pipe_wm_parameters *p,
1964                                  struct intel_wm_level *result)
1965 {
1966         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1967         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1968         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1969
1970         /* WM1+ latency values stored in 0.5us units */
1971         if (level > 0) {
1972                 pri_latency *= 5;
1973                 spr_latency *= 5;
1974                 cur_latency *= 5;
1975         }
1976
1977         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1978         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1979         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1980         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1981         result->enable = true;
1982 }
1983
1984 static uint32_t
1985 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1986 {
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1990         u32 linetime, ips_linetime;
1991
1992         if (!intel_crtc_active(crtc))
1993                 return 0;
1994
1995         /* The WM are computed with base on how long it takes to fill a single
1996          * row at the given clock rate, multiplied by 8.
1997          * */
1998         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1999                                      mode->crtc_clock);
2000         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2001                                          intel_ddi_get_cdclk_freq(dev_priv));
2002
2003         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2004                PIPE_WM_LINETIME_TIME(linetime);
2005 }
2006
2007 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2008 {
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010
2011         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2012                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2013
2014                 wm[0] = (sskpd >> 56) & 0xFF;
2015                 if (wm[0] == 0)
2016                         wm[0] = sskpd & 0xF;
2017                 wm[1] = (sskpd >> 4) & 0xFF;
2018                 wm[2] = (sskpd >> 12) & 0xFF;
2019                 wm[3] = (sskpd >> 20) & 0x1FF;
2020                 wm[4] = (sskpd >> 32) & 0x1FF;
2021         } else if (INTEL_INFO(dev)->gen >= 6) {
2022                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2023
2024                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2025                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2026                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2027                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2028         } else if (INTEL_INFO(dev)->gen >= 5) {
2029                 uint32_t mltr = I915_READ(MLTR_ILK);
2030
2031                 /* ILK primary LP0 latency is 700 ns */
2032                 wm[0] = 7;
2033                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2034                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2035         }
2036 }
2037
2038 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2039 {
2040         /* ILK sprite LP0 latency is 1300 ns */
2041         if (INTEL_INFO(dev)->gen == 5)
2042                 wm[0] = 13;
2043 }
2044
2045 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2046 {
2047         /* ILK cursor LP0 latency is 1300 ns */
2048         if (INTEL_INFO(dev)->gen == 5)
2049                 wm[0] = 13;
2050
2051         /* WaDoubleCursorLP3Latency:ivb */
2052         if (IS_IVYBRIDGE(dev))
2053                 wm[3] *= 2;
2054 }
2055
2056 static int ilk_wm_max_level(const struct drm_device *dev)
2057 {
2058         /* how many WM levels are we expecting */
2059         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2060                 return 4;
2061         else if (INTEL_INFO(dev)->gen >= 6)
2062                 return 3;
2063         else
2064                 return 2;
2065 }
2066
2067 static void intel_print_wm_latency(struct drm_device *dev,
2068                                    const char *name,
2069                                    const uint16_t wm[5])
2070 {
2071         int level, max_level = ilk_wm_max_level(dev);
2072
2073         for (level = 0; level <= max_level; level++) {
2074                 unsigned int latency = wm[level];
2075
2076                 if (latency == 0) {
2077                         DRM_ERROR("%s WM%d latency not provided\n",
2078                                   name, level);
2079                         continue;
2080                 }
2081
2082                 /* WM1+ latency values in 0.5us units */
2083                 if (level > 0)
2084                         latency *= 5;
2085
2086                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2087                               name, level, wm[level],
2088                               latency / 10, latency % 10);
2089         }
2090 }
2091
2092 static void intel_setup_wm_latency(struct drm_device *dev)
2093 {
2094         struct drm_i915_private *dev_priv = dev->dev_private;
2095
2096         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2097
2098         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2099                sizeof(dev_priv->wm.pri_latency));
2100         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2101                sizeof(dev_priv->wm.pri_latency));
2102
2103         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2104         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2105
2106         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2107         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2108         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2109 }
2110
2111 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2112                                       struct ilk_pipe_wm_parameters *p,
2113                                       struct intel_wm_config *config)
2114 {
2115         struct drm_device *dev = crtc->dev;
2116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2117         enum pipe pipe = intel_crtc->pipe;
2118         struct drm_plane *plane;
2119
2120         p->active = intel_crtc_active(crtc);
2121         if (p->active) {
2122                 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2123                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2124                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2125                 p->cur.bytes_per_pixel = 4;
2126                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2127                 p->cur.horiz_pixels = 64;
2128                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2129                 p->pri.enabled = true;
2130                 p->cur.enabled = true;
2131         }
2132
2133         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2134                 config->num_pipes_active += intel_crtc_active(crtc);
2135
2136         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2137                 struct intel_plane *intel_plane = to_intel_plane(plane);
2138
2139                 if (intel_plane->pipe == pipe)
2140                         p->spr = intel_plane->wm;
2141
2142                 config->sprites_enabled |= intel_plane->wm.enabled;
2143                 config->sprites_scaled |= intel_plane->wm.scaled;
2144         }
2145 }
2146
2147 /* Compute new watermarks for the pipe */
2148 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2149                                   const struct ilk_pipe_wm_parameters *params,
2150                                   struct intel_pipe_wm *pipe_wm)
2151 {
2152         struct drm_device *dev = crtc->dev;
2153         struct drm_i915_private *dev_priv = dev->dev_private;
2154         int level, max_level = ilk_wm_max_level(dev);
2155         /* LP0 watermark maximums depend on this pipe alone */
2156         struct intel_wm_config config = {
2157                 .num_pipes_active = 1,
2158                 .sprites_enabled = params->spr.enabled,
2159                 .sprites_scaled = params->spr.scaled,
2160         };
2161         struct ilk_wm_maximums max;
2162
2163         /* LP0 watermarks always use 1/2 DDB partitioning */
2164         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2165
2166         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2167         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2168                 max_level = 1;
2169
2170         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2171         if (params->spr.scaled)
2172                 max_level = 0;
2173
2174         for (level = 0; level <= max_level; level++)
2175                 ilk_compute_wm_level(dev_priv, level, params,
2176                                      &pipe_wm->wm[level]);
2177
2178         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2179                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2180
2181         /* At least LP0 must be valid */
2182         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2183 }
2184
2185 /*
2186  * Merge the watermarks from all active pipes for a specific level.
2187  */
2188 static void ilk_merge_wm_level(struct drm_device *dev,
2189                                int level,
2190                                struct intel_wm_level *ret_wm)
2191 {
2192         const struct intel_crtc *intel_crtc;
2193
2194         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2195                 const struct intel_wm_level *wm =
2196                         &intel_crtc->wm.active.wm[level];
2197
2198                 if (!wm->enable)
2199                         return;
2200
2201                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2202                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2203                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2204                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2205         }
2206
2207         ret_wm->enable = true;
2208 }
2209
2210 /*
2211  * Merge all low power watermarks for all active pipes.
2212  */
2213 static void ilk_wm_merge(struct drm_device *dev,
2214                          const struct intel_wm_config *config,
2215                          const struct ilk_wm_maximums *max,
2216                          struct intel_pipe_wm *merged)
2217 {
2218         int level, max_level = ilk_wm_max_level(dev);
2219
2220         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2221         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2222             config->num_pipes_active > 1)
2223                 return;
2224
2225         /* ILK: FBC WM must be disabled always */
2226         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2227
2228         /* merge each WM1+ level */
2229         for (level = 1; level <= max_level; level++) {
2230                 struct intel_wm_level *wm = &merged->wm[level];
2231
2232                 ilk_merge_wm_level(dev, level, wm);
2233
2234                 if (!ilk_validate_wm_level(level, max, wm))
2235                         break;
2236
2237                 /*
2238                  * The spec says it is preferred to disable
2239                  * FBC WMs instead of disabling a WM level.
2240                  */
2241                 if (wm->fbc_val > max->fbc) {
2242                         merged->fbc_wm_enabled = false;
2243                         wm->fbc_val = 0;
2244                 }
2245         }
2246
2247         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2248         /*
2249          * FIXME this is racy. FBC might get enabled later.
2250          * What we should check here is whether FBC can be
2251          * enabled sometime later.
2252          */
2253         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2254                 for (level = 2; level <= max_level; level++) {
2255                         struct intel_wm_level *wm = &merged->wm[level];
2256
2257                         wm->enable = false;
2258                 }
2259         }
2260 }
2261
2262 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2263 {
2264         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2265         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2266 }
2267
2268 /* The value we need to program into the WM_LPx latency field */
2269 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2270 {
2271         struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2274                 return 2 * level;
2275         else
2276                 return dev_priv->wm.pri_latency[level];
2277 }
2278
2279 static void ilk_compute_wm_results(struct drm_device *dev,
2280                                    const struct intel_pipe_wm *merged,
2281                                    enum intel_ddb_partitioning partitioning,
2282                                    struct ilk_wm_values *results)
2283 {
2284         struct intel_crtc *intel_crtc;
2285         int level, wm_lp;
2286
2287         results->enable_fbc_wm = merged->fbc_wm_enabled;
2288         results->partitioning = partitioning;
2289
2290         /* LP1+ register values */
2291         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2292                 const struct intel_wm_level *r;
2293
2294                 level = ilk_wm_lp_to_level(wm_lp, merged);
2295
2296                 r = &merged->wm[level];
2297                 if (!r->enable)
2298                         break;
2299
2300                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2301                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2302                         (r->pri_val << WM1_LP_SR_SHIFT) |
2303                         r->cur_val;
2304
2305                 if (INTEL_INFO(dev)->gen >= 8)
2306                         results->wm_lp[wm_lp - 1] |=
2307                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2308                 else
2309                         results->wm_lp[wm_lp - 1] |=
2310                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2311
2312                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2313                         WARN_ON(wm_lp != 1);
2314                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2315                 } else
2316                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2317         }
2318
2319         /* LP0 register values */
2320         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2321                 enum pipe pipe = intel_crtc->pipe;
2322                 const struct intel_wm_level *r =
2323                         &intel_crtc->wm.active.wm[0];
2324
2325                 if (WARN_ON(!r->enable))
2326                         continue;
2327
2328                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2329
2330                 results->wm_pipe[pipe] =
2331                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2332                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2333                         r->cur_val;
2334         }
2335 }
2336
2337 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2338  * case both are at the same level. Prefer r1 in case they're the same. */
2339 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2340                                                   struct intel_pipe_wm *r1,
2341                                                   struct intel_pipe_wm *r2)
2342 {
2343         int level, max_level = ilk_wm_max_level(dev);
2344         int level1 = 0, level2 = 0;
2345
2346         for (level = 1; level <= max_level; level++) {
2347                 if (r1->wm[level].enable)
2348                         level1 = level;
2349                 if (r2->wm[level].enable)
2350                         level2 = level;
2351         }
2352
2353         if (level1 == level2) {
2354                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2355                         return r2;
2356                 else
2357                         return r1;
2358         } else if (level1 > level2) {
2359                 return r1;
2360         } else {
2361                 return r2;
2362         }
2363 }
2364
2365 /* dirty bits used to track which watermarks need changes */
2366 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2367 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2368 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2369 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2370 #define WM_DIRTY_FBC (1 << 24)
2371 #define WM_DIRTY_DDB (1 << 25)
2372
2373 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2374                                          const struct ilk_wm_values *old,
2375                                          const struct ilk_wm_values *new)
2376 {
2377         unsigned int dirty = 0;
2378         enum pipe pipe;
2379         int wm_lp;
2380
2381         for_each_pipe(pipe) {
2382                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2383                         dirty |= WM_DIRTY_LINETIME(pipe);
2384                         /* Must disable LP1+ watermarks too */
2385                         dirty |= WM_DIRTY_LP_ALL;
2386                 }
2387
2388                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2389                         dirty |= WM_DIRTY_PIPE(pipe);
2390                         /* Must disable LP1+ watermarks too */
2391                         dirty |= WM_DIRTY_LP_ALL;
2392                 }
2393         }
2394
2395         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2396                 dirty |= WM_DIRTY_FBC;
2397                 /* Must disable LP1+ watermarks too */
2398                 dirty |= WM_DIRTY_LP_ALL;
2399         }
2400
2401         if (old->partitioning != new->partitioning) {
2402                 dirty |= WM_DIRTY_DDB;
2403                 /* Must disable LP1+ watermarks too */
2404                 dirty |= WM_DIRTY_LP_ALL;
2405         }
2406
2407         /* LP1+ watermarks already deemed dirty, no need to continue */
2408         if (dirty & WM_DIRTY_LP_ALL)
2409                 return dirty;
2410
2411         /* Find the lowest numbered LP1+ watermark in need of an update... */
2412         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2413                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2414                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2415                         break;
2416         }
2417
2418         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2419         for (; wm_lp <= 3; wm_lp++)
2420                 dirty |= WM_DIRTY_LP(wm_lp);
2421
2422         return dirty;
2423 }
2424
2425 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2426                                unsigned int dirty)
2427 {
2428         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2429         bool changed = false;
2430
2431         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2432                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2433                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2434                 changed = true;
2435         }
2436         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2437                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2438                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2439                 changed = true;
2440         }
2441         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2442                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2443                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2444                 changed = true;
2445         }
2446
2447         /*
2448          * Don't touch WM1S_LP_EN here.
2449          * Doing so could cause underruns.
2450          */
2451
2452         return changed;
2453 }
2454
2455 /*
2456  * The spec says we shouldn't write when we don't need, because every write
2457  * causes WMs to be re-evaluated, expending some power.
2458  */
2459 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2460                                 struct ilk_wm_values *results)
2461 {
2462         struct drm_device *dev = dev_priv->dev;
2463         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2464         unsigned int dirty;
2465         uint32_t val;
2466
2467         dirty = ilk_compute_wm_dirty(dev, previous, results);
2468         if (!dirty)
2469                 return;
2470
2471         _ilk_disable_lp_wm(dev_priv, dirty);
2472
2473         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2474                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2475         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2476                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2477         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2478                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2479
2480         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2481                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2482         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2483                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2484         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2485                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2486
2487         if (dirty & WM_DIRTY_DDB) {
2488                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2489                         val = I915_READ(WM_MISC);
2490                         if (results->partitioning == INTEL_DDB_PART_1_2)
2491                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2492                         else
2493                                 val |= WM_MISC_DATA_PARTITION_5_6;
2494                         I915_WRITE(WM_MISC, val);
2495                 } else {
2496                         val = I915_READ(DISP_ARB_CTL2);
2497                         if (results->partitioning == INTEL_DDB_PART_1_2)
2498                                 val &= ~DISP_DATA_PARTITION_5_6;
2499                         else
2500                                 val |= DISP_DATA_PARTITION_5_6;
2501                         I915_WRITE(DISP_ARB_CTL2, val);
2502                 }
2503         }
2504
2505         if (dirty & WM_DIRTY_FBC) {
2506                 val = I915_READ(DISP_ARB_CTL);
2507                 if (results->enable_fbc_wm)
2508                         val &= ~DISP_FBC_WM_DIS;
2509                 else
2510                         val |= DISP_FBC_WM_DIS;
2511                 I915_WRITE(DISP_ARB_CTL, val);
2512         }
2513
2514         if (dirty & WM_DIRTY_LP(1) &&
2515             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2516                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2517
2518         if (INTEL_INFO(dev)->gen >= 7) {
2519                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2520                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2521                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2522                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2523         }
2524
2525         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2526                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2527         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2528                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2529         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2530                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2531
2532         dev_priv->wm.hw = *results;
2533 }
2534
2535 static bool ilk_disable_lp_wm(struct drm_device *dev)
2536 {
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538
2539         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2540 }
2541
2542 static void ilk_update_wm(struct drm_crtc *crtc)
2543 {
2544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545         struct drm_device *dev = crtc->dev;
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         struct ilk_wm_maximums max;
2548         struct ilk_pipe_wm_parameters params = {};
2549         struct ilk_wm_values results = {};
2550         enum intel_ddb_partitioning partitioning;
2551         struct intel_pipe_wm pipe_wm = {};
2552         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2553         struct intel_wm_config config = {};
2554
2555         ilk_compute_wm_parameters(crtc, &params, &config);
2556
2557         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2558
2559         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2560                 return;
2561
2562         intel_crtc->wm.active = pipe_wm;
2563
2564         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2565         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2566
2567         /* 5/6 split only in single pipe config on IVB+ */
2568         if (INTEL_INFO(dev)->gen >= 7 &&
2569             config.num_pipes_active == 1 && config.sprites_enabled) {
2570                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2571                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2572
2573                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2574         } else {
2575                 best_lp_wm = &lp_wm_1_2;
2576         }
2577
2578         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2579                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2580
2581         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2582
2583         ilk_write_wm_values(dev_priv, &results);
2584 }
2585
2586 static void ilk_update_sprite_wm(struct drm_plane *plane,
2587                                      struct drm_crtc *crtc,
2588                                      uint32_t sprite_width, int pixel_size,
2589                                      bool enabled, bool scaled)
2590 {
2591         struct drm_device *dev = plane->dev;
2592         struct intel_plane *intel_plane = to_intel_plane(plane);
2593
2594         intel_plane->wm.enabled = enabled;
2595         intel_plane->wm.scaled = scaled;
2596         intel_plane->wm.horiz_pixels = sprite_width;
2597         intel_plane->wm.bytes_per_pixel = pixel_size;
2598
2599         /*
2600          * IVB workaround: must disable low power watermarks for at least
2601          * one frame before enabling scaling.  LP watermarks can be re-enabled
2602          * when scaling is disabled.
2603          *
2604          * WaCxSRDisabledForSpriteScaling:ivb
2605          */
2606         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2607                 intel_wait_for_vblank(dev, intel_plane->pipe);
2608
2609         ilk_update_wm(crtc);
2610 }
2611
2612 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2613 {
2614         struct drm_device *dev = crtc->dev;
2615         struct drm_i915_private *dev_priv = dev->dev_private;
2616         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2619         enum pipe pipe = intel_crtc->pipe;
2620         static const unsigned int wm0_pipe_reg[] = {
2621                 [PIPE_A] = WM0_PIPEA_ILK,
2622                 [PIPE_B] = WM0_PIPEB_ILK,
2623                 [PIPE_C] = WM0_PIPEC_IVB,
2624         };
2625
2626         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2627         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2628                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2629
2630         if (intel_crtc_active(crtc)) {
2631                 u32 tmp = hw->wm_pipe[pipe];
2632
2633                 /*
2634                  * For active pipes LP0 watermark is marked as
2635                  * enabled, and LP1+ watermaks as disabled since
2636                  * we can't really reverse compute them in case
2637                  * multiple pipes are active.
2638                  */
2639                 active->wm[0].enable = true;
2640                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2641                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2642                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2643                 active->linetime = hw->wm_linetime[pipe];
2644         } else {
2645                 int level, max_level = ilk_wm_max_level(dev);
2646
2647                 /*
2648                  * For inactive pipes, all watermark levels
2649                  * should be marked as enabled but zeroed,
2650                  * which is what we'd compute them to.
2651                  */
2652                 for (level = 0; level <= max_level; level++)
2653                         active->wm[level].enable = true;
2654         }
2655 }
2656
2657 void ilk_wm_get_hw_state(struct drm_device *dev)
2658 {
2659         struct drm_i915_private *dev_priv = dev->dev_private;
2660         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2661         struct drm_crtc *crtc;
2662
2663         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2664                 ilk_pipe_wm_get_hw_state(crtc);
2665
2666         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2667         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2668         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2669
2670         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2671         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2672         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2673
2674         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2675                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2676                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2677         else if (IS_IVYBRIDGE(dev))
2678                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2679                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2680
2681         hw->enable_fbc_wm =
2682                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2683 }
2684
2685 /**
2686  * intel_update_watermarks - update FIFO watermark values based on current modes
2687  *
2688  * Calculate watermark values for the various WM regs based on current mode
2689  * and plane configuration.
2690  *
2691  * There are several cases to deal with here:
2692  *   - normal (i.e. non-self-refresh)
2693  *   - self-refresh (SR) mode
2694  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2695  *   - lines are small relative to FIFO size (buffer can hold more than 2
2696  *     lines), so need to account for TLB latency
2697  *
2698  *   The normal calculation is:
2699  *     watermark = dotclock * bytes per pixel * latency
2700  *   where latency is platform & configuration dependent (we assume pessimal
2701  *   values here).
2702  *
2703  *   The SR calculation is:
2704  *     watermark = (trunc(latency/line time)+1) * surface width *
2705  *       bytes per pixel
2706  *   where
2707  *     line time = htotal / dotclock
2708  *     surface width = hdisplay for normal plane and 64 for cursor
2709  *   and latency is assumed to be high, as above.
2710  *
2711  * The final value programmed to the register should always be rounded up,
2712  * and include an extra 2 entries to account for clock crossings.
2713  *
2714  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2715  * to set the non-SR watermarks to 8.
2716  */
2717 void intel_update_watermarks(struct drm_crtc *crtc)
2718 {
2719         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2720
2721         if (dev_priv->display.update_wm)
2722                 dev_priv->display.update_wm(crtc);
2723 }
2724
2725 void intel_update_sprite_watermarks(struct drm_plane *plane,
2726                                     struct drm_crtc *crtc,
2727                                     uint32_t sprite_width, int pixel_size,
2728                                     bool enabled, bool scaled)
2729 {
2730         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2731
2732         if (dev_priv->display.update_sprite_wm)
2733                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2734                                                    pixel_size, enabled, scaled);
2735 }
2736
2737 static struct drm_i915_gem_object *
2738 intel_alloc_context_page(struct drm_device *dev)
2739 {
2740         struct drm_i915_gem_object *ctx;
2741         int ret;
2742
2743         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2744
2745         ctx = i915_gem_alloc_object(dev, 4096);
2746         if (!ctx) {
2747                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2748                 return NULL;
2749         }
2750
2751         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2752         if (ret) {
2753                 DRM_ERROR("failed to pin power context: %d\n", ret);
2754                 goto err_unref;
2755         }
2756
2757         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2758         if (ret) {
2759                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2760                 goto err_unpin;
2761         }
2762
2763         return ctx;
2764
2765 err_unpin:
2766         i915_gem_object_unpin(ctx);
2767 err_unref:
2768         drm_gem_object_unreference(&ctx->base);
2769         return NULL;
2770 }
2771
2772 /**
2773  * Lock protecting IPS related data structures
2774  */
2775 DEFINE_SPINLOCK(mchdev_lock);
2776
2777 /* Global for IPS driver to get at the current i915 device. Protected by
2778  * mchdev_lock. */
2779 static struct drm_i915_private *i915_mch_dev;
2780
2781 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         u16 rgvswctl;
2785
2786         assert_spin_locked(&mchdev_lock);
2787
2788         rgvswctl = I915_READ16(MEMSWCTL);
2789         if (rgvswctl & MEMCTL_CMD_STS) {
2790                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2791                 return false; /* still busy with another command */
2792         }
2793
2794         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2795                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2796         I915_WRITE16(MEMSWCTL, rgvswctl);
2797         POSTING_READ16(MEMSWCTL);
2798
2799         rgvswctl |= MEMCTL_CMD_STS;
2800         I915_WRITE16(MEMSWCTL, rgvswctl);
2801
2802         return true;
2803 }
2804
2805 static void ironlake_enable_drps(struct drm_device *dev)
2806 {
2807         struct drm_i915_private *dev_priv = dev->dev_private;
2808         u32 rgvmodectl = I915_READ(MEMMODECTL);
2809         u8 fmax, fmin, fstart, vstart;
2810
2811         spin_lock_irq(&mchdev_lock);
2812
2813         /* Enable temp reporting */
2814         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2815         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2816
2817         /* 100ms RC evaluation intervals */
2818         I915_WRITE(RCUPEI, 100000);
2819         I915_WRITE(RCDNEI, 100000);
2820
2821         /* Set max/min thresholds to 90ms and 80ms respectively */
2822         I915_WRITE(RCBMAXAVG, 90000);
2823         I915_WRITE(RCBMINAVG, 80000);
2824
2825         I915_WRITE(MEMIHYST, 1);
2826
2827         /* Set up min, max, and cur for interrupt handling */
2828         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2829         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2830         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2831                 MEMMODE_FSTART_SHIFT;
2832
2833         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2834                 PXVFREQ_PX_SHIFT;
2835
2836         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2837         dev_priv->ips.fstart = fstart;
2838
2839         dev_priv->ips.max_delay = fstart;
2840         dev_priv->ips.min_delay = fmin;
2841         dev_priv->ips.cur_delay = fstart;
2842
2843         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2844                          fmax, fmin, fstart);
2845
2846         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2847
2848         /*
2849          * Interrupts will be enabled in ironlake_irq_postinstall
2850          */
2851
2852         I915_WRITE(VIDSTART, vstart);
2853         POSTING_READ(VIDSTART);
2854
2855         rgvmodectl |= MEMMODE_SWMODE_EN;
2856         I915_WRITE(MEMMODECTL, rgvmodectl);
2857
2858         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2859                 DRM_ERROR("stuck trying to change perf mode\n");
2860         mdelay(1);
2861
2862         ironlake_set_drps(dev, fstart);
2863
2864         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2865                 I915_READ(0x112e0);
2866         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2867         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2868         getrawmonotonic(&dev_priv->ips.last_time2);
2869
2870         spin_unlock_irq(&mchdev_lock);
2871 }
2872
2873 static void ironlake_disable_drps(struct drm_device *dev)
2874 {
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         u16 rgvswctl;
2877
2878         spin_lock_irq(&mchdev_lock);
2879
2880         rgvswctl = I915_READ16(MEMSWCTL);
2881
2882         /* Ack interrupts, disable EFC interrupt */
2883         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2884         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2885         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2886         I915_WRITE(DEIIR, DE_PCU_EVENT);
2887         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2888
2889         /* Go back to the starting frequency */
2890         ironlake_set_drps(dev, dev_priv->ips.fstart);
2891         mdelay(1);
2892         rgvswctl |= MEMCTL_CMD_STS;
2893         I915_WRITE(MEMSWCTL, rgvswctl);
2894         mdelay(1);
2895
2896         spin_unlock_irq(&mchdev_lock);
2897 }
2898
2899 /* There's a funny hw issue where the hw returns all 0 when reading from
2900  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2901  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2902  * all limits and the gpu stuck at whatever frequency it is at atm).
2903  */
2904 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2905 {
2906         u32 limits;
2907
2908         /* Only set the down limit when we've reached the lowest level to avoid
2909          * getting more interrupts, otherwise leave this clear. This prevents a
2910          * race in the hw when coming out of rc6: There's a tiny window where
2911          * the hw runs at the minimal clock before selecting the desired
2912          * frequency, if the down threshold expires in that window we will not
2913          * receive a down interrupt. */
2914         limits = dev_priv->rps.max_delay << 24;
2915         if (val <= dev_priv->rps.min_delay)
2916                 limits |= dev_priv->rps.min_delay << 16;
2917
2918         return limits;
2919 }
2920
2921 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2922 {
2923         int new_power;
2924
2925         new_power = dev_priv->rps.power;
2926         switch (dev_priv->rps.power) {
2927         case LOW_POWER:
2928                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2929                         new_power = BETWEEN;
2930                 break;
2931
2932         case BETWEEN:
2933                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2934                         new_power = LOW_POWER;
2935                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2936                         new_power = HIGH_POWER;
2937                 break;
2938
2939         case HIGH_POWER:
2940                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2941                         new_power = BETWEEN;
2942                 break;
2943         }
2944         /* Max/min bins are special */
2945         if (val == dev_priv->rps.min_delay)
2946                 new_power = LOW_POWER;
2947         if (val == dev_priv->rps.max_delay)
2948                 new_power = HIGH_POWER;
2949         if (new_power == dev_priv->rps.power)
2950                 return;
2951
2952         /* Note the units here are not exactly 1us, but 1280ns. */
2953         switch (new_power) {
2954         case LOW_POWER:
2955                 /* Upclock if more than 95% busy over 16ms */
2956                 I915_WRITE(GEN6_RP_UP_EI, 12500);
2957                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2958
2959                 /* Downclock if less than 85% busy over 32ms */
2960                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2961                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2962
2963                 I915_WRITE(GEN6_RP_CONTROL,
2964                            GEN6_RP_MEDIA_TURBO |
2965                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2966                            GEN6_RP_MEDIA_IS_GFX |
2967                            GEN6_RP_ENABLE |
2968                            GEN6_RP_UP_BUSY_AVG |
2969                            GEN6_RP_DOWN_IDLE_AVG);
2970                 break;
2971
2972         case BETWEEN:
2973                 /* Upclock if more than 90% busy over 13ms */
2974                 I915_WRITE(GEN6_RP_UP_EI, 10250);
2975                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2976
2977                 /* Downclock if less than 75% busy over 32ms */
2978                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2979                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2980
2981                 I915_WRITE(GEN6_RP_CONTROL,
2982                            GEN6_RP_MEDIA_TURBO |
2983                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2984                            GEN6_RP_MEDIA_IS_GFX |
2985                            GEN6_RP_ENABLE |
2986                            GEN6_RP_UP_BUSY_AVG |
2987                            GEN6_RP_DOWN_IDLE_AVG);
2988                 break;
2989
2990         case HIGH_POWER:
2991                 /* Upclock if more than 85% busy over 10ms */
2992                 I915_WRITE(GEN6_RP_UP_EI, 8000);
2993                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2994
2995                 /* Downclock if less than 60% busy over 32ms */
2996                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2997                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
2998
2999                 I915_WRITE(GEN6_RP_CONTROL,
3000                            GEN6_RP_MEDIA_TURBO |
3001                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3002                            GEN6_RP_MEDIA_IS_GFX |
3003                            GEN6_RP_ENABLE |
3004                            GEN6_RP_UP_BUSY_AVG |
3005                            GEN6_RP_DOWN_IDLE_AVG);
3006                 break;
3007         }
3008
3009         dev_priv->rps.power = new_power;
3010         dev_priv->rps.last_adj = 0;
3011 }
3012
3013 void gen6_set_rps(struct drm_device *dev, u8 val)
3014 {
3015         struct drm_i915_private *dev_priv = dev->dev_private;
3016
3017         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3018         WARN_ON(val > dev_priv->rps.max_delay);
3019         WARN_ON(val < dev_priv->rps.min_delay);
3020
3021         if (val == dev_priv->rps.cur_delay)
3022                 return;
3023
3024         gen6_set_rps_thresholds(dev_priv, val);
3025
3026         if (IS_HASWELL(dev))
3027                 I915_WRITE(GEN6_RPNSWREQ,
3028                            HSW_FREQUENCY(val));
3029         else
3030                 I915_WRITE(GEN6_RPNSWREQ,
3031                            GEN6_FREQUENCY(val) |
3032                            GEN6_OFFSET(0) |
3033                            GEN6_AGGRESSIVE_TURBO);
3034
3035         /* Make sure we continue to get interrupts
3036          * until we hit the minimum or maximum frequencies.
3037          */
3038         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3039                    gen6_rps_limits(dev_priv, val));
3040
3041         POSTING_READ(GEN6_RPNSWREQ);
3042
3043         dev_priv->rps.cur_delay = val;
3044
3045         trace_intel_gpu_freq_change(val * 50);
3046 }
3047
3048 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3049 {
3050         struct drm_device *dev = dev_priv->dev;
3051
3052         mutex_lock(&dev_priv->rps.hw_lock);
3053         if (dev_priv->rps.enabled) {
3054                 if (IS_VALLEYVIEW(dev))
3055                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3056                 else
3057                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3058                 dev_priv->rps.last_adj = 0;
3059         }
3060         mutex_unlock(&dev_priv->rps.hw_lock);
3061 }
3062
3063 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3064 {
3065         struct drm_device *dev = dev_priv->dev;
3066
3067         mutex_lock(&dev_priv->rps.hw_lock);
3068         if (dev_priv->rps.enabled) {
3069                 if (IS_VALLEYVIEW(dev))
3070                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3071                 else
3072                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3073                 dev_priv->rps.last_adj = 0;
3074         }
3075         mutex_unlock(&dev_priv->rps.hw_lock);
3076 }
3077
3078 void valleyview_set_rps(struct drm_device *dev, u8 val)
3079 {
3080         struct drm_i915_private *dev_priv = dev->dev_private;
3081
3082         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3083         WARN_ON(val > dev_priv->rps.max_delay);
3084         WARN_ON(val < dev_priv->rps.min_delay);
3085
3086         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3087                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3088                          dev_priv->rps.cur_delay,
3089                          vlv_gpu_freq(dev_priv, val), val);
3090
3091         if (val == dev_priv->rps.cur_delay)
3092                 return;
3093
3094         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3095
3096         dev_priv->rps.cur_delay = val;
3097
3098         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3099 }
3100
3101 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3102 {
3103         struct drm_i915_private *dev_priv = dev->dev_private;
3104
3105         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3106         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3107         /* Complete PM interrupt masking here doesn't race with the rps work
3108          * item again unmasking PM interrupts because that is using a different
3109          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3110          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3111
3112         spin_lock_irq(&dev_priv->irq_lock);
3113         dev_priv->rps.pm_iir = 0;
3114         spin_unlock_irq(&dev_priv->irq_lock);
3115
3116         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3117 }
3118
3119 static void gen6_disable_rps(struct drm_device *dev)
3120 {
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122
3123         I915_WRITE(GEN6_RC_CONTROL, 0);
3124         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3125
3126         gen6_disable_rps_interrupts(dev);
3127 }
3128
3129 static void valleyview_disable_rps(struct drm_device *dev)
3130 {
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132
3133         I915_WRITE(GEN6_RC_CONTROL, 0);
3134
3135         gen6_disable_rps_interrupts(dev);
3136
3137         if (dev_priv->vlv_pctx) {
3138                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3139                 dev_priv->vlv_pctx = NULL;
3140         }
3141 }
3142
3143 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3144 {
3145         if (IS_GEN6(dev))
3146                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3147
3148         if (IS_HASWELL(dev))
3149                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3150
3151         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3152                         (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3153                         (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3154                         (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3155 }
3156
3157 int intel_enable_rc6(const struct drm_device *dev)
3158 {
3159         /* No RC6 before Ironlake */
3160         if (INTEL_INFO(dev)->gen < 5)
3161                 return 0;
3162
3163         /* Respect the kernel parameter if it is set */
3164         if (i915_enable_rc6 >= 0)
3165                 return i915_enable_rc6;
3166
3167         /* Disable RC6 on Ironlake */
3168         if (INTEL_INFO(dev)->gen == 5)
3169                 return 0;
3170
3171         if (IS_HASWELL(dev))
3172                 return INTEL_RC6_ENABLE;
3173
3174         /* snb/ivb have more than one rc6 state. */
3175         if (INTEL_INFO(dev)->gen == 6)
3176                 return INTEL_RC6_ENABLE;
3177
3178         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3179 }
3180
3181 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3182 {
3183         struct drm_i915_private *dev_priv = dev->dev_private;
3184         u32 enabled_intrs;
3185
3186         spin_lock_irq(&dev_priv->irq_lock);
3187         WARN_ON(dev_priv->rps.pm_iir);
3188         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3189         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3190         spin_unlock_irq(&dev_priv->irq_lock);
3191
3192         /* only unmask PM interrupts we need. Mask all others. */
3193         enabled_intrs = GEN6_PM_RPS_EVENTS;
3194
3195         /* IVB and SNB hard hangs on looping batchbuffer
3196          * if GEN6_PM_UP_EI_EXPIRED is masked.
3197          */
3198         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3199                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3200
3201         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3202 }
3203
3204 static void gen8_enable_rps(struct drm_device *dev)
3205 {
3206         struct drm_i915_private *dev_priv = dev->dev_private;
3207         struct intel_ring_buffer *ring;
3208         uint32_t rc6_mask = 0, rp_state_cap;
3209         int unused;
3210
3211         /* 1a: Software RC state - RC0 */
3212         I915_WRITE(GEN6_RC_STATE, 0);
3213
3214         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3215          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3216         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3217
3218         /* 2a: Disable RC states. */
3219         I915_WRITE(GEN6_RC_CONTROL, 0);
3220
3221         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3222
3223         /* 2b: Program RC6 thresholds.*/
3224         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3225         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3226         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3227         for_each_ring(ring, dev_priv, unused)
3228                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3229         I915_WRITE(GEN6_RC_SLEEP, 0);
3230         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3231
3232         /* 3: Enable RC6 */
3233         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3234                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3235         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3236         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3237                         GEN6_RC_CTL_EI_MODE(1) |
3238                         rc6_mask);
3239
3240         /* 4 Program defaults and thresholds for RPS*/
3241         I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3242         I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3243         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3244         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3245
3246         /* Docs recommend 900MHz, and 300 MHz respectively */
3247         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3248                    dev_priv->rps.max_delay << 24 |
3249                    dev_priv->rps.min_delay << 16);
3250
3251         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3252         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3253         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3254         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3255
3256         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3257
3258         /* 5: Enable RPS */
3259         I915_WRITE(GEN6_RP_CONTROL,
3260                    GEN6_RP_MEDIA_TURBO |
3261                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3262                    GEN6_RP_MEDIA_IS_GFX |
3263                    GEN6_RP_ENABLE |
3264                    GEN6_RP_UP_BUSY_AVG |
3265                    GEN6_RP_DOWN_IDLE_AVG);
3266
3267         /* 6: Ring frequency + overclocking (our driver does this later */
3268
3269         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3270
3271         gen6_enable_rps_interrupts(dev);
3272
3273         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3274 }
3275
3276 static void gen6_enable_rps(struct drm_device *dev)
3277 {
3278         struct drm_i915_private *dev_priv = dev->dev_private;
3279         struct intel_ring_buffer *ring;
3280         u32 rp_state_cap;
3281         u32 gt_perf_status;
3282         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3283         u32 gtfifodbg;
3284         int rc6_mode;
3285         int i, ret;
3286
3287         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3288
3289         /* Here begins a magic sequence of register writes to enable
3290          * auto-downclocking.
3291          *
3292          * Perhaps there might be some value in exposing these to
3293          * userspace...
3294          */
3295         I915_WRITE(GEN6_RC_STATE, 0);
3296
3297         /* Clear the DBG now so we don't confuse earlier errors */
3298         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3299                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3300                 I915_WRITE(GTFIFODBG, gtfifodbg);
3301         }
3302
3303         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3304
3305         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3306         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3307
3308         /* In units of 50MHz */
3309         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3310         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3311         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3312         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3313         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3314         dev_priv->rps.cur_delay = 0;
3315
3316         /* disable the counters and set deterministic thresholds */
3317         I915_WRITE(GEN6_RC_CONTROL, 0);
3318
3319         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3320         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3321         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3322         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3323         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3324
3325         for_each_ring(ring, dev_priv, i)
3326                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3327
3328         I915_WRITE(GEN6_RC_SLEEP, 0);
3329         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3330         if (IS_IVYBRIDGE(dev))
3331                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3332         else
3333                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3334         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3335         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3336
3337         /* Check if we are enabling RC6 */
3338         rc6_mode = intel_enable_rc6(dev_priv->dev);
3339         if (rc6_mode & INTEL_RC6_ENABLE)
3340                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3341
3342         /* We don't use those on Haswell */
3343         if (!IS_HASWELL(dev)) {
3344                 if (rc6_mode & INTEL_RC6p_ENABLE)
3345                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3346
3347                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3348                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3349         }
3350
3351         intel_print_rc6_info(dev, rc6_mask);
3352
3353         I915_WRITE(GEN6_RC_CONTROL,
3354                    rc6_mask |
3355                    GEN6_RC_CTL_EI_MODE(1) |
3356                    GEN6_RC_CTL_HW_ENABLE);
3357
3358         /* Power down if completely idle for over 50ms */
3359         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3360         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3361
3362         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3363         if (!ret) {
3364                 pcu_mbox = 0;
3365                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3366                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3367                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3368                                          (dev_priv->rps.max_delay & 0xff) * 50,
3369                                          (pcu_mbox & 0xff) * 50);
3370                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3371                 }
3372         } else {
3373                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3374         }
3375
3376         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3377         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3378
3379         gen6_enable_rps_interrupts(dev);
3380
3381         rc6vids = 0;
3382         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3383         if (IS_GEN6(dev) && ret) {
3384                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3385         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3386                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3387                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3388                 rc6vids &= 0xffff00;
3389                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3390                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3391                 if (ret)
3392                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3393         }
3394
3395         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3396 }
3397
3398 void gen6_update_ring_freq(struct drm_device *dev)
3399 {
3400         struct drm_i915_private *dev_priv = dev->dev_private;
3401         int min_freq = 15;
3402         unsigned int gpu_freq;
3403         unsigned int max_ia_freq, min_ring_freq;
3404         int scaling_factor = 180;
3405         struct cpufreq_policy *policy;
3406
3407         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3408
3409         policy = cpufreq_cpu_get(0);
3410         if (policy) {
3411                 max_ia_freq = policy->cpuinfo.max_freq;
3412                 cpufreq_cpu_put(policy);
3413         } else {
3414                 /*
3415                  * Default to measured freq if none found, PCU will ensure we
3416                  * don't go over
3417                  */
3418                 max_ia_freq = tsc_khz;
3419         }
3420
3421         /* Convert from kHz to MHz */
3422         max_ia_freq /= 1000;
3423
3424         min_ring_freq = I915_READ(DCLK) & 0xf;
3425         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3426         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3427
3428         /*
3429          * For each potential GPU frequency, load a ring frequency we'd like
3430          * to use for memory access.  We do this by specifying the IA frequency
3431          * the PCU should use as a reference to determine the ring frequency.
3432          */
3433         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3434              gpu_freq--) {
3435                 int diff = dev_priv->rps.max_delay - gpu_freq;
3436                 unsigned int ia_freq = 0, ring_freq = 0;
3437
3438                 if (INTEL_INFO(dev)->gen >= 8) {
3439                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3440                         ring_freq = max(min_ring_freq, gpu_freq);
3441                 } else if (IS_HASWELL(dev)) {
3442                         ring_freq = mult_frac(gpu_freq, 5, 4);
3443                         ring_freq = max(min_ring_freq, ring_freq);
3444                         /* leave ia_freq as the default, chosen by cpufreq */
3445                 } else {
3446                         /* On older processors, there is no separate ring
3447                          * clock domain, so in order to boost the bandwidth
3448                          * of the ring, we need to upclock the CPU (ia_freq).
3449                          *
3450                          * For GPU frequencies less than 750MHz,
3451                          * just use the lowest ring freq.
3452                          */
3453                         if (gpu_freq < min_freq)
3454                                 ia_freq = 800;
3455                         else
3456                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3457                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3458                 }
3459
3460                 sandybridge_pcode_write(dev_priv,
3461                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3462                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3463                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3464                                         gpu_freq);
3465         }
3466 }
3467
3468 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3469 {
3470         u32 val, rp0;
3471
3472         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3473
3474         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3475         /* Clamp to max */
3476         rp0 = min_t(u32, rp0, 0xea);
3477
3478         return rp0;
3479 }
3480
3481 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3482 {
3483         u32 val, rpe;
3484
3485         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3486         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3487         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3488         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3489
3490         return rpe;
3491 }
3492
3493 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3494 {
3495         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3496 }
3497
3498 static void valleyview_setup_pctx(struct drm_device *dev)
3499 {
3500         struct drm_i915_private *dev_priv = dev->dev_private;
3501         struct drm_i915_gem_object *pctx;
3502         unsigned long pctx_paddr;
3503         u32 pcbr;
3504         int pctx_size = 24*1024;
3505
3506         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3507
3508         pcbr = I915_READ(VLV_PCBR);
3509         if (pcbr) {
3510                 /* BIOS set it up already, grab the pre-alloc'd space */
3511                 int pcbr_offset;
3512
3513                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3514                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3515                                                                       pcbr_offset,
3516                                                                       I915_GTT_OFFSET_NONE,
3517                                                                       pctx_size);
3518                 goto out;
3519         }
3520
3521         /*
3522          * From the Gunit register HAS:
3523          * The Gfx driver is expected to program this register and ensure
3524          * proper allocation within Gfx stolen memory.  For example, this
3525          * register should be programmed such than the PCBR range does not
3526          * overlap with other ranges, such as the frame buffer, protected
3527          * memory, or any other relevant ranges.
3528          */
3529         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3530         if (!pctx) {
3531                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3532                 return;
3533         }
3534
3535         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3536         I915_WRITE(VLV_PCBR, pctx_paddr);
3537
3538 out:
3539         dev_priv->vlv_pctx = pctx;
3540 }
3541
3542 static void valleyview_enable_rps(struct drm_device *dev)
3543 {
3544         struct drm_i915_private *dev_priv = dev->dev_private;
3545         struct intel_ring_buffer *ring;
3546         u32 gtfifodbg, val, rc6_mode = 0;
3547         int i;
3548
3549         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3550
3551         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3552                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3553                                  gtfifodbg);
3554                 I915_WRITE(GTFIFODBG, gtfifodbg);
3555         }
3556
3557         /* If VLV, Forcewake all wells, else re-direct to regular path */
3558         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3559
3560         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3561         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3562         I915_WRITE(GEN6_RP_UP_EI, 66000);
3563         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3564
3565         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3566
3567         I915_WRITE(GEN6_RP_CONTROL,
3568                    GEN6_RP_MEDIA_TURBO |
3569                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3570                    GEN6_RP_MEDIA_IS_GFX |
3571                    GEN6_RP_ENABLE |
3572                    GEN6_RP_UP_BUSY_AVG |
3573                    GEN6_RP_DOWN_IDLE_CONT);
3574
3575         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3576         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3577         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3578
3579         for_each_ring(ring, dev_priv, i)
3580                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3581
3582         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3583
3584         /* allows RC6 residency counter to work */
3585         I915_WRITE(VLV_COUNTER_CONTROL,
3586                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3587                                       VLV_MEDIA_RC6_COUNT_EN |
3588                                       VLV_RENDER_RC6_COUNT_EN));
3589         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3590                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3591
3592         intel_print_rc6_info(dev, rc6_mode);
3593
3594         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3595
3596         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3597
3598         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3599         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3600
3601         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3602         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3603                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3604                          dev_priv->rps.cur_delay);
3605
3606         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3607         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3608         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3609                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
3610                          dev_priv->rps.max_delay);
3611
3612         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3613         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3614                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3615                          dev_priv->rps.rpe_delay);
3616
3617         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3618         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3619                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
3620                          dev_priv->rps.min_delay);
3621
3622         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3623                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3624                          dev_priv->rps.rpe_delay);
3625
3626         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3627
3628         gen6_enable_rps_interrupts(dev);
3629
3630         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3631 }
3632
3633 void ironlake_teardown_rc6(struct drm_device *dev)
3634 {
3635         struct drm_i915_private *dev_priv = dev->dev_private;
3636
3637         if (dev_priv->ips.renderctx) {
3638                 i915_gem_object_unpin(dev_priv->ips.renderctx);
3639                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3640                 dev_priv->ips.renderctx = NULL;
3641         }
3642
3643         if (dev_priv->ips.pwrctx) {
3644                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3645                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3646                 dev_priv->ips.pwrctx = NULL;
3647         }
3648 }
3649
3650 static void ironlake_disable_rc6(struct drm_device *dev)
3651 {
3652         struct drm_i915_private *dev_priv = dev->dev_private;
3653
3654         if (I915_READ(PWRCTXA)) {
3655                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3656                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3657                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3658                          50);
3659
3660                 I915_WRITE(PWRCTXA, 0);
3661                 POSTING_READ(PWRCTXA);
3662
3663                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3664                 POSTING_READ(RSTDBYCTL);
3665         }
3666 }
3667
3668 static int ironlake_setup_rc6(struct drm_device *dev)
3669 {
3670         struct drm_i915_private *dev_priv = dev->dev_private;
3671
3672         if (dev_priv->ips.renderctx == NULL)
3673                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3674         if (!dev_priv->ips.renderctx)
3675                 return -ENOMEM;
3676
3677         if (dev_priv->ips.pwrctx == NULL)
3678                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3679         if (!dev_priv->ips.pwrctx) {
3680                 ironlake_teardown_rc6(dev);
3681                 return -ENOMEM;
3682         }
3683
3684         return 0;
3685 }
3686
3687 static void ironlake_enable_rc6(struct drm_device *dev)
3688 {
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3691         bool was_interruptible;
3692         int ret;
3693
3694         /* rc6 disabled by default due to repeated reports of hanging during
3695          * boot and resume.
3696          */
3697         if (!intel_enable_rc6(dev))
3698                 return;
3699
3700         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3701
3702         ret = ironlake_setup_rc6(dev);
3703         if (ret)
3704                 return;
3705
3706         was_interruptible = dev_priv->mm.interruptible;
3707         dev_priv->mm.interruptible = false;
3708
3709         /*
3710          * GPU can automatically power down the render unit if given a page
3711          * to save state.
3712          */
3713         ret = intel_ring_begin(ring, 6);
3714         if (ret) {
3715                 ironlake_teardown_rc6(dev);
3716                 dev_priv->mm.interruptible = was_interruptible;
3717                 return;
3718         }
3719
3720         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3721         intel_ring_emit(ring, MI_SET_CONTEXT);
3722         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3723                         MI_MM_SPACE_GTT |
3724                         MI_SAVE_EXT_STATE_EN |
3725                         MI_RESTORE_EXT_STATE_EN |
3726                         MI_RESTORE_INHIBIT);
3727         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3728         intel_ring_emit(ring, MI_NOOP);
3729         intel_ring_emit(ring, MI_FLUSH);
3730         intel_ring_advance(ring);
3731
3732         /*
3733          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3734          * does an implicit flush, combined with MI_FLUSH above, it should be
3735          * safe to assume that renderctx is valid
3736          */
3737         ret = intel_ring_idle(ring);
3738         dev_priv->mm.interruptible = was_interruptible;
3739         if (ret) {
3740                 DRM_ERROR("failed to enable ironlake power savings\n");
3741                 ironlake_teardown_rc6(dev);
3742                 return;
3743         }
3744
3745         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3746         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3747
3748         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
3749 }
3750
3751 static unsigned long intel_pxfreq(u32 vidfreq)
3752 {
3753         unsigned long freq;
3754         int div = (vidfreq & 0x3f0000) >> 16;
3755         int post = (vidfreq & 0x3000) >> 12;
3756         int pre = (vidfreq & 0x7);
3757
3758         if (!pre)
3759                 return 0;
3760
3761         freq = ((div * 133333) / ((1<<post) * pre));
3762
3763         return freq;
3764 }
3765
3766 static const struct cparams {
3767         u16 i;
3768         u16 t;
3769         u16 m;
3770         u16 c;
3771 } cparams[] = {
3772         { 1, 1333, 301, 28664 },
3773         { 1, 1066, 294, 24460 },
3774         { 1, 800, 294, 25192 },
3775         { 0, 1333, 276, 27605 },
3776         { 0, 1066, 276, 27605 },
3777         { 0, 800, 231, 23784 },
3778 };
3779
3780 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3781 {
3782         u64 total_count, diff, ret;
3783         u32 count1, count2, count3, m = 0, c = 0;
3784         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3785         int i;
3786
3787         assert_spin_locked(&mchdev_lock);
3788
3789         diff1 = now - dev_priv->ips.last_time1;
3790
3791         /* Prevent division-by-zero if we are asking too fast.
3792          * Also, we don't get interesting results if we are polling
3793          * faster than once in 10ms, so just return the saved value
3794          * in such cases.
3795          */
3796         if (diff1 <= 10)
3797                 return dev_priv->ips.chipset_power;
3798
3799         count1 = I915_READ(DMIEC);
3800         count2 = I915_READ(DDREC);
3801         count3 = I915_READ(CSIEC);
3802
3803         total_count = count1 + count2 + count3;
3804
3805         /* FIXME: handle per-counter overflow */
3806         if (total_count < dev_priv->ips.last_count1) {
3807                 diff = ~0UL - dev_priv->ips.last_count1;
3808                 diff += total_count;
3809         } else {
3810                 diff = total_count - dev_priv->ips.last_count1;
3811         }
3812
3813         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3814                 if (cparams[i].i == dev_priv->ips.c_m &&
3815                     cparams[i].t == dev_priv->ips.r_t) {
3816                         m = cparams[i].m;
3817                         c = cparams[i].c;
3818                         break;
3819                 }
3820         }
3821
3822         diff = div_u64(diff, diff1);
3823         ret = ((m * diff) + c);
3824         ret = div_u64(ret, 10);
3825
3826         dev_priv->ips.last_count1 = total_count;
3827         dev_priv->ips.last_time1 = now;
3828
3829         dev_priv->ips.chipset_power = ret;
3830
3831         return ret;
3832 }
3833
3834 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3835 {
3836         unsigned long val;
3837
3838         if (dev_priv->info->gen != 5)
3839                 return 0;
3840
3841         spin_lock_irq(&mchdev_lock);
3842
3843         val = __i915_chipset_val(dev_priv);
3844
3845         spin_unlock_irq(&mchdev_lock);
3846
3847         return val;
3848 }
3849
3850 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3851 {
3852         unsigned long m, x, b;
3853         u32 tsfs;
3854
3855         tsfs = I915_READ(TSFS);
3856
3857         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3858         x = I915_READ8(TR1);
3859
3860         b = tsfs & TSFS_INTR_MASK;
3861
3862         return ((m * x) / 127) - b;
3863 }
3864
3865 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3866 {
3867         static const struct v_table {
3868                 u16 vd; /* in .1 mil */
3869                 u16 vm; /* in .1 mil */
3870         } v_table[] = {
3871                 { 0, 0, },
3872                 { 375, 0, },
3873                 { 500, 0, },
3874                 { 625, 0, },
3875                 { 750, 0, },
3876                 { 875, 0, },
3877                 { 1000, 0, },
3878                 { 1125, 0, },
3879                 { 4125, 3000, },
3880                 { 4125, 3000, },
3881                 { 4125, 3000, },
3882                 { 4125, 3000, },
3883                 { 4125, 3000, },
3884                 { 4125, 3000, },
3885                 { 4125, 3000, },
3886                 { 4125, 3000, },
3887                 { 4125, 3000, },
3888                 { 4125, 3000, },
3889                 { 4125, 3000, },
3890                 { 4125, 3000, },
3891                 { 4125, 3000, },
3892                 { 4125, 3000, },
3893                 { 4125, 3000, },
3894                 { 4125, 3000, },
3895                 { 4125, 3000, },
3896                 { 4125, 3000, },
3897                 { 4125, 3000, },
3898                 { 4125, 3000, },
3899                 { 4125, 3000, },
3900                 { 4125, 3000, },
3901                 { 4125, 3000, },
3902                 { 4125, 3000, },
3903                 { 4250, 3125, },
3904                 { 4375, 3250, },
3905                 { 4500, 3375, },
3906                 { 4625, 3500, },
3907                 { 4750, 3625, },
3908                 { 4875, 3750, },
3909                 { 5000, 3875, },
3910                 { 5125, 4000, },
3911                 { 5250, 4125, },
3912                 { 5375, 4250, },
3913                 { 5500, 4375, },
3914                 { 5625, 4500, },
3915                 { 5750, 4625, },
3916                 { 5875, 4750, },
3917                 { 6000, 4875, },
3918                 { 6125, 5000, },
3919                 { 6250, 5125, },
3920                 { 6375, 5250, },
3921                 { 6500, 5375, },
3922                 { 6625, 5500, },
3923                 { 6750, 5625, },
3924                 { 6875, 5750, },
3925                 { 7000, 5875, },
3926                 { 7125, 6000, },
3927                 { 7250, 6125, },
3928                 { 7375, 6250, },
3929                 { 7500, 6375, },
3930                 { 7625, 6500, },
3931                 { 7750, 6625, },
3932                 { 7875, 6750, },
3933                 { 8000, 6875, },
3934                 { 8125, 7000, },
3935                 { 8250, 7125, },
3936                 { 8375, 7250, },
3937                 { 8500, 7375, },
3938                 { 8625, 7500, },
3939                 { 8750, 7625, },
3940                 { 8875, 7750, },
3941                 { 9000, 7875, },
3942                 { 9125, 8000, },
3943                 { 9250, 8125, },
3944                 { 9375, 8250, },
3945                 { 9500, 8375, },
3946                 { 9625, 8500, },
3947                 { 9750, 8625, },
3948                 { 9875, 8750, },
3949                 { 10000, 8875, },
3950                 { 10125, 9000, },
3951                 { 10250, 9125, },
3952                 { 10375, 9250, },
3953                 { 10500, 9375, },
3954                 { 10625, 9500, },
3955                 { 10750, 9625, },
3956                 { 10875, 9750, },
3957                 { 11000, 9875, },
3958                 { 11125, 10000, },
3959                 { 11250, 10125, },
3960                 { 11375, 10250, },
3961                 { 11500, 10375, },
3962                 { 11625, 10500, },
3963                 { 11750, 10625, },
3964                 { 11875, 10750, },
3965                 { 12000, 10875, },
3966                 { 12125, 11000, },
3967                 { 12250, 11125, },
3968                 { 12375, 11250, },
3969                 { 12500, 11375, },
3970                 { 12625, 11500, },
3971                 { 12750, 11625, },
3972                 { 12875, 11750, },
3973                 { 13000, 11875, },
3974                 { 13125, 12000, },
3975                 { 13250, 12125, },
3976                 { 13375, 12250, },
3977                 { 13500, 12375, },
3978                 { 13625, 12500, },
3979                 { 13750, 12625, },
3980                 { 13875, 12750, },
3981                 { 14000, 12875, },
3982                 { 14125, 13000, },
3983                 { 14250, 13125, },
3984                 { 14375, 13250, },
3985                 { 14500, 13375, },
3986                 { 14625, 13500, },
3987                 { 14750, 13625, },
3988                 { 14875, 13750, },
3989                 { 15000, 13875, },
3990                 { 15125, 14000, },
3991                 { 15250, 14125, },
3992                 { 15375, 14250, },
3993                 { 15500, 14375, },
3994                 { 15625, 14500, },
3995                 { 15750, 14625, },
3996                 { 15875, 14750, },
3997                 { 16000, 14875, },
3998                 { 16125, 15000, },
3999         };
4000         if (dev_priv->info->is_mobile)
4001                 return v_table[pxvid].vm;
4002         else
4003                 return v_table[pxvid].vd;
4004 }
4005
4006 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4007 {
4008         struct timespec now, diff1;
4009         u64 diff;
4010         unsigned long diffms;
4011         u32 count;
4012
4013         assert_spin_locked(&mchdev_lock);
4014
4015         getrawmonotonic(&now);
4016         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4017
4018         /* Don't divide by 0 */
4019         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4020         if (!diffms)
4021                 return;
4022
4023         count = I915_READ(GFXEC);
4024
4025         if (count < dev_priv->ips.last_count2) {
4026                 diff = ~0UL - dev_priv->ips.last_count2;
4027                 diff += count;
4028         } else {
4029                 diff = count - dev_priv->ips.last_count2;
4030         }
4031
4032         dev_priv->ips.last_count2 = count;
4033         dev_priv->ips.last_time2 = now;
4034
4035         /* More magic constants... */
4036         diff = diff * 1181;
4037         diff = div_u64(diff, diffms * 10);
4038         dev_priv->ips.gfx_power = diff;
4039 }
4040
4041 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4042 {
4043         if (dev_priv->info->gen != 5)
4044                 return;
4045
4046         spin_lock_irq(&mchdev_lock);
4047
4048         __i915_update_gfx_val(dev_priv);
4049
4050         spin_unlock_irq(&mchdev_lock);
4051 }
4052
4053 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4054 {
4055         unsigned long t, corr, state1, corr2, state2;
4056         u32 pxvid, ext_v;
4057
4058         assert_spin_locked(&mchdev_lock);
4059
4060         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4061         pxvid = (pxvid >> 24) & 0x7f;
4062         ext_v = pvid_to_extvid(dev_priv, pxvid);
4063
4064         state1 = ext_v;
4065
4066         t = i915_mch_val(dev_priv);
4067
4068         /* Revel in the empirically derived constants */
4069
4070         /* Correction factor in 1/100000 units */
4071         if (t > 80)
4072                 corr = ((t * 2349) + 135940);
4073         else if (t >= 50)
4074                 corr = ((t * 964) + 29317);
4075         else /* < 50 */
4076                 corr = ((t * 301) + 1004);
4077
4078         corr = corr * ((150142 * state1) / 10000 - 78642);
4079         corr /= 100000;
4080         corr2 = (corr * dev_priv->ips.corr);
4081
4082         state2 = (corr2 * state1) / 10000;
4083         state2 /= 100; /* convert to mW */
4084
4085         __i915_update_gfx_val(dev_priv);
4086
4087         return dev_priv->ips.gfx_power + state2;
4088 }
4089
4090 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4091 {
4092         unsigned long val;
4093
4094         if (dev_priv->info->gen != 5)
4095                 return 0;
4096
4097         spin_lock_irq(&mchdev_lock);
4098
4099         val = __i915_gfx_val(dev_priv);
4100
4101         spin_unlock_irq(&mchdev_lock);
4102
4103         return val;
4104 }
4105
4106 /**
4107  * i915_read_mch_val - return value for IPS use
4108  *
4109  * Calculate and return a value for the IPS driver to use when deciding whether
4110  * we have thermal and power headroom to increase CPU or GPU power budget.
4111  */
4112 unsigned long i915_read_mch_val(void)
4113 {
4114         struct drm_i915_private *dev_priv;
4115         unsigned long chipset_val, graphics_val, ret = 0;
4116
4117         spin_lock_irq(&mchdev_lock);
4118         if (!i915_mch_dev)
4119                 goto out_unlock;
4120         dev_priv = i915_mch_dev;
4121
4122         chipset_val = __i915_chipset_val(dev_priv);
4123         graphics_val = __i915_gfx_val(dev_priv);
4124
4125         ret = chipset_val + graphics_val;
4126
4127 out_unlock:
4128         spin_unlock_irq(&mchdev_lock);
4129
4130         return ret;
4131 }
4132 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4133
4134 /**
4135  * i915_gpu_raise - raise GPU frequency limit
4136  *
4137  * Raise the limit; IPS indicates we have thermal headroom.
4138  */
4139 bool i915_gpu_raise(void)
4140 {
4141         struct drm_i915_private *dev_priv;
4142         bool ret = true;
4143
4144         spin_lock_irq(&mchdev_lock);
4145         if (!i915_mch_dev) {
4146                 ret = false;
4147                 goto out_unlock;
4148         }
4149         dev_priv = i915_mch_dev;
4150
4151         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4152                 dev_priv->ips.max_delay--;
4153
4154 out_unlock:
4155         spin_unlock_irq(&mchdev_lock);
4156
4157         return ret;
4158 }
4159 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4160
4161 /**
4162  * i915_gpu_lower - lower GPU frequency limit
4163  *
4164  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4165  * frequency maximum.
4166  */
4167 bool i915_gpu_lower(void)
4168 {
4169         struct drm_i915_private *dev_priv;
4170         bool ret = true;
4171
4172         spin_lock_irq(&mchdev_lock);
4173         if (!i915_mch_dev) {
4174                 ret = false;
4175                 goto out_unlock;
4176         }
4177         dev_priv = i915_mch_dev;
4178
4179         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4180                 dev_priv->ips.max_delay++;
4181
4182 out_unlock:
4183         spin_unlock_irq(&mchdev_lock);
4184
4185         return ret;
4186 }
4187 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4188
4189 /**
4190  * i915_gpu_busy - indicate GPU business to IPS
4191  *
4192  * Tell the IPS driver whether or not the GPU is busy.
4193  */
4194 bool i915_gpu_busy(void)
4195 {
4196         struct drm_i915_private *dev_priv;
4197         struct intel_ring_buffer *ring;
4198         bool ret = false;
4199         int i;
4200
4201         spin_lock_irq(&mchdev_lock);
4202         if (!i915_mch_dev)
4203                 goto out_unlock;
4204         dev_priv = i915_mch_dev;
4205
4206         for_each_ring(ring, dev_priv, i)
4207                 ret |= !list_empty(&ring->request_list);
4208
4209 out_unlock:
4210         spin_unlock_irq(&mchdev_lock);
4211
4212         return ret;
4213 }
4214 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4215
4216 /**
4217  * i915_gpu_turbo_disable - disable graphics turbo
4218  *
4219  * Disable graphics turbo by resetting the max frequency and setting the
4220  * current frequency to the default.
4221  */
4222 bool i915_gpu_turbo_disable(void)
4223 {
4224         struct drm_i915_private *dev_priv;
4225         bool ret = true;
4226
4227         spin_lock_irq(&mchdev_lock);
4228         if (!i915_mch_dev) {
4229                 ret = false;
4230                 goto out_unlock;
4231         }
4232         dev_priv = i915_mch_dev;
4233
4234         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4235
4236         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4237                 ret = false;
4238
4239 out_unlock:
4240         spin_unlock_irq(&mchdev_lock);
4241
4242         return ret;
4243 }
4244 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4245
4246 /**
4247  * Tells the intel_ips driver that the i915 driver is now loaded, if
4248  * IPS got loaded first.
4249  *
4250  * This awkward dance is so that neither module has to depend on the
4251  * other in order for IPS to do the appropriate communication of
4252  * GPU turbo limits to i915.
4253  */
4254 static void
4255 ips_ping_for_i915_load(void)
4256 {
4257         void (*link)(void);
4258
4259         link = symbol_get(ips_link_to_i915_driver);
4260         if (link) {
4261                 link();
4262                 symbol_put(ips_link_to_i915_driver);
4263         }
4264 }
4265
4266 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4267 {
4268         /* We only register the i915 ips part with intel-ips once everything is
4269          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4270         spin_lock_irq(&mchdev_lock);
4271         i915_mch_dev = dev_priv;
4272         spin_unlock_irq(&mchdev_lock);
4273
4274         ips_ping_for_i915_load();
4275 }
4276
4277 void intel_gpu_ips_teardown(void)
4278 {
4279         spin_lock_irq(&mchdev_lock);
4280         i915_mch_dev = NULL;
4281         spin_unlock_irq(&mchdev_lock);
4282 }
4283 static void intel_init_emon(struct drm_device *dev)
4284 {
4285         struct drm_i915_private *dev_priv = dev->dev_private;
4286         u32 lcfuse;
4287         u8 pxw[16];
4288         int i;
4289
4290         /* Disable to program */
4291         I915_WRITE(ECR, 0);
4292         POSTING_READ(ECR);
4293
4294         /* Program energy weights for various events */
4295         I915_WRITE(SDEW, 0x15040d00);
4296         I915_WRITE(CSIEW0, 0x007f0000);
4297         I915_WRITE(CSIEW1, 0x1e220004);
4298         I915_WRITE(CSIEW2, 0x04000004);
4299
4300         for (i = 0; i < 5; i++)
4301                 I915_WRITE(PEW + (i * 4), 0);
4302         for (i = 0; i < 3; i++)
4303                 I915_WRITE(DEW + (i * 4), 0);
4304
4305         /* Program P-state weights to account for frequency power adjustment */
4306         for (i = 0; i < 16; i++) {
4307                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4308                 unsigned long freq = intel_pxfreq(pxvidfreq);
4309                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4310                         PXVFREQ_PX_SHIFT;
4311                 unsigned long val;
4312
4313                 val = vid * vid;
4314                 val *= (freq / 1000);
4315                 val *= 255;
4316                 val /= (127*127*900);
4317                 if (val > 0xff)
4318                         DRM_ERROR("bad pxval: %ld\n", val);
4319                 pxw[i] = val;
4320         }
4321         /* Render standby states get 0 weight */
4322         pxw[14] = 0;
4323         pxw[15] = 0;
4324
4325         for (i = 0; i < 4; i++) {
4326                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4327                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4328                 I915_WRITE(PXW + (i * 4), val);
4329         }
4330
4331         /* Adjust magic regs to magic values (more experimental results) */
4332         I915_WRITE(OGW0, 0);
4333         I915_WRITE(OGW1, 0);
4334         I915_WRITE(EG0, 0x00007f00);
4335         I915_WRITE(EG1, 0x0000000e);
4336         I915_WRITE(EG2, 0x000e0000);
4337         I915_WRITE(EG3, 0x68000300);
4338         I915_WRITE(EG4, 0x42000000);
4339         I915_WRITE(EG5, 0x00140031);
4340         I915_WRITE(EG6, 0);
4341         I915_WRITE(EG7, 0);
4342
4343         for (i = 0; i < 8; i++)
4344                 I915_WRITE(PXWL + (i * 4), 0);
4345
4346         /* Enable PMON + select events */
4347         I915_WRITE(ECR, 0x80000019);
4348
4349         lcfuse = I915_READ(LCFUSE02);
4350
4351         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4352 }
4353
4354 void intel_disable_gt_powersave(struct drm_device *dev)
4355 {
4356         struct drm_i915_private *dev_priv = dev->dev_private;
4357
4358         /* Interrupts should be disabled already to avoid re-arming. */
4359         WARN_ON(dev->irq_enabled);
4360
4361         if (IS_IRONLAKE_M(dev)) {
4362                 ironlake_disable_drps(dev);
4363                 ironlake_disable_rc6(dev);
4364         } else if (INTEL_INFO(dev)->gen >= 6) {
4365                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4366                 cancel_work_sync(&dev_priv->rps.work);
4367                 mutex_lock(&dev_priv->rps.hw_lock);
4368                 if (IS_VALLEYVIEW(dev))
4369                         valleyview_disable_rps(dev);
4370                 else
4371                         gen6_disable_rps(dev);
4372                 dev_priv->rps.enabled = false;
4373                 mutex_unlock(&dev_priv->rps.hw_lock);
4374         }
4375 }
4376
4377 static void intel_gen6_powersave_work(struct work_struct *work)
4378 {
4379         struct drm_i915_private *dev_priv =
4380                 container_of(work, struct drm_i915_private,
4381                              rps.delayed_resume_work.work);
4382         struct drm_device *dev = dev_priv->dev;
4383
4384         mutex_lock(&dev_priv->rps.hw_lock);
4385
4386         if (IS_VALLEYVIEW(dev)) {
4387                 valleyview_enable_rps(dev);
4388         } else if (IS_BROADWELL(dev)) {
4389                 gen8_enable_rps(dev);
4390                 gen6_update_ring_freq(dev);
4391         } else {
4392                 gen6_enable_rps(dev);
4393                 gen6_update_ring_freq(dev);
4394         }
4395         dev_priv->rps.enabled = true;
4396         mutex_unlock(&dev_priv->rps.hw_lock);
4397 }
4398
4399 void intel_enable_gt_powersave(struct drm_device *dev)
4400 {
4401         struct drm_i915_private *dev_priv = dev->dev_private;
4402
4403         if (IS_IRONLAKE_M(dev)) {
4404                 ironlake_enable_drps(dev);
4405                 ironlake_enable_rc6(dev);
4406                 intel_init_emon(dev);
4407         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4408                 if (IS_VALLEYVIEW(dev))
4409                         valleyview_setup_pctx(dev);
4410                 /*
4411                  * PCU communication is slow and this doesn't need to be
4412                  * done at any specific time, so do this out of our fast path
4413                  * to make resume and init faster.
4414                  */
4415                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4416                                       round_jiffies_up_relative(HZ));
4417         }
4418 }
4419
4420 static void ibx_init_clock_gating(struct drm_device *dev)
4421 {
4422         struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424         /*
4425          * On Ibex Peak and Cougar Point, we need to disable clock
4426          * gating for the panel power sequencer or it will fail to
4427          * start up when no ports are active.
4428          */
4429         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4430 }
4431
4432 static void g4x_disable_trickle_feed(struct drm_device *dev)
4433 {
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         int pipe;
4436
4437         for_each_pipe(pipe) {
4438                 I915_WRITE(DSPCNTR(pipe),
4439                            I915_READ(DSPCNTR(pipe)) |
4440                            DISPPLANE_TRICKLE_FEED_DISABLE);
4441                 intel_flush_primary_plane(dev_priv, pipe);
4442         }
4443 }
4444
4445 static void ilk_init_lp_watermarks(struct drm_device *dev)
4446 {
4447         struct drm_i915_private *dev_priv = dev->dev_private;
4448
4449         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4450         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4451         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4452
4453         /*
4454          * Don't touch WM1S_LP_EN here.
4455          * Doing so could cause underruns.
4456          */
4457 }
4458
4459 static void ironlake_init_clock_gating(struct drm_device *dev)
4460 {
4461         struct drm_i915_private *dev_priv = dev->dev_private;
4462         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4463
4464         /*
4465          * Required for FBC
4466          * WaFbcDisableDpfcClockGating:ilk
4467          */
4468         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4469                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4470                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4471
4472         I915_WRITE(PCH_3DCGDIS0,
4473                    MARIUNIT_CLOCK_GATE_DISABLE |
4474                    SVSMUNIT_CLOCK_GATE_DISABLE);
4475         I915_WRITE(PCH_3DCGDIS1,
4476                    VFMUNIT_CLOCK_GATE_DISABLE);
4477
4478         /*
4479          * According to the spec the following bits should be set in
4480          * order to enable memory self-refresh
4481          * The bit 22/21 of 0x42004
4482          * The bit 5 of 0x42020
4483          * The bit 15 of 0x45000
4484          */
4485         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4486                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4487                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4488         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4489         I915_WRITE(DISP_ARB_CTL,
4490                    (I915_READ(DISP_ARB_CTL) |
4491                     DISP_FBC_WM_DIS));
4492
4493         ilk_init_lp_watermarks(dev);
4494
4495         /*
4496          * Based on the document from hardware guys the following bits
4497          * should be set unconditionally in order to enable FBC.
4498          * The bit 22 of 0x42000
4499          * The bit 22 of 0x42004
4500          * The bit 7,8,9 of 0x42020.
4501          */
4502         if (IS_IRONLAKE_M(dev)) {
4503                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4504                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4505                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4506                            ILK_FBCQ_DIS);
4507                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4508                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4509                            ILK_DPARB_GATE);
4510         }
4511
4512         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4513
4514         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4515                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4516                    ILK_ELPIN_409_SELECT);
4517         I915_WRITE(_3D_CHICKEN2,
4518                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4519                    _3D_CHICKEN2_WM_READ_PIPELINED);
4520
4521         /* WaDisableRenderCachePipelinedFlush:ilk */
4522         I915_WRITE(CACHE_MODE_0,
4523                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4524
4525         g4x_disable_trickle_feed(dev);
4526
4527         ibx_init_clock_gating(dev);
4528 }
4529
4530 static void cpt_init_clock_gating(struct drm_device *dev)
4531 {
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533         int pipe;
4534         uint32_t val;
4535
4536         /*
4537          * On Ibex Peak and Cougar Point, we need to disable clock
4538          * gating for the panel power sequencer or it will fail to
4539          * start up when no ports are active.
4540          */
4541         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4542                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4543                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4544         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4545                    DPLS_EDP_PPS_FIX_DIS);
4546         /* The below fixes the weird display corruption, a few pixels shifted
4547          * downward, on (only) LVDS of some HP laptops with IVY.
4548          */
4549         for_each_pipe(pipe) {
4550                 val = I915_READ(TRANS_CHICKEN2(pipe));
4551                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4552                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4553                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4554                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4555                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4556                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4557                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4558                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4559         }
4560         /* WADP0ClockGatingDisable */
4561         for_each_pipe(pipe) {
4562                 I915_WRITE(TRANS_CHICKEN1(pipe),
4563                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4564         }
4565 }
4566
4567 static void gen6_check_mch_setup(struct drm_device *dev)
4568 {
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570         uint32_t tmp;
4571
4572         tmp = I915_READ(MCH_SSKPD);
4573         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4574                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4575                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4576                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4577         }
4578 }
4579
4580 static void gen6_init_clock_gating(struct drm_device *dev)
4581 {
4582         struct drm_i915_private *dev_priv = dev->dev_private;
4583         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4584
4585         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4586
4587         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4588                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4589                    ILK_ELPIN_409_SELECT);
4590
4591         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4592         I915_WRITE(_3D_CHICKEN,
4593                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4594
4595         /* WaSetupGtModeTdRowDispatch:snb */
4596         if (IS_SNB_GT1(dev))
4597                 I915_WRITE(GEN6_GT_MODE,
4598                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4599
4600         ilk_init_lp_watermarks(dev);
4601
4602         I915_WRITE(CACHE_MODE_0,
4603                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4604
4605         I915_WRITE(GEN6_UCGCTL1,
4606                    I915_READ(GEN6_UCGCTL1) |
4607                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4608                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4609
4610         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4611          * gating disable must be set.  Failure to set it results in
4612          * flickering pixels due to Z write ordering failures after
4613          * some amount of runtime in the Mesa "fire" demo, and Unigine
4614          * Sanctuary and Tropics, and apparently anything else with
4615          * alpha test or pixel discard.
4616          *
4617          * According to the spec, bit 11 (RCCUNIT) must also be set,
4618          * but we didn't debug actual testcases to find it out.
4619          *
4620          * Also apply WaDisableVDSUnitClockGating:snb and
4621          * WaDisableRCPBUnitClockGating:snb.
4622          */
4623         I915_WRITE(GEN6_UCGCTL2,
4624                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4625                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4626                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4627
4628         /* Bspec says we need to always set all mask bits. */
4629         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4630                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4631
4632         /*
4633          * According to the spec the following bits should be
4634          * set in order to enable memory self-refresh and fbc:
4635          * The bit21 and bit22 of 0x42000
4636          * The bit21 and bit22 of 0x42004
4637          * The bit5 and bit7 of 0x42020
4638          * The bit14 of 0x70180
4639          * The bit14 of 0x71180
4640          *
4641          * WaFbcAsynchFlipDisableFbcQueue:snb
4642          */
4643         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4644                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4645                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4646         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4647                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4648                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4649         I915_WRITE(ILK_DSPCLK_GATE_D,
4650                    I915_READ(ILK_DSPCLK_GATE_D) |
4651                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4652                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4653
4654         g4x_disable_trickle_feed(dev);
4655
4656         /* The default value should be 0x200 according to docs, but the two
4657          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4658         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4659         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4660
4661         cpt_init_clock_gating(dev);
4662
4663         gen6_check_mch_setup(dev);
4664 }
4665
4666 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4667 {
4668         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4669
4670         reg &= ~GEN7_FF_SCHED_MASK;
4671         reg |= GEN7_FF_TS_SCHED_HW;
4672         reg |= GEN7_FF_VS_SCHED_HW;
4673         reg |= GEN7_FF_DS_SCHED_HW;
4674
4675         if (IS_HASWELL(dev_priv->dev))
4676                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4677
4678         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4679 }
4680
4681 static void lpt_init_clock_gating(struct drm_device *dev)
4682 {
4683         struct drm_i915_private *dev_priv = dev->dev_private;
4684
4685         /*
4686          * TODO: this bit should only be enabled when really needed, then
4687          * disabled when not needed anymore in order to save power.
4688          */
4689         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4690                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4691                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4692                            PCH_LP_PARTITION_LEVEL_DISABLE);
4693
4694         /* WADPOClockGatingDisable:hsw */
4695         I915_WRITE(_TRANSA_CHICKEN1,
4696                    I915_READ(_TRANSA_CHICKEN1) |
4697                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4698 }
4699
4700 static void lpt_suspend_hw(struct drm_device *dev)
4701 {
4702         struct drm_i915_private *dev_priv = dev->dev_private;
4703
4704         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4705                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4706
4707                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4708                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4709         }
4710 }
4711
4712 static void gen8_init_clock_gating(struct drm_device *dev)
4713 {
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         enum pipe i;
4716
4717         I915_WRITE(WM3_LP_ILK, 0);
4718         I915_WRITE(WM2_LP_ILK, 0);
4719         I915_WRITE(WM1_LP_ILK, 0);
4720
4721         /* FIXME(BDW): Check all the w/a, some might only apply to
4722          * pre-production hw. */
4723
4724         WARN(!i915_preliminary_hw_support,
4725              "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
4726         I915_WRITE(HALF_SLICE_CHICKEN3,
4727                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4728         I915_WRITE(HALF_SLICE_CHICKEN3,
4729                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4730         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4731
4732         I915_WRITE(_3D_CHICKEN3,
4733                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4734
4735         I915_WRITE(COMMON_SLICE_CHICKEN2,
4736                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4737
4738         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4739                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4740
4741         /* WaSwitchSolVfFArbitrationPriority:bdw */
4742         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4743
4744         /* WaPsrDPAMaskVBlankInSRD:bdw */
4745         I915_WRITE(CHICKEN_PAR1_1,
4746                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4747
4748         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4749         for_each_pipe(i) {
4750                 I915_WRITE(CHICKEN_PIPESL_1(i),
4751                            I915_READ(CHICKEN_PIPESL_1(i) |
4752                                      DPRS_MASK_VBLANK_SRD));
4753         }
4754
4755         /* Use Force Non-Coherent whenever executing a 3D context. This is a
4756          * workaround for for a possible hang in the unlikely event a TLB
4757          * invalidation occurs during a PSD flush.
4758          */
4759         I915_WRITE(HDC_CHICKEN0,
4760                    I915_READ(HDC_CHICKEN0) |
4761                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
4762
4763         /* WaVSRefCountFullforceMissDisable:bdw */
4764         /* WaDSRefCountFullforceMissDisable:bdw */
4765         I915_WRITE(GEN7_FF_THREAD_MODE,
4766                    I915_READ(GEN7_FF_THREAD_MODE) &
4767                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4768 }
4769
4770 static void haswell_init_clock_gating(struct drm_device *dev)
4771 {
4772         struct drm_i915_private *dev_priv = dev->dev_private;
4773
4774         ilk_init_lp_watermarks(dev);
4775
4776         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4777          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4778          */
4779         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4780
4781         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4782         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4783                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4784
4785         /* WaApplyL3ControlAndL3ChickenMode:hsw */
4786         I915_WRITE(GEN7_L3CNTLREG1,
4787                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4788         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4789                         GEN7_WA_L3_CHICKEN_MODE);
4790
4791         /* L3 caching of data atomics doesn't work -- disable it. */
4792         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4793         I915_WRITE(HSW_ROW_CHICKEN3,
4794                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4795
4796         /* This is required by WaCatErrorRejectionIssue:hsw */
4797         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4798                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4799                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4800
4801         /* WaVSRefCountFullforceMissDisable:hsw */
4802         gen7_setup_fixed_func_scheduler(dev_priv);
4803
4804         /* WaDisable4x2SubspanOptimization:hsw */
4805         I915_WRITE(CACHE_MODE_1,
4806                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4807
4808         /* WaSwitchSolVfFArbitrationPriority:hsw */
4809         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4810
4811         /* WaRsPkgCStateDisplayPMReq:hsw */
4812         I915_WRITE(CHICKEN_PAR1_1,
4813                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4814
4815         lpt_init_clock_gating(dev);
4816 }
4817
4818 static void ivybridge_init_clock_gating(struct drm_device *dev)
4819 {
4820         struct drm_i915_private *dev_priv = dev->dev_private;
4821         uint32_t snpcr;
4822
4823         ilk_init_lp_watermarks(dev);
4824
4825         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4826
4827         /* WaDisableEarlyCull:ivb */
4828         I915_WRITE(_3D_CHICKEN3,
4829                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4830
4831         /* WaDisableBackToBackFlipFix:ivb */
4832         I915_WRITE(IVB_CHICKEN3,
4833                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4834                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4835
4836         /* WaDisablePSDDualDispatchEnable:ivb */
4837         if (IS_IVB_GT1(dev))
4838                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4839                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4840         else
4841                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4842                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4843
4844         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4845         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4846                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4847
4848         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4849         I915_WRITE(GEN7_L3CNTLREG1,
4850                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4851         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4852                    GEN7_WA_L3_CHICKEN_MODE);
4853         if (IS_IVB_GT1(dev))
4854                 I915_WRITE(GEN7_ROW_CHICKEN2,
4855                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4856         else
4857                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4858                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4859
4860
4861         /* WaForceL3Serialization:ivb */
4862         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4863                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4864
4865         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4866          * gating disable must be set.  Failure to set it results in
4867          * flickering pixels due to Z write ordering failures after
4868          * some amount of runtime in the Mesa "fire" demo, and Unigine
4869          * Sanctuary and Tropics, and apparently anything else with
4870          * alpha test or pixel discard.
4871          *
4872          * According to the spec, bit 11 (RCCUNIT) must also be set,
4873          * but we didn't debug actual testcases to find it out.
4874          *
4875          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4876          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4877          */
4878         I915_WRITE(GEN6_UCGCTL2,
4879                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4880                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4881
4882         /* This is required by WaCatErrorRejectionIssue:ivb */
4883         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4884                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4885                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4886
4887         g4x_disable_trickle_feed(dev);
4888
4889         /* WaVSRefCountFullforceMissDisable:ivb */
4890         gen7_setup_fixed_func_scheduler(dev_priv);
4891
4892         /* WaDisable4x2SubspanOptimization:ivb */
4893         I915_WRITE(CACHE_MODE_1,
4894                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4895
4896         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4897         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4898         snpcr |= GEN6_MBC_SNPCR_MED;
4899         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4900
4901         if (!HAS_PCH_NOP(dev))
4902                 cpt_init_clock_gating(dev);
4903
4904         gen6_check_mch_setup(dev);
4905 }
4906
4907 static void valleyview_init_clock_gating(struct drm_device *dev)
4908 {
4909         struct drm_i915_private *dev_priv = dev->dev_private;
4910         u32 val;
4911
4912         mutex_lock(&dev_priv->rps.hw_lock);
4913         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4914         mutex_unlock(&dev_priv->rps.hw_lock);
4915         switch ((val >> 6) & 3) {
4916         case 0:
4917                 dev_priv->mem_freq = 800;
4918                 break;
4919         case 1:
4920                 dev_priv->mem_freq = 1066;
4921                 break;
4922         case 2:
4923                 dev_priv->mem_freq = 1333;
4924                 break;
4925         case 3:
4926                 dev_priv->mem_freq = 1333;
4927                 break;
4928         }
4929         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4930
4931         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
4932
4933         /* WaDisableEarlyCull:vlv */
4934         I915_WRITE(_3D_CHICKEN3,
4935                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4936
4937         /* WaDisableBackToBackFlipFix:vlv */
4938         I915_WRITE(IVB_CHICKEN3,
4939                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4940                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4941
4942         /* WaDisablePSDDualDispatchEnable:vlv */
4943         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4944                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4945                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4946
4947         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4948         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4949                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4950
4951         /* WaApplyL3ControlAndL3ChickenMode:vlv */
4952         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4953         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4954
4955         /* WaForceL3Serialization:vlv */
4956         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4957                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4958
4959         /* WaDisableDopClockGating:vlv */
4960         I915_WRITE(GEN7_ROW_CHICKEN2,
4961                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4962
4963         /* This is required by WaCatErrorRejectionIssue:vlv */
4964         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4965                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4966                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4967
4968         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4969          * gating disable must be set.  Failure to set it results in
4970          * flickering pixels due to Z write ordering failures after
4971          * some amount of runtime in the Mesa "fire" demo, and Unigine
4972          * Sanctuary and Tropics, and apparently anything else with
4973          * alpha test or pixel discard.
4974          *
4975          * According to the spec, bit 11 (RCCUNIT) must also be set,
4976          * but we didn't debug actual testcases to find it out.
4977          *
4978          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4979          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4980          *
4981          * Also apply WaDisableVDSUnitClockGating:vlv and
4982          * WaDisableRCPBUnitClockGating:vlv.
4983          */
4984         I915_WRITE(GEN6_UCGCTL2,
4985                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4986                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4987                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4988                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4989                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4990
4991         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4992
4993         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
4994
4995         I915_WRITE(CACHE_MODE_1,
4996                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4997
4998         /*
4999          * WaDisableVLVClockGating_VBIIssue:vlv
5000          * Disable clock gating on th GCFG unit to prevent a delay
5001          * in the reporting of vblank events.
5002          */
5003         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5004
5005         /* Conservative clock gating settings for now */
5006         I915_WRITE(0x9400, 0xffffffff);
5007         I915_WRITE(0x9404, 0xffffffff);
5008         I915_WRITE(0x9408, 0xffffffff);
5009         I915_WRITE(0x940c, 0xffffffff);
5010         I915_WRITE(0x9410, 0xffffffff);
5011         I915_WRITE(0x9414, 0xffffffff);
5012         I915_WRITE(0x9418, 0xffffffff);
5013 }
5014
5015 static void g4x_init_clock_gating(struct drm_device *dev)
5016 {
5017         struct drm_i915_private *dev_priv = dev->dev_private;
5018         uint32_t dspclk_gate;
5019
5020         I915_WRITE(RENCLK_GATE_D1, 0);
5021         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5022                    GS_UNIT_CLOCK_GATE_DISABLE |
5023                    CL_UNIT_CLOCK_GATE_DISABLE);
5024         I915_WRITE(RAMCLK_GATE_D, 0);
5025         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5026                 OVRUNIT_CLOCK_GATE_DISABLE |
5027                 OVCUNIT_CLOCK_GATE_DISABLE;
5028         if (IS_GM45(dev))
5029                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5030         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5031
5032         /* WaDisableRenderCachePipelinedFlush */
5033         I915_WRITE(CACHE_MODE_0,
5034                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5035
5036         g4x_disable_trickle_feed(dev);
5037 }
5038
5039 static void crestline_init_clock_gating(struct drm_device *dev)
5040 {
5041         struct drm_i915_private *dev_priv = dev->dev_private;
5042
5043         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5044         I915_WRITE(RENCLK_GATE_D2, 0);
5045         I915_WRITE(DSPCLK_GATE_D, 0);
5046         I915_WRITE(RAMCLK_GATE_D, 0);
5047         I915_WRITE16(DEUC, 0);
5048         I915_WRITE(MI_ARB_STATE,
5049                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5050 }
5051
5052 static void broadwater_init_clock_gating(struct drm_device *dev)
5053 {
5054         struct drm_i915_private *dev_priv = dev->dev_private;
5055
5056         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5057                    I965_RCC_CLOCK_GATE_DISABLE |
5058                    I965_RCPB_CLOCK_GATE_DISABLE |
5059                    I965_ISC_CLOCK_GATE_DISABLE |
5060                    I965_FBC_CLOCK_GATE_DISABLE);
5061         I915_WRITE(RENCLK_GATE_D2, 0);
5062         I915_WRITE(MI_ARB_STATE,
5063                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5064 }
5065
5066 static void gen3_init_clock_gating(struct drm_device *dev)
5067 {
5068         struct drm_i915_private *dev_priv = dev->dev_private;
5069         u32 dstate = I915_READ(D_STATE);
5070
5071         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5072                 DSTATE_DOT_CLOCK_GATING;
5073         I915_WRITE(D_STATE, dstate);
5074
5075         if (IS_PINEVIEW(dev))
5076                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5077
5078         /* IIR "flip pending" means done if this bit is set */
5079         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5080 }
5081
5082 static void i85x_init_clock_gating(struct drm_device *dev)
5083 {
5084         struct drm_i915_private *dev_priv = dev->dev_private;
5085
5086         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5087 }
5088
5089 static void i830_init_clock_gating(struct drm_device *dev)
5090 {
5091         struct drm_i915_private *dev_priv = dev->dev_private;
5092
5093         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5094 }
5095
5096 void intel_init_clock_gating(struct drm_device *dev)
5097 {
5098         struct drm_i915_private *dev_priv = dev->dev_private;
5099
5100         dev_priv->display.init_clock_gating(dev);
5101 }
5102
5103 void intel_suspend_hw(struct drm_device *dev)
5104 {
5105         if (HAS_PCH_LPT(dev))
5106                 lpt_suspend_hw(dev);
5107 }
5108
5109 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5110         for (i = 0;                                                     \
5111              i < (power_domains)->power_well_count &&                   \
5112                  ((power_well) = &(power_domains)->power_wells[i]);     \
5113              i++)                                                       \
5114                 if ((power_well)->domains & (domain_mask))
5115
5116 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5117         for (i = (power_domains)->power_well_count - 1;                  \
5118              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5119              i--)                                                        \
5120                 if ((power_well)->domains & (domain_mask))
5121
5122 /**
5123  * We should only use the power well if we explicitly asked the hardware to
5124  * enable it, so check if it's enabled and also check if we've requested it to
5125  * be enabled.
5126  */
5127 static bool hsw_power_well_enabled(struct drm_device *dev,
5128                                    struct i915_power_well *power_well)
5129 {
5130         struct drm_i915_private *dev_priv = dev->dev_private;
5131
5132         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5133                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5134 }
5135
5136 bool intel_display_power_enabled_sw(struct drm_device *dev,
5137                                     enum intel_display_power_domain domain)
5138 {
5139         struct drm_i915_private *dev_priv = dev->dev_private;
5140         struct i915_power_domains *power_domains;
5141
5142         power_domains = &dev_priv->power_domains;
5143
5144         return power_domains->domain_use_count[domain];
5145 }
5146
5147 bool intel_display_power_enabled(struct drm_device *dev,
5148                                  enum intel_display_power_domain domain)
5149 {
5150         struct drm_i915_private *dev_priv = dev->dev_private;
5151         struct i915_power_domains *power_domains;
5152         struct i915_power_well *power_well;
5153         bool is_enabled;
5154         int i;
5155
5156         power_domains = &dev_priv->power_domains;
5157
5158         is_enabled = true;
5159
5160         mutex_lock(&power_domains->lock);
5161         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5162                 if (power_well->always_on)
5163                         continue;
5164
5165                 if (!power_well->is_enabled(dev, power_well)) {
5166                         is_enabled = false;
5167                         break;
5168                 }
5169         }
5170         mutex_unlock(&power_domains->lock);
5171
5172         return is_enabled;
5173 }
5174
5175 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5176 {
5177         struct drm_device *dev = dev_priv->dev;
5178         unsigned long irqflags;
5179
5180         /*
5181          * After we re-enable the power well, if we touch VGA register 0x3d5
5182          * we'll get unclaimed register interrupts. This stops after we write
5183          * anything to the VGA MSR register. The vgacon module uses this
5184          * register all the time, so if we unbind our driver and, as a
5185          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5186          * console_unlock(). So make here we touch the VGA MSR register, making
5187          * sure vgacon can keep working normally without triggering interrupts
5188          * and error messages.
5189          */
5190         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5191         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5192         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5193
5194         if (IS_BROADWELL(dev)) {
5195                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5196                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5197                            dev_priv->de_irq_mask[PIPE_B]);
5198                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5199                            ~dev_priv->de_irq_mask[PIPE_B] |
5200                            GEN8_PIPE_VBLANK);
5201                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5202                            dev_priv->de_irq_mask[PIPE_C]);
5203                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5204                            ~dev_priv->de_irq_mask[PIPE_C] |
5205                            GEN8_PIPE_VBLANK);
5206                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5207                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5208         }
5209 }
5210
5211 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5212 {
5213         struct drm_device *dev = dev_priv->dev;
5214         enum pipe p;
5215         unsigned long irqflags;
5216
5217         /*
5218          * After this, the registers on the pipes that are part of the power
5219          * well will become zero, so we have to adjust our counters according to
5220          * that.
5221          *
5222          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5223          */
5224         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5225         for_each_pipe(p)
5226                 if (p != PIPE_A)
5227                         dev->vblank[p].last = 0;
5228         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5229 }
5230
5231 static void hsw_set_power_well(struct drm_device *dev,
5232                                struct i915_power_well *power_well, bool enable)
5233 {
5234         struct drm_i915_private *dev_priv = dev->dev_private;
5235         bool is_enabled, enable_requested;
5236         uint32_t tmp;
5237
5238         WARN_ON(dev_priv->pc8.enabled);
5239
5240         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5241         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5242         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5243
5244         if (enable) {
5245                 if (!enable_requested)
5246                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5247                                    HSW_PWR_WELL_ENABLE_REQUEST);
5248
5249                 if (!is_enabled) {
5250                         DRM_DEBUG_KMS("Enabling power well\n");
5251                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5252                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5253                                 DRM_ERROR("Timeout enabling power well\n");
5254                 }
5255
5256                 hsw_power_well_post_enable(dev_priv);
5257         } else {
5258                 if (enable_requested) {
5259                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5260                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5261                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5262
5263                         hsw_power_well_post_disable(dev_priv);
5264                 }
5265         }
5266 }
5267
5268 static void __intel_power_well_get(struct drm_device *dev,
5269                                    struct i915_power_well *power_well)
5270 {
5271         struct drm_i915_private *dev_priv = dev->dev_private;
5272
5273         if (!power_well->count++ && power_well->set) {
5274                 hsw_disable_package_c8(dev_priv);
5275                 power_well->set(dev, power_well, true);
5276         }
5277 }
5278
5279 static void __intel_power_well_put(struct drm_device *dev,
5280                                    struct i915_power_well *power_well)
5281 {
5282         struct drm_i915_private *dev_priv = dev->dev_private;
5283
5284         WARN_ON(!power_well->count);
5285
5286         if (!--power_well->count && power_well->set &&
5287             i915_disable_power_well) {
5288                 power_well->set(dev, power_well, false);
5289                 hsw_enable_package_c8(dev_priv);
5290         }
5291 }
5292
5293 void intel_display_power_get(struct drm_device *dev,
5294                              enum intel_display_power_domain domain)
5295 {
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297         struct i915_power_domains *power_domains;
5298         struct i915_power_well *power_well;
5299         int i;
5300
5301         power_domains = &dev_priv->power_domains;
5302
5303         mutex_lock(&power_domains->lock);
5304
5305         for_each_power_well(i, power_well, BIT(domain), power_domains)
5306                 __intel_power_well_get(dev, power_well);
5307
5308         power_domains->domain_use_count[domain]++;
5309
5310         mutex_unlock(&power_domains->lock);
5311 }
5312
5313 void intel_display_power_put(struct drm_device *dev,
5314                              enum intel_display_power_domain domain)
5315 {
5316         struct drm_i915_private *dev_priv = dev->dev_private;
5317         struct i915_power_domains *power_domains;
5318         struct i915_power_well *power_well;
5319         int i;
5320
5321         power_domains = &dev_priv->power_domains;
5322
5323         mutex_lock(&power_domains->lock);
5324
5325         WARN_ON(!power_domains->domain_use_count[domain]);
5326         power_domains->domain_use_count[domain]--;
5327
5328         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5329                 __intel_power_well_put(dev, power_well);
5330
5331         mutex_unlock(&power_domains->lock);
5332 }
5333
5334 static struct i915_power_domains *hsw_pwr;
5335
5336 /* Display audio driver power well request */
5337 void i915_request_power_well(void)
5338 {
5339         struct drm_i915_private *dev_priv;
5340
5341         if (WARN_ON(!hsw_pwr))
5342                 return;
5343
5344         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5345                                 power_domains);
5346         intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5347 }
5348 EXPORT_SYMBOL_GPL(i915_request_power_well);
5349
5350 /* Display audio driver power well release */
5351 void i915_release_power_well(void)
5352 {
5353         struct drm_i915_private *dev_priv;
5354
5355         if (WARN_ON(!hsw_pwr))
5356                 return;
5357
5358         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5359                                 power_domains);
5360         intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5361 }
5362 EXPORT_SYMBOL_GPL(i915_release_power_well);
5363
5364 static struct i915_power_well i9xx_always_on_power_well[] = {
5365         {
5366                 .name = "always-on",
5367                 .always_on = 1,
5368                 .domains = POWER_DOMAIN_MASK,
5369         },
5370 };
5371
5372 static struct i915_power_well hsw_power_wells[] = {
5373         {
5374                 .name = "always-on",
5375                 .always_on = 1,
5376                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5377         },
5378         {
5379                 .name = "display",
5380                 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5381                 .is_enabled = hsw_power_well_enabled,
5382                 .set = hsw_set_power_well,
5383         },
5384 };
5385
5386 static struct i915_power_well bdw_power_wells[] = {
5387         {
5388                 .name = "always-on",
5389                 .always_on = 1,
5390                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5391         },
5392         {
5393                 .name = "display",
5394                 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5395                 .is_enabled = hsw_power_well_enabled,
5396                 .set = hsw_set_power_well,
5397         },
5398 };
5399
5400 #define set_power_wells(power_domains, __power_wells) ({                \
5401         (power_domains)->power_wells = (__power_wells);                 \
5402         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
5403 })
5404
5405 int intel_power_domains_init(struct drm_device *dev)
5406 {
5407         struct drm_i915_private *dev_priv = dev->dev_private;
5408         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5409
5410         mutex_init(&power_domains->lock);
5411
5412         /*
5413          * The enabling order will be from lower to higher indexed wells,
5414          * the disabling order is reversed.
5415          */
5416         if (IS_HASWELL(dev)) {
5417                 set_power_wells(power_domains, hsw_power_wells);
5418                 hsw_pwr = power_domains;
5419         } else if (IS_BROADWELL(dev)) {
5420                 set_power_wells(power_domains, bdw_power_wells);
5421                 hsw_pwr = power_domains;
5422         } else {
5423                 set_power_wells(power_domains, i9xx_always_on_power_well);
5424         }
5425
5426         return 0;
5427 }
5428
5429 void intel_power_domains_remove(struct drm_device *dev)
5430 {
5431         hsw_pwr = NULL;
5432 }
5433
5434 static void intel_power_domains_resume(struct drm_device *dev)
5435 {
5436         struct drm_i915_private *dev_priv = dev->dev_private;
5437         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5438         struct i915_power_well *power_well;
5439         int i;
5440
5441         mutex_lock(&power_domains->lock);
5442         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5443                 if (power_well->set)
5444                         power_well->set(dev, power_well, power_well->count > 0);
5445         }
5446         mutex_unlock(&power_domains->lock);
5447 }
5448
5449 /*
5450  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5451  * when not needed anymore. We have 4 registers that can request the power well
5452  * to be enabled, and it will only be disabled if none of the registers is
5453  * requesting it to be enabled.
5454  */
5455 void intel_power_domains_init_hw(struct drm_device *dev)
5456 {
5457         struct drm_i915_private *dev_priv = dev->dev_private;
5458
5459         /* For now, we need the power well to be always enabled. */
5460         intel_display_set_init_power(dev, true);
5461         intel_power_domains_resume(dev);
5462
5463         if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5464                 return;
5465
5466         /* We're taking over the BIOS, so clear any requests made by it since
5467          * the driver is in charge now. */
5468         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5469                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5470 }
5471
5472 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5473 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5474 {
5475         hsw_disable_package_c8(dev_priv);
5476 }
5477
5478 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5479 {
5480         hsw_enable_package_c8(dev_priv);
5481 }
5482
5483 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5484 {
5485         struct drm_device *dev = dev_priv->dev;
5486         struct device *device = &dev->pdev->dev;
5487
5488         if (!HAS_RUNTIME_PM(dev))
5489                 return;
5490
5491         pm_runtime_get_sync(device);
5492         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5493 }
5494
5495 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5496 {
5497         struct drm_device *dev = dev_priv->dev;
5498         struct device *device = &dev->pdev->dev;
5499
5500         if (!HAS_RUNTIME_PM(dev))
5501                 return;
5502
5503         pm_runtime_mark_last_busy(device);
5504         pm_runtime_put_autosuspend(device);
5505 }
5506
5507 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5508 {
5509         struct drm_device *dev = dev_priv->dev;
5510         struct device *device = &dev->pdev->dev;
5511
5512         dev_priv->pm.suspended = false;
5513
5514         if (!HAS_RUNTIME_PM(dev))
5515                 return;
5516
5517         pm_runtime_set_active(device);
5518
5519         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5520         pm_runtime_mark_last_busy(device);
5521         pm_runtime_use_autosuspend(device);
5522 }
5523
5524 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5525 {
5526         struct drm_device *dev = dev_priv->dev;
5527         struct device *device = &dev->pdev->dev;
5528
5529         if (!HAS_RUNTIME_PM(dev))
5530                 return;
5531
5532         /* Make sure we're not suspended first. */
5533         pm_runtime_get_sync(device);
5534         pm_runtime_disable(device);
5535 }
5536
5537 /* Set up chip specific power management-related functions */
5538 void intel_init_pm(struct drm_device *dev)
5539 {
5540         struct drm_i915_private *dev_priv = dev->dev_private;
5541
5542         if (HAS_FBC(dev)) {
5543                 if (INTEL_INFO(dev)->gen >= 7) {
5544                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5545                         dev_priv->display.enable_fbc = gen7_enable_fbc;
5546                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5547                 } else if (INTEL_INFO(dev)->gen >= 5) {
5548                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5549                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5550                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5551                 } else if (IS_GM45(dev)) {
5552                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5553                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5554                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5555                 } else {
5556                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5557                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5558                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5559
5560                         /* This value was pulled out of someone's hat */
5561                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
5562                 }
5563         }
5564
5565         /* For cxsr */
5566         if (IS_PINEVIEW(dev))
5567                 i915_pineview_get_mem_freq(dev);
5568         else if (IS_GEN5(dev))
5569                 i915_ironlake_get_mem_freq(dev);
5570
5571         /* For FIFO watermark updates */
5572         if (HAS_PCH_SPLIT(dev)) {
5573                 intel_setup_wm_latency(dev);
5574
5575                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
5576                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5577                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
5578                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
5579                         dev_priv->display.update_wm = ilk_update_wm;
5580                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
5581                 } else {
5582                         DRM_DEBUG_KMS("Failed to read display plane latency. "
5583                                       "Disable CxSR\n");
5584                 }
5585
5586                 if (IS_GEN5(dev))
5587                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5588                 else if (IS_GEN6(dev))
5589                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5590                 else if (IS_IVYBRIDGE(dev))
5591                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5592                 else if (IS_HASWELL(dev))
5593                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5594                 else if (INTEL_INFO(dev)->gen == 8)
5595                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
5596         } else if (IS_VALLEYVIEW(dev)) {
5597                 dev_priv->display.update_wm = valleyview_update_wm;
5598                 dev_priv->display.init_clock_gating =
5599                         valleyview_init_clock_gating;
5600         } else if (IS_PINEVIEW(dev)) {
5601                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5602                                             dev_priv->is_ddr3,
5603                                             dev_priv->fsb_freq,
5604                                             dev_priv->mem_freq)) {
5605                         DRM_INFO("failed to find known CxSR latency "
5606                                  "(found ddr%s fsb freq %d, mem freq %d), "
5607                                  "disabling CxSR\n",
5608                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5609                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5610                         /* Disable CxSR and never update its watermark again */
5611                         pineview_disable_cxsr(dev);
5612                         dev_priv->display.update_wm = NULL;
5613                 } else
5614                         dev_priv->display.update_wm = pineview_update_wm;
5615                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5616         } else if (IS_G4X(dev)) {
5617                 dev_priv->display.update_wm = g4x_update_wm;
5618                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5619         } else if (IS_GEN4(dev)) {
5620                 dev_priv->display.update_wm = i965_update_wm;
5621                 if (IS_CRESTLINE(dev))
5622                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5623                 else if (IS_BROADWATER(dev))
5624                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5625         } else if (IS_GEN3(dev)) {
5626                 dev_priv->display.update_wm = i9xx_update_wm;
5627                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5628                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5629         } else if (IS_GEN2(dev)) {
5630                 if (INTEL_INFO(dev)->num_pipes == 1) {
5631                         dev_priv->display.update_wm = i845_update_wm;
5632                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5633                 } else {
5634                         dev_priv->display.update_wm = i9xx_update_wm;
5635                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5636                 }
5637
5638                 if (IS_I85X(dev) || IS_I865G(dev))
5639                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5640                 else
5641                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
5642         } else {
5643                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
5644         }
5645 }
5646
5647 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5648 {
5649         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5650
5651         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5652                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5653                 return -EAGAIN;
5654         }
5655
5656         I915_WRITE(GEN6_PCODE_DATA, *val);
5657         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5658
5659         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5660                      500)) {
5661                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5662                 return -ETIMEDOUT;
5663         }
5664
5665         *val = I915_READ(GEN6_PCODE_DATA);
5666         I915_WRITE(GEN6_PCODE_DATA, 0);
5667
5668         return 0;
5669 }
5670
5671 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5672 {
5673         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5674
5675         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5676                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5677                 return -EAGAIN;
5678         }
5679
5680         I915_WRITE(GEN6_PCODE_DATA, val);
5681         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5682
5683         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5684                      500)) {
5685                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5686                 return -ETIMEDOUT;
5687         }
5688
5689         I915_WRITE(GEN6_PCODE_DATA, 0);
5690
5691         return 0;
5692 }
5693
5694 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
5695 {
5696         int div;
5697
5698         /* 4 x czclk */
5699         switch (dev_priv->mem_freq) {
5700         case 800:
5701                 div = 10;
5702                 break;
5703         case 1066:
5704                 div = 12;
5705                 break;
5706         case 1333:
5707                 div = 16;
5708                 break;
5709         default:
5710                 return -1;
5711         }
5712
5713         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
5714 }
5715
5716 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
5717 {
5718         int mul;
5719
5720         /* 4 x czclk */
5721         switch (dev_priv->mem_freq) {
5722         case 800:
5723                 mul = 10;
5724                 break;
5725         case 1066:
5726                 mul = 12;
5727                 break;
5728         case 1333:
5729                 mul = 16;
5730                 break;
5731         default:
5732                 return -1;
5733         }
5734
5735         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
5736 }
5737
5738 void intel_pm_setup(struct drm_device *dev)
5739 {
5740         struct drm_i915_private *dev_priv = dev->dev_private;
5741
5742         mutex_init(&dev_priv->rps.hw_lock);
5743
5744         mutex_init(&dev_priv->pc8.lock);
5745         dev_priv->pc8.requirements_met = false;
5746         dev_priv->pc8.gpu_idle = false;
5747         dev_priv->pc8.irqs_disabled = false;
5748         dev_priv->pc8.enabled = false;
5749         dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
5750         INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
5751         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5752                           intel_gen6_powersave_work);
5753 }