drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static bool intel_crtc_active(struct drm_crtc *crtc)
  48 {
  49         /* Be paranoid as we can arrive here with only partial
  50          * state retrieved from the hardware during setup.
  51          */
  52         return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  53 }
  54
  55 static void i8xx_disable_fbc(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         u32 fbc_ctl;
  59
  60         /* Disable compression */
  61         fbc_ctl = I915_READ(FBC_CONTROL);
  62         if ((fbc_ctl & FBC_CTL_EN) == 0)
  63                 return;
  64
  65         fbc_ctl &= ~FBC_CTL_EN;
  66         I915_WRITE(FBC_CONTROL, fbc_ctl);
  67
  68         /* Wait for compressing bit to clear */
  69         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  70                 DRM_DEBUG_KMS("FBC idle timed out\n");
  71                 return;
  72         }
  73
  74         DRM_DEBUG_KMS("disabled FBC\n");
  75 }
  76
  77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  78 {
  79         struct drm_device *dev = crtc->dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct drm_framebuffer *fb = crtc->fb;
  82         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  83         struct drm_i915_gem_object *obj = intel_fb->obj;
  84         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  85         int cfb_pitch;
  86         int plane, i;
  87         u32 fbc_ctl, fbc_ctl2;
  88
  89         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  90         if (fb->pitches[0] < cfb_pitch)
  91                 cfb_pitch = fb->pitches[0];
  92
  93         /* FBC_CTL wants 64B units */
  94         cfb_pitch = (cfb_pitch / 64) - 1;
  95         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  96
  97         /* Clear old tags */
  98         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  99                 I915_WRITE(FBC_TAG + (i * 4), 0);
 100
 101         /* Set it up... */
 102         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 103         fbc_ctl2 |= plane;
 104         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 105         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 106
 107         /* enable it... */
 108         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 109         if (IS_I945GM(dev))
 110                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 111         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 112         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 113         fbc_ctl |= obj->fence_reg;
 114         I915_WRITE(FBC_CONTROL, fbc_ctl);
 115
 116         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
 117                       cfb_pitch, crtc->y, intel_crtc->plane);
 118 }
 119
 120 static bool i8xx_fbc_enabled(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123
 124         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 125 }
 126
 127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 128 {
 129         struct drm_device *dev = crtc->dev;
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         struct drm_framebuffer *fb = crtc->fb;
 132         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 133         struct drm_i915_gem_object *obj = intel_fb->obj;
 134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 135         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 136         unsigned long stall_watermark = 200;
 137         u32 dpfc_ctl;
 138
 139         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 140         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 141         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 142
 143         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 144                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 145                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 146         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 147
 148         /* enable it... */
 149         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 150
 151         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 152 }
 153
 154 static void g4x_disable_fbc(struct drm_device *dev)
 155 {
 156         struct drm_i915_private *dev_priv = dev->dev_private;
 157         u32 dpfc_ctl;
 158
 159         /* Disable compression */
 160         dpfc_ctl = I915_READ(DPFC_CONTROL);
 161         if (dpfc_ctl & DPFC_CTL_EN) {
 162                 dpfc_ctl &= ~DPFC_CTL_EN;
 163                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 164
 165                 DRM_DEBUG_KMS("disabled FBC\n");
 166         }
 167 }
 168
 169 static bool g4x_fbc_enabled(struct drm_device *dev)
 170 {
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172
 173         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 174 }
 175
 176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 177 {
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         u32 blt_ecoskpd;
 180
 181         /* Make sure blitter notifies FBC of writes */
 182         gen6_gt_force_wake_get(dev_priv);
 183         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 184         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 185                 GEN6_BLITTER_LOCK_SHIFT;
 186         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 187         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 188         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 189         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 190                          GEN6_BLITTER_LOCK_SHIFT);
 191         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 192         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 193         gen6_gt_force_wake_put(dev_priv);
 194 }
 195
 196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 197 {
 198         struct drm_device *dev = crtc->dev;
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         struct drm_framebuffer *fb = crtc->fb;
 201         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 202         struct drm_i915_gem_object *obj = intel_fb->obj;
 203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 204         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 205         unsigned long stall_watermark = 200;
 206         u32 dpfc_ctl;
 207
 208         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 209         dpfc_ctl &= DPFC_RESERVED;
 210         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 211         /* Set persistent mode for front-buffer rendering, ala X. */
 212         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 213         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 214         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 215
 216         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 217                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 218                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 219         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 220         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 221         /* enable it... */
 222         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 223
 224         if (IS_GEN6(dev)) {
 225                 I915_WRITE(SNB_DPFC_CTL_SA,
 226                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 227                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 228                 sandybridge_blit_fbc_update(dev);
 229         }
 230
 231         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 232 }
 233
 234 static void ironlake_disable_fbc(struct drm_device *dev)
 235 {
 236         struct drm_i915_private *dev_priv = dev->dev_private;
 237         u32 dpfc_ctl;
 238
 239         /* Disable compression */
 240         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 241         if (dpfc_ctl & DPFC_CTL_EN) {
 242                 dpfc_ctl &= ~DPFC_CTL_EN;
 243                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 244
 245                 DRM_DEBUG_KMS("disabled FBC\n");
 246         }
 247 }
 248
 249 static bool ironlake_fbc_enabled(struct drm_device *dev)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252
 253         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 254 }
 255
 256 bool intel_fbc_enabled(struct drm_device *dev)
 257 {
 258         struct drm_i915_private *dev_priv = dev->dev_private;
 259
 260         if (!dev_priv->display.fbc_enabled)
 261                 return false;
 262
 263         return dev_priv->display.fbc_enabled(dev);
 264 }
 265
 266 static void intel_fbc_work_fn(struct work_struct *__work)
 267 {
 268         struct intel_fbc_work *work =
 269                 container_of(to_delayed_work(__work),
 270                              struct intel_fbc_work, work);
 271         struct drm_device *dev = work->crtc->dev;
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         mutex_lock(&dev->struct_mutex);
 275         if (work == dev_priv->fbc_work) {
 276                 /* Double check that we haven't switched fb without cancelling
 277                  * the prior work.
 278                  */
 279                 if (work->crtc->fb == work->fb) {
 280                         dev_priv->display.enable_fbc(work->crtc,
 281                                                      work->interval);
 282
 283                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 284                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 285                         dev_priv->cfb_y = work->crtc->y;
 286                 }
 287
 288                 dev_priv->fbc_work = NULL;
 289         }
 290         mutex_unlock(&dev->struct_mutex);
 291
 292         kfree(work);
 293 }
 294
 295 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 296 {
 297         if (dev_priv->fbc_work == NULL)
 298                 return;
 299
 300         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 301
 302         /* Synchronisation is provided by struct_mutex and checking of
 303          * dev_priv->fbc_work, so we can perform the cancellation
 304          * entirely asynchronously.
 305          */
 306         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 307                 /* tasklet was killed before being run, clean up */
 308                 kfree(dev_priv->fbc_work);
 309
 310         /* Mark the work as no longer wanted so that if it does
 311          * wake-up (because the work was already running and waiting
 312          * for our mutex), it will discover that is no longer
 313          * necessary to run.
 314          */
 315         dev_priv->fbc_work = NULL;
 316 }
 317
 318 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 319 {
 320         struct intel_fbc_work *work;
 321         struct drm_device *dev = crtc->dev;
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         if (!dev_priv->display.enable_fbc)
 325                 return;
 326
 327         intel_cancel_fbc_work(dev_priv);
 328
 329         work = kzalloc(sizeof *work, GFP_KERNEL);
 330         if (work == NULL) {
 331                 dev_priv->display.enable_fbc(crtc, interval);
 332                 return;
 333         }
 334
 335         work->crtc = crtc;
 336         work->fb = crtc->fb;
 337         work->interval = interval;
 338         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 339
 340         dev_priv->fbc_work = work;
 341
 342         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 343
 344         /* Delay the actual enabling to let pageflipping cease and the
 345          * display to settle before starting the compression. Note that
 346          * this delay also serves a second purpose: it allows for a
 347          * vblank to pass after disabling the FBC before we attempt
 348          * to modify the control registers.
 349          *
 350          * A more complicated solution would involve tracking vblanks
 351          * following the termination of the page-flipping sequence
 352          * and indeed performing the enable as a co-routine and not
 353          * waiting synchronously upon the vblank.
 354          */
 355         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 356 }
 357
 358 void intel_disable_fbc(struct drm_device *dev)
 359 {
 360         struct drm_i915_private *dev_priv = dev->dev_private;
 361
 362         intel_cancel_fbc_work(dev_priv);
 363
 364         if (!dev_priv->display.disable_fbc)
 365                 return;
 366
 367         dev_priv->display.disable_fbc(dev);
 368         dev_priv->cfb_plane = -1;
 369 }
 370
 371 /**
 372  * intel_update_fbc - enable/disable FBC as needed
 373  * @dev: the drm_device
 374  *
 375  * Set up the framebuffer compression hardware at mode set time.  We
 376  * enable it if possible:
 377  *   - plane A only (on pre-965)
 378  *   - no pixel mulitply/line duplication
 379  *   - no alpha buffer discard
 380  *   - no dual wide
 381  *   - framebuffer <= 2048 in width, 1536 in height
 382  *
 383  * We can't assume that any compression will take place (worst case),
 384  * so the compressed buffer has to be the same size as the uncompressed
 385  * one.  It also must reside (along with the line length buffer) in
 386  * stolen memory.
 387  *
 388  * We need to enable/disable FBC on a global basis.
 389  */
 390 void intel_update_fbc(struct drm_device *dev)
 391 {
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         struct drm_crtc *crtc = NULL, *tmp_crtc;
 394         struct intel_crtc *intel_crtc;
 395         struct drm_framebuffer *fb;
 396         struct intel_framebuffer *intel_fb;
 397         struct drm_i915_gem_object *obj;
 398         int enable_fbc;
 399
 400         if (!i915_powersave)
 401                 return;
 402
 403         if (!I915_HAS_FBC(dev))
 404                 return;
 405
 406         /*
 407          * If FBC is already on, we just have to verify that we can
 408          * keep it that way...
 409          * Need to disable if:
 410          *   - more than one pipe is active
 411          *   - changing FBC params (stride, fence, mode)
 412          *   - new fb is too large to fit in compressed buffer
 413          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 414          */
 415         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 416                 if (intel_crtc_active(tmp_crtc) &&
 417                     !to_intel_crtc(tmp_crtc)->primary_disabled) {
 418                         if (crtc) {
 419                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 420                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 421                                 goto out_disable;
 422                         }
 423                         crtc = tmp_crtc;
 424                 }
 425         }
 426
 427         if (!crtc || crtc->fb == NULL) {
 428                 DRM_DEBUG_KMS("no output, disabling\n");
 429                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 430                 goto out_disable;
 431         }
 432
 433         intel_crtc = to_intel_crtc(crtc);
 434         fb = crtc->fb;
 435         intel_fb = to_intel_framebuffer(fb);
 436         obj = intel_fb->obj;
 437
 438         enable_fbc = i915_enable_fbc;
 439         if (enable_fbc < 0) {
 440                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 441                 enable_fbc = 1;
 442                 if (INTEL_INFO(dev)->gen <= 6)
 443                         enable_fbc = 0;
 444         }
 445         if (!enable_fbc) {
 446                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 447                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 448                 goto out_disable;
 449         }
 450         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 451             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 452                 DRM_DEBUG_KMS("mode incompatible with compression, "
 453                               "disabling\n");
 454                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 455                 goto out_disable;
 456         }
 457         if ((crtc->mode.hdisplay > 2048) ||
 458             (crtc->mode.vdisplay > 1536)) {
 459                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 460                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 461                 goto out_disable;
 462         }
 463         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 464                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 465                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 466                 goto out_disable;
 467         }
 468
 469         /* The use of a CPU fence is mandatory in order to detect writes
 470          * by the CPU to the scanout and trigger updates to the FBC.
 471          */
 472         if (obj->tiling_mode != I915_TILING_X ||
 473             obj->fence_reg == I915_FENCE_REG_NONE) {
 474                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 475                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 476                 goto out_disable;
 477         }
 478
 479         /* If the kernel debugger is active, always disable compression */
 480         if (in_dbg_master())
 481                 goto out_disable;
 482
 483         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 484                 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size);
 485                 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
 486                 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 487                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 488                 goto out_disable;
 489         }
 490
 491         /* If the scanout has not changed, don't modify the FBC settings.
 492          * Note that we make the fundamental assumption that the fb->obj
 493          * cannot be unpinned (and have its GTT offset and fence revoked)
 494          * without first being decoupled from the scanout and FBC disabled.
 495          */
 496         if (dev_priv->cfb_plane == intel_crtc->plane &&
 497             dev_priv->cfb_fb == fb->base.id &&
 498             dev_priv->cfb_y == crtc->y)
 499                 return;
 500
 501         if (intel_fbc_enabled(dev)) {
 502                 /* We update FBC along two paths, after changing fb/crtc
 503                  * configuration (modeswitching) and after page-flipping
 504                  * finishes. For the latter, we know that not only did
 505                  * we disable the FBC at the start of the page-flip
 506                  * sequence, but also more than one vblank has passed.
 507                  *
 508                  * For the former case of modeswitching, it is possible
 509                  * to switch between two FBC valid configurations
 510                  * instantaneously so we do need to disable the FBC
 511                  * before we can modify its control registers. We also
 512                  * have to wait for the next vblank for that to take
 513                  * effect. However, since we delay enabling FBC we can
 514                  * assume that a vblank has passed since disabling and
 515                  * that we can safely alter the registers in the deferred
 516                  * callback.
 517                  *
 518                  * In the scenario that we go from a valid to invalid
 519                  * and then back to valid FBC configuration we have
 520                  * no strict enforcement that a vblank occurred since
 521                  * disabling the FBC. However, along all current pipe
 522                  * disabling paths we do need to wait for a vblank at
 523                  * some point. And we wait before enabling FBC anyway.
 524                  */
 525                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 526                 intel_disable_fbc(dev);
 527         }
 528
 529         intel_enable_fbc(crtc, 500);
 530         return;
 531
 532 out_disable:
 533         /* Multiple disables should be harmless */
 534         if (intel_fbc_enabled(dev)) {
 535                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 536                 intel_disable_fbc(dev);
 537         }
 538         i915_gem_stolen_cleanup_compression(dev);
 539 }
 540
 541 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 542 {
 543         drm_i915_private_t *dev_priv = dev->dev_private;
 544         u32 tmp;
 545
 546         tmp = I915_READ(CLKCFG);
 547
 548         switch (tmp & CLKCFG_FSB_MASK) {
 549         case CLKCFG_FSB_533:
 550                 dev_priv->fsb_freq = 533; /* 133*4 */
 551                 break;
 552         case CLKCFG_FSB_800:
 553                 dev_priv->fsb_freq = 800; /* 200*4 */
 554                 break;
 555         case CLKCFG_FSB_667:
 556                 dev_priv->fsb_freq =  667; /* 167*4 */
 557                 break;
 558         case CLKCFG_FSB_400:
 559                 dev_priv->fsb_freq = 400; /* 100*4 */
 560                 break;
 561         }
 562
 563         switch (tmp & CLKCFG_MEM_MASK) {
 564         case CLKCFG_MEM_533:
 565                 dev_priv->mem_freq = 533;
 566                 break;
 567         case CLKCFG_MEM_667:
 568                 dev_priv->mem_freq = 667;
 569                 break;
 570         case CLKCFG_MEM_800:
 571                 dev_priv->mem_freq = 800;
 572                 break;
 573         }
 574
 575         /* detect pineview DDR3 setting */
 576         tmp = I915_READ(CSHRDDR3CTL);
 577         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 578 }
 579
 580 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 581 {
 582         drm_i915_private_t *dev_priv = dev->dev_private;
 583         u16 ddrpll, csipll;
 584
 585         ddrpll = I915_READ16(DDRMPLL1);
 586         csipll = I915_READ16(CSIPLL0);
 587
 588         switch (ddrpll & 0xff) {
 589         case 0xc:
 590                 dev_priv->mem_freq = 800;
 591                 break;
 592         case 0x10:
 593                 dev_priv->mem_freq = 1066;
 594                 break;
 595         case 0x14:
 596                 dev_priv->mem_freq = 1333;
 597                 break;
 598         case 0x18:
 599                 dev_priv->mem_freq = 1600;
 600                 break;
 601         default:
 602                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 603                                  ddrpll & 0xff);
 604                 dev_priv->mem_freq = 0;
 605                 break;
 606         }
 607
 608         dev_priv->ips.r_t = dev_priv->mem_freq;
 609
 610         switch (csipll & 0x3ff) {
 611         case 0x00c:
 612                 dev_priv->fsb_freq = 3200;
 613                 break;
 614         case 0x00e:
 615                 dev_priv->fsb_freq = 3733;
 616                 break;
 617         case 0x010:
 618                 dev_priv->fsb_freq = 4266;
 619                 break;
 620         case 0x012:
 621                 dev_priv->fsb_freq = 4800;
 622                 break;
 623         case 0x014:
 624                 dev_priv->fsb_freq = 5333;
 625                 break;
 626         case 0x016:
 627                 dev_priv->fsb_freq = 5866;
 628                 break;
 629         case 0x018:
 630                 dev_priv->fsb_freq = 6400;
 631                 break;
 632         default:
 633                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 634                                  csipll & 0x3ff);
 635                 dev_priv->fsb_freq = 0;
 636                 break;
 637         }
 638
 639         if (dev_priv->fsb_freq == 3200) {
 640                 dev_priv->ips.c_m = 0;
 641         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 642                 dev_priv->ips.c_m = 1;
 643         } else {
 644                 dev_priv->ips.c_m = 2;
 645         }
 646 }
 647
 648 static const struct cxsr_latency cxsr_latency_table[] = {
 649         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 650         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 651         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 652         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 653         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 654
 655         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 656         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 657         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 658         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 659         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 660
 661         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 662         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 663         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 664         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 665         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 666
 667         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 668         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 669         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 670         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 671         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 672
 673         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 674         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 675         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 676         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 677         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 678
 679         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 680         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 681         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 682         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 683         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 684 };
 685
 686 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 687                                                          int is_ddr3,
 688                                                          int fsb,
 689                                                          int mem)
 690 {
 691         const struct cxsr_latency *latency;
 692         int i;
 693
 694         if (fsb == 0 || mem == 0)
 695                 return NULL;
 696
 697         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 698                 latency = &cxsr_latency_table[i];
 699                 if (is_desktop == latency->is_desktop &&
 700                     is_ddr3 == latency->is_ddr3 &&
 701                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 702                         return latency;
 703         }
 704
 705         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 706
 707         return NULL;
 708 }
 709
 710 static void pineview_disable_cxsr(struct drm_device *dev)
 711 {
 712         struct drm_i915_private *dev_priv = dev->dev_private;
 713
 714         /* deactivate cxsr */
 715         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 716 }
 717
 718 /*
 719  * Latency for FIFO fetches is dependent on several factors:
 720  *   - memory configuration (speed, channels)
 721  *   - chipset
 722  *   - current MCH state
 723  * It can be fairly high in some situations, so here we assume a fairly
 724  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 725  * set this value too high, the FIFO will fetch frequently to stay full)
 726  * and power consumption (set it too low to save power and we might see
 727  * FIFO underruns and display "flicker").
 728  *
 729  * A value of 5us seems to be a good balance; safe for very low end
 730  * platforms but not overly aggressive on lower latency configs.
 731  */
 732 static const int latency_ns = 5000;
 733
 734 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 735 {
 736         struct drm_i915_private *dev_priv = dev->dev_private;
 737         uint32_t dsparb = I915_READ(DSPARB);
 738         int size;
 739
 740         size = dsparb & 0x7f;
 741         if (plane)
 742                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 743
 744         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 745                       plane ? "B" : "A", size);
 746
 747         return size;
 748 }
 749
 750 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 751 {
 752         struct drm_i915_private *dev_priv = dev->dev_private;
 753         uint32_t dsparb = I915_READ(DSPARB);
 754         int size;
 755
 756         size = dsparb & 0x1ff;
 757         if (plane)
 758                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 759         size >>= 1; /* Convert to cachelines */
 760
 761         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 762                       plane ? "B" : "A", size);
 763
 764         return size;
 765 }
 766
 767 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 768 {
 769         struct drm_i915_private *dev_priv = dev->dev_private;
 770         uint32_t dsparb = I915_READ(DSPARB);
 771         int size;
 772
 773         size = dsparb & 0x7f;
 774         size >>= 2; /* Convert to cachelines */
 775
 776         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 777                       plane ? "B" : "A",
 778                       size);
 779
 780         return size;
 781 }
 782
 783 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 784 {
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         uint32_t dsparb = I915_READ(DSPARB);
 787         int size;
 788
 789         size = dsparb & 0x7f;
 790         size >>= 1; /* Convert to cachelines */
 791
 792         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 793                       plane ? "B" : "A", size);
 794
 795         return size;
 796 }
 797
 798 /* Pineview has different values for various configs */
 799 static const struct intel_watermark_params pineview_display_wm = {
 800         PINEVIEW_DISPLAY_FIFO,
 801         PINEVIEW_MAX_WM,
 802         PINEVIEW_DFT_WM,
 803         PINEVIEW_GUARD_WM,
 804         PINEVIEW_FIFO_LINE_SIZE
 805 };
 806 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 807         PINEVIEW_DISPLAY_FIFO,
 808         PINEVIEW_MAX_WM,
 809         PINEVIEW_DFT_HPLLOFF_WM,
 810         PINEVIEW_GUARD_WM,
 811         PINEVIEW_FIFO_LINE_SIZE
 812 };
 813 static const struct intel_watermark_params pineview_cursor_wm = {
 814         PINEVIEW_CURSOR_FIFO,
 815         PINEVIEW_CURSOR_MAX_WM,
 816         PINEVIEW_CURSOR_DFT_WM,
 817         PINEVIEW_CURSOR_GUARD_WM,
 818         PINEVIEW_FIFO_LINE_SIZE,
 819 };
 820 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 821         PINEVIEW_CURSOR_FIFO,
 822         PINEVIEW_CURSOR_MAX_WM,
 823         PINEVIEW_CURSOR_DFT_WM,
 824         PINEVIEW_CURSOR_GUARD_WM,
 825         PINEVIEW_FIFO_LINE_SIZE
 826 };
 827 static const struct intel_watermark_params g4x_wm_info = {
 828         G4X_FIFO_SIZE,
 829         G4X_MAX_WM,
 830         G4X_MAX_WM,
 831         2,
 832         G4X_FIFO_LINE_SIZE,
 833 };
 834 static const struct intel_watermark_params g4x_cursor_wm_info = {
 835         I965_CURSOR_FIFO,
 836         I965_CURSOR_MAX_WM,
 837         I965_CURSOR_DFT_WM,
 838         2,
 839         G4X_FIFO_LINE_SIZE,
 840 };
 841 static const struct intel_watermark_params valleyview_wm_info = {
 842         VALLEYVIEW_FIFO_SIZE,
 843         VALLEYVIEW_MAX_WM,
 844         VALLEYVIEW_MAX_WM,
 845         2,
 846         G4X_FIFO_LINE_SIZE,
 847 };
 848 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 849         I965_CURSOR_FIFO,
 850         VALLEYVIEW_CURSOR_MAX_WM,
 851         I965_CURSOR_DFT_WM,
 852         2,
 853         G4X_FIFO_LINE_SIZE,
 854 };
 855 static const struct intel_watermark_params i965_cursor_wm_info = {
 856         I965_CURSOR_FIFO,
 857         I965_CURSOR_MAX_WM,
 858         I965_CURSOR_DFT_WM,
 859         2,
 860         I915_FIFO_LINE_SIZE,
 861 };
 862 static const struct intel_watermark_params i945_wm_info = {
 863         I945_FIFO_SIZE,
 864         I915_MAX_WM,
 865         1,
 866         2,
 867         I915_FIFO_LINE_SIZE
 868 };
 869 static const struct intel_watermark_params i915_wm_info = {
 870         I915_FIFO_SIZE,
 871         I915_MAX_WM,
 872         1,
 873         2,
 874         I915_FIFO_LINE_SIZE
 875 };
 876 static const struct intel_watermark_params i855_wm_info = {
 877         I855GM_FIFO_SIZE,
 878         I915_MAX_WM,
 879         1,
 880         2,
 881         I830_FIFO_LINE_SIZE
 882 };
 883 static const struct intel_watermark_params i830_wm_info = {
 884         I830_FIFO_SIZE,
 885         I915_MAX_WM,
 886         1,
 887         2,
 888         I830_FIFO_LINE_SIZE
 889 };
 890
 891 static const struct intel_watermark_params ironlake_display_wm_info = {
 892         ILK_DISPLAY_FIFO,
 893         ILK_DISPLAY_MAXWM,
 894         ILK_DISPLAY_DFTWM,
 895         2,
 896         ILK_FIFO_LINE_SIZE
 897 };
 898 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 899         ILK_CURSOR_FIFO,
 900         ILK_CURSOR_MAXWM,
 901         ILK_CURSOR_DFTWM,
 902         2,
 903         ILK_FIFO_LINE_SIZE
 904 };
 905 static const struct intel_watermark_params ironlake_display_srwm_info = {
 906         ILK_DISPLAY_SR_FIFO,
 907         ILK_DISPLAY_MAX_SRWM,
 908         ILK_DISPLAY_DFT_SRWM,
 909         2,
 910         ILK_FIFO_LINE_SIZE
 911 };
 912 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 913         ILK_CURSOR_SR_FIFO,
 914         ILK_CURSOR_MAX_SRWM,
 915         ILK_CURSOR_DFT_SRWM,
 916         2,
 917         ILK_FIFO_LINE_SIZE
 918 };
 919
 920 static const struct intel_watermark_params sandybridge_display_wm_info = {
 921         SNB_DISPLAY_FIFO,
 922         SNB_DISPLAY_MAXWM,
 923         SNB_DISPLAY_DFTWM,
 924         2,
 925         SNB_FIFO_LINE_SIZE
 926 };
 927 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 928         SNB_CURSOR_FIFO,
 929         SNB_CURSOR_MAXWM,
 930         SNB_CURSOR_DFTWM,
 931         2,
 932         SNB_FIFO_LINE_SIZE
 933 };
 934 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 935         SNB_DISPLAY_SR_FIFO,
 936         SNB_DISPLAY_MAX_SRWM,
 937         SNB_DISPLAY_DFT_SRWM,
 938         2,
 939         SNB_FIFO_LINE_SIZE
 940 };
 941 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 942         SNB_CURSOR_SR_FIFO,
 943         SNB_CURSOR_MAX_SRWM,
 944         SNB_CURSOR_DFT_SRWM,
 945         2,
 946         SNB_FIFO_LINE_SIZE
 947 };
 948
 949
 950 /**
 951  * intel_calculate_wm - calculate watermark level
 952  * @clock_in_khz: pixel clock
 953  * @wm: chip FIFO params
 954  * @pixel_size: display pixel size
 955  * @latency_ns: memory latency for the platform
 956  *
 957  * Calculate the watermark level (the level at which the display plane will
 958  * start fetching from memory again).  Each chip has a different display
 959  * FIFO size and allocation, so the caller needs to figure that out and pass
 960  * in the correct intel_watermark_params structure.
 961  *
 962  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 963  * on the pixel size.  When it reaches the watermark level, it'll start
 964  * fetching FIFO line sized based chunks from memory until the FIFO fills
 965  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 966  * will occur, and a display engine hang could result.
 967  */
 968 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 969                                         const struct intel_watermark_params *wm,
 970                                         int fifo_size,
 971                                         int pixel_size,
 972                                         unsigned long latency_ns)
 973 {
 974         long entries_required, wm_size;
 975
 976         /*
 977          * Note: we need to make sure we don't overflow for various clock &
 978          * latency values.
 979          * clocks go from a few thousand to several hundred thousand.
 980          * latency is usually a few thousand
 981          */
 982         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 983                 1000;
 984         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 985
 986         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 987
 988         wm_size = fifo_size - (entries_required + wm->guard_size);
 989
 990         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 991
 992         /* Don't promote wm_size to unsigned... */
 993         if (wm_size > (long)wm->max_wm)
 994                 wm_size = wm->max_wm;
 995         if (wm_size <= 0)
 996                 wm_size = wm->default_wm;
 997         return wm_size;
 998 }
 999
1000 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1001 {
1002         struct drm_crtc *crtc, *enabled = NULL;
1003
1004         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1005                 if (intel_crtc_active(crtc)) {
1006                         if (enabled)
1007                                 return NULL;
1008                         enabled = crtc;
1009                 }
1010         }
1011
1012         return enabled;
1013 }
1014
1015 static void pineview_update_wm(struct drm_device *dev)
1016 {
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         struct drm_crtc *crtc;
1019         const struct cxsr_latency *latency;
1020         u32 reg;
1021         unsigned long wm;
1022
1023         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1024                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1025         if (!latency) {
1026                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1027                 pineview_disable_cxsr(dev);
1028                 return;
1029         }
1030
1031         crtc = single_enabled_crtc(dev);
1032         if (crtc) {
1033                 int clock = crtc->mode.clock;
1034                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1035
1036                 /* Display SR */
1037                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1038                                         pineview_display_wm.fifo_size,
1039                                         pixel_size, latency->display_sr);
1040                 reg = I915_READ(DSPFW1);
1041                 reg &= ~DSPFW_SR_MASK;
1042                 reg |= wm << DSPFW_SR_SHIFT;
1043                 I915_WRITE(DSPFW1, reg);
1044                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1045
1046                 /* cursor SR */
1047                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1048                                         pineview_display_wm.fifo_size,
1049                                         pixel_size, latency->cursor_sr);
1050                 reg = I915_READ(DSPFW3);
1051                 reg &= ~DSPFW_CURSOR_SR_MASK;
1052                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1053                 I915_WRITE(DSPFW3, reg);
1054
1055                 /* Display HPLL off SR */
1056                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1057                                         pineview_display_hplloff_wm.fifo_size,
1058                                         pixel_size, latency->display_hpll_disable);
1059                 reg = I915_READ(DSPFW3);
1060                 reg &= ~DSPFW_HPLL_SR_MASK;
1061                 reg |= wm & DSPFW_HPLL_SR_MASK;
1062                 I915_WRITE(DSPFW3, reg);
1063
1064                 /* cursor HPLL off SR */
1065                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1066                                         pineview_display_hplloff_wm.fifo_size,
1067                                         pixel_size, latency->cursor_hpll_disable);
1068                 reg = I915_READ(DSPFW3);
1069                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1070                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1071                 I915_WRITE(DSPFW3, reg);
1072                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1073
1074                 /* activate cxsr */
1075                 I915_WRITE(DSPFW3,
1076                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1077                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1078         } else {
1079                 pineview_disable_cxsr(dev);
1080                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1081         }
1082 }
1083
1084 static bool g4x_compute_wm0(struct drm_device *dev,
1085                             int plane,
1086                             const struct intel_watermark_params *display,
1087                             int display_latency_ns,
1088                             const struct intel_watermark_params *cursor,
1089                             int cursor_latency_ns,
1090                             int *plane_wm,
1091                             int *cursor_wm)
1092 {
1093         struct drm_crtc *crtc;
1094         int htotal, hdisplay, clock, pixel_size;
1095         int line_time_us, line_count;
1096         int entries, tlb_miss;
1097
1098         crtc = intel_get_crtc_for_plane(dev, plane);
1099         if (!intel_crtc_active(crtc)) {
1100                 *cursor_wm = cursor->guard_size;
1101                 *plane_wm = display->guard_size;
1102                 return false;
1103         }
1104
1105         htotal = crtc->mode.htotal;
1106         hdisplay = crtc->mode.hdisplay;
1107         clock = crtc->mode.clock;
1108         pixel_size = crtc->fb->bits_per_pixel / 8;
1109
1110         /* Use the small buffer method to calculate plane watermark */
1111         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1112         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1113         if (tlb_miss > 0)
1114                 entries += tlb_miss;
1115         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1116         *plane_wm = entries + display->guard_size;
1117         if (*plane_wm > (int)display->max_wm)
1118                 *plane_wm = display->max_wm;
1119
1120         /* Use the large buffer method to calculate cursor watermark */
1121         line_time_us = ((htotal * 1000) / clock);
1122         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1123         entries = line_count * 64 * pixel_size;
1124         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1125         if (tlb_miss > 0)
1126                 entries += tlb_miss;
1127         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1128         *cursor_wm = entries + cursor->guard_size;
1129         if (*cursor_wm > (int)cursor->max_wm)
1130                 *cursor_wm = (int)cursor->max_wm;
1131
1132         return true;
1133 }
1134
1135 /*
1136  * Check the wm result.
1137  *
1138  * If any calculated watermark values is larger than the maximum value that
1139  * can be programmed into the associated watermark register, that watermark
1140  * must be disabled.
1141  */
1142 static bool g4x_check_srwm(struct drm_device *dev,
1143                            int display_wm, int cursor_wm,
1144                            const struct intel_watermark_params *display,
1145                            const struct intel_watermark_params *cursor)
1146 {
1147         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1148                       display_wm, cursor_wm);
1149
1150         if (display_wm > display->max_wm) {
1151                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1152                               display_wm, display->max_wm);
1153                 return false;
1154         }
1155
1156         if (cursor_wm > cursor->max_wm) {
1157                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1158                               cursor_wm, cursor->max_wm);
1159                 return false;
1160         }
1161
1162         if (!(display_wm || cursor_wm)) {
1163                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1164                 return false;
1165         }
1166
1167         return true;
1168 }
1169
1170 static bool g4x_compute_srwm(struct drm_device *dev,
1171                              int plane,
1172                              int latency_ns,
1173                              const struct intel_watermark_params *display,
1174                              const struct intel_watermark_params *cursor,
1175                              int *display_wm, int *cursor_wm)
1176 {
1177         struct drm_crtc *crtc;
1178         int hdisplay, htotal, pixel_size, clock;
1179         unsigned long line_time_us;
1180         int line_count, line_size;
1181         int small, large;
1182         int entries;
1183
1184         if (!latency_ns) {
1185                 *display_wm = *cursor_wm = 0;
1186                 return false;
1187         }
1188
1189         crtc = intel_get_crtc_for_plane(dev, plane);
1190         hdisplay = crtc->mode.hdisplay;
1191         htotal = crtc->mode.htotal;
1192         clock = crtc->mode.clock;
1193         pixel_size = crtc->fb->bits_per_pixel / 8;
1194
1195         line_time_us = (htotal * 1000) / clock;
1196         line_count = (latency_ns / line_time_us + 1000) / 1000;
1197         line_size = hdisplay * pixel_size;
1198
1199         /* Use the minimum of the small and large buffer method for primary */
1200         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1201         large = line_count * line_size;
1202
1203         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1204         *display_wm = entries + display->guard_size;
1205
1206         /* calculate the self-refresh watermark for display cursor */
1207         entries = line_count * pixel_size * 64;
1208         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1209         *cursor_wm = entries + cursor->guard_size;
1210
1211         return g4x_check_srwm(dev,
1212                               *display_wm, *cursor_wm,
1213                               display, cursor);
1214 }
1215
1216 static bool vlv_compute_drain_latency(struct drm_device *dev,
1217                                      int plane,
1218                                      int *plane_prec_mult,
1219                                      int *plane_dl,
1220                                      int *cursor_prec_mult,
1221                                      int *cursor_dl)
1222 {
1223         struct drm_crtc *crtc;
1224         int clock, pixel_size;
1225         int entries;
1226
1227         crtc = intel_get_crtc_for_plane(dev, plane);
1228         if (!intel_crtc_active(crtc))
1229                 return false;
1230
1231         clock = crtc->mode.clock;       /* VESA DOT Clock */
1232         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1233
1234         entries = (clock / 1000) * pixel_size;
1235         *plane_prec_mult = (entries > 256) ?
1236                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1237         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1238                                                      pixel_size);
1239
1240         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1241         *cursor_prec_mult = (entries > 256) ?
1242                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1243         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1244
1245         return true;
1246 }
1247
1248 /*
1249  * Update drain latency registers of memory arbiter
1250  *
1251  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1252  * to be programmed. Each plane has a drain latency multiplier and a drain
1253  * latency value.
1254  */
1255
1256 static void vlv_update_drain_latency(struct drm_device *dev)
1257 {
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1260         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1261         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1262                                                         either 16 or 32 */
1263
1264         /* For plane A, Cursor A */
1265         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1266                                       &cursor_prec_mult, &cursora_dl)) {
1267                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1268                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1269                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1270                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1271
1272                 I915_WRITE(VLV_DDL1, cursora_prec |
1273                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1274                                 planea_prec | planea_dl);
1275         }
1276
1277         /* For plane B, Cursor B */
1278         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1279                                       &cursor_prec_mult, &cursorb_dl)) {
1280                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1281                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1282                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1283                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1284
1285                 I915_WRITE(VLV_DDL2, cursorb_prec |
1286                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1287                                 planeb_prec | planeb_dl);
1288         }
1289 }
1290
1291 #define single_plane_enabled(mask) is_power_of_2(mask)
1292
1293 static void valleyview_update_wm(struct drm_device *dev)
1294 {
1295         static const int sr_latency_ns = 12000;
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1298         int plane_sr, cursor_sr;
1299         int ignore_plane_sr, ignore_cursor_sr;
1300         unsigned int enabled = 0;
1301
1302         vlv_update_drain_latency(dev);
1303
1304         if (g4x_compute_wm0(dev, 0,
1305                             &valleyview_wm_info, latency_ns,
1306                             &valleyview_cursor_wm_info, latency_ns,
1307                             &planea_wm, &cursora_wm))
1308                 enabled |= 1;
1309
1310         if (g4x_compute_wm0(dev, 1,
1311                             &valleyview_wm_info, latency_ns,
1312                             &valleyview_cursor_wm_info, latency_ns,
1313                             &planeb_wm, &cursorb_wm))
1314                 enabled |= 2;
1315
1316         if (single_plane_enabled(enabled) &&
1317             g4x_compute_srwm(dev, ffs(enabled) - 1,
1318                              sr_latency_ns,
1319                              &valleyview_wm_info,
1320                              &valleyview_cursor_wm_info,
1321                              &plane_sr, &ignore_cursor_sr) &&
1322             g4x_compute_srwm(dev, ffs(enabled) - 1,
1323                              2*sr_latency_ns,
1324                              &valleyview_wm_info,
1325                              &valleyview_cursor_wm_info,
1326                              &ignore_plane_sr, &cursor_sr)) {
1327                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1328         } else {
1329                 I915_WRITE(FW_BLC_SELF_VLV,
1330                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1331                 plane_sr = cursor_sr = 0;
1332         }
1333
1334         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1335                       planea_wm, cursora_wm,
1336                       planeb_wm, cursorb_wm,
1337                       plane_sr, cursor_sr);
1338
1339         I915_WRITE(DSPFW1,
1340                    (plane_sr << DSPFW_SR_SHIFT) |
1341                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1342                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1343                    planea_wm);
1344         I915_WRITE(DSPFW2,
1345                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1346                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1347         I915_WRITE(DSPFW3,
1348                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1349                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1350 }
1351
1352 static void g4x_update_wm(struct drm_device *dev)
1353 {
1354         static const int sr_latency_ns = 12000;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357         int plane_sr, cursor_sr;
1358         unsigned int enabled = 0;
1359
1360         if (g4x_compute_wm0(dev, 0,
1361                             &g4x_wm_info, latency_ns,
1362                             &g4x_cursor_wm_info, latency_ns,
1363                             &planea_wm, &cursora_wm))
1364                 enabled |= 1;
1365
1366         if (g4x_compute_wm0(dev, 1,
1367                             &g4x_wm_info, latency_ns,
1368                             &g4x_cursor_wm_info, latency_ns,
1369                             &planeb_wm, &cursorb_wm))
1370                 enabled |= 2;
1371
1372         if (single_plane_enabled(enabled) &&
1373             g4x_compute_srwm(dev, ffs(enabled) - 1,
1374                              sr_latency_ns,
1375                              &g4x_wm_info,
1376                              &g4x_cursor_wm_info,
1377                              &plane_sr, &cursor_sr)) {
1378                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1379         } else {
1380                 I915_WRITE(FW_BLC_SELF,
1381                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1382                 plane_sr = cursor_sr = 0;
1383         }
1384
1385         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1386                       planea_wm, cursora_wm,
1387                       planeb_wm, cursorb_wm,
1388                       plane_sr, cursor_sr);
1389
1390         I915_WRITE(DSPFW1,
1391                    (plane_sr << DSPFW_SR_SHIFT) |
1392                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1393                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1394                    planea_wm);
1395         I915_WRITE(DSPFW2,
1396                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1397                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1398         /* HPLL off in SR has some issues on G4x... disable it */
1399         I915_WRITE(DSPFW3,
1400                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1401                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1402 }
1403
1404 static void i965_update_wm(struct drm_device *dev)
1405 {
1406         struct drm_i915_private *dev_priv = dev->dev_private;
1407         struct drm_crtc *crtc;
1408         int srwm = 1;
1409         int cursor_sr = 16;
1410
1411         /* Calc sr entries for one plane configs */
1412         crtc = single_enabled_crtc(dev);
1413         if (crtc) {
1414                 /* self-refresh has much higher latency */
1415                 static const int sr_latency_ns = 12000;
1416                 int clock = crtc->mode.clock;
1417                 int htotal = crtc->mode.htotal;
1418                 int hdisplay = crtc->mode.hdisplay;
1419                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1420                 unsigned long line_time_us;
1421                 int entries;
1422
1423                 line_time_us = ((htotal * 1000) / clock);
1424
1425                 /* Use ns/us then divide to preserve precision */
1426                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1427                         pixel_size * hdisplay;
1428                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1429                 srwm = I965_FIFO_SIZE - entries;
1430                 if (srwm < 0)
1431                         srwm = 1;
1432                 srwm &= 0x1ff;
1433                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1434                               entries, srwm);
1435
1436                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1437                         pixel_size * 64;
1438                 entries = DIV_ROUND_UP(entries,
1439                                           i965_cursor_wm_info.cacheline_size);
1440                 cursor_sr = i965_cursor_wm_info.fifo_size -
1441                         (entries + i965_cursor_wm_info.guard_size);
1442
1443                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1444                         cursor_sr = i965_cursor_wm_info.max_wm;
1445
1446                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1447                               "cursor %d\n", srwm, cursor_sr);
1448
1449                 if (IS_CRESTLINE(dev))
1450                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1451         } else {
1452                 /* Turn off self refresh if both pipes are enabled */
1453                 if (IS_CRESTLINE(dev))
1454                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1455                                    & ~FW_BLC_SELF_EN);
1456         }
1457
1458         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1459                       srwm);
1460
1461         /* 965 has limitations... */
1462         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1463                    (8 << 16) | (8 << 8) | (8 << 0));
1464         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1465         /* update cursor SR watermark */
1466         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1467 }
1468
1469 static void i9xx_update_wm(struct drm_device *dev)
1470 {
1471         struct drm_i915_private *dev_priv = dev->dev_private;
1472         const struct intel_watermark_params *wm_info;
1473         uint32_t fwater_lo;
1474         uint32_t fwater_hi;
1475         int cwm, srwm = 1;
1476         int fifo_size;
1477         int planea_wm, planeb_wm;
1478         struct drm_crtc *crtc, *enabled = NULL;
1479
1480         if (IS_I945GM(dev))
1481                 wm_info = &i945_wm_info;
1482         else if (!IS_GEN2(dev))
1483                 wm_info = &i915_wm_info;
1484         else
1485                 wm_info = &i855_wm_info;
1486
1487         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1488         crtc = intel_get_crtc_for_plane(dev, 0);
1489         if (intel_crtc_active(crtc)) {
1490                 int cpp = crtc->fb->bits_per_pixel / 8;
1491                 if (IS_GEN2(dev))
1492                         cpp = 4;
1493
1494                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1495                                                wm_info, fifo_size, cpp,
1496                                                latency_ns);
1497                 enabled = crtc;
1498         } else
1499                 planea_wm = fifo_size - wm_info->guard_size;
1500
1501         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1502         crtc = intel_get_crtc_for_plane(dev, 1);
1503         if (intel_crtc_active(crtc)) {
1504                 int cpp = crtc->fb->bits_per_pixel / 8;
1505                 if (IS_GEN2(dev))
1506                         cpp = 4;
1507
1508                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1509                                                wm_info, fifo_size, cpp,
1510                                                latency_ns);
1511                 if (enabled == NULL)
1512                         enabled = crtc;
1513                 else
1514                         enabled = NULL;
1515         } else
1516                 planeb_wm = fifo_size - wm_info->guard_size;
1517
1518         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1519
1520         /*
1521          * Overlay gets an aggressive default since video jitter is bad.
1522          */
1523         cwm = 2;
1524
1525         /* Play safe and disable self-refresh before adjusting watermarks. */
1526         if (IS_I945G(dev) || IS_I945GM(dev))
1527                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1528         else if (IS_I915GM(dev))
1529                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1530
1531         /* Calc sr entries for one plane configs */
1532         if (HAS_FW_BLC(dev) && enabled) {
1533                 /* self-refresh has much higher latency */
1534                 static const int sr_latency_ns = 6000;
1535                 int clock = enabled->mode.clock;
1536                 int htotal = enabled->mode.htotal;
1537                 int hdisplay = enabled->mode.hdisplay;
1538                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1539                 unsigned long line_time_us;
1540                 int entries;
1541
1542                 line_time_us = (htotal * 1000) / clock;
1543
1544                 /* Use ns/us then divide to preserve precision */
1545                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1546                         pixel_size * hdisplay;
1547                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1548                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1549                 srwm = wm_info->fifo_size - entries;
1550                 if (srwm < 0)
1551                         srwm = 1;
1552
1553                 if (IS_I945G(dev) || IS_I945GM(dev))
1554                         I915_WRITE(FW_BLC_SELF,
1555                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1556                 else if (IS_I915GM(dev))
1557                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1558         }
1559
1560         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1561                       planea_wm, planeb_wm, cwm, srwm);
1562
1563         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1564         fwater_hi = (cwm & 0x1f);
1565
1566         /* Set request length to 8 cachelines per fetch */
1567         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1568         fwater_hi = fwater_hi | (1 << 8);
1569
1570         I915_WRITE(FW_BLC, fwater_lo);
1571         I915_WRITE(FW_BLC2, fwater_hi);
1572
1573         if (HAS_FW_BLC(dev)) {
1574                 if (enabled) {
1575                         if (IS_I945G(dev) || IS_I945GM(dev))
1576                                 I915_WRITE(FW_BLC_SELF,
1577                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1578                         else if (IS_I915GM(dev))
1579                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1580                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1581                 } else
1582                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1583         }
1584 }
1585
1586 static void i830_update_wm(struct drm_device *dev)
1587 {
1588         struct drm_i915_private *dev_priv = dev->dev_private;
1589         struct drm_crtc *crtc;
1590         uint32_t fwater_lo;
1591         int planea_wm;
1592
1593         crtc = single_enabled_crtc(dev);
1594         if (crtc == NULL)
1595                 return;
1596
1597         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1598                                        dev_priv->display.get_fifo_size(dev, 0),
1599                                        4, latency_ns);
1600         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1601         fwater_lo |= (3<<8) | planea_wm;
1602
1603         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1604
1605         I915_WRITE(FW_BLC, fwater_lo);
1606 }
1607
1608 #define ILK_LP0_PLANE_LATENCY           700
1609 #define ILK_LP0_CURSOR_LATENCY          1300
1610
1611 /*
1612  * Check the wm result.
1613  *
1614  * If any calculated watermark values is larger than the maximum value that
1615  * can be programmed into the associated watermark register, that watermark
1616  * must be disabled.
1617  */
1618 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1619                                 int fbc_wm, int display_wm, int cursor_wm,
1620                                 const struct intel_watermark_params *display,
1621                                 const struct intel_watermark_params *cursor)
1622 {
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624
1625         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1626                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1627
1628         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1629                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1630                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1631
1632                 /* fbc has it's own way to disable FBC WM */
1633                 I915_WRITE(DISP_ARB_CTL,
1634                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1635                 return false;
1636         }
1637
1638         if (display_wm > display->max_wm) {
1639                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1640                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1641                 return false;
1642         }
1643
1644         if (cursor_wm > cursor->max_wm) {
1645                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1646                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1647                 return false;
1648         }
1649
1650         if (!(fbc_wm || display_wm || cursor_wm)) {
1651                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1652                 return false;
1653         }
1654
1655         return true;
1656 }
1657
1658 /*
1659  * Compute watermark values of WM[1-3],
1660  */
1661 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1662                                   int latency_ns,
1663                                   const struct intel_watermark_params *display,
1664                                   const struct intel_watermark_params *cursor,
1665                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1666 {
1667         struct drm_crtc *crtc;
1668         unsigned long line_time_us;
1669         int hdisplay, htotal, pixel_size, clock;
1670         int line_count, line_size;
1671         int small, large;
1672         int entries;
1673
1674         if (!latency_ns) {
1675                 *fbc_wm = *display_wm = *cursor_wm = 0;
1676                 return false;
1677         }
1678
1679         crtc = intel_get_crtc_for_plane(dev, plane);
1680         hdisplay = crtc->mode.hdisplay;
1681         htotal = crtc->mode.htotal;
1682         clock = crtc->mode.clock;
1683         pixel_size = crtc->fb->bits_per_pixel / 8;
1684
1685         line_time_us = (htotal * 1000) / clock;
1686         line_count = (latency_ns / line_time_us + 1000) / 1000;
1687         line_size = hdisplay * pixel_size;
1688
1689         /* Use the minimum of the small and large buffer method for primary */
1690         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1691         large = line_count * line_size;
1692
1693         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1694         *display_wm = entries + display->guard_size;
1695
1696         /*
1697          * Spec says:
1698          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1699          */
1700         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1701
1702         /* calculate the self-refresh watermark for display cursor */
1703         entries = line_count * pixel_size * 64;
1704         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1705         *cursor_wm = entries + cursor->guard_size;
1706
1707         return ironlake_check_srwm(dev, level,
1708                                    *fbc_wm, *display_wm, *cursor_wm,
1709                                    display, cursor);
1710 }
1711
1712 static void ironlake_update_wm(struct drm_device *dev)
1713 {
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715         int fbc_wm, plane_wm, cursor_wm;
1716         unsigned int enabled;
1717
1718         enabled = 0;
1719         if (g4x_compute_wm0(dev, 0,
1720                             &ironlake_display_wm_info,
1721                             ILK_LP0_PLANE_LATENCY,
1722                             &ironlake_cursor_wm_info,
1723                             ILK_LP0_CURSOR_LATENCY,
1724                             &plane_wm, &cursor_wm)) {
1725                 I915_WRITE(WM0_PIPEA_ILK,
1726                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1727                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1728                               " plane %d, " "cursor: %d\n",
1729                               plane_wm, cursor_wm);
1730                 enabled |= 1;
1731         }
1732
1733         if (g4x_compute_wm0(dev, 1,
1734                             &ironlake_display_wm_info,
1735                             ILK_LP0_PLANE_LATENCY,
1736                             &ironlake_cursor_wm_info,
1737                             ILK_LP0_CURSOR_LATENCY,
1738                             &plane_wm, &cursor_wm)) {
1739                 I915_WRITE(WM0_PIPEB_ILK,
1740                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1741                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1742                               " plane %d, cursor: %d\n",
1743                               plane_wm, cursor_wm);
1744                 enabled |= 2;
1745         }
1746
1747         /*
1748          * Calculate and update the self-refresh watermark only when one
1749          * display plane is used.
1750          */
1751         I915_WRITE(WM3_LP_ILK, 0);
1752         I915_WRITE(WM2_LP_ILK, 0);
1753         I915_WRITE(WM1_LP_ILK, 0);
1754
1755         if (!single_plane_enabled(enabled))
1756                 return;
1757         enabled = ffs(enabled) - 1;
1758
1759         /* WM1 */
1760         if (!ironlake_compute_srwm(dev, 1, enabled,
1761                                    ILK_READ_WM1_LATENCY() * 500,
1762                                    &ironlake_display_srwm_info,
1763                                    &ironlake_cursor_srwm_info,
1764                                    &fbc_wm, &plane_wm, &cursor_wm))
1765                 return;
1766
1767         I915_WRITE(WM1_LP_ILK,
1768                    WM1_LP_SR_EN |
1769                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1770                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1771                    (plane_wm << WM1_LP_SR_SHIFT) |
1772                    cursor_wm);
1773
1774         /* WM2 */
1775         if (!ironlake_compute_srwm(dev, 2, enabled,
1776                                    ILK_READ_WM2_LATENCY() * 500,
1777                                    &ironlake_display_srwm_info,
1778                                    &ironlake_cursor_srwm_info,
1779                                    &fbc_wm, &plane_wm, &cursor_wm))
1780                 return;
1781
1782         I915_WRITE(WM2_LP_ILK,
1783                    WM2_LP_EN |
1784                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1785                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1786                    (plane_wm << WM1_LP_SR_SHIFT) |
1787                    cursor_wm);
1788
1789         /*
1790          * WM3 is unsupported on ILK, probably because we don't have latency
1791          * data for that power state
1792          */
1793 }
1794
1795 static void sandybridge_update_wm(struct drm_device *dev)
1796 {
1797         struct drm_i915_private *dev_priv = dev->dev_private;
1798         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1799         u32 val;
1800         int fbc_wm, plane_wm, cursor_wm;
1801         unsigned int enabled;
1802
1803         enabled = 0;
1804         if (g4x_compute_wm0(dev, 0,
1805                             &sandybridge_display_wm_info, latency,
1806                             &sandybridge_cursor_wm_info, latency,
1807                             &plane_wm, &cursor_wm)) {
1808                 val = I915_READ(WM0_PIPEA_ILK);
1809                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1810                 I915_WRITE(WM0_PIPEA_ILK, val |
1811                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1812                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1813                               " plane %d, " "cursor: %d\n",
1814                               plane_wm, cursor_wm);
1815                 enabled |= 1;
1816         }
1817
1818         if (g4x_compute_wm0(dev, 1,
1819                             &sandybridge_display_wm_info, latency,
1820                             &sandybridge_cursor_wm_info, latency,
1821                             &plane_wm, &cursor_wm)) {
1822                 val = I915_READ(WM0_PIPEB_ILK);
1823                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1824                 I915_WRITE(WM0_PIPEB_ILK, val |
1825                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1826                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1827                               " plane %d, cursor: %d\n",
1828                               plane_wm, cursor_wm);
1829                 enabled |= 2;
1830         }
1831
1832         /*
1833          * Calculate and update the self-refresh watermark only when one
1834          * display plane is used.
1835          *
1836          * SNB support 3 levels of watermark.
1837          *
1838          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1839          * and disabled in the descending order
1840          *
1841          */
1842         I915_WRITE(WM3_LP_ILK, 0);
1843         I915_WRITE(WM2_LP_ILK, 0);
1844         I915_WRITE(WM1_LP_ILK, 0);
1845
1846         if (!single_plane_enabled(enabled) ||
1847             dev_priv->sprite_scaling_enabled)
1848                 return;
1849         enabled = ffs(enabled) - 1;
1850
1851         /* WM1 */
1852         if (!ironlake_compute_srwm(dev, 1, enabled,
1853                                    SNB_READ_WM1_LATENCY() * 500,
1854                                    &sandybridge_display_srwm_info,
1855                                    &sandybridge_cursor_srwm_info,
1856                                    &fbc_wm, &plane_wm, &cursor_wm))
1857                 return;
1858
1859         I915_WRITE(WM1_LP_ILK,
1860                    WM1_LP_SR_EN |
1861                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1862                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1863                    (plane_wm << WM1_LP_SR_SHIFT) |
1864                    cursor_wm);
1865
1866         /* WM2 */
1867         if (!ironlake_compute_srwm(dev, 2, enabled,
1868                                    SNB_READ_WM2_LATENCY() * 500,
1869                                    &sandybridge_display_srwm_info,
1870                                    &sandybridge_cursor_srwm_info,
1871                                    &fbc_wm, &plane_wm, &cursor_wm))
1872                 return;
1873
1874         I915_WRITE(WM2_LP_ILK,
1875                    WM2_LP_EN |
1876                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1877                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1878                    (plane_wm << WM1_LP_SR_SHIFT) |
1879                    cursor_wm);
1880
1881         /* WM3 */
1882         if (!ironlake_compute_srwm(dev, 3, enabled,
1883                                    SNB_READ_WM3_LATENCY() * 500,
1884                                    &sandybridge_display_srwm_info,
1885                                    &sandybridge_cursor_srwm_info,
1886                                    &fbc_wm, &plane_wm, &cursor_wm))
1887                 return;
1888
1889         I915_WRITE(WM3_LP_ILK,
1890                    WM3_LP_EN |
1891                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1892                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1893                    (plane_wm << WM1_LP_SR_SHIFT) |
1894                    cursor_wm);
1895 }
1896
1897 static void ivybridge_update_wm(struct drm_device *dev)
1898 {
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1901         u32 val;
1902         int fbc_wm, plane_wm, cursor_wm;
1903         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1904         unsigned int enabled;
1905
1906         enabled = 0;
1907         if (g4x_compute_wm0(dev, 0,
1908                             &sandybridge_display_wm_info, latency,
1909                             &sandybridge_cursor_wm_info, latency,
1910                             &plane_wm, &cursor_wm)) {
1911                 val = I915_READ(WM0_PIPEA_ILK);
1912                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1913                 I915_WRITE(WM0_PIPEA_ILK, val |
1914                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1915                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1916                               " plane %d, " "cursor: %d\n",
1917                               plane_wm, cursor_wm);
1918                 enabled |= 1;
1919         }
1920
1921         if (g4x_compute_wm0(dev, 1,
1922                             &sandybridge_display_wm_info, latency,
1923                             &sandybridge_cursor_wm_info, latency,
1924                             &plane_wm, &cursor_wm)) {
1925                 val = I915_READ(WM0_PIPEB_ILK);
1926                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1927                 I915_WRITE(WM0_PIPEB_ILK, val |
1928                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1929                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1930                               " plane %d, cursor: %d\n",
1931                               plane_wm, cursor_wm);
1932                 enabled |= 2;
1933         }
1934
1935         if (g4x_compute_wm0(dev, 2,
1936                             &sandybridge_display_wm_info, latency,
1937                             &sandybridge_cursor_wm_info, latency,
1938                             &plane_wm, &cursor_wm)) {
1939                 val = I915_READ(WM0_PIPEC_IVB);
1940                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1941                 I915_WRITE(WM0_PIPEC_IVB, val |
1942                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1943                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1944                               " plane %d, cursor: %d\n",
1945                               plane_wm, cursor_wm);
1946                 enabled |= 3;
1947         }
1948
1949         /*
1950          * Calculate and update the self-refresh watermark only when one
1951          * display plane is used.
1952          *
1953          * SNB support 3 levels of watermark.
1954          *
1955          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1956          * and disabled in the descending order
1957          *
1958          */
1959         I915_WRITE(WM3_LP_ILK, 0);
1960         I915_WRITE(WM2_LP_ILK, 0);
1961         I915_WRITE(WM1_LP_ILK, 0);
1962
1963         if (!single_plane_enabled(enabled) ||
1964             dev_priv->sprite_scaling_enabled)
1965                 return;
1966         enabled = ffs(enabled) - 1;
1967
1968         /* WM1 */
1969         if (!ironlake_compute_srwm(dev, 1, enabled,
1970                                    SNB_READ_WM1_LATENCY() * 500,
1971                                    &sandybridge_display_srwm_info,
1972                                    &sandybridge_cursor_srwm_info,
1973                                    &fbc_wm, &plane_wm, &cursor_wm))
1974                 return;
1975
1976         I915_WRITE(WM1_LP_ILK,
1977                    WM1_LP_SR_EN |
1978                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1979                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1980                    (plane_wm << WM1_LP_SR_SHIFT) |
1981                    cursor_wm);
1982
1983         /* WM2 */
1984         if (!ironlake_compute_srwm(dev, 2, enabled,
1985                                    SNB_READ_WM2_LATENCY() * 500,
1986                                    &sandybridge_display_srwm_info,
1987                                    &sandybridge_cursor_srwm_info,
1988                                    &fbc_wm, &plane_wm, &cursor_wm))
1989                 return;
1990
1991         I915_WRITE(WM2_LP_ILK,
1992                    WM2_LP_EN |
1993                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1994                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1995                    (plane_wm << WM1_LP_SR_SHIFT) |
1996                    cursor_wm);
1997
1998         /* WM3, note we have to correct the cursor latency */
1999         if (!ironlake_compute_srwm(dev, 3, enabled,
2000                                    SNB_READ_WM3_LATENCY() * 500,
2001                                    &sandybridge_display_srwm_info,
2002                                    &sandybridge_cursor_srwm_info,
2003                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2004             !ironlake_compute_srwm(dev, 3, enabled,
2005                                    2 * SNB_READ_WM3_LATENCY() * 500,
2006                                    &sandybridge_display_srwm_info,
2007                                    &sandybridge_cursor_srwm_info,
2008                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2009                 return;
2010
2011         I915_WRITE(WM3_LP_ILK,
2012                    WM3_LP_EN |
2013                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2014                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2015                    (plane_wm << WM1_LP_SR_SHIFT) |
2016                    cursor_wm);
2017 }
2018
2019 static void
2020 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2021                                  struct drm_display_mode *mode)
2022 {
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         u32 temp;
2025
2026         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2027         temp &= ~PIPE_WM_LINETIME_MASK;
2028
2029         /* The WM are computed with base on how long it takes to fill a single
2030          * row at the given clock rate, multiplied by 8.
2031          * */
2032         temp |= PIPE_WM_LINETIME_TIME(
2033                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2034
2035         /* IPS watermarks are only used by pipe A, and are ignored by
2036          * pipes B and C.  They are calculated similarly to the common
2037          * linetime values, except that we are using CD clock frequency
2038          * in MHz instead of pixel rate for the division.
2039          *
2040          * This is a placeholder for the IPS watermark calculation code.
2041          */
2042
2043         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2044 }
2045
2046 static bool
2047 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2048                               uint32_t sprite_width, int pixel_size,
2049                               const struct intel_watermark_params *display,
2050                               int display_latency_ns, int *sprite_wm)
2051 {
2052         struct drm_crtc *crtc;
2053         int clock;
2054         int entries, tlb_miss;
2055
2056         crtc = intel_get_crtc_for_plane(dev, plane);
2057         if (!intel_crtc_active(crtc)) {
2058                 *sprite_wm = display->guard_size;
2059                 return false;
2060         }
2061
2062         clock = crtc->mode.clock;
2063
2064         /* Use the small buffer method to calculate the sprite watermark */
2065         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2066         tlb_miss = display->fifo_size*display->cacheline_size -
2067                 sprite_width * 8;
2068         if (tlb_miss > 0)
2069                 entries += tlb_miss;
2070         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2071         *sprite_wm = entries + display->guard_size;
2072         if (*sprite_wm > (int)display->max_wm)
2073                 *sprite_wm = display->max_wm;
2074
2075         return true;
2076 }
2077
2078 static bool
2079 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2080                                 uint32_t sprite_width, int pixel_size,
2081                                 const struct intel_watermark_params *display,
2082                                 int latency_ns, int *sprite_wm)
2083 {
2084         struct drm_crtc *crtc;
2085         unsigned long line_time_us;
2086         int clock;
2087         int line_count, line_size;
2088         int small, large;
2089         int entries;
2090
2091         if (!latency_ns) {
2092                 *sprite_wm = 0;
2093                 return false;
2094         }
2095
2096         crtc = intel_get_crtc_for_plane(dev, plane);
2097         clock = crtc->mode.clock;
2098         if (!clock) {
2099                 *sprite_wm = 0;
2100                 return false;
2101         }
2102
2103         line_time_us = (sprite_width * 1000) / clock;
2104         if (!line_time_us) {
2105                 *sprite_wm = 0;
2106                 return false;
2107         }
2108
2109         line_count = (latency_ns / line_time_us + 1000) / 1000;
2110         line_size = sprite_width * pixel_size;
2111
2112         /* Use the minimum of the small and large buffer method for primary */
2113         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2114         large = line_count * line_size;
2115
2116         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2117         *sprite_wm = entries + display->guard_size;
2118
2119         return *sprite_wm > 0x3ff ? false : true;
2120 }
2121
2122 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2123                                          uint32_t sprite_width, int pixel_size)
2124 {
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2127         u32 val;
2128         int sprite_wm, reg;
2129         int ret;
2130
2131         switch (pipe) {
2132         case 0:
2133                 reg = WM0_PIPEA_ILK;
2134                 break;
2135         case 1:
2136                 reg = WM0_PIPEB_ILK;
2137                 break;
2138         case 2:
2139                 reg = WM0_PIPEC_IVB;
2140                 break;
2141         default:
2142                 return; /* bad pipe */
2143         }
2144
2145         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2146                                             &sandybridge_display_wm_info,
2147                                             latency, &sprite_wm);
2148         if (!ret) {
2149                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2150                               pipe);
2151                 return;
2152         }
2153
2154         val = I915_READ(reg);
2155         val &= ~WM0_PIPE_SPRITE_MASK;
2156         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2157         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2158
2159
2160         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2161                                               pixel_size,
2162                                               &sandybridge_display_srwm_info,
2163                                               SNB_READ_WM1_LATENCY() * 500,
2164                                               &sprite_wm);
2165         if (!ret) {
2166                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2167                               pipe);
2168                 return;
2169         }
2170         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2171
2172         /* Only IVB has two more LP watermarks for sprite */
2173         if (!IS_IVYBRIDGE(dev))
2174                 return;
2175
2176         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2177                                               pixel_size,
2178                                               &sandybridge_display_srwm_info,
2179                                               SNB_READ_WM2_LATENCY() * 500,
2180                                               &sprite_wm);
2181         if (!ret) {
2182                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2183                               pipe);
2184                 return;
2185         }
2186         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2187
2188         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2189                                               pixel_size,
2190                                               &sandybridge_display_srwm_info,
2191                                               SNB_READ_WM3_LATENCY() * 500,
2192                                               &sprite_wm);
2193         if (!ret) {
2194                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2195                               pipe);
2196                 return;
2197         }
2198         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2199 }
2200
2201 /**
2202  * intel_update_watermarks - update FIFO watermark values based on current modes
2203  *
2204  * Calculate watermark values for the various WM regs based on current mode
2205  * and plane configuration.
2206  *
2207  * There are several cases to deal with here:
2208  *   - normal (i.e. non-self-refresh)
2209  *   - self-refresh (SR) mode
2210  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2211  *   - lines are small relative to FIFO size (buffer can hold more than 2
2212  *     lines), so need to account for TLB latency
2213  *
2214  *   The normal calculation is:
2215  *     watermark = dotclock * bytes per pixel * latency
2216  *   where latency is platform & configuration dependent (we assume pessimal
2217  *   values here).
2218  *
2219  *   The SR calculation is:
2220  *     watermark = (trunc(latency/line time)+1) * surface width *
2221  *       bytes per pixel
2222  *   where
2223  *     line time = htotal / dotclock
2224  *     surface width = hdisplay for normal plane and 64 for cursor
2225  *   and latency is assumed to be high, as above.
2226  *
2227  * The final value programmed to the register should always be rounded up,
2228  * and include an extra 2 entries to account for clock crossings.
2229  *
2230  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2231  * to set the non-SR watermarks to 8.
2232  */
2233 void intel_update_watermarks(struct drm_device *dev)
2234 {
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236
2237         if (dev_priv->display.update_wm)
2238                 dev_priv->display.update_wm(dev);
2239 }
2240
2241 void intel_update_linetime_watermarks(struct drm_device *dev,
2242                 int pipe, struct drm_display_mode *mode)
2243 {
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245
2246         if (dev_priv->display.update_linetime_wm)
2247                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2248 }
2249
2250 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2251                                     uint32_t sprite_width, int pixel_size)
2252 {
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255         if (dev_priv->display.update_sprite_wm)
2256                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2257                                                    pixel_size);
2258 }
2259
2260 static struct drm_i915_gem_object *
2261 intel_alloc_context_page(struct drm_device *dev)
2262 {
2263         struct drm_i915_gem_object *ctx;
2264         int ret;
2265
2266         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2267
2268         ctx = i915_gem_alloc_object(dev, 4096);
2269         if (!ctx) {
2270                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2271                 return NULL;
2272         }
2273
2274         ret = i915_gem_object_pin(ctx, 4096, true, false);
2275         if (ret) {
2276                 DRM_ERROR("failed to pin power context: %d\n", ret);
2277                 goto err_unref;
2278         }
2279
2280         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2281         if (ret) {
2282                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2283                 goto err_unpin;
2284         }
2285
2286         return ctx;
2287
2288 err_unpin:
2289         i915_gem_object_unpin(ctx);
2290 err_unref:
2291         drm_gem_object_unreference(&ctx->base);
2292         return NULL;
2293 }
2294
2295 /**
2296  * Lock protecting IPS related data structures
2297  */
2298 DEFINE_SPINLOCK(mchdev_lock);
2299
2300 /* Global for IPS driver to get at the current i915 device. Protected by
2301  * mchdev_lock. */
2302 static struct drm_i915_private *i915_mch_dev;
2303
2304 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2305 {
2306         struct drm_i915_private *dev_priv = dev->dev_private;
2307         u16 rgvswctl;
2308
2309         assert_spin_locked(&mchdev_lock);
2310
2311         rgvswctl = I915_READ16(MEMSWCTL);
2312         if (rgvswctl & MEMCTL_CMD_STS) {
2313                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2314                 return false; /* still busy with another command */
2315         }
2316
2317         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2318                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2319         I915_WRITE16(MEMSWCTL, rgvswctl);
2320         POSTING_READ16(MEMSWCTL);
2321
2322         rgvswctl |= MEMCTL_CMD_STS;
2323         I915_WRITE16(MEMSWCTL, rgvswctl);
2324
2325         return true;
2326 }
2327
2328 static void ironlake_enable_drps(struct drm_device *dev)
2329 {
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         u32 rgvmodectl = I915_READ(MEMMODECTL);
2332         u8 fmax, fmin, fstart, vstart;
2333
2334         spin_lock_irq(&mchdev_lock);
2335
2336         /* Enable temp reporting */
2337         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2338         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2339
2340         /* 100ms RC evaluation intervals */
2341         I915_WRITE(RCUPEI, 100000);
2342         I915_WRITE(RCDNEI, 100000);
2343
2344         /* Set max/min thresholds to 90ms and 80ms respectively */
2345         I915_WRITE(RCBMAXAVG, 90000);
2346         I915_WRITE(RCBMINAVG, 80000);
2347
2348         I915_WRITE(MEMIHYST, 1);
2349
2350         /* Set up min, max, and cur for interrupt handling */
2351         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2352         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2353         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2354                 MEMMODE_FSTART_SHIFT;
2355
2356         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2357                 PXVFREQ_PX_SHIFT;
2358
2359         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2360         dev_priv->ips.fstart = fstart;
2361
2362         dev_priv->ips.max_delay = fstart;
2363         dev_priv->ips.min_delay = fmin;
2364         dev_priv->ips.cur_delay = fstart;
2365
2366         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2367                          fmax, fmin, fstart);
2368
2369         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2370
2371         /*
2372          * Interrupts will be enabled in ironlake_irq_postinstall
2373          */
2374
2375         I915_WRITE(VIDSTART, vstart);
2376         POSTING_READ(VIDSTART);
2377
2378         rgvmodectl |= MEMMODE_SWMODE_EN;
2379         I915_WRITE(MEMMODECTL, rgvmodectl);
2380
2381         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2382                 DRM_ERROR("stuck trying to change perf mode\n");
2383         mdelay(1);
2384
2385         ironlake_set_drps(dev, fstart);
2386
2387         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2388                 I915_READ(0x112e0);
2389         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2390         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2391         getrawmonotonic(&dev_priv->ips.last_time2);
2392
2393         spin_unlock_irq(&mchdev_lock);
2394 }
2395
2396 static void ironlake_disable_drps(struct drm_device *dev)
2397 {
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         u16 rgvswctl;
2400
2401         spin_lock_irq(&mchdev_lock);
2402
2403         rgvswctl = I915_READ16(MEMSWCTL);
2404
2405         /* Ack interrupts, disable EFC interrupt */
2406         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2407         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2408         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2409         I915_WRITE(DEIIR, DE_PCU_EVENT);
2410         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2411
2412         /* Go back to the starting frequency */
2413         ironlake_set_drps(dev, dev_priv->ips.fstart);
2414         mdelay(1);
2415         rgvswctl |= MEMCTL_CMD_STS;
2416         I915_WRITE(MEMSWCTL, rgvswctl);
2417         mdelay(1);
2418
2419         spin_unlock_irq(&mchdev_lock);
2420 }
2421
2422 /* There's a funny hw issue where the hw returns all 0 when reading from
2423  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2424  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2425  * all limits and the gpu stuck at whatever frequency it is at atm).
2426  */
2427 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2428 {
2429         u32 limits;
2430
2431         limits = 0;
2432
2433         if (*val >= dev_priv->rps.max_delay)
2434                 *val = dev_priv->rps.max_delay;
2435         limits |= dev_priv->rps.max_delay << 24;
2436
2437         /* Only set the down limit when we've reached the lowest level to avoid
2438          * getting more interrupts, otherwise leave this clear. This prevents a
2439          * race in the hw when coming out of rc6: There's a tiny window where
2440          * the hw runs at the minimal clock before selecting the desired
2441          * frequency, if the down threshold expires in that window we will not
2442          * receive a down interrupt. */
2443         if (*val <= dev_priv->rps.min_delay) {
2444                 *val = dev_priv->rps.min_delay;
2445                 limits |= dev_priv->rps.min_delay << 16;
2446         }
2447
2448         return limits;
2449 }
2450
2451 void gen6_set_rps(struct drm_device *dev, u8 val)
2452 {
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         u32 limits = gen6_rps_limits(dev_priv, &val);
2455
2456         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2457         WARN_ON(val > dev_priv->rps.max_delay);
2458         WARN_ON(val < dev_priv->rps.min_delay);
2459
2460         if (val == dev_priv->rps.cur_delay)
2461                 return;
2462
2463         I915_WRITE(GEN6_RPNSWREQ,
2464                    GEN6_FREQUENCY(val) |
2465                    GEN6_OFFSET(0) |
2466                    GEN6_AGGRESSIVE_TURBO);
2467
2468         /* Make sure we continue to get interrupts
2469          * until we hit the minimum or maximum frequencies.
2470          */
2471         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2472
2473         POSTING_READ(GEN6_RPNSWREQ);
2474
2475         dev_priv->rps.cur_delay = val;
2476
2477         trace_intel_gpu_freq_change(val * 50);
2478 }
2479
2480 static void gen6_disable_rps(struct drm_device *dev)
2481 {
2482         struct drm_i915_private *dev_priv = dev->dev_private;
2483
2484         I915_WRITE(GEN6_RC_CONTROL, 0);
2485         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2486         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2487         I915_WRITE(GEN6_PMIER, 0);
2488         /* Complete PM interrupt masking here doesn't race with the rps work
2489          * item again unmasking PM interrupts because that is using a different
2490          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2491          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2492
2493         spin_lock_irq(&dev_priv->rps.lock);
2494         dev_priv->rps.pm_iir = 0;
2495         spin_unlock_irq(&dev_priv->rps.lock);
2496
2497         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2498 }
2499
2500 int intel_enable_rc6(const struct drm_device *dev)
2501 {
2502         /* Respect the kernel parameter if it is set */
2503         if (i915_enable_rc6 >= 0)
2504                 return i915_enable_rc6;
2505
2506         /* Disable RC6 on Ironlake */
2507         if (INTEL_INFO(dev)->gen == 5)
2508                 return 0;
2509
2510         if (IS_HASWELL(dev)) {
2511                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2512                 return INTEL_RC6_ENABLE;
2513         }
2514
2515         /* snb/ivb have more than one rc6 state. */
2516         if (INTEL_INFO(dev)->gen == 6) {
2517                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2518                 return INTEL_RC6_ENABLE;
2519         }
2520
2521         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2522         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2523 }
2524
2525 static void gen6_enable_rps(struct drm_device *dev)
2526 {
2527         struct drm_i915_private *dev_priv = dev->dev_private;
2528         struct intel_ring_buffer *ring;
2529         u32 rp_state_cap;
2530         u32 gt_perf_status;
2531         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2532         u32 gtfifodbg;
2533         int rc6_mode;
2534         int i, ret;
2535
2536         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2537
2538         /* Here begins a magic sequence of register writes to enable
2539          * auto-downclocking.
2540          *
2541          * Perhaps there might be some value in exposing these to
2542          * userspace...
2543          */
2544         I915_WRITE(GEN6_RC_STATE, 0);
2545
2546         /* Clear the DBG now so we don't confuse earlier errors */
2547         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2548                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2549                 I915_WRITE(GTFIFODBG, gtfifodbg);
2550         }
2551
2552         gen6_gt_force_wake_get(dev_priv);
2553
2554         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2555         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2556
2557         /* In units of 100MHz */
2558         dev_priv->rps.max_delay = rp_state_cap & 0xff;
2559         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2560         dev_priv->rps.cur_delay = 0;
2561
2562         /* disable the counters and set deterministic thresholds */
2563         I915_WRITE(GEN6_RC_CONTROL, 0);
2564
2565         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2566         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2567         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2568         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2569         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2570
2571         for_each_ring(ring, dev_priv, i)
2572                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2573
2574         I915_WRITE(GEN6_RC_SLEEP, 0);
2575         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2576         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2577         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2578         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2579
2580         /* Check if we are enabling RC6 */
2581         rc6_mode = intel_enable_rc6(dev_priv->dev);
2582         if (rc6_mode & INTEL_RC6_ENABLE)
2583                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2584
2585         /* We don't use those on Haswell */
2586         if (!IS_HASWELL(dev)) {
2587                 if (rc6_mode & INTEL_RC6p_ENABLE)
2588                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2589
2590                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2591                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2592         }
2593
2594         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2595                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2596                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2597                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2598
2599         I915_WRITE(GEN6_RC_CONTROL,
2600                    rc6_mask |
2601                    GEN6_RC_CTL_EI_MODE(1) |
2602                    GEN6_RC_CTL_HW_ENABLE);
2603
2604         I915_WRITE(GEN6_RPNSWREQ,
2605                    GEN6_FREQUENCY(10) |
2606                    GEN6_OFFSET(0) |
2607                    GEN6_AGGRESSIVE_TURBO);
2608         I915_WRITE(GEN6_RC_VIDEO_FREQ,
2609                    GEN6_FREQUENCY(12));
2610
2611         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2612         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2613                    dev_priv->rps.max_delay << 24 |
2614                    dev_priv->rps.min_delay << 16);
2615
2616         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2617         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2618         I915_WRITE(GEN6_RP_UP_EI, 66000);
2619         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2620
2621         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2622         I915_WRITE(GEN6_RP_CONTROL,
2623                    GEN6_RP_MEDIA_TURBO |
2624                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2625                    GEN6_RP_MEDIA_IS_GFX |
2626                    GEN6_RP_ENABLE |
2627                    GEN6_RP_UP_BUSY_AVG |
2628                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2629
2630         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2631         if (!ret) {
2632                 pcu_mbox = 0;
2633                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2634                 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2635                         dev_priv->rps.max_delay = pcu_mbox & 0xff;
2636                         DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2637                 }
2638         } else {
2639                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2640         }
2641
2642         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2643
2644         /* requires MSI enabled */
2645         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2646         spin_lock_irq(&dev_priv->rps.lock);
2647         WARN_ON(dev_priv->rps.pm_iir != 0);
2648         I915_WRITE(GEN6_PMIMR, 0);
2649         spin_unlock_irq(&dev_priv->rps.lock);
2650         /* enable all PM interrupts */
2651         I915_WRITE(GEN6_PMINTRMSK, 0);
2652
2653         rc6vids = 0;
2654         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2655         if (IS_GEN6(dev) && ret) {
2656                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2657         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2658                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2659                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2660                 rc6vids &= 0xffff00;
2661                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2662                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2663                 if (ret)
2664                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2665         }
2666
2667         gen6_gt_force_wake_put(dev_priv);
2668 }
2669
2670 static void gen6_update_ring_freq(struct drm_device *dev)
2671 {
2672         struct drm_i915_private *dev_priv = dev->dev_private;
2673         int min_freq = 15;
2674         int gpu_freq;
2675         unsigned int ia_freq, max_ia_freq;
2676         int scaling_factor = 180;
2677
2678         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2679
2680         max_ia_freq = cpufreq_quick_get_max(0);
2681         /*
2682          * Default to measured freq if none found, PCU will ensure we don't go
2683          * over
2684          */
2685         if (!max_ia_freq)
2686                 max_ia_freq = tsc_khz;
2687
2688         /* Convert from kHz to MHz */
2689         max_ia_freq /= 1000;
2690
2691         /*
2692          * For each potential GPU frequency, load a ring frequency we'd like
2693          * to use for memory access.  We do this by specifying the IA frequency
2694          * the PCU should use as a reference to determine the ring frequency.
2695          */
2696         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2697              gpu_freq--) {
2698                 int diff = dev_priv->rps.max_delay - gpu_freq;
2699
2700                 /*
2701                  * For GPU frequencies less than 750MHz, just use the lowest
2702                  * ring freq.
2703                  */
2704                 if (gpu_freq < min_freq)
2705                         ia_freq = 800;
2706                 else
2707                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2708                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2709                 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2710
2711                 sandybridge_pcode_write(dev_priv,
2712                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2713                                         ia_freq | gpu_freq);
2714         }
2715 }
2716
2717 void ironlake_teardown_rc6(struct drm_device *dev)
2718 {
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720
2721         if (dev_priv->ips.renderctx) {
2722                 i915_gem_object_unpin(dev_priv->ips.renderctx);
2723                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2724                 dev_priv->ips.renderctx = NULL;
2725         }
2726
2727         if (dev_priv->ips.pwrctx) {
2728                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2729                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2730                 dev_priv->ips.pwrctx = NULL;
2731         }
2732 }
2733
2734 static void ironlake_disable_rc6(struct drm_device *dev)
2735 {
2736         struct drm_i915_private *dev_priv = dev->dev_private;
2737
2738         if (I915_READ(PWRCTXA)) {
2739                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2740                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2741                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2742                          50);
2743
2744                 I915_WRITE(PWRCTXA, 0);
2745                 POSTING_READ(PWRCTXA);
2746
2747                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2748                 POSTING_READ(RSTDBYCTL);
2749         }
2750 }
2751
2752 static int ironlake_setup_rc6(struct drm_device *dev)
2753 {
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755
2756         if (dev_priv->ips.renderctx == NULL)
2757                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2758         if (!dev_priv->ips.renderctx)
2759                 return -ENOMEM;
2760
2761         if (dev_priv->ips.pwrctx == NULL)
2762                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2763         if (!dev_priv->ips.pwrctx) {
2764                 ironlake_teardown_rc6(dev);
2765                 return -ENOMEM;
2766         }
2767
2768         return 0;
2769 }
2770
2771 static void ironlake_enable_rc6(struct drm_device *dev)
2772 {
2773         struct drm_i915_private *dev_priv = dev->dev_private;
2774         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2775         bool was_interruptible;
2776         int ret;
2777
2778         /* rc6 disabled by default due to repeated reports of hanging during
2779          * boot and resume.
2780          */
2781         if (!intel_enable_rc6(dev))
2782                 return;
2783
2784         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2785
2786         ret = ironlake_setup_rc6(dev);
2787         if (ret)
2788                 return;
2789
2790         was_interruptible = dev_priv->mm.interruptible;
2791         dev_priv->mm.interruptible = false;
2792
2793         /*
2794          * GPU can automatically power down the render unit if given a page
2795          * to save state.
2796          */
2797         ret = intel_ring_begin(ring, 6);
2798         if (ret) {
2799                 ironlake_teardown_rc6(dev);
2800                 dev_priv->mm.interruptible = was_interruptible;
2801                 return;
2802         }
2803
2804         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2805         intel_ring_emit(ring, MI_SET_CONTEXT);
2806         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2807                         MI_MM_SPACE_GTT |
2808                         MI_SAVE_EXT_STATE_EN |
2809                         MI_RESTORE_EXT_STATE_EN |
2810                         MI_RESTORE_INHIBIT);
2811         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2812         intel_ring_emit(ring, MI_NOOP);
2813         intel_ring_emit(ring, MI_FLUSH);
2814         intel_ring_advance(ring);
2815
2816         /*
2817          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2818          * does an implicit flush, combined with MI_FLUSH above, it should be
2819          * safe to assume that renderctx is valid
2820          */
2821         ret = intel_ring_idle(ring);
2822         dev_priv->mm.interruptible = was_interruptible;
2823         if (ret) {
2824                 DRM_ERROR("failed to enable ironlake power power savings\n");
2825                 ironlake_teardown_rc6(dev);
2826                 return;
2827         }
2828
2829         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2830         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2831 }
2832
2833 static unsigned long intel_pxfreq(u32 vidfreq)
2834 {
2835         unsigned long freq;
2836         int div = (vidfreq & 0x3f0000) >> 16;
2837         int post = (vidfreq & 0x3000) >> 12;
2838         int pre = (vidfreq & 0x7);
2839
2840         if (!pre)
2841                 return 0;
2842
2843         freq = ((div * 133333) / ((1<<post) * pre));
2844
2845         return freq;
2846 }
2847
2848 static const struct cparams {
2849         u16 i;
2850         u16 t;
2851         u16 m;
2852         u16 c;
2853 } cparams[] = {
2854         { 1, 1333, 301, 28664 },
2855         { 1, 1066, 294, 24460 },
2856         { 1, 800, 294, 25192 },
2857         { 0, 1333, 276, 27605 },
2858         { 0, 1066, 276, 27605 },
2859         { 0, 800, 231, 23784 },
2860 };
2861
2862 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2863 {
2864         u64 total_count, diff, ret;
2865         u32 count1, count2, count3, m = 0, c = 0;
2866         unsigned long now = jiffies_to_msecs(jiffies), diff1;
2867         int i;
2868
2869         assert_spin_locked(&mchdev_lock);
2870
2871         diff1 = now - dev_priv->ips.last_time1;
2872
2873         /* Prevent division-by-zero if we are asking too fast.
2874          * Also, we don't get interesting results if we are polling
2875          * faster than once in 10ms, so just return the saved value
2876          * in such cases.
2877          */
2878         if (diff1 <= 10)
2879                 return dev_priv->ips.chipset_power;
2880
2881         count1 = I915_READ(DMIEC);
2882         count2 = I915_READ(DDREC);
2883         count3 = I915_READ(CSIEC);
2884
2885         total_count = count1 + count2 + count3;
2886
2887         /* FIXME: handle per-counter overflow */
2888         if (total_count < dev_priv->ips.last_count1) {
2889                 diff = ~0UL - dev_priv->ips.last_count1;
2890                 diff += total_count;
2891         } else {
2892                 diff = total_count - dev_priv->ips.last_count1;
2893         }
2894
2895         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2896                 if (cparams[i].i == dev_priv->ips.c_m &&
2897                     cparams[i].t == dev_priv->ips.r_t) {
2898                         m = cparams[i].m;
2899                         c = cparams[i].c;
2900                         break;
2901                 }
2902         }
2903
2904         diff = div_u64(diff, diff1);
2905         ret = ((m * diff) + c);
2906         ret = div_u64(ret, 10);
2907
2908         dev_priv->ips.last_count1 = total_count;
2909         dev_priv->ips.last_time1 = now;
2910
2911         dev_priv->ips.chipset_power = ret;
2912
2913         return ret;
2914 }
2915
2916 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2917 {
2918         unsigned long val;
2919
2920         if (dev_priv->info->gen != 5)
2921                 return 0;
2922
2923         spin_lock_irq(&mchdev_lock);
2924
2925         val = __i915_chipset_val(dev_priv);
2926
2927         spin_unlock_irq(&mchdev_lock);
2928
2929         return val;
2930 }
2931
2932 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2933 {
2934         unsigned long m, x, b;
2935         u32 tsfs;
2936
2937         tsfs = I915_READ(TSFS);
2938
2939         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2940         x = I915_READ8(TR1);
2941
2942         b = tsfs & TSFS_INTR_MASK;
2943
2944         return ((m * x) / 127) - b;
2945 }
2946
2947 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2948 {
2949         static const struct v_table {
2950                 u16 vd; /* in .1 mil */
2951                 u16 vm; /* in .1 mil */
2952         } v_table[] = {
2953                 { 0, 0, },
2954                 { 375, 0, },
2955                 { 500, 0, },
2956                 { 625, 0, },
2957                 { 750, 0, },
2958                 { 875, 0, },
2959                 { 1000, 0, },
2960                 { 1125, 0, },
2961                 { 4125, 3000, },
2962                 { 4125, 3000, },
2963                 { 4125, 3000, },
2964                 { 4125, 3000, },
2965                 { 4125, 3000, },
2966                 { 4125, 3000, },
2967                 { 4125, 3000, },
2968                 { 4125, 3000, },
2969                 { 4125, 3000, },
2970                 { 4125, 3000, },
2971                 { 4125, 3000, },
2972                 { 4125, 3000, },
2973                 { 4125, 3000, },
2974                 { 4125, 3000, },
2975                 { 4125, 3000, },
2976                 { 4125, 3000, },
2977                 { 4125, 3000, },
2978                 { 4125, 3000, },
2979                 { 4125, 3000, },
2980                 { 4125, 3000, },
2981                 { 4125, 3000, },
2982                 { 4125, 3000, },
2983                 { 4125, 3000, },
2984                 { 4125, 3000, },
2985                 { 4250, 3125, },
2986                 { 4375, 3250, },
2987                 { 4500, 3375, },
2988                 { 4625, 3500, },
2989                 { 4750, 3625, },
2990                 { 4875, 3750, },
2991                 { 5000, 3875, },
2992                 { 5125, 4000, },
2993                 { 5250, 4125, },
2994                 { 5375, 4250, },
2995                 { 5500, 4375, },
2996                 { 5625, 4500, },
2997                 { 5750, 4625, },
2998                 { 5875, 4750, },
2999                 { 6000, 4875, },
3000                 { 6125, 5000, },
3001                 { 6250, 5125, },
3002                 { 6375, 5250, },
3003                 { 6500, 5375, },
3004                 { 6625, 5500, },
3005                 { 6750, 5625, },
3006                 { 6875, 5750, },
3007                 { 7000, 5875, },
3008                 { 7125, 6000, },
3009                 { 7250, 6125, },
3010                 { 7375, 6250, },
3011                 { 7500, 6375, },
3012                 { 7625, 6500, },
3013                 { 7750, 6625, },
3014                 { 7875, 6750, },
3015                 { 8000, 6875, },
3016                 { 8125, 7000, },
3017                 { 8250, 7125, },
3018                 { 8375, 7250, },
3019                 { 8500, 7375, },
3020                 { 8625, 7500, },
3021                 { 8750, 7625, },
3022                 { 8875, 7750, },
3023                 { 9000, 7875, },
3024                 { 9125, 8000, },
3025                 { 9250, 8125, },
3026                 { 9375, 8250, },
3027                 { 9500, 8375, },
3028                 { 9625, 8500, },
3029                 { 9750, 8625, },
3030                 { 9875, 8750, },
3031                 { 10000, 8875, },
3032                 { 10125, 9000, },
3033                 { 10250, 9125, },
3034                 { 10375, 9250, },
3035                 { 10500, 9375, },
3036                 { 10625, 9500, },
3037                 { 10750, 9625, },
3038                 { 10875, 9750, },
3039                 { 11000, 9875, },
3040                 { 11125, 10000, },
3041                 { 11250, 10125, },
3042                 { 11375, 10250, },
3043                 { 11500, 10375, },
3044                 { 11625, 10500, },
3045                 { 11750, 10625, },
3046                 { 11875, 10750, },
3047                 { 12000, 10875, },
3048                 { 12125, 11000, },
3049                 { 12250, 11125, },
3050                 { 12375, 11250, },
3051                 { 12500, 11375, },
3052                 { 12625, 11500, },
3053                 { 12750, 11625, },
3054                 { 12875, 11750, },
3055                 { 13000, 11875, },
3056                 { 13125, 12000, },
3057                 { 13250, 12125, },
3058                 { 13375, 12250, },
3059                 { 13500, 12375, },
3060                 { 13625, 12500, },
3061                 { 13750, 12625, },
3062                 { 13875, 12750, },
3063                 { 14000, 12875, },
3064                 { 14125, 13000, },
3065                 { 14250, 13125, },
3066                 { 14375, 13250, },
3067                 { 14500, 13375, },
3068                 { 14625, 13500, },
3069                 { 14750, 13625, },
3070                 { 14875, 13750, },
3071                 { 15000, 13875, },
3072                 { 15125, 14000, },
3073                 { 15250, 14125, },
3074                 { 15375, 14250, },
3075                 { 15500, 14375, },
3076                 { 15625, 14500, },
3077                 { 15750, 14625, },
3078                 { 15875, 14750, },
3079                 { 16000, 14875, },
3080                 { 16125, 15000, },
3081         };
3082         if (dev_priv->info->is_mobile)
3083                 return v_table[pxvid].vm;
3084         else
3085                 return v_table[pxvid].vd;
3086 }
3087
3088 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3089 {
3090         struct timespec now, diff1;
3091         u64 diff;
3092         unsigned long diffms;
3093         u32 count;
3094
3095         assert_spin_locked(&mchdev_lock);
3096
3097         getrawmonotonic(&now);
3098         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3099
3100         /* Don't divide by 0 */
3101         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3102         if (!diffms)
3103                 return;
3104
3105         count = I915_READ(GFXEC);
3106
3107         if (count < dev_priv->ips.last_count2) {
3108                 diff = ~0UL - dev_priv->ips.last_count2;
3109                 diff += count;
3110         } else {
3111                 diff = count - dev_priv->ips.last_count2;
3112         }
3113
3114         dev_priv->ips.last_count2 = count;
3115         dev_priv->ips.last_time2 = now;
3116
3117         /* More magic constants... */
3118         diff = diff * 1181;
3119         diff = div_u64(diff, diffms * 10);
3120         dev_priv->ips.gfx_power = diff;
3121 }
3122
3123 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3124 {
3125         if (dev_priv->info->gen != 5)
3126                 return;
3127
3128         spin_lock_irq(&mchdev_lock);
3129
3130         __i915_update_gfx_val(dev_priv);
3131
3132         spin_unlock_irq(&mchdev_lock);
3133 }
3134
3135 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3136 {
3137         unsigned long t, corr, state1, corr2, state2;
3138         u32 pxvid, ext_v;
3139
3140         assert_spin_locked(&mchdev_lock);
3141
3142         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3143         pxvid = (pxvid >> 24) & 0x7f;
3144         ext_v = pvid_to_extvid(dev_priv, pxvid);
3145
3146         state1 = ext_v;
3147
3148         t = i915_mch_val(dev_priv);
3149
3150         /* Revel in the empirically derived constants */
3151
3152         /* Correction factor in 1/100000 units */
3153         if (t > 80)
3154                 corr = ((t * 2349) + 135940);
3155         else if (t >= 50)
3156                 corr = ((t * 964) + 29317);
3157         else /* < 50 */
3158                 corr = ((t * 301) + 1004);
3159
3160         corr = corr * ((150142 * state1) / 10000 - 78642);
3161         corr /= 100000;
3162         corr2 = (corr * dev_priv->ips.corr);
3163
3164         state2 = (corr2 * state1) / 10000;
3165         state2 /= 100; /* convert to mW */
3166
3167         __i915_update_gfx_val(dev_priv);
3168
3169         return dev_priv->ips.gfx_power + state2;
3170 }
3171
3172 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3173 {
3174         unsigned long val;
3175
3176         if (dev_priv->info->gen != 5)
3177                 return 0;
3178
3179         spin_lock_irq(&mchdev_lock);
3180
3181         val = __i915_gfx_val(dev_priv);
3182
3183         spin_unlock_irq(&mchdev_lock);
3184
3185         return val;
3186 }
3187
3188 /**
3189  * i915_read_mch_val - return value for IPS use
3190  *
3191  * Calculate and return a value for the IPS driver to use when deciding whether
3192  * we have thermal and power headroom to increase CPU or GPU power budget.
3193  */
3194 unsigned long i915_read_mch_val(void)
3195 {
3196         struct drm_i915_private *dev_priv;
3197         unsigned long chipset_val, graphics_val, ret = 0;
3198
3199         spin_lock_irq(&mchdev_lock);
3200         if (!i915_mch_dev)
3201                 goto out_unlock;
3202         dev_priv = i915_mch_dev;
3203
3204         chipset_val = __i915_chipset_val(dev_priv);
3205         graphics_val = __i915_gfx_val(dev_priv);
3206
3207         ret = chipset_val + graphics_val;
3208
3209 out_unlock:
3210         spin_unlock_irq(&mchdev_lock);
3211
3212         return ret;
3213 }
3214 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3215
3216 /**
3217  * i915_gpu_raise - raise GPU frequency limit
3218  *
3219  * Raise the limit; IPS indicates we have thermal headroom.
3220  */
3221 bool i915_gpu_raise(void)
3222 {
3223         struct drm_i915_private *dev_priv;
3224         bool ret = true;
3225
3226         spin_lock_irq(&mchdev_lock);
3227         if (!i915_mch_dev) {
3228                 ret = false;
3229                 goto out_unlock;
3230         }
3231         dev_priv = i915_mch_dev;
3232
3233         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3234                 dev_priv->ips.max_delay--;
3235
3236 out_unlock:
3237         spin_unlock_irq(&mchdev_lock);
3238
3239         return ret;
3240 }
3241 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3242
3243 /**
3244  * i915_gpu_lower - lower GPU frequency limit
3245  *
3246  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3247  * frequency maximum.
3248  */
3249 bool i915_gpu_lower(void)
3250 {
3251         struct drm_i915_private *dev_priv;
3252         bool ret = true;
3253
3254         spin_lock_irq(&mchdev_lock);
3255         if (!i915_mch_dev) {
3256                 ret = false;
3257                 goto out_unlock;
3258         }
3259         dev_priv = i915_mch_dev;
3260
3261         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3262                 dev_priv->ips.max_delay++;
3263
3264 out_unlock:
3265         spin_unlock_irq(&mchdev_lock);
3266
3267         return ret;
3268 }
3269 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3270
3271 /**
3272  * i915_gpu_busy - indicate GPU business to IPS
3273  *
3274  * Tell the IPS driver whether or not the GPU is busy.
3275  */
3276 bool i915_gpu_busy(void)
3277 {
3278         struct drm_i915_private *dev_priv;
3279         struct intel_ring_buffer *ring;
3280         bool ret = false;
3281         int i;
3282
3283         spin_lock_irq(&mchdev_lock);
3284         if (!i915_mch_dev)
3285                 goto out_unlock;
3286         dev_priv = i915_mch_dev;
3287
3288         for_each_ring(ring, dev_priv, i)
3289                 ret |= !list_empty(&ring->request_list);
3290
3291 out_unlock:
3292         spin_unlock_irq(&mchdev_lock);
3293
3294         return ret;
3295 }
3296 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3297
3298 /**
3299  * i915_gpu_turbo_disable - disable graphics turbo
3300  *
3301  * Disable graphics turbo by resetting the max frequency and setting the
3302  * current frequency to the default.
3303  */
3304 bool i915_gpu_turbo_disable(void)
3305 {
3306         struct drm_i915_private *dev_priv;
3307         bool ret = true;
3308
3309         spin_lock_irq(&mchdev_lock);
3310         if (!i915_mch_dev) {
3311                 ret = false;
3312                 goto out_unlock;
3313         }
3314         dev_priv = i915_mch_dev;
3315
3316         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3317
3318         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3319                 ret = false;
3320
3321 out_unlock:
3322         spin_unlock_irq(&mchdev_lock);
3323
3324         return ret;
3325 }
3326 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3327
3328 /**
3329  * Tells the intel_ips driver that the i915 driver is now loaded, if
3330  * IPS got loaded first.
3331  *
3332  * This awkward dance is so that neither module has to depend on the
3333  * other in order for IPS to do the appropriate communication of
3334  * GPU turbo limits to i915.
3335  */
3336 static void
3337 ips_ping_for_i915_load(void)
3338 {
3339         void (*link)(void);
3340
3341         link = symbol_get(ips_link_to_i915_driver);
3342         if (link) {
3343                 link();
3344                 symbol_put(ips_link_to_i915_driver);
3345         }
3346 }
3347
3348 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3349 {
3350         /* We only register the i915 ips part with intel-ips once everything is
3351          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3352         spin_lock_irq(&mchdev_lock);
3353         i915_mch_dev = dev_priv;
3354         spin_unlock_irq(&mchdev_lock);
3355
3356         ips_ping_for_i915_load();
3357 }
3358
3359 void intel_gpu_ips_teardown(void)
3360 {
3361         spin_lock_irq(&mchdev_lock);
3362         i915_mch_dev = NULL;
3363         spin_unlock_irq(&mchdev_lock);
3364 }
3365 static void intel_init_emon(struct drm_device *dev)
3366 {
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         u32 lcfuse;
3369         u8 pxw[16];
3370         int i;
3371
3372         /* Disable to program */
3373         I915_WRITE(ECR, 0);
3374         POSTING_READ(ECR);
3375
3376         /* Program energy weights for various events */
3377         I915_WRITE(SDEW, 0x15040d00);
3378         I915_WRITE(CSIEW0, 0x007f0000);
3379         I915_WRITE(CSIEW1, 0x1e220004);
3380         I915_WRITE(CSIEW2, 0x04000004);
3381
3382         for (i = 0; i < 5; i++)
3383                 I915_WRITE(PEW + (i * 4), 0);
3384         for (i = 0; i < 3; i++)
3385                 I915_WRITE(DEW + (i * 4), 0);
3386
3387         /* Program P-state weights to account for frequency power adjustment */
3388         for (i = 0; i < 16; i++) {
3389                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3390                 unsigned long freq = intel_pxfreq(pxvidfreq);
3391                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3392                         PXVFREQ_PX_SHIFT;
3393                 unsigned long val;
3394
3395                 val = vid * vid;
3396                 val *= (freq / 1000);
3397                 val *= 255;
3398                 val /= (127*127*900);
3399                 if (val > 0xff)
3400                         DRM_ERROR("bad pxval: %ld\n", val);
3401                 pxw[i] = val;
3402         }
3403         /* Render standby states get 0 weight */
3404         pxw[14] = 0;
3405         pxw[15] = 0;
3406
3407         for (i = 0; i < 4; i++) {
3408                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3409                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3410                 I915_WRITE(PXW + (i * 4), val);
3411         }
3412
3413         /* Adjust magic regs to magic values (more experimental results) */
3414         I915_WRITE(OGW0, 0);
3415         I915_WRITE(OGW1, 0);
3416         I915_WRITE(EG0, 0x00007f00);
3417         I915_WRITE(EG1, 0x0000000e);
3418         I915_WRITE(EG2, 0x000e0000);
3419         I915_WRITE(EG3, 0x68000300);
3420         I915_WRITE(EG4, 0x42000000);
3421         I915_WRITE(EG5, 0x00140031);
3422         I915_WRITE(EG6, 0);
3423         I915_WRITE(EG7, 0);
3424
3425         for (i = 0; i < 8; i++)
3426                 I915_WRITE(PXWL + (i * 4), 0);
3427
3428         /* Enable PMON + select events */
3429         I915_WRITE(ECR, 0x80000019);
3430
3431         lcfuse = I915_READ(LCFUSE02);
3432
3433         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3434 }
3435
3436 void intel_disable_gt_powersave(struct drm_device *dev)
3437 {
3438         struct drm_i915_private *dev_priv = dev->dev_private;
3439
3440         if (IS_IRONLAKE_M(dev)) {
3441                 ironlake_disable_drps(dev);
3442                 ironlake_disable_rc6(dev);
3443         } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3444                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3445                 mutex_lock(&dev_priv->rps.hw_lock);
3446                 gen6_disable_rps(dev);
3447                 mutex_unlock(&dev_priv->rps.hw_lock);
3448         }
3449 }
3450
3451 static void intel_gen6_powersave_work(struct work_struct *work)
3452 {
3453         struct drm_i915_private *dev_priv =
3454                 container_of(work, struct drm_i915_private,
3455                              rps.delayed_resume_work.work);
3456         struct drm_device *dev = dev_priv->dev;
3457
3458         mutex_lock(&dev_priv->rps.hw_lock);
3459         gen6_enable_rps(dev);
3460         gen6_update_ring_freq(dev);
3461         mutex_unlock(&dev_priv->rps.hw_lock);
3462 }
3463
3464 void intel_enable_gt_powersave(struct drm_device *dev)
3465 {
3466         struct drm_i915_private *dev_priv = dev->dev_private;
3467
3468         if (IS_IRONLAKE_M(dev)) {
3469                 ironlake_enable_drps(dev);
3470                 ironlake_enable_rc6(dev);
3471                 intel_init_emon(dev);
3472         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3473                 /*
3474                  * PCU communication is slow and this doesn't need to be
3475                  * done at any specific time, so do this out of our fast path
3476                  * to make resume and init faster.
3477                  */
3478                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3479                                       round_jiffies_up_relative(HZ));
3480         }
3481 }
3482
3483 static void ibx_init_clock_gating(struct drm_device *dev)
3484 {
3485         struct drm_i915_private *dev_priv = dev->dev_private;
3486
3487         /*
3488          * On Ibex Peak and Cougar Point, we need to disable clock
3489          * gating for the panel power sequencer or it will fail to
3490          * start up when no ports are active.
3491          */
3492         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3493 }
3494
3495 static void ironlake_init_clock_gating(struct drm_device *dev)
3496 {
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3499
3500         /* Required for FBC */
3501         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3502                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3503                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3504
3505         I915_WRITE(PCH_3DCGDIS0,
3506                    MARIUNIT_CLOCK_GATE_DISABLE |
3507                    SVSMUNIT_CLOCK_GATE_DISABLE);
3508         I915_WRITE(PCH_3DCGDIS1,
3509                    VFMUNIT_CLOCK_GATE_DISABLE);
3510
3511         /*
3512          * According to the spec the following bits should be set in
3513          * order to enable memory self-refresh
3514          * The bit 22/21 of 0x42004
3515          * The bit 5 of 0x42020
3516          * The bit 15 of 0x45000
3517          */
3518         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3519                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3520                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3521         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3522         I915_WRITE(DISP_ARB_CTL,
3523                    (I915_READ(DISP_ARB_CTL) |
3524                     DISP_FBC_WM_DIS));
3525         I915_WRITE(WM3_LP_ILK, 0);
3526         I915_WRITE(WM2_LP_ILK, 0);
3527         I915_WRITE(WM1_LP_ILK, 0);
3528
3529         /*
3530          * Based on the document from hardware guys the following bits
3531          * should be set unconditionally in order to enable FBC.
3532          * The bit 22 of 0x42000
3533          * The bit 22 of 0x42004
3534          * The bit 7,8,9 of 0x42020.
3535          */
3536         if (IS_IRONLAKE_M(dev)) {
3537                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3538                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3539                            ILK_FBCQ_DIS);
3540                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3541                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3542                            ILK_DPARB_GATE);
3543         }
3544
3545         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3546
3547         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3548                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3549                    ILK_ELPIN_409_SELECT);
3550         I915_WRITE(_3D_CHICKEN2,
3551                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3552                    _3D_CHICKEN2_WM_READ_PIPELINED);
3553
3554         /* WaDisableRenderCachePipelinedFlush */
3555         I915_WRITE(CACHE_MODE_0,
3556                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3557
3558         ibx_init_clock_gating(dev);
3559 }
3560
3561 static void cpt_init_clock_gating(struct drm_device *dev)
3562 {
3563         struct drm_i915_private *dev_priv = dev->dev_private;
3564         int pipe;
3565
3566         /*
3567          * On Ibex Peak and Cougar Point, we need to disable clock
3568          * gating for the panel power sequencer or it will fail to
3569          * start up when no ports are active.
3570          */
3571         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3572         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3573                    DPLS_EDP_PPS_FIX_DIS);
3574         /* The below fixes the weird display corruption, a few pixels shifted
3575          * downward, on (only) LVDS of some HP laptops with IVY.
3576          */
3577         for_each_pipe(pipe)
3578                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
3579         /* WADP0ClockGatingDisable */
3580         for_each_pipe(pipe) {
3581                 I915_WRITE(TRANS_CHICKEN1(pipe),
3582                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3583         }
3584 }
3585
3586 static void gen6_check_mch_setup(struct drm_device *dev)
3587 {
3588         struct drm_i915_private *dev_priv = dev->dev_private;
3589         uint32_t tmp;
3590
3591         tmp = I915_READ(MCH_SSKPD);
3592         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3593                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3594                 DRM_INFO("This can cause pipe underruns and display issues.\n");
3595                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3596         }
3597 }
3598
3599 static void gen6_init_clock_gating(struct drm_device *dev)
3600 {
3601         struct drm_i915_private *dev_priv = dev->dev_private;
3602         int pipe;
3603         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3604
3605         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3606
3607         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3608                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3609                    ILK_ELPIN_409_SELECT);
3610
3611         /* WaDisableHiZPlanesWhenMSAAEnabled */
3612         I915_WRITE(_3D_CHICKEN,
3613                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3614
3615         /* WaSetupGtModeTdRowDispatch */
3616         if (IS_SNB_GT1(dev))
3617                 I915_WRITE(GEN6_GT_MODE,
3618                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3619
3620         I915_WRITE(WM3_LP_ILK, 0);
3621         I915_WRITE(WM2_LP_ILK, 0);
3622         I915_WRITE(WM1_LP_ILK, 0);
3623
3624         I915_WRITE(CACHE_MODE_0,
3625                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3626
3627         I915_WRITE(GEN6_UCGCTL1,
3628                    I915_READ(GEN6_UCGCTL1) |
3629                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3630                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3631
3632         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3633          * gating disable must be set.  Failure to set it results in
3634          * flickering pixels due to Z write ordering failures after
3635          * some amount of runtime in the Mesa "fire" demo, and Unigine
3636          * Sanctuary and Tropics, and apparently anything else with
3637          * alpha test or pixel discard.
3638          *
3639          * According to the spec, bit 11 (RCCUNIT) must also be set,
3640          * but we didn't debug actual testcases to find it out.
3641          *
3642          * Also apply WaDisableVDSUnitClockGating and
3643          * WaDisableRCPBUnitClockGating.
3644          */
3645         I915_WRITE(GEN6_UCGCTL2,
3646                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3647                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3648                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3649
3650         /* Bspec says we need to always set all mask bits. */
3651         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3652                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3653
3654         /*
3655          * According to the spec the following bits should be
3656          * set in order to enable memory self-refresh and fbc:
3657          * The bit21 and bit22 of 0x42000
3658          * The bit21 and bit22 of 0x42004
3659          * The bit5 and bit7 of 0x42020
3660          * The bit14 of 0x70180
3661          * The bit14 of 0x71180
3662          */
3663         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3664                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3665                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3666         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3667                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3668                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3669         I915_WRITE(ILK_DSPCLK_GATE_D,
3670                    I915_READ(ILK_DSPCLK_GATE_D) |
3671                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
3672                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3673
3674         /* WaMbcDriverBootEnable */
3675         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3676                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3677
3678         for_each_pipe(pipe) {
3679                 I915_WRITE(DSPCNTR(pipe),
3680                            I915_READ(DSPCNTR(pipe)) |
3681                            DISPPLANE_TRICKLE_FEED_DISABLE);
3682                 intel_flush_display_plane(dev_priv, pipe);
3683         }
3684
3685         /* The default value should be 0x200 according to docs, but the two
3686          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3687         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3688         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3689
3690         cpt_init_clock_gating(dev);
3691
3692         gen6_check_mch_setup(dev);
3693 }
3694
3695 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3696 {
3697         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3698
3699         reg &= ~GEN7_FF_SCHED_MASK;
3700         reg |= GEN7_FF_TS_SCHED_HW;
3701         reg |= GEN7_FF_VS_SCHED_HW;
3702         reg |= GEN7_FF_DS_SCHED_HW;
3703
3704         /* WaVSRefCountFullforceMissDisable */
3705         if (IS_HASWELL(dev_priv->dev))
3706                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
3707
3708         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3709 }
3710
3711 static void lpt_init_clock_gating(struct drm_device *dev)
3712 {
3713         struct drm_i915_private *dev_priv = dev->dev_private;
3714
3715         /*
3716          * TODO: this bit should only be enabled when really needed, then
3717          * disabled when not needed anymore in order to save power.
3718          */
3719         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3720                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3721                            I915_READ(SOUTH_DSPCLK_GATE_D) |
3722                            PCH_LP_PARTITION_LEVEL_DISABLE);
3723 }
3724
3725 static void haswell_init_clock_gating(struct drm_device *dev)
3726 {
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728         int pipe;
3729
3730         I915_WRITE(WM3_LP_ILK, 0);
3731         I915_WRITE(WM2_LP_ILK, 0);
3732         I915_WRITE(WM1_LP_ILK, 0);
3733
3734         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3735          * This implements the WaDisableRCZUnitClockGating workaround.
3736          */
3737         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3738
3739         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3740         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3741                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3742
3743         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3744         I915_WRITE(GEN7_L3CNTLREG1,
3745                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3746         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3747                         GEN7_WA_L3_CHICKEN_MODE);
3748
3749         /* This is required by WaCatErrorRejectionIssue */
3750         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3751                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3752                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3753
3754         for_each_pipe(pipe) {
3755                 I915_WRITE(DSPCNTR(pipe),
3756                            I915_READ(DSPCNTR(pipe)) |
3757                            DISPPLANE_TRICKLE_FEED_DISABLE);
3758                 intel_flush_display_plane(dev_priv, pipe);
3759         }
3760
3761         gen7_setup_fixed_func_scheduler(dev_priv);
3762
3763         /* WaDisable4x2SubspanOptimization */
3764         I915_WRITE(CACHE_MODE_1,
3765                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3766
3767         /* WaMbcDriverBootEnable */
3768         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3769                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3770
3771         /* XXX: This is a workaround for early silicon revisions and should be
3772          * removed later.
3773          */
3774         I915_WRITE(WM_DBG,
3775                         I915_READ(WM_DBG) |
3776                         WM_DBG_DISALLOW_MULTIPLE_LP |
3777                         WM_DBG_DISALLOW_SPRITE |
3778                         WM_DBG_DISALLOW_MAXFIFO);
3779
3780         lpt_init_clock_gating(dev);
3781 }
3782
3783 static void ivybridge_init_clock_gating(struct drm_device *dev)
3784 {
3785         struct drm_i915_private *dev_priv = dev->dev_private;
3786         int pipe;
3787         uint32_t snpcr;
3788
3789         I915_WRITE(WM3_LP_ILK, 0);
3790         I915_WRITE(WM2_LP_ILK, 0);
3791         I915_WRITE(WM1_LP_ILK, 0);
3792
3793         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3794
3795         /* WaDisableEarlyCull */
3796         I915_WRITE(_3D_CHICKEN3,
3797                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3798
3799         /* WaDisableBackToBackFlipFix */
3800         I915_WRITE(IVB_CHICKEN3,
3801                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3802                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3803
3804         /* WaDisablePSDDualDispatchEnable */
3805         if (IS_IVB_GT1(dev))
3806                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3807                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3808         else
3809                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3810                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3811
3812         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3813         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3814                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3815
3816         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3817         I915_WRITE(GEN7_L3CNTLREG1,
3818                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3819         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3820                    GEN7_WA_L3_CHICKEN_MODE);
3821         if (IS_IVB_GT1(dev))
3822                 I915_WRITE(GEN7_ROW_CHICKEN2,
3823                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3824         else
3825                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3826                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3827
3828
3829         /* WaForceL3Serialization */
3830         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3831                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3832
3833         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3834          * gating disable must be set.  Failure to set it results in
3835          * flickering pixels due to Z write ordering failures after
3836          * some amount of runtime in the Mesa "fire" demo, and Unigine
3837          * Sanctuary and Tropics, and apparently anything else with
3838          * alpha test or pixel discard.
3839          *
3840          * According to the spec, bit 11 (RCCUNIT) must also be set,
3841          * but we didn't debug actual testcases to find it out.
3842          *
3843          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3844          * This implements the WaDisableRCZUnitClockGating workaround.
3845          */
3846         I915_WRITE(GEN6_UCGCTL2,
3847                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3848                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3849
3850         /* This is required by WaCatErrorRejectionIssue */
3851         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3852                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3853                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3854
3855         for_each_pipe(pipe) {
3856                 I915_WRITE(DSPCNTR(pipe),
3857                            I915_READ(DSPCNTR(pipe)) |
3858                            DISPPLANE_TRICKLE_FEED_DISABLE);
3859                 intel_flush_display_plane(dev_priv, pipe);
3860         }
3861
3862         /* WaMbcDriverBootEnable */
3863         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3864                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3865
3866         gen7_setup_fixed_func_scheduler(dev_priv);
3867
3868         /* WaDisable4x2SubspanOptimization */
3869         I915_WRITE(CACHE_MODE_1,
3870                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3871
3872         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3873         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3874         snpcr |= GEN6_MBC_SNPCR_MED;
3875         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3876
3877         cpt_init_clock_gating(dev);
3878
3879         gen6_check_mch_setup(dev);
3880 }
3881
3882 static void valleyview_init_clock_gating(struct drm_device *dev)
3883 {
3884         struct drm_i915_private *dev_priv = dev->dev_private;
3885         int pipe;
3886
3887         I915_WRITE(WM3_LP_ILK, 0);
3888         I915_WRITE(WM2_LP_ILK, 0);
3889         I915_WRITE(WM1_LP_ILK, 0);
3890
3891         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3892
3893         /* WaDisableEarlyCull */
3894         I915_WRITE(_3D_CHICKEN3,
3895                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3896
3897         /* WaDisableBackToBackFlipFix */
3898         I915_WRITE(IVB_CHICKEN3,
3899                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3900                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3901
3902         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3903                    _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3904
3905         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3906         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3907                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3908
3909         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3910         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3911         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3912
3913         /* WaForceL3Serialization */
3914         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3915                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3916
3917         /* WaDisableDopClockGating */
3918         I915_WRITE(GEN7_ROW_CHICKEN2,
3919                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3920
3921         /* WaForceL3Serialization */
3922         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3923                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3924
3925         /* This is required by WaCatErrorRejectionIssue */
3926         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3927                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3928                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3929
3930         /* WaMbcDriverBootEnable */
3931         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3932                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3933
3934
3935         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3936          * gating disable must be set.  Failure to set it results in
3937          * flickering pixels due to Z write ordering failures after
3938          * some amount of runtime in the Mesa "fire" demo, and Unigine
3939          * Sanctuary and Tropics, and apparently anything else with
3940          * alpha test or pixel discard.
3941          *
3942          * According to the spec, bit 11 (RCCUNIT) must also be set,
3943          * but we didn't debug actual testcases to find it out.
3944          *
3945          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3946          * This implements the WaDisableRCZUnitClockGating workaround.
3947          *
3948          * Also apply WaDisableVDSUnitClockGating and
3949          * WaDisableRCPBUnitClockGating.
3950          */
3951         I915_WRITE(GEN6_UCGCTL2,
3952                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3953                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3954                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3955                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3956                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3957
3958         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3959
3960         for_each_pipe(pipe) {
3961                 I915_WRITE(DSPCNTR(pipe),
3962                            I915_READ(DSPCNTR(pipe)) |
3963                            DISPPLANE_TRICKLE_FEED_DISABLE);
3964                 intel_flush_display_plane(dev_priv, pipe);
3965         }
3966
3967         I915_WRITE(CACHE_MODE_1,
3968                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3969
3970         /*
3971          * On ValleyView, the GUnit needs to signal the GT
3972          * when flip and other events complete.  So enable
3973          * all the GUnit->GT interrupts here
3974          */
3975         I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3976                    PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3977                    SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3978                    PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3979                    PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3980                    SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3981                    PLANEA_FLIPDONE_INT_EN);
3982
3983         /*
3984          * WaDisableVLVClockGating_VBIIssue
3985          * Disable clock gating on th GCFG unit to prevent a delay
3986          * in the reporting of vblank events.
3987          */
3988         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
3989 }
3990
3991 static void g4x_init_clock_gating(struct drm_device *dev)
3992 {
3993         struct drm_i915_private *dev_priv = dev->dev_private;
3994         uint32_t dspclk_gate;
3995
3996         I915_WRITE(RENCLK_GATE_D1, 0);
3997         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3998                    GS_UNIT_CLOCK_GATE_DISABLE |
3999                    CL_UNIT_CLOCK_GATE_DISABLE);
4000         I915_WRITE(RAMCLK_GATE_D, 0);
4001         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4002                 OVRUNIT_CLOCK_GATE_DISABLE |
4003                 OVCUNIT_CLOCK_GATE_DISABLE;
4004         if (IS_GM45(dev))
4005                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4006         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4007
4008         /* WaDisableRenderCachePipelinedFlush */
4009         I915_WRITE(CACHE_MODE_0,
4010                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4011 }
4012
4013 static void crestline_init_clock_gating(struct drm_device *dev)
4014 {
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016
4017         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4018         I915_WRITE(RENCLK_GATE_D2, 0);
4019         I915_WRITE(DSPCLK_GATE_D, 0);
4020         I915_WRITE(RAMCLK_GATE_D, 0);
4021         I915_WRITE16(DEUC, 0);
4022 }
4023
4024 static void broadwater_init_clock_gating(struct drm_device *dev)
4025 {
4026         struct drm_i915_private *dev_priv = dev->dev_private;
4027
4028         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4029                    I965_RCC_CLOCK_GATE_DISABLE |
4030                    I965_RCPB_CLOCK_GATE_DISABLE |
4031                    I965_ISC_CLOCK_GATE_DISABLE |
4032                    I965_FBC_CLOCK_GATE_DISABLE);
4033         I915_WRITE(RENCLK_GATE_D2, 0);
4034 }
4035
4036 static void gen3_init_clock_gating(struct drm_device *dev)
4037 {
4038         struct drm_i915_private *dev_priv = dev->dev_private;
4039         u32 dstate = I915_READ(D_STATE);
4040
4041         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4042                 DSTATE_DOT_CLOCK_GATING;
4043         I915_WRITE(D_STATE, dstate);
4044
4045         if (IS_PINEVIEW(dev))
4046                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4047
4048         /* IIR "flip pending" means done if this bit is set */
4049         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4050 }
4051
4052 static void i85x_init_clock_gating(struct drm_device *dev)
4053 {
4054         struct drm_i915_private *dev_priv = dev->dev_private;
4055
4056         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4057 }
4058
4059 static void i830_init_clock_gating(struct drm_device *dev)
4060 {
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062
4063         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4064 }
4065
4066 void intel_init_clock_gating(struct drm_device *dev)
4067 {
4068         struct drm_i915_private *dev_priv = dev->dev_private;
4069
4070         dev_priv->display.init_clock_gating(dev);
4071 }
4072
4073 void intel_set_power_well(struct drm_device *dev, bool enable)
4074 {
4075         struct drm_i915_private *dev_priv = dev->dev_private;
4076         bool is_enabled, enable_requested;
4077         uint32_t tmp;
4078
4079         if (!IS_HASWELL(dev))
4080                 return;
4081
4082         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4083         is_enabled = tmp & HSW_PWR_WELL_STATE;
4084         enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4085
4086         if (enable) {
4087                 if (!enable_requested)
4088                         I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4089
4090                 if (!is_enabled) {
4091                         DRM_DEBUG_KMS("Enabling power well\n");
4092                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4093                                       HSW_PWR_WELL_STATE), 20))
4094                                 DRM_ERROR("Timeout enabling power well\n");
4095                 }
4096         } else {
4097                 if (enable_requested) {
4098                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4099                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
4100                 }
4101         }
4102 }
4103
4104 /*
4105  * Starting with Haswell, we have a "Power Down Well" that can be turned off
4106  * when not needed anymore. We have 4 registers that can request the power well
4107  * to be enabled, and it will only be disabled if none of the registers is
4108  * requesting it to be enabled.
4109  */
4110 void intel_init_power_well(struct drm_device *dev)
4111 {
4112         struct drm_i915_private *dev_priv = dev->dev_private;
4113
4114         if (!IS_HASWELL(dev))
4115                 return;
4116
4117         /* For now, we need the power well to be always enabled. */
4118         intel_set_power_well(dev, true);
4119
4120         /* We're taking over the BIOS, so clear any requests made by it since
4121          * the driver is in charge now. */
4122         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4123                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4124 }
4125
4126 /* Set up chip specific power management-related functions */
4127 void intel_init_pm(struct drm_device *dev)
4128 {
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130
4131         if (I915_HAS_FBC(dev)) {
4132                 if (HAS_PCH_SPLIT(dev)) {
4133                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4134                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
4135                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4136                 } else if (IS_GM45(dev)) {
4137                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4138                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4139                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4140                 } else if (IS_CRESTLINE(dev)) {
4141                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4142                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4143                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4144                 }
4145                 /* 855GM needs testing */
4146         }
4147
4148         /* For cxsr */
4149         if (IS_PINEVIEW(dev))
4150                 i915_pineview_get_mem_freq(dev);
4151         else if (IS_GEN5(dev))
4152                 i915_ironlake_get_mem_freq(dev);
4153
4154         /* For FIFO watermark updates */
4155         if (HAS_PCH_SPLIT(dev)) {
4156                 if (IS_GEN5(dev)) {
4157                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4158                                 dev_priv->display.update_wm = ironlake_update_wm;
4159                         else {
4160                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4161                                               "Disable CxSR\n");
4162                                 dev_priv->display.update_wm = NULL;
4163                         }
4164                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4165                 } else if (IS_GEN6(dev)) {
4166                         if (SNB_READ_WM0_LATENCY()) {
4167                                 dev_priv->display.update_wm = sandybridge_update_wm;
4168                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4169                         } else {
4170                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4171                                               "Disable CxSR\n");
4172                                 dev_priv->display.update_wm = NULL;
4173                         }
4174                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4175                 } else if (IS_IVYBRIDGE(dev)) {
4176                         /* FIXME: detect B0+ stepping and use auto training */
4177                         if (SNB_READ_WM0_LATENCY()) {
4178                                 dev_priv->display.update_wm = ivybridge_update_wm;
4179                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4180                         } else {
4181                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4182                                               "Disable CxSR\n");
4183                                 dev_priv->display.update_wm = NULL;
4184                         }
4185                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4186                 } else if (IS_HASWELL(dev)) {
4187                         if (SNB_READ_WM0_LATENCY()) {
4188                                 dev_priv->display.update_wm = sandybridge_update_wm;
4189                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4190                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4191                         } else {
4192                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4193                                               "Disable CxSR\n");
4194                                 dev_priv->display.update_wm = NULL;
4195                         }
4196                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4197                 } else
4198                         dev_priv->display.update_wm = NULL;
4199         } else if (IS_VALLEYVIEW(dev)) {
4200                 dev_priv->display.update_wm = valleyview_update_wm;
4201                 dev_priv->display.init_clock_gating =
4202                         valleyview_init_clock_gating;
4203         } else if (IS_PINEVIEW(dev)) {
4204                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4205                                             dev_priv->is_ddr3,
4206                                             dev_priv->fsb_freq,
4207                                             dev_priv->mem_freq)) {
4208                         DRM_INFO("failed to find known CxSR latency "
4209                                  "(found ddr%s fsb freq %d, mem freq %d), "
4210                                  "disabling CxSR\n",
4211                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4212                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4213                         /* Disable CxSR and never update its watermark again */
4214                         pineview_disable_cxsr(dev);
4215                         dev_priv->display.update_wm = NULL;
4216                 } else
4217                         dev_priv->display.update_wm = pineview_update_wm;
4218                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4219         } else if (IS_G4X(dev)) {
4220                 dev_priv->display.update_wm = g4x_update_wm;
4221                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4222         } else if (IS_GEN4(dev)) {
4223                 dev_priv->display.update_wm = i965_update_wm;
4224                 if (IS_CRESTLINE(dev))
4225                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4226                 else if (IS_BROADWATER(dev))
4227                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4228         } else if (IS_GEN3(dev)) {
4229                 dev_priv->display.update_wm = i9xx_update_wm;
4230                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4231                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4232         } else if (IS_I865G(dev)) {
4233                 dev_priv->display.update_wm = i830_update_wm;
4234                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4235                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4236         } else if (IS_I85X(dev)) {
4237                 dev_priv->display.update_wm = i9xx_update_wm;
4238                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4239                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4240         } else {
4241                 dev_priv->display.update_wm = i830_update_wm;
4242                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4243                 if (IS_845G(dev))
4244                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4245                 else
4246                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4247         }
4248 }
4249
4250 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4251 {
4252         u32 gt_thread_status_mask;
4253
4254         if (IS_HASWELL(dev_priv->dev))
4255                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4256         else
4257                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4258
4259         /* w/a for a sporadic read returning 0 by waiting for the GT
4260          * thread to wake up.
4261          */
4262         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4263                 DRM_ERROR("GT thread status wait timed out\n");
4264 }
4265
4266 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4267 {
4268         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4269         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4270 }
4271
4272 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4273 {
4274         u32 forcewake_ack;
4275
4276         if (IS_HASWELL(dev_priv->dev))
4277                 forcewake_ack = FORCEWAKE_ACK_HSW;
4278         else
4279                 forcewake_ack = FORCEWAKE_ACK;
4280
4281         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4282                             FORCEWAKE_ACK_TIMEOUT_MS))
4283                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4284
4285         I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4286         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4287
4288         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4289                             FORCEWAKE_ACK_TIMEOUT_MS))
4290                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4291
4292         __gen6_gt_wait_for_thread_c0(dev_priv);
4293 }
4294
4295 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4296 {
4297         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4298         /* something from same cacheline, but !FORCEWAKE_MT */
4299         POSTING_READ(ECOBUS);
4300 }
4301
4302 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4303 {
4304         u32 forcewake_ack;
4305
4306         if (IS_HASWELL(dev_priv->dev))
4307                 forcewake_ack = FORCEWAKE_ACK_HSW;
4308         else
4309                 forcewake_ack = FORCEWAKE_MT_ACK;
4310
4311         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4312                             FORCEWAKE_ACK_TIMEOUT_MS))
4313                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4314
4315         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4316         /* something from same cacheline, but !FORCEWAKE_MT */
4317         POSTING_READ(ECOBUS);
4318
4319         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4320                             FORCEWAKE_ACK_TIMEOUT_MS))
4321                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4322
4323         __gen6_gt_wait_for_thread_c0(dev_priv);
4324 }
4325
4326 /*
4327  * Generally this is called implicitly by the register read function. However,
4328  * if some sequence requires the GT to not power down then this function should
4329  * be called at the beginning of the sequence followed by a call to
4330  * gen6_gt_force_wake_put() at the end of the sequence.
4331  */
4332 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4333 {
4334         unsigned long irqflags;
4335
4336         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4337         if (dev_priv->forcewake_count++ == 0)
4338                 dev_priv->gt.force_wake_get(dev_priv);
4339         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4340 }
4341
4342 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4343 {
4344         u32 gtfifodbg;
4345         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4346         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4347              "MMIO read or write has been dropped %x\n", gtfifodbg))
4348                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4349 }
4350
4351 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4352 {
4353         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4354         /* something from same cacheline, but !FORCEWAKE */
4355         POSTING_READ(ECOBUS);
4356         gen6_gt_check_fifodbg(dev_priv);
4357 }
4358
4359 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4360 {
4361         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4362         /* something from same cacheline, but !FORCEWAKE_MT */
4363         POSTING_READ(ECOBUS);
4364         gen6_gt_check_fifodbg(dev_priv);
4365 }
4366
4367 /*
4368  * see gen6_gt_force_wake_get()
4369  */
4370 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4371 {
4372         unsigned long irqflags;
4373
4374         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4375         if (--dev_priv->forcewake_count == 0)
4376                 dev_priv->gt.force_wake_put(dev_priv);
4377         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4378 }
4379
4380 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4381 {
4382         int ret = 0;
4383
4384         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4385                 int loop = 500;
4386                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4387                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4388                         udelay(10);
4389                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4390                 }
4391                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4392                         ++ret;
4393                 dev_priv->gt_fifo_count = fifo;
4394         }
4395         dev_priv->gt_fifo_count--;
4396
4397         return ret;
4398 }
4399
4400 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4401 {
4402         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4403         /* something from same cacheline, but !FORCEWAKE_VLV */
4404         POSTING_READ(FORCEWAKE_ACK_VLV);
4405 }
4406
4407 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4408 {
4409         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4410                             FORCEWAKE_ACK_TIMEOUT_MS))
4411                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4412
4413         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4414
4415         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4416                             FORCEWAKE_ACK_TIMEOUT_MS))
4417                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4418
4419         __gen6_gt_wait_for_thread_c0(dev_priv);
4420 }
4421
4422 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4423 {
4424         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4425         /* something from same cacheline, but !FORCEWAKE_VLV */
4426         POSTING_READ(FORCEWAKE_ACK_VLV);
4427         gen6_gt_check_fifodbg(dev_priv);
4428 }
4429
4430 void intel_gt_reset(struct drm_device *dev)
4431 {
4432         struct drm_i915_private *dev_priv = dev->dev_private;
4433
4434         if (IS_VALLEYVIEW(dev)) {
4435                 vlv_force_wake_reset(dev_priv);
4436         } else if (INTEL_INFO(dev)->gen >= 6) {
4437                 __gen6_gt_force_wake_reset(dev_priv);
4438                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4439                         __gen6_gt_force_wake_mt_reset(dev_priv);
4440         }
4441 }
4442
4443 void intel_gt_init(struct drm_device *dev)
4444 {
4445         struct drm_i915_private *dev_priv = dev->dev_private;
4446
4447         spin_lock_init(&dev_priv->gt_lock);
4448
4449         intel_gt_reset(dev);
4450
4451         if (IS_VALLEYVIEW(dev)) {
4452                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4453                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4454         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4455                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4456                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4457         } else if (IS_GEN6(dev)) {
4458                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4459                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4460         }
4461         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4462                           intel_gen6_powersave_work);
4463 }
4464
4465 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4466 {
4467         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4468
4469         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4470                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4471                 return -EAGAIN;
4472         }
4473
4474         I915_WRITE(GEN6_PCODE_DATA, *val);
4475         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4476
4477         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4478                      500)) {
4479                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4480                 return -ETIMEDOUT;
4481         }
4482
4483         *val = I915_READ(GEN6_PCODE_DATA);
4484         I915_WRITE(GEN6_PCODE_DATA, 0);
4485
4486         return 0;
4487 }
4488
4489 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4490 {
4491         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4492
4493         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4494                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4495                 return -EAGAIN;
4496         }
4497
4498         I915_WRITE(GEN6_PCODE_DATA, val);
4499         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4500
4501         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4502                      500)) {
4503                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4504                 return -ETIMEDOUT;
4505         }
4506
4507         I915_WRITE(GEN6_PCODE_DATA, 0);
4508
4509         return 0;
4510 }