2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
47 static void i8xx_disable_fbc(struct drm_device *dev)
49 struct drm_i915_private *dev_priv = dev->dev_private;
52 /* Disable compression */
53 fbc_ctl = I915_READ(FBC_CONTROL);
54 if ((fbc_ctl & FBC_CTL_EN) == 0)
57 fbc_ctl &= ~FBC_CTL_EN;
58 I915_WRITE(FBC_CONTROL, fbc_ctl);
60 /* Wait for compressing bit to clear */
61 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
62 DRM_DEBUG_KMS("FBC idle timed out\n");
66 DRM_DEBUG_KMS("disabled FBC\n");
69 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
71 struct drm_device *dev = crtc->dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
73 struct drm_framebuffer *fb = crtc->fb;
74 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
75 struct drm_i915_gem_object *obj = intel_fb->obj;
76 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79 u32 fbc_ctl, fbc_ctl2;
81 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
82 if (fb->pitches[0] < cfb_pitch)
83 cfb_pitch = fb->pitches[0];
85 /* FBC_CTL wants 64B units */
86 cfb_pitch = (cfb_pitch / 64) - 1;
87 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
90 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
91 I915_WRITE(FBC_TAG + (i * 4), 0);
94 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
96 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
97 I915_WRITE(FBC_FENCE_OFF, crtc->y);
100 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
102 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
103 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
104 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
105 fbc_ctl |= obj->fence_reg;
106 I915_WRITE(FBC_CONTROL, fbc_ctl);
108 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
109 cfb_pitch, crtc->y, intel_crtc->plane);
112 static bool i8xx_fbc_enabled(struct drm_device *dev)
114 struct drm_i915_private *dev_priv = dev->dev_private;
116 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
119 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
121 struct drm_device *dev = crtc->dev;
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct drm_framebuffer *fb = crtc->fb;
124 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
125 struct drm_i915_gem_object *obj = intel_fb->obj;
126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
127 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
128 unsigned long stall_watermark = 200;
131 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
132 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
133 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
135 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
136 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
137 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
138 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
141 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
143 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
146 static void g4x_disable_fbc(struct drm_device *dev)
148 struct drm_i915_private *dev_priv = dev->dev_private;
151 /* Disable compression */
152 dpfc_ctl = I915_READ(DPFC_CONTROL);
153 if (dpfc_ctl & DPFC_CTL_EN) {
154 dpfc_ctl &= ~DPFC_CTL_EN;
155 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
157 DRM_DEBUG_KMS("disabled FBC\n");
161 static bool g4x_fbc_enabled(struct drm_device *dev)
163 struct drm_i915_private *dev_priv = dev->dev_private;
165 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
168 static void sandybridge_blit_fbc_update(struct drm_device *dev)
170 struct drm_i915_private *dev_priv = dev->dev_private;
173 /* Make sure blitter notifies FBC of writes */
174 gen6_gt_force_wake_get(dev_priv);
175 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
176 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
177 GEN6_BLITTER_LOCK_SHIFT;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
179 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
180 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
181 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
182 GEN6_BLITTER_LOCK_SHIFT);
183 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
184 POSTING_READ(GEN6_BLITTER_ECOSKPD);
185 gen6_gt_force_wake_put(dev_priv);
188 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
190 struct drm_device *dev = crtc->dev;
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct drm_framebuffer *fb = crtc->fb;
193 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
194 struct drm_i915_gem_object *obj = intel_fb->obj;
195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
196 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
197 unsigned long stall_watermark = 200;
200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
201 dpfc_ctl &= DPFC_RESERVED;
202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
203 /* Set persistent mode for front-buffer rendering, ala X. */
204 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
205 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
206 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
208 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
209 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
210 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
211 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
212 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
214 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
217 I915_WRITE(SNB_DPFC_CTL_SA,
218 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
219 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
220 sandybridge_blit_fbc_update(dev);
223 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
226 static void ironlake_disable_fbc(struct drm_device *dev)
228 struct drm_i915_private *dev_priv = dev->dev_private;
231 /* Disable compression */
232 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
233 if (dpfc_ctl & DPFC_CTL_EN) {
234 dpfc_ctl &= ~DPFC_CTL_EN;
235 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
237 DRM_DEBUG_KMS("disabled FBC\n");
241 static bool ironlake_fbc_enabled(struct drm_device *dev)
243 struct drm_i915_private *dev_priv = dev->dev_private;
245 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
248 bool intel_fbc_enabled(struct drm_device *dev)
250 struct drm_i915_private *dev_priv = dev->dev_private;
252 if (!dev_priv->display.fbc_enabled)
255 return dev_priv->display.fbc_enabled(dev);
258 static void intel_fbc_work_fn(struct work_struct *__work)
260 struct intel_fbc_work *work =
261 container_of(to_delayed_work(__work),
262 struct intel_fbc_work, work);
263 struct drm_device *dev = work->crtc->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private;
266 mutex_lock(&dev->struct_mutex);
267 if (work == dev_priv->fbc_work) {
268 /* Double check that we haven't switched fb without cancelling
271 if (work->crtc->fb == work->fb) {
272 dev_priv->display.enable_fbc(work->crtc,
275 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
276 dev_priv->cfb_fb = work->crtc->fb->base.id;
277 dev_priv->cfb_y = work->crtc->y;
280 dev_priv->fbc_work = NULL;
282 mutex_unlock(&dev->struct_mutex);
287 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
289 if (dev_priv->fbc_work == NULL)
292 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
294 /* Synchronisation is provided by struct_mutex and checking of
295 * dev_priv->fbc_work, so we can perform the cancellation
296 * entirely asynchronously.
298 if (cancel_delayed_work(&dev_priv->fbc_work->work))
299 /* tasklet was killed before being run, clean up */
300 kfree(dev_priv->fbc_work);
302 /* Mark the work as no longer wanted so that if it does
303 * wake-up (because the work was already running and waiting
304 * for our mutex), it will discover that is no longer
307 dev_priv->fbc_work = NULL;
310 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
312 struct intel_fbc_work *work;
313 struct drm_device *dev = crtc->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
316 if (!dev_priv->display.enable_fbc)
319 intel_cancel_fbc_work(dev_priv);
321 work = kzalloc(sizeof *work, GFP_KERNEL);
323 dev_priv->display.enable_fbc(crtc, interval);
329 work->interval = interval;
330 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
332 dev_priv->fbc_work = work;
334 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
336 /* Delay the actual enabling to let pageflipping cease and the
337 * display to settle before starting the compression. Note that
338 * this delay also serves a second purpose: it allows for a
339 * vblank to pass after disabling the FBC before we attempt
340 * to modify the control registers.
342 * A more complicated solution would involve tracking vblanks
343 * following the termination of the page-flipping sequence
344 * and indeed performing the enable as a co-routine and not
345 * waiting synchronously upon the vblank.
347 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
350 void intel_disable_fbc(struct drm_device *dev)
352 struct drm_i915_private *dev_priv = dev->dev_private;
354 intel_cancel_fbc_work(dev_priv);
356 if (!dev_priv->display.disable_fbc)
359 dev_priv->display.disable_fbc(dev);
360 dev_priv->cfb_plane = -1;
364 * intel_update_fbc - enable/disable FBC as needed
365 * @dev: the drm_device
367 * Set up the framebuffer compression hardware at mode set time. We
368 * enable it if possible:
369 * - plane A only (on pre-965)
370 * - no pixel mulitply/line duplication
371 * - no alpha buffer discard
373 * - framebuffer <= 2048 in width, 1536 in height
375 * We can't assume that any compression will take place (worst case),
376 * so the compressed buffer has to be the same size as the uncompressed
377 * one. It also must reside (along with the line length buffer) in
380 * We need to enable/disable FBC on a global basis.
382 void intel_update_fbc(struct drm_device *dev)
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 struct drm_crtc *crtc = NULL, *tmp_crtc;
386 struct intel_crtc *intel_crtc;
387 struct drm_framebuffer *fb;
388 struct intel_framebuffer *intel_fb;
389 struct drm_i915_gem_object *obj;
395 if (!I915_HAS_FBC(dev))
399 * If FBC is already on, we just have to verify that we can
400 * keep it that way...
401 * Need to disable if:
402 * - more than one pipe is active
403 * - changing FBC params (stride, fence, mode)
404 * - new fb is too large to fit in compressed buffer
405 * - going to an unsupported config (interlace, pixel multiply, etc.)
407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
408 if (tmp_crtc->enabled &&
409 !to_intel_crtc(tmp_crtc)->primary_disabled &&
412 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
413 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
420 if (!crtc || crtc->fb == NULL) {
421 DRM_DEBUG_KMS("no output, disabling\n");
422 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
426 intel_crtc = to_intel_crtc(crtc);
428 intel_fb = to_intel_framebuffer(fb);
431 enable_fbc = i915_enable_fbc;
432 if (enable_fbc < 0) {
433 DRM_DEBUG_KMS("fbc set to per-chip default\n");
435 if (INTEL_INFO(dev)->gen <= 6)
439 DRM_DEBUG_KMS("fbc disabled per module param\n");
440 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
443 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
444 DRM_DEBUG_KMS("framebuffer too large, disabling "
446 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
451 DRM_DEBUG_KMS("mode incompatible with compression, "
453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
456 if ((crtc->mode.hdisplay > 2048) ||
457 (crtc->mode.vdisplay > 1536)) {
458 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
463 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
464 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
468 /* The use of a CPU fence is mandatory in order to detect writes
469 * by the CPU to the scanout and trigger updates to the FBC.
471 if (obj->tiling_mode != I915_TILING_X ||
472 obj->fence_reg == I915_FENCE_REG_NONE) {
473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
474 dev_priv->no_fbc_reason = FBC_NOT_TILED;
478 /* If the kernel debugger is active, always disable compression */
482 /* If the scanout has not changed, don't modify the FBC settings.
483 * Note that we make the fundamental assumption that the fb->obj
484 * cannot be unpinned (and have its GTT offset and fence revoked)
485 * without first being decoupled from the scanout and FBC disabled.
487 if (dev_priv->cfb_plane == intel_crtc->plane &&
488 dev_priv->cfb_fb == fb->base.id &&
489 dev_priv->cfb_y == crtc->y)
492 if (intel_fbc_enabled(dev)) {
493 /* We update FBC along two paths, after changing fb/crtc
494 * configuration (modeswitching) and after page-flipping
495 * finishes. For the latter, we know that not only did
496 * we disable the FBC at the start of the page-flip
497 * sequence, but also more than one vblank has passed.
499 * For the former case of modeswitching, it is possible
500 * to switch between two FBC valid configurations
501 * instantaneously so we do need to disable the FBC
502 * before we can modify its control registers. We also
503 * have to wait for the next vblank for that to take
504 * effect. However, since we delay enabling FBC we can
505 * assume that a vblank has passed since disabling and
506 * that we can safely alter the registers in the deferred
509 * In the scenario that we go from a valid to invalid
510 * and then back to valid FBC configuration we have
511 * no strict enforcement that a vblank occurred since
512 * disabling the FBC. However, along all current pipe
513 * disabling paths we do need to wait for a vblank at
514 * some point. And we wait before enabling FBC anyway.
516 DRM_DEBUG_KMS("disabling active FBC for update\n");
517 intel_disable_fbc(dev);
520 intel_enable_fbc(crtc, 500);
524 /* Multiple disables should be harmless */
525 if (intel_fbc_enabled(dev)) {
526 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
527 intel_disable_fbc(dev);
531 static void i915_pineview_get_mem_freq(struct drm_device *dev)
533 drm_i915_private_t *dev_priv = dev->dev_private;
536 tmp = I915_READ(CLKCFG);
538 switch (tmp & CLKCFG_FSB_MASK) {
540 dev_priv->fsb_freq = 533; /* 133*4 */
543 dev_priv->fsb_freq = 800; /* 200*4 */
546 dev_priv->fsb_freq = 667; /* 167*4 */
549 dev_priv->fsb_freq = 400; /* 100*4 */
553 switch (tmp & CLKCFG_MEM_MASK) {
555 dev_priv->mem_freq = 533;
558 dev_priv->mem_freq = 667;
561 dev_priv->mem_freq = 800;
565 /* detect pineview DDR3 setting */
566 tmp = I915_READ(CSHRDDR3CTL);
567 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
570 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
572 drm_i915_private_t *dev_priv = dev->dev_private;
575 ddrpll = I915_READ16(DDRMPLL1);
576 csipll = I915_READ16(CSIPLL0);
578 switch (ddrpll & 0xff) {
580 dev_priv->mem_freq = 800;
583 dev_priv->mem_freq = 1066;
586 dev_priv->mem_freq = 1333;
589 dev_priv->mem_freq = 1600;
592 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
594 dev_priv->mem_freq = 0;
598 dev_priv->ips.r_t = dev_priv->mem_freq;
600 switch (csipll & 0x3ff) {
602 dev_priv->fsb_freq = 3200;
605 dev_priv->fsb_freq = 3733;
608 dev_priv->fsb_freq = 4266;
611 dev_priv->fsb_freq = 4800;
614 dev_priv->fsb_freq = 5333;
617 dev_priv->fsb_freq = 5866;
620 dev_priv->fsb_freq = 6400;
623 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
625 dev_priv->fsb_freq = 0;
629 if (dev_priv->fsb_freq == 3200) {
630 dev_priv->ips.c_m = 0;
631 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
632 dev_priv->ips.c_m = 1;
634 dev_priv->ips.c_m = 2;
638 static const struct cxsr_latency cxsr_latency_table[] = {
639 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
640 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
641 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
642 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
643 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
645 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
646 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
647 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
648 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
649 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
651 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
652 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
653 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
654 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
655 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
657 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
658 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
659 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
660 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
661 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
663 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
664 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
665 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
666 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
667 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
669 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
670 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
671 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
672 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
673 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
676 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
681 const struct cxsr_latency *latency;
684 if (fsb == 0 || mem == 0)
687 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
688 latency = &cxsr_latency_table[i];
689 if (is_desktop == latency->is_desktop &&
690 is_ddr3 == latency->is_ddr3 &&
691 fsb == latency->fsb_freq && mem == latency->mem_freq)
695 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
700 static void pineview_disable_cxsr(struct drm_device *dev)
702 struct drm_i915_private *dev_priv = dev->dev_private;
704 /* deactivate cxsr */
705 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
709 * Latency for FIFO fetches is dependent on several factors:
710 * - memory configuration (speed, channels)
712 * - current MCH state
713 * It can be fairly high in some situations, so here we assume a fairly
714 * pessimal value. It's a tradeoff between extra memory fetches (if we
715 * set this value too high, the FIFO will fetch frequently to stay full)
716 * and power consumption (set it too low to save power and we might see
717 * FIFO underruns and display "flicker").
719 * A value of 5us seems to be a good balance; safe for very low end
720 * platforms but not overly aggressive on lower latency configs.
722 static const int latency_ns = 5000;
724 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t dsparb = I915_READ(DSPARB);
730 size = dsparb & 0x7f;
732 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
734 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
735 plane ? "B" : "A", size);
740 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 uint32_t dsparb = I915_READ(DSPARB);
746 size = dsparb & 0x1ff;
748 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
749 size >>= 1; /* Convert to cachelines */
751 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
752 plane ? "B" : "A", size);
757 static int i845_get_fifo_size(struct drm_device *dev, int plane)
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 uint32_t dsparb = I915_READ(DSPARB);
763 size = dsparb & 0x7f;
764 size >>= 2; /* Convert to cachelines */
766 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
773 static int i830_get_fifo_size(struct drm_device *dev, int plane)
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 uint32_t dsparb = I915_READ(DSPARB);
779 size = dsparb & 0x7f;
780 size >>= 1; /* Convert to cachelines */
782 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
783 plane ? "B" : "A", size);
788 /* Pineview has different values for various configs */
789 static const struct intel_watermark_params pineview_display_wm = {
790 PINEVIEW_DISPLAY_FIFO,
794 PINEVIEW_FIFO_LINE_SIZE
796 static const struct intel_watermark_params pineview_display_hplloff_wm = {
797 PINEVIEW_DISPLAY_FIFO,
799 PINEVIEW_DFT_HPLLOFF_WM,
801 PINEVIEW_FIFO_LINE_SIZE
803 static const struct intel_watermark_params pineview_cursor_wm = {
804 PINEVIEW_CURSOR_FIFO,
805 PINEVIEW_CURSOR_MAX_WM,
806 PINEVIEW_CURSOR_DFT_WM,
807 PINEVIEW_CURSOR_GUARD_WM,
808 PINEVIEW_FIFO_LINE_SIZE,
810 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
811 PINEVIEW_CURSOR_FIFO,
812 PINEVIEW_CURSOR_MAX_WM,
813 PINEVIEW_CURSOR_DFT_WM,
814 PINEVIEW_CURSOR_GUARD_WM,
815 PINEVIEW_FIFO_LINE_SIZE
817 static const struct intel_watermark_params g4x_wm_info = {
824 static const struct intel_watermark_params g4x_cursor_wm_info = {
831 static const struct intel_watermark_params valleyview_wm_info = {
832 VALLEYVIEW_FIFO_SIZE,
838 static const struct intel_watermark_params valleyview_cursor_wm_info = {
840 VALLEYVIEW_CURSOR_MAX_WM,
845 static const struct intel_watermark_params i965_cursor_wm_info = {
852 static const struct intel_watermark_params i945_wm_info = {
859 static const struct intel_watermark_params i915_wm_info = {
866 static const struct intel_watermark_params i855_wm_info = {
873 static const struct intel_watermark_params i830_wm_info = {
881 static const struct intel_watermark_params ironlake_display_wm_info = {
888 static const struct intel_watermark_params ironlake_cursor_wm_info = {
895 static const struct intel_watermark_params ironlake_display_srwm_info = {
897 ILK_DISPLAY_MAX_SRWM,
898 ILK_DISPLAY_DFT_SRWM,
902 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
910 static const struct intel_watermark_params sandybridge_display_wm_info = {
917 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
924 static const struct intel_watermark_params sandybridge_display_srwm_info = {
926 SNB_DISPLAY_MAX_SRWM,
927 SNB_DISPLAY_DFT_SRWM,
931 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
941 * intel_calculate_wm - calculate watermark level
942 * @clock_in_khz: pixel clock
943 * @wm: chip FIFO params
944 * @pixel_size: display pixel size
945 * @latency_ns: memory latency for the platform
947 * Calculate the watermark level (the level at which the display plane will
948 * start fetching from memory again). Each chip has a different display
949 * FIFO size and allocation, so the caller needs to figure that out and pass
950 * in the correct intel_watermark_params structure.
952 * As the pixel clock runs, the FIFO will be drained at a rate that depends
953 * on the pixel size. When it reaches the watermark level, it'll start
954 * fetching FIFO line sized based chunks from memory until the FIFO fills
955 * past the watermark point. If the FIFO drains completely, a FIFO underrun
956 * will occur, and a display engine hang could result.
958 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
959 const struct intel_watermark_params *wm,
962 unsigned long latency_ns)
964 long entries_required, wm_size;
967 * Note: we need to make sure we don't overflow for various clock &
969 * clocks go from a few thousand to several hundred thousand.
970 * latency is usually a few thousand
972 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
974 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
976 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
978 wm_size = fifo_size - (entries_required + wm->guard_size);
980 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
982 /* Don't promote wm_size to unsigned... */
983 if (wm_size > (long)wm->max_wm)
984 wm_size = wm->max_wm;
986 wm_size = wm->default_wm;
990 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
992 struct drm_crtc *crtc, *enabled = NULL;
994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
995 if (crtc->enabled && crtc->fb) {
1005 static void pineview_update_wm(struct drm_device *dev)
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 struct drm_crtc *crtc;
1009 const struct cxsr_latency *latency;
1013 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014 dev_priv->fsb_freq, dev_priv->mem_freq);
1016 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017 pineview_disable_cxsr(dev);
1021 crtc = single_enabled_crtc(dev);
1023 int clock = crtc->mode.clock;
1024 int pixel_size = crtc->fb->bits_per_pixel / 8;
1027 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028 pineview_display_wm.fifo_size,
1029 pixel_size, latency->display_sr);
1030 reg = I915_READ(DSPFW1);
1031 reg &= ~DSPFW_SR_MASK;
1032 reg |= wm << DSPFW_SR_SHIFT;
1033 I915_WRITE(DSPFW1, reg);
1034 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1037 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038 pineview_display_wm.fifo_size,
1039 pixel_size, latency->cursor_sr);
1040 reg = I915_READ(DSPFW3);
1041 reg &= ~DSPFW_CURSOR_SR_MASK;
1042 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043 I915_WRITE(DSPFW3, reg);
1045 /* Display HPLL off SR */
1046 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047 pineview_display_hplloff_wm.fifo_size,
1048 pixel_size, latency->display_hpll_disable);
1049 reg = I915_READ(DSPFW3);
1050 reg &= ~DSPFW_HPLL_SR_MASK;
1051 reg |= wm & DSPFW_HPLL_SR_MASK;
1052 I915_WRITE(DSPFW3, reg);
1054 /* cursor HPLL off SR */
1055 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056 pineview_display_hplloff_wm.fifo_size,
1057 pixel_size, latency->cursor_hpll_disable);
1058 reg = I915_READ(DSPFW3);
1059 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061 I915_WRITE(DSPFW3, reg);
1062 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1066 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1069 pineview_disable_cxsr(dev);
1070 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1074 static bool g4x_compute_wm0(struct drm_device *dev,
1076 const struct intel_watermark_params *display,
1077 int display_latency_ns,
1078 const struct intel_watermark_params *cursor,
1079 int cursor_latency_ns,
1083 struct drm_crtc *crtc;
1084 int htotal, hdisplay, clock, pixel_size;
1085 int line_time_us, line_count;
1086 int entries, tlb_miss;
1088 crtc = intel_get_crtc_for_plane(dev, plane);
1089 if (crtc->fb == NULL || !crtc->enabled) {
1090 *cursor_wm = cursor->guard_size;
1091 *plane_wm = display->guard_size;
1095 htotal = crtc->mode.htotal;
1096 hdisplay = crtc->mode.hdisplay;
1097 clock = crtc->mode.clock;
1098 pixel_size = crtc->fb->bits_per_pixel / 8;
1100 /* Use the small buffer method to calculate plane watermark */
1101 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1104 entries += tlb_miss;
1105 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106 *plane_wm = entries + display->guard_size;
1107 if (*plane_wm > (int)display->max_wm)
1108 *plane_wm = display->max_wm;
1110 /* Use the large buffer method to calculate cursor watermark */
1111 line_time_us = ((htotal * 1000) / clock);
1112 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113 entries = line_count * 64 * pixel_size;
1114 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1116 entries += tlb_miss;
1117 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118 *cursor_wm = entries + cursor->guard_size;
1119 if (*cursor_wm > (int)cursor->max_wm)
1120 *cursor_wm = (int)cursor->max_wm;
1126 * Check the wm result.
1128 * If any calculated watermark values is larger than the maximum value that
1129 * can be programmed into the associated watermark register, that watermark
1132 static bool g4x_check_srwm(struct drm_device *dev,
1133 int display_wm, int cursor_wm,
1134 const struct intel_watermark_params *display,
1135 const struct intel_watermark_params *cursor)
1137 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138 display_wm, cursor_wm);
1140 if (display_wm > display->max_wm) {
1141 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142 display_wm, display->max_wm);
1146 if (cursor_wm > cursor->max_wm) {
1147 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148 cursor_wm, cursor->max_wm);
1152 if (!(display_wm || cursor_wm)) {
1153 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1160 static bool g4x_compute_srwm(struct drm_device *dev,
1163 const struct intel_watermark_params *display,
1164 const struct intel_watermark_params *cursor,
1165 int *display_wm, int *cursor_wm)
1167 struct drm_crtc *crtc;
1168 int hdisplay, htotal, pixel_size, clock;
1169 unsigned long line_time_us;
1170 int line_count, line_size;
1175 *display_wm = *cursor_wm = 0;
1179 crtc = intel_get_crtc_for_plane(dev, plane);
1180 hdisplay = crtc->mode.hdisplay;
1181 htotal = crtc->mode.htotal;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1185 line_time_us = (htotal * 1000) / clock;
1186 line_count = (latency_ns / line_time_us + 1000) / 1000;
1187 line_size = hdisplay * pixel_size;
1189 /* Use the minimum of the small and large buffer method for primary */
1190 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191 large = line_count * line_size;
1193 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194 *display_wm = entries + display->guard_size;
1196 /* calculate the self-refresh watermark for display cursor */
1197 entries = line_count * pixel_size * 64;
1198 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199 *cursor_wm = entries + cursor->guard_size;
1201 return g4x_check_srwm(dev,
1202 *display_wm, *cursor_wm,
1206 static bool vlv_compute_drain_latency(struct drm_device *dev,
1208 int *plane_prec_mult,
1210 int *cursor_prec_mult,
1213 struct drm_crtc *crtc;
1214 int clock, pixel_size;
1217 crtc = intel_get_crtc_for_plane(dev, plane);
1218 if (crtc->fb == NULL || !crtc->enabled)
1221 clock = crtc->mode.clock; /* VESA DOT Clock */
1222 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1224 entries = (clock / 1000) * pixel_size;
1225 *plane_prec_mult = (entries > 256) ?
1226 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1230 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1231 *cursor_prec_mult = (entries > 256) ?
1232 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1239 * Update drain latency registers of memory arbiter
1241 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242 * to be programmed. Each plane has a drain latency multiplier and a drain
1246 static void vlv_update_drain_latency(struct drm_device *dev)
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1254 /* For plane A, Cursor A */
1255 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256 &cursor_prec_mult, &cursora_dl)) {
1257 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1262 I915_WRITE(VLV_DDL1, cursora_prec |
1263 (cursora_dl << DDL_CURSORA_SHIFT) |
1264 planea_prec | planea_dl);
1267 /* For plane B, Cursor B */
1268 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269 &cursor_prec_mult, &cursorb_dl)) {
1270 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1275 I915_WRITE(VLV_DDL2, cursorb_prec |
1276 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277 planeb_prec | planeb_dl);
1281 #define single_plane_enabled(mask) is_power_of_2(mask)
1283 static void valleyview_update_wm(struct drm_device *dev)
1285 static const int sr_latency_ns = 12000;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288 int plane_sr, cursor_sr;
1289 unsigned int enabled = 0;
1291 vlv_update_drain_latency(dev);
1293 if (g4x_compute_wm0(dev, 0,
1294 &valleyview_wm_info, latency_ns,
1295 &valleyview_cursor_wm_info, latency_ns,
1296 &planea_wm, &cursora_wm))
1299 if (g4x_compute_wm0(dev, 1,
1300 &valleyview_wm_info, latency_ns,
1301 &valleyview_cursor_wm_info, latency_ns,
1302 &planeb_wm, &cursorb_wm))
1305 plane_sr = cursor_sr = 0;
1306 if (single_plane_enabled(enabled) &&
1307 g4x_compute_srwm(dev, ffs(enabled) - 1,
1309 &valleyview_wm_info,
1310 &valleyview_cursor_wm_info,
1311 &plane_sr, &cursor_sr))
1312 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1314 I915_WRITE(FW_BLC_SELF_VLV,
1315 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1317 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1318 planea_wm, cursora_wm,
1319 planeb_wm, cursorb_wm,
1320 plane_sr, cursor_sr);
1323 (plane_sr << DSPFW_SR_SHIFT) |
1324 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1325 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1328 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1329 (cursora_wm << DSPFW_CURSORA_SHIFT));
1331 (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
1334 static void g4x_update_wm(struct drm_device *dev)
1336 static const int sr_latency_ns = 12000;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1339 int plane_sr, cursor_sr;
1340 unsigned int enabled = 0;
1342 if (g4x_compute_wm0(dev, 0,
1343 &g4x_wm_info, latency_ns,
1344 &g4x_cursor_wm_info, latency_ns,
1345 &planea_wm, &cursora_wm))
1348 if (g4x_compute_wm0(dev, 1,
1349 &g4x_wm_info, latency_ns,
1350 &g4x_cursor_wm_info, latency_ns,
1351 &planeb_wm, &cursorb_wm))
1354 plane_sr = cursor_sr = 0;
1355 if (single_plane_enabled(enabled) &&
1356 g4x_compute_srwm(dev, ffs(enabled) - 1,
1359 &g4x_cursor_wm_info,
1360 &plane_sr, &cursor_sr))
1361 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1363 I915_WRITE(FW_BLC_SELF,
1364 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1366 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1367 planea_wm, cursora_wm,
1368 planeb_wm, cursorb_wm,
1369 plane_sr, cursor_sr);
1372 (plane_sr << DSPFW_SR_SHIFT) |
1373 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1374 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1377 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1378 (cursora_wm << DSPFW_CURSORA_SHIFT));
1379 /* HPLL off in SR has some issues on G4x... disable it */
1381 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
1382 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1385 static void i965_update_wm(struct drm_device *dev)
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 struct drm_crtc *crtc;
1392 /* Calc sr entries for one plane configs */
1393 crtc = single_enabled_crtc(dev);
1395 /* self-refresh has much higher latency */
1396 static const int sr_latency_ns = 12000;
1397 int clock = crtc->mode.clock;
1398 int htotal = crtc->mode.htotal;
1399 int hdisplay = crtc->mode.hdisplay;
1400 int pixel_size = crtc->fb->bits_per_pixel / 8;
1401 unsigned long line_time_us;
1404 line_time_us = ((htotal * 1000) / clock);
1406 /* Use ns/us then divide to preserve precision */
1407 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1408 pixel_size * hdisplay;
1409 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1410 srwm = I965_FIFO_SIZE - entries;
1414 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1417 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1419 entries = DIV_ROUND_UP(entries,
1420 i965_cursor_wm_info.cacheline_size);
1421 cursor_sr = i965_cursor_wm_info.fifo_size -
1422 (entries + i965_cursor_wm_info.guard_size);
1424 if (cursor_sr > i965_cursor_wm_info.max_wm)
1425 cursor_sr = i965_cursor_wm_info.max_wm;
1427 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1428 "cursor %d\n", srwm, cursor_sr);
1430 if (IS_CRESTLINE(dev))
1431 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1433 /* Turn off self refresh if both pipes are enabled */
1434 if (IS_CRESTLINE(dev))
1435 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1439 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1442 /* 965 has limitations... */
1443 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1444 (8 << 16) | (8 << 8) | (8 << 0));
1445 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1446 /* update cursor SR watermark */
1447 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1450 static void i9xx_update_wm(struct drm_device *dev)
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 const struct intel_watermark_params *wm_info;
1458 int planea_wm, planeb_wm;
1459 struct drm_crtc *crtc, *enabled = NULL;
1462 wm_info = &i945_wm_info;
1463 else if (!IS_GEN2(dev))
1464 wm_info = &i915_wm_info;
1466 wm_info = &i855_wm_info;
1468 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1469 crtc = intel_get_crtc_for_plane(dev, 0);
1470 if (crtc->enabled && crtc->fb) {
1471 planea_wm = intel_calculate_wm(crtc->mode.clock,
1473 crtc->fb->bits_per_pixel / 8,
1477 planea_wm = fifo_size - wm_info->guard_size;
1479 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1480 crtc = intel_get_crtc_for_plane(dev, 1);
1481 if (crtc->enabled && crtc->fb) {
1482 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1484 crtc->fb->bits_per_pixel / 8,
1486 if (enabled == NULL)
1491 planeb_wm = fifo_size - wm_info->guard_size;
1493 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1496 * Overlay gets an aggressive default since video jitter is bad.
1500 /* Play safe and disable self-refresh before adjusting watermarks. */
1501 if (IS_I945G(dev) || IS_I945GM(dev))
1502 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1503 else if (IS_I915GM(dev))
1504 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1506 /* Calc sr entries for one plane configs */
1507 if (HAS_FW_BLC(dev) && enabled) {
1508 /* self-refresh has much higher latency */
1509 static const int sr_latency_ns = 6000;
1510 int clock = enabled->mode.clock;
1511 int htotal = enabled->mode.htotal;
1512 int hdisplay = enabled->mode.hdisplay;
1513 int pixel_size = enabled->fb->bits_per_pixel / 8;
1514 unsigned long line_time_us;
1517 line_time_us = (htotal * 1000) / clock;
1519 /* Use ns/us then divide to preserve precision */
1520 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 pixel_size * hdisplay;
1522 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1523 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1524 srwm = wm_info->fifo_size - entries;
1528 if (IS_I945G(dev) || IS_I945GM(dev))
1529 I915_WRITE(FW_BLC_SELF,
1530 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1531 else if (IS_I915GM(dev))
1532 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1535 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1536 planea_wm, planeb_wm, cwm, srwm);
1538 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1539 fwater_hi = (cwm & 0x1f);
1541 /* Set request length to 8 cachelines per fetch */
1542 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1543 fwater_hi = fwater_hi | (1 << 8);
1545 I915_WRITE(FW_BLC, fwater_lo);
1546 I915_WRITE(FW_BLC2, fwater_hi);
1548 if (HAS_FW_BLC(dev)) {
1550 if (IS_I945G(dev) || IS_I945GM(dev))
1551 I915_WRITE(FW_BLC_SELF,
1552 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1553 else if (IS_I915GM(dev))
1554 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1555 DRM_DEBUG_KMS("memory self refresh enabled\n");
1557 DRM_DEBUG_KMS("memory self refresh disabled\n");
1561 static void i830_update_wm(struct drm_device *dev)
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 struct drm_crtc *crtc;
1568 crtc = single_enabled_crtc(dev);
1572 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1573 dev_priv->display.get_fifo_size(dev, 0),
1574 crtc->fb->bits_per_pixel / 8,
1576 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1577 fwater_lo |= (3<<8) | planea_wm;
1579 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1581 I915_WRITE(FW_BLC, fwater_lo);
1584 #define ILK_LP0_PLANE_LATENCY 700
1585 #define ILK_LP0_CURSOR_LATENCY 1300
1588 * Check the wm result.
1590 * If any calculated watermark values is larger than the maximum value that
1591 * can be programmed into the associated watermark register, that watermark
1594 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1595 int fbc_wm, int display_wm, int cursor_wm,
1596 const struct intel_watermark_params *display,
1597 const struct intel_watermark_params *cursor)
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1601 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1602 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1604 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1605 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1606 fbc_wm, SNB_FBC_MAX_SRWM, level);
1608 /* fbc has it's own way to disable FBC WM */
1609 I915_WRITE(DISP_ARB_CTL,
1610 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1614 if (display_wm > display->max_wm) {
1615 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1616 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1620 if (cursor_wm > cursor->max_wm) {
1621 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1622 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1626 if (!(fbc_wm || display_wm || cursor_wm)) {
1627 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1635 * Compute watermark values of WM[1-3],
1637 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1639 const struct intel_watermark_params *display,
1640 const struct intel_watermark_params *cursor,
1641 int *fbc_wm, int *display_wm, int *cursor_wm)
1643 struct drm_crtc *crtc;
1644 unsigned long line_time_us;
1645 int hdisplay, htotal, pixel_size, clock;
1646 int line_count, line_size;
1651 *fbc_wm = *display_wm = *cursor_wm = 0;
1655 crtc = intel_get_crtc_for_plane(dev, plane);
1656 hdisplay = crtc->mode.hdisplay;
1657 htotal = crtc->mode.htotal;
1658 clock = crtc->mode.clock;
1659 pixel_size = crtc->fb->bits_per_pixel / 8;
1661 line_time_us = (htotal * 1000) / clock;
1662 line_count = (latency_ns / line_time_us + 1000) / 1000;
1663 line_size = hdisplay * pixel_size;
1665 /* Use the minimum of the small and large buffer method for primary */
1666 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1667 large = line_count * line_size;
1669 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1670 *display_wm = entries + display->guard_size;
1674 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1676 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1678 /* calculate the self-refresh watermark for display cursor */
1679 entries = line_count * pixel_size * 64;
1680 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1681 *cursor_wm = entries + cursor->guard_size;
1683 return ironlake_check_srwm(dev, level,
1684 *fbc_wm, *display_wm, *cursor_wm,
1688 static void ironlake_update_wm(struct drm_device *dev)
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int fbc_wm, plane_wm, cursor_wm;
1692 unsigned int enabled;
1695 if (g4x_compute_wm0(dev, 0,
1696 &ironlake_display_wm_info,
1697 ILK_LP0_PLANE_LATENCY,
1698 &ironlake_cursor_wm_info,
1699 ILK_LP0_CURSOR_LATENCY,
1700 &plane_wm, &cursor_wm)) {
1701 I915_WRITE(WM0_PIPEA_ILK,
1702 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1703 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1704 " plane %d, " "cursor: %d\n",
1705 plane_wm, cursor_wm);
1709 if (g4x_compute_wm0(dev, 1,
1710 &ironlake_display_wm_info,
1711 ILK_LP0_PLANE_LATENCY,
1712 &ironlake_cursor_wm_info,
1713 ILK_LP0_CURSOR_LATENCY,
1714 &plane_wm, &cursor_wm)) {
1715 I915_WRITE(WM0_PIPEB_ILK,
1716 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1717 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1718 " plane %d, cursor: %d\n",
1719 plane_wm, cursor_wm);
1724 * Calculate and update the self-refresh watermark only when one
1725 * display plane is used.
1727 I915_WRITE(WM3_LP_ILK, 0);
1728 I915_WRITE(WM2_LP_ILK, 0);
1729 I915_WRITE(WM1_LP_ILK, 0);
1731 if (!single_plane_enabled(enabled))
1733 enabled = ffs(enabled) - 1;
1736 if (!ironlake_compute_srwm(dev, 1, enabled,
1737 ILK_READ_WM1_LATENCY() * 500,
1738 &ironlake_display_srwm_info,
1739 &ironlake_cursor_srwm_info,
1740 &fbc_wm, &plane_wm, &cursor_wm))
1743 I915_WRITE(WM1_LP_ILK,
1745 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1746 (fbc_wm << WM1_LP_FBC_SHIFT) |
1747 (plane_wm << WM1_LP_SR_SHIFT) |
1751 if (!ironlake_compute_srwm(dev, 2, enabled,
1752 ILK_READ_WM2_LATENCY() * 500,
1753 &ironlake_display_srwm_info,
1754 &ironlake_cursor_srwm_info,
1755 &fbc_wm, &plane_wm, &cursor_wm))
1758 I915_WRITE(WM2_LP_ILK,
1760 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1761 (fbc_wm << WM1_LP_FBC_SHIFT) |
1762 (plane_wm << WM1_LP_SR_SHIFT) |
1766 * WM3 is unsupported on ILK, probably because we don't have latency
1767 * data for that power state
1771 static void sandybridge_update_wm(struct drm_device *dev)
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1776 int fbc_wm, plane_wm, cursor_wm;
1777 unsigned int enabled;
1780 if (g4x_compute_wm0(dev, 0,
1781 &sandybridge_display_wm_info, latency,
1782 &sandybridge_cursor_wm_info, latency,
1783 &plane_wm, &cursor_wm)) {
1784 val = I915_READ(WM0_PIPEA_ILK);
1785 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1786 I915_WRITE(WM0_PIPEA_ILK, val |
1787 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1788 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1789 " plane %d, " "cursor: %d\n",
1790 plane_wm, cursor_wm);
1794 if (g4x_compute_wm0(dev, 1,
1795 &sandybridge_display_wm_info, latency,
1796 &sandybridge_cursor_wm_info, latency,
1797 &plane_wm, &cursor_wm)) {
1798 val = I915_READ(WM0_PIPEB_ILK);
1799 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1800 I915_WRITE(WM0_PIPEB_ILK, val |
1801 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1802 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1803 " plane %d, cursor: %d\n",
1804 plane_wm, cursor_wm);
1808 if ((dev_priv->num_pipe == 3) &&
1809 g4x_compute_wm0(dev, 2,
1810 &sandybridge_display_wm_info, latency,
1811 &sandybridge_cursor_wm_info, latency,
1812 &plane_wm, &cursor_wm)) {
1813 val = I915_READ(WM0_PIPEC_IVB);
1814 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1815 I915_WRITE(WM0_PIPEC_IVB, val |
1816 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1817 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1818 " plane %d, cursor: %d\n",
1819 plane_wm, cursor_wm);
1824 * Calculate and update the self-refresh watermark only when one
1825 * display plane is used.
1827 * SNB support 3 levels of watermark.
1829 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1830 * and disabled in the descending order
1833 I915_WRITE(WM3_LP_ILK, 0);
1834 I915_WRITE(WM2_LP_ILK, 0);
1835 I915_WRITE(WM1_LP_ILK, 0);
1837 if (!single_plane_enabled(enabled) ||
1838 dev_priv->sprite_scaling_enabled)
1840 enabled = ffs(enabled) - 1;
1843 if (!ironlake_compute_srwm(dev, 1, enabled,
1844 SNB_READ_WM1_LATENCY() * 500,
1845 &sandybridge_display_srwm_info,
1846 &sandybridge_cursor_srwm_info,
1847 &fbc_wm, &plane_wm, &cursor_wm))
1850 I915_WRITE(WM1_LP_ILK,
1852 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1853 (fbc_wm << WM1_LP_FBC_SHIFT) |
1854 (plane_wm << WM1_LP_SR_SHIFT) |
1858 if (!ironlake_compute_srwm(dev, 2, enabled,
1859 SNB_READ_WM2_LATENCY() * 500,
1860 &sandybridge_display_srwm_info,
1861 &sandybridge_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1865 I915_WRITE(WM2_LP_ILK,
1867 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1873 if (!ironlake_compute_srwm(dev, 3, enabled,
1874 SNB_READ_WM3_LATENCY() * 500,
1875 &sandybridge_display_srwm_info,
1876 &sandybridge_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1880 I915_WRITE(WM3_LP_ILK,
1882 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1889 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
1890 struct drm_display_mode *mode)
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1895 temp = I915_READ(PIPE_WM_LINETIME(pipe));
1896 temp &= ~PIPE_WM_LINETIME_MASK;
1898 /* The WM are computed with base on how long it takes to fill a single
1899 * row at the given clock rate, multiplied by 8.
1901 temp |= PIPE_WM_LINETIME_TIME(
1902 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
1904 /* IPS watermarks are only used by pipe A, and are ignored by
1905 * pipes B and C. They are calculated similarly to the common
1906 * linetime values, except that we are using CD clock frequency
1907 * in MHz instead of pixel rate for the division.
1909 * This is a placeholder for the IPS watermark calculation code.
1912 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
1916 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1917 uint32_t sprite_width, int pixel_size,
1918 const struct intel_watermark_params *display,
1919 int display_latency_ns, int *sprite_wm)
1921 struct drm_crtc *crtc;
1923 int entries, tlb_miss;
1925 crtc = intel_get_crtc_for_plane(dev, plane);
1926 if (crtc->fb == NULL || !crtc->enabled) {
1927 *sprite_wm = display->guard_size;
1931 clock = crtc->mode.clock;
1933 /* Use the small buffer method to calculate the sprite watermark */
1934 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1935 tlb_miss = display->fifo_size*display->cacheline_size -
1938 entries += tlb_miss;
1939 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1940 *sprite_wm = entries + display->guard_size;
1941 if (*sprite_wm > (int)display->max_wm)
1942 *sprite_wm = display->max_wm;
1948 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1949 uint32_t sprite_width, int pixel_size,
1950 const struct intel_watermark_params *display,
1951 int latency_ns, int *sprite_wm)
1953 struct drm_crtc *crtc;
1954 unsigned long line_time_us;
1956 int line_count, line_size;
1965 crtc = intel_get_crtc_for_plane(dev, plane);
1966 clock = crtc->mode.clock;
1972 line_time_us = (sprite_width * 1000) / clock;
1973 if (!line_time_us) {
1978 line_count = (latency_ns / line_time_us + 1000) / 1000;
1979 line_size = sprite_width * pixel_size;
1981 /* Use the minimum of the small and large buffer method for primary */
1982 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1983 large = line_count * line_size;
1985 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1986 *sprite_wm = entries + display->guard_size;
1988 return *sprite_wm > 0x3ff ? false : true;
1991 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
1992 uint32_t sprite_width, int pixel_size)
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2002 reg = WM0_PIPEA_ILK;
2005 reg = WM0_PIPEB_ILK;
2008 reg = WM0_PIPEC_IVB;
2011 return; /* bad pipe */
2014 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2015 &sandybridge_display_wm_info,
2016 latency, &sprite_wm);
2018 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2023 val = I915_READ(reg);
2024 val &= ~WM0_PIPE_SPRITE_MASK;
2025 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2026 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2029 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2031 &sandybridge_display_srwm_info,
2032 SNB_READ_WM1_LATENCY() * 500,
2035 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2039 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2041 /* Only IVB has two more LP watermarks for sprite */
2042 if (!IS_IVYBRIDGE(dev))
2045 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2047 &sandybridge_display_srwm_info,
2048 SNB_READ_WM2_LATENCY() * 500,
2051 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2055 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2057 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2059 &sandybridge_display_srwm_info,
2060 SNB_READ_WM3_LATENCY() * 500,
2063 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2067 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2071 * intel_update_watermarks - update FIFO watermark values based on current modes
2073 * Calculate watermark values for the various WM regs based on current mode
2074 * and plane configuration.
2076 * There are several cases to deal with here:
2077 * - normal (i.e. non-self-refresh)
2078 * - self-refresh (SR) mode
2079 * - lines are large relative to FIFO size (buffer can hold up to 2)
2080 * - lines are small relative to FIFO size (buffer can hold more than 2
2081 * lines), so need to account for TLB latency
2083 * The normal calculation is:
2084 * watermark = dotclock * bytes per pixel * latency
2085 * where latency is platform & configuration dependent (we assume pessimal
2088 * The SR calculation is:
2089 * watermark = (trunc(latency/line time)+1) * surface width *
2092 * line time = htotal / dotclock
2093 * surface width = hdisplay for normal plane and 64 for cursor
2094 * and latency is assumed to be high, as above.
2096 * The final value programmed to the register should always be rounded up,
2097 * and include an extra 2 entries to account for clock crossings.
2099 * We don't use the sprite, so we can ignore that. And on Crestline we have
2100 * to set the non-SR watermarks to 8.
2102 void intel_update_watermarks(struct drm_device *dev)
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2106 if (dev_priv->display.update_wm)
2107 dev_priv->display.update_wm(dev);
2110 void intel_update_linetime_watermarks(struct drm_device *dev,
2111 int pipe, struct drm_display_mode *mode)
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2115 if (dev_priv->display.update_linetime_wm)
2116 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2119 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2120 uint32_t sprite_width, int pixel_size)
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2124 if (dev_priv->display.update_sprite_wm)
2125 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2129 static struct drm_i915_gem_object *
2130 intel_alloc_context_page(struct drm_device *dev)
2132 struct drm_i915_gem_object *ctx;
2135 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2137 ctx = i915_gem_alloc_object(dev, 4096);
2139 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2143 ret = i915_gem_object_pin(ctx, 4096, true, false);
2145 DRM_ERROR("failed to pin power context: %d\n", ret);
2149 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2151 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2158 i915_gem_object_unpin(ctx);
2160 drm_gem_object_unreference(&ctx->base);
2161 mutex_unlock(&dev->struct_mutex);
2166 * Lock protecting IPS related data structures
2168 DEFINE_SPINLOCK(mchdev_lock);
2170 /* Global for IPS driver to get at the current i915 device. Protected by
2172 static struct drm_i915_private *i915_mch_dev;
2174 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2179 assert_spin_locked(&mchdev_lock);
2181 rgvswctl = I915_READ16(MEMSWCTL);
2182 if (rgvswctl & MEMCTL_CMD_STS) {
2183 DRM_DEBUG("gpu busy, RCS change rejected\n");
2184 return false; /* still busy with another command */
2187 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2188 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2189 I915_WRITE16(MEMSWCTL, rgvswctl);
2190 POSTING_READ16(MEMSWCTL);
2192 rgvswctl |= MEMCTL_CMD_STS;
2193 I915_WRITE16(MEMSWCTL, rgvswctl);
2198 static void ironlake_enable_drps(struct drm_device *dev)
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 u32 rgvmodectl = I915_READ(MEMMODECTL);
2202 u8 fmax, fmin, fstart, vstart;
2204 spin_lock_irq(&mchdev_lock);
2206 /* Enable temp reporting */
2207 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2208 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2210 /* 100ms RC evaluation intervals */
2211 I915_WRITE(RCUPEI, 100000);
2212 I915_WRITE(RCDNEI, 100000);
2214 /* Set max/min thresholds to 90ms and 80ms respectively */
2215 I915_WRITE(RCBMAXAVG, 90000);
2216 I915_WRITE(RCBMINAVG, 80000);
2218 I915_WRITE(MEMIHYST, 1);
2220 /* Set up min, max, and cur for interrupt handling */
2221 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2222 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2223 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2224 MEMMODE_FSTART_SHIFT;
2226 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2229 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2230 dev_priv->ips.fstart = fstart;
2232 dev_priv->ips.max_delay = fstart;
2233 dev_priv->ips.min_delay = fmin;
2234 dev_priv->ips.cur_delay = fstart;
2236 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2237 fmax, fmin, fstart);
2239 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2242 * Interrupts will be enabled in ironlake_irq_postinstall
2245 I915_WRITE(VIDSTART, vstart);
2246 POSTING_READ(VIDSTART);
2248 rgvmodectl |= MEMMODE_SWMODE_EN;
2249 I915_WRITE(MEMMODECTL, rgvmodectl);
2251 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2252 DRM_ERROR("stuck trying to change perf mode\n");
2255 ironlake_set_drps(dev, fstart);
2257 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2259 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2260 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2261 getrawmonotonic(&dev_priv->ips.last_time2);
2263 spin_unlock_irq(&mchdev_lock);
2266 static void ironlake_disable_drps(struct drm_device *dev)
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2271 spin_lock_irq(&mchdev_lock);
2273 rgvswctl = I915_READ16(MEMSWCTL);
2275 /* Ack interrupts, disable EFC interrupt */
2276 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2277 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2278 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2279 I915_WRITE(DEIIR, DE_PCU_EVENT);
2280 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2282 /* Go back to the starting frequency */
2283 ironlake_set_drps(dev, dev_priv->ips.fstart);
2285 rgvswctl |= MEMCTL_CMD_STS;
2286 I915_WRITE(MEMSWCTL, rgvswctl);
2289 spin_unlock_irq(&mchdev_lock);
2292 /* There's a funny hw issue where the hw returns all 0 when reading from
2293 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2294 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2295 * all limits and the gpu stuck at whatever frequency it is at atm).
2297 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2303 if (*val >= dev_priv->rps.max_delay)
2304 *val = dev_priv->rps.max_delay;
2305 limits |= dev_priv->rps.max_delay << 24;
2307 /* Only set the down limit when we've reached the lowest level to avoid
2308 * getting more interrupts, otherwise leave this clear. This prevents a
2309 * race in the hw when coming out of rc6: There's a tiny window where
2310 * the hw runs at the minimal clock before selecting the desired
2311 * frequency, if the down threshold expires in that window we will not
2312 * receive a down interrupt. */
2313 if (*val <= dev_priv->rps.min_delay) {
2314 *val = dev_priv->rps.min_delay;
2315 limits |= dev_priv->rps.min_delay << 16;
2321 void gen6_set_rps(struct drm_device *dev, u8 val)
2323 struct drm_i915_private *dev_priv = dev->dev_private;
2324 u32 limits = gen6_rps_limits(dev_priv, &val);
2326 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2327 WARN_ON(val > dev_priv->rps.max_delay);
2328 WARN_ON(val < dev_priv->rps.min_delay);
2330 if (val == dev_priv->rps.cur_delay)
2333 I915_WRITE(GEN6_RPNSWREQ,
2334 GEN6_FREQUENCY(val) |
2336 GEN6_AGGRESSIVE_TURBO);
2338 /* Make sure we continue to get interrupts
2339 * until we hit the minimum or maximum frequencies.
2341 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2343 POSTING_READ(GEN6_RPNSWREQ);
2345 dev_priv->rps.cur_delay = val;
2347 trace_intel_gpu_freq_change(val * 50);
2350 static void gen6_disable_rps(struct drm_device *dev)
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2354 I915_WRITE(GEN6_RC_CONTROL, 0);
2355 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2356 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2357 I915_WRITE(GEN6_PMIER, 0);
2358 /* Complete PM interrupt masking here doesn't race with the rps work
2359 * item again unmasking PM interrupts because that is using a different
2360 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2361 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2363 spin_lock_irq(&dev_priv->rps.lock);
2364 dev_priv->rps.pm_iir = 0;
2365 spin_unlock_irq(&dev_priv->rps.lock);
2367 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2370 int intel_enable_rc6(const struct drm_device *dev)
2372 /* Respect the kernel parameter if it is set */
2373 if (i915_enable_rc6 >= 0)
2374 return i915_enable_rc6;
2376 if (INTEL_INFO(dev)->gen == 5) {
2377 #ifdef CONFIG_INTEL_IOMMU
2378 /* Disable rc6 on ilk if VT-d is on. */
2379 if (intel_iommu_gfx_mapped)
2382 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2383 return INTEL_RC6_ENABLE;
2386 if (IS_HASWELL(dev)) {
2387 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2388 return INTEL_RC6_ENABLE;
2391 /* snb/ivb have more than one rc6 state. */
2392 if (INTEL_INFO(dev)->gen == 6) {
2393 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2394 return INTEL_RC6_ENABLE;
2397 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2398 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2401 static void gen6_enable_rps(struct drm_device *dev)
2403 struct drm_i915_private *dev_priv = dev->dev_private;
2404 struct intel_ring_buffer *ring;
2407 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2412 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2414 /* Here begins a magic sequence of register writes to enable
2415 * auto-downclocking.
2417 * Perhaps there might be some value in exposing these to
2420 I915_WRITE(GEN6_RC_STATE, 0);
2422 /* Clear the DBG now so we don't confuse earlier errors */
2423 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2424 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2425 I915_WRITE(GTFIFODBG, gtfifodbg);
2428 gen6_gt_force_wake_get(dev_priv);
2430 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2431 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2433 /* In units of 100MHz */
2434 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2435 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2436 dev_priv->rps.cur_delay = 0;
2438 /* disable the counters and set deterministic thresholds */
2439 I915_WRITE(GEN6_RC_CONTROL, 0);
2441 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2442 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2443 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2444 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2445 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2447 for_each_ring(ring, dev_priv, i)
2448 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2450 I915_WRITE(GEN6_RC_SLEEP, 0);
2451 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2452 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2453 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2454 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2456 /* Check if we are enabling RC6 */
2457 rc6_mode = intel_enable_rc6(dev_priv->dev);
2458 if (rc6_mode & INTEL_RC6_ENABLE)
2459 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2461 /* We don't use those on Haswell */
2462 if (!IS_HASWELL(dev)) {
2463 if (rc6_mode & INTEL_RC6p_ENABLE)
2464 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2466 if (rc6_mode & INTEL_RC6pp_ENABLE)
2467 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2470 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2471 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2472 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2473 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2475 I915_WRITE(GEN6_RC_CONTROL,
2477 GEN6_RC_CTL_EI_MODE(1) |
2478 GEN6_RC_CTL_HW_ENABLE);
2480 I915_WRITE(GEN6_RPNSWREQ,
2481 GEN6_FREQUENCY(10) |
2483 GEN6_AGGRESSIVE_TURBO);
2484 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2485 GEN6_FREQUENCY(12));
2487 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2488 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2489 dev_priv->rps.max_delay << 24 |
2490 dev_priv->rps.min_delay << 16);
2492 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2493 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2494 I915_WRITE(GEN6_RP_UP_EI, 66000);
2495 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2497 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2498 I915_WRITE(GEN6_RP_CONTROL,
2499 GEN6_RP_MEDIA_TURBO |
2500 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2501 GEN6_RP_MEDIA_IS_GFX |
2503 GEN6_RP_UP_BUSY_AVG |
2504 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2506 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2509 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2510 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2511 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2512 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2515 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2518 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2520 /* requires MSI enabled */
2521 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2522 spin_lock_irq(&dev_priv->rps.lock);
2523 WARN_ON(dev_priv->rps.pm_iir != 0);
2524 I915_WRITE(GEN6_PMIMR, 0);
2525 spin_unlock_irq(&dev_priv->rps.lock);
2526 /* enable all PM interrupts */
2527 I915_WRITE(GEN6_PMINTRMSK, 0);
2530 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2531 if (IS_GEN6(dev) && ret) {
2532 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2533 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2534 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2535 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2536 rc6vids &= 0xffff00;
2537 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2538 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2540 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2543 gen6_gt_force_wake_put(dev_priv);
2546 static void gen6_update_ring_freq(struct drm_device *dev)
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2550 int gpu_freq, ia_freq, max_ia_freq;
2551 int scaling_factor = 180;
2553 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2555 max_ia_freq = cpufreq_quick_get_max(0);
2557 * Default to measured freq if none found, PCU will ensure we don't go
2561 max_ia_freq = tsc_khz;
2563 /* Convert from kHz to MHz */
2564 max_ia_freq /= 1000;
2567 * For each potential GPU frequency, load a ring frequency we'd like
2568 * to use for memory access. We do this by specifying the IA frequency
2569 * the PCU should use as a reference to determine the ring frequency.
2571 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2573 int diff = dev_priv->rps.max_delay - gpu_freq;
2576 * For GPU frequencies less than 750MHz, just use the lowest
2579 if (gpu_freq < min_freq)
2582 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2583 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2584 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2586 sandybridge_pcode_write(dev_priv,
2587 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2588 ia_freq | gpu_freq);
2592 void ironlake_teardown_rc6(struct drm_device *dev)
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2596 if (dev_priv->ips.renderctx) {
2597 i915_gem_object_unpin(dev_priv->ips.renderctx);
2598 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2599 dev_priv->ips.renderctx = NULL;
2602 if (dev_priv->ips.pwrctx) {
2603 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2604 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2605 dev_priv->ips.pwrctx = NULL;
2609 static void ironlake_disable_rc6(struct drm_device *dev)
2611 struct drm_i915_private *dev_priv = dev->dev_private;
2613 if (I915_READ(PWRCTXA)) {
2614 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2615 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2616 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2619 I915_WRITE(PWRCTXA, 0);
2620 POSTING_READ(PWRCTXA);
2622 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2623 POSTING_READ(RSTDBYCTL);
2627 static int ironlake_setup_rc6(struct drm_device *dev)
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2631 if (dev_priv->ips.renderctx == NULL)
2632 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2633 if (!dev_priv->ips.renderctx)
2636 if (dev_priv->ips.pwrctx == NULL)
2637 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2638 if (!dev_priv->ips.pwrctx) {
2639 ironlake_teardown_rc6(dev);
2646 static void ironlake_enable_rc6(struct drm_device *dev)
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2652 /* rc6 disabled by default due to repeated reports of hanging during
2655 if (!intel_enable_rc6(dev))
2658 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2660 ret = ironlake_setup_rc6(dev);
2665 * GPU can automatically power down the render unit if given a page
2668 ret = intel_ring_begin(ring, 6);
2670 ironlake_teardown_rc6(dev);
2674 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2675 intel_ring_emit(ring, MI_SET_CONTEXT);
2676 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2678 MI_SAVE_EXT_STATE_EN |
2679 MI_RESTORE_EXT_STATE_EN |
2680 MI_RESTORE_INHIBIT);
2681 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2682 intel_ring_emit(ring, MI_NOOP);
2683 intel_ring_emit(ring, MI_FLUSH);
2684 intel_ring_advance(ring);
2687 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2688 * does an implicit flush, combined with MI_FLUSH above, it should be
2689 * safe to assume that renderctx is valid
2691 ret = intel_wait_ring_idle(ring);
2693 DRM_ERROR("failed to enable ironlake power power savings\n");
2694 ironlake_teardown_rc6(dev);
2698 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2699 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2702 static unsigned long intel_pxfreq(u32 vidfreq)
2705 int div = (vidfreq & 0x3f0000) >> 16;
2706 int post = (vidfreq & 0x3000) >> 12;
2707 int pre = (vidfreq & 0x7);
2712 freq = ((div * 133333) / ((1<<post) * pre));
2717 static const struct cparams {
2723 { 1, 1333, 301, 28664 },
2724 { 1, 1066, 294, 24460 },
2725 { 1, 800, 294, 25192 },
2726 { 0, 1333, 276, 27605 },
2727 { 0, 1066, 276, 27605 },
2728 { 0, 800, 231, 23784 },
2731 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2733 u64 total_count, diff, ret;
2734 u32 count1, count2, count3, m = 0, c = 0;
2735 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2738 assert_spin_locked(&mchdev_lock);
2740 diff1 = now - dev_priv->ips.last_time1;
2742 /* Prevent division-by-zero if we are asking too fast.
2743 * Also, we don't get interesting results if we are polling
2744 * faster than once in 10ms, so just return the saved value
2748 return dev_priv->ips.chipset_power;
2750 count1 = I915_READ(DMIEC);
2751 count2 = I915_READ(DDREC);
2752 count3 = I915_READ(CSIEC);
2754 total_count = count1 + count2 + count3;
2756 /* FIXME: handle per-counter overflow */
2757 if (total_count < dev_priv->ips.last_count1) {
2758 diff = ~0UL - dev_priv->ips.last_count1;
2759 diff += total_count;
2761 diff = total_count - dev_priv->ips.last_count1;
2764 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2765 if (cparams[i].i == dev_priv->ips.c_m &&
2766 cparams[i].t == dev_priv->ips.r_t) {
2773 diff = div_u64(diff, diff1);
2774 ret = ((m * diff) + c);
2775 ret = div_u64(ret, 10);
2777 dev_priv->ips.last_count1 = total_count;
2778 dev_priv->ips.last_time1 = now;
2780 dev_priv->ips.chipset_power = ret;
2785 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2789 if (dev_priv->info->gen != 5)
2792 spin_lock_irq(&mchdev_lock);
2794 val = __i915_chipset_val(dev_priv);
2796 spin_unlock_irq(&mchdev_lock);
2801 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2803 unsigned long m, x, b;
2806 tsfs = I915_READ(TSFS);
2808 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2809 x = I915_READ8(TR1);
2811 b = tsfs & TSFS_INTR_MASK;
2813 return ((m * x) / 127) - b;
2816 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2818 static const struct v_table {
2819 u16 vd; /* in .1 mil */
2820 u16 vm; /* in .1 mil */
2951 if (dev_priv->info->is_mobile)
2952 return v_table[pxvid].vm;
2954 return v_table[pxvid].vd;
2957 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
2959 struct timespec now, diff1;
2961 unsigned long diffms;
2964 assert_spin_locked(&mchdev_lock);
2966 getrawmonotonic(&now);
2967 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
2969 /* Don't divide by 0 */
2970 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
2974 count = I915_READ(GFXEC);
2976 if (count < dev_priv->ips.last_count2) {
2977 diff = ~0UL - dev_priv->ips.last_count2;
2980 diff = count - dev_priv->ips.last_count2;
2983 dev_priv->ips.last_count2 = count;
2984 dev_priv->ips.last_time2 = now;
2986 /* More magic constants... */
2988 diff = div_u64(diff, diffms * 10);
2989 dev_priv->ips.gfx_power = diff;
2992 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
2994 if (dev_priv->info->gen != 5)
2997 spin_lock_irq(&mchdev_lock);
2999 __i915_update_gfx_val(dev_priv);
3001 spin_unlock_irq(&mchdev_lock);
3004 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3006 unsigned long t, corr, state1, corr2, state2;
3009 assert_spin_locked(&mchdev_lock);
3011 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3012 pxvid = (pxvid >> 24) & 0x7f;
3013 ext_v = pvid_to_extvid(dev_priv, pxvid);
3017 t = i915_mch_val(dev_priv);
3019 /* Revel in the empirically derived constants */
3021 /* Correction factor in 1/100000 units */
3023 corr = ((t * 2349) + 135940);
3025 corr = ((t * 964) + 29317);
3027 corr = ((t * 301) + 1004);
3029 corr = corr * ((150142 * state1) / 10000 - 78642);
3031 corr2 = (corr * dev_priv->ips.corr);
3033 state2 = (corr2 * state1) / 10000;
3034 state2 /= 100; /* convert to mW */
3036 __i915_update_gfx_val(dev_priv);
3038 return dev_priv->ips.gfx_power + state2;
3041 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3045 if (dev_priv->info->gen != 5)
3048 spin_lock_irq(&mchdev_lock);
3050 val = __i915_gfx_val(dev_priv);
3052 spin_unlock_irq(&mchdev_lock);
3058 * i915_read_mch_val - return value for IPS use
3060 * Calculate and return a value for the IPS driver to use when deciding whether
3061 * we have thermal and power headroom to increase CPU or GPU power budget.
3063 unsigned long i915_read_mch_val(void)
3065 struct drm_i915_private *dev_priv;
3066 unsigned long chipset_val, graphics_val, ret = 0;
3068 spin_lock_irq(&mchdev_lock);
3071 dev_priv = i915_mch_dev;
3073 chipset_val = __i915_chipset_val(dev_priv);
3074 graphics_val = __i915_gfx_val(dev_priv);
3076 ret = chipset_val + graphics_val;
3079 spin_unlock_irq(&mchdev_lock);
3083 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3086 * i915_gpu_raise - raise GPU frequency limit
3088 * Raise the limit; IPS indicates we have thermal headroom.
3090 bool i915_gpu_raise(void)
3092 struct drm_i915_private *dev_priv;
3095 spin_lock_irq(&mchdev_lock);
3096 if (!i915_mch_dev) {
3100 dev_priv = i915_mch_dev;
3102 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3103 dev_priv->ips.max_delay--;
3106 spin_unlock_irq(&mchdev_lock);
3110 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3113 * i915_gpu_lower - lower GPU frequency limit
3115 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3116 * frequency maximum.
3118 bool i915_gpu_lower(void)
3120 struct drm_i915_private *dev_priv;
3123 spin_lock_irq(&mchdev_lock);
3124 if (!i915_mch_dev) {
3128 dev_priv = i915_mch_dev;
3130 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3131 dev_priv->ips.max_delay++;
3134 spin_unlock_irq(&mchdev_lock);
3138 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3141 * i915_gpu_busy - indicate GPU business to IPS
3143 * Tell the IPS driver whether or not the GPU is busy.
3145 bool i915_gpu_busy(void)
3147 struct drm_i915_private *dev_priv;
3148 struct intel_ring_buffer *ring;
3152 spin_lock_irq(&mchdev_lock);
3155 dev_priv = i915_mch_dev;
3157 for_each_ring(ring, dev_priv, i)
3158 ret |= !list_empty(&ring->request_list);
3161 spin_unlock_irq(&mchdev_lock);
3165 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3168 * i915_gpu_turbo_disable - disable graphics turbo
3170 * Disable graphics turbo by resetting the max frequency and setting the
3171 * current frequency to the default.
3173 bool i915_gpu_turbo_disable(void)
3175 struct drm_i915_private *dev_priv;
3178 spin_lock_irq(&mchdev_lock);
3179 if (!i915_mch_dev) {
3183 dev_priv = i915_mch_dev;
3185 dev_priv->ips.max_delay = dev_priv->ips.fstart;
3187 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3191 spin_unlock_irq(&mchdev_lock);
3195 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3198 * Tells the intel_ips driver that the i915 driver is now loaded, if
3199 * IPS got loaded first.
3201 * This awkward dance is so that neither module has to depend on the
3202 * other in order for IPS to do the appropriate communication of
3203 * GPU turbo limits to i915.
3206 ips_ping_for_i915_load(void)
3210 link = symbol_get(ips_link_to_i915_driver);
3213 symbol_put(ips_link_to_i915_driver);
3217 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3219 /* We only register the i915 ips part with intel-ips once everything is
3220 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3221 spin_lock_irq(&mchdev_lock);
3222 i915_mch_dev = dev_priv;
3223 spin_unlock_irq(&mchdev_lock);
3225 ips_ping_for_i915_load();
3228 void intel_gpu_ips_teardown(void)
3230 spin_lock_irq(&mchdev_lock);
3231 i915_mch_dev = NULL;
3232 spin_unlock_irq(&mchdev_lock);
3234 static void intel_init_emon(struct drm_device *dev)
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3241 /* Disable to program */
3245 /* Program energy weights for various events */
3246 I915_WRITE(SDEW, 0x15040d00);
3247 I915_WRITE(CSIEW0, 0x007f0000);
3248 I915_WRITE(CSIEW1, 0x1e220004);
3249 I915_WRITE(CSIEW2, 0x04000004);
3251 for (i = 0; i < 5; i++)
3252 I915_WRITE(PEW + (i * 4), 0);
3253 for (i = 0; i < 3; i++)
3254 I915_WRITE(DEW + (i * 4), 0);
3256 /* Program P-state weights to account for frequency power adjustment */
3257 for (i = 0; i < 16; i++) {
3258 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3259 unsigned long freq = intel_pxfreq(pxvidfreq);
3260 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3265 val *= (freq / 1000);
3267 val /= (127*127*900);
3269 DRM_ERROR("bad pxval: %ld\n", val);
3272 /* Render standby states get 0 weight */
3276 for (i = 0; i < 4; i++) {
3277 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3278 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3279 I915_WRITE(PXW + (i * 4), val);
3282 /* Adjust magic regs to magic values (more experimental results) */
3283 I915_WRITE(OGW0, 0);
3284 I915_WRITE(OGW1, 0);
3285 I915_WRITE(EG0, 0x00007f00);
3286 I915_WRITE(EG1, 0x0000000e);
3287 I915_WRITE(EG2, 0x000e0000);
3288 I915_WRITE(EG3, 0x68000300);
3289 I915_WRITE(EG4, 0x42000000);
3290 I915_WRITE(EG5, 0x00140031);
3294 for (i = 0; i < 8; i++)
3295 I915_WRITE(PXWL + (i * 4), 0);
3297 /* Enable PMON + select events */
3298 I915_WRITE(ECR, 0x80000019);
3300 lcfuse = I915_READ(LCFUSE02);
3302 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3305 void intel_disable_gt_powersave(struct drm_device *dev)
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3309 if (IS_IRONLAKE_M(dev)) {
3310 ironlake_disable_drps(dev);
3311 ironlake_disable_rc6(dev);
3312 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3313 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3314 gen6_disable_rps(dev);
3318 static void intel_gen6_powersave_work(struct work_struct *work)
3320 struct drm_i915_private *dev_priv =
3321 container_of(work, struct drm_i915_private,
3322 rps.delayed_resume_work.work);
3323 struct drm_device *dev = dev_priv->dev;
3325 mutex_lock(&dev->struct_mutex);
3326 gen6_enable_rps(dev);
3327 gen6_update_ring_freq(dev);
3328 mutex_unlock(&dev->struct_mutex);
3331 void intel_enable_gt_powersave(struct drm_device *dev)
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3335 if (IS_IRONLAKE_M(dev)) {
3336 ironlake_enable_drps(dev);
3337 ironlake_enable_rc6(dev);
3338 intel_init_emon(dev);
3339 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3341 * PCU communication is slow and this doesn't need to be
3342 * done at any specific time, so do this out of our fast path
3343 * to make resume and init faster.
3345 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3346 round_jiffies_up_relative(HZ));
3350 static void ibx_init_clock_gating(struct drm_device *dev)
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3355 * On Ibex Peak and Cougar Point, we need to disable clock
3356 * gating for the panel power sequencer or it will fail to
3357 * start up when no ports are active.
3359 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3362 static void ironlake_init_clock_gating(struct drm_device *dev)
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3367 /* Required for FBC */
3368 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3369 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3370 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3372 I915_WRITE(PCH_3DCGDIS0,
3373 MARIUNIT_CLOCK_GATE_DISABLE |
3374 SVSMUNIT_CLOCK_GATE_DISABLE);
3375 I915_WRITE(PCH_3DCGDIS1,
3376 VFMUNIT_CLOCK_GATE_DISABLE);
3379 * According to the spec the following bits should be set in
3380 * order to enable memory self-refresh
3381 * The bit 22/21 of 0x42004
3382 * The bit 5 of 0x42020
3383 * The bit 15 of 0x45000
3385 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3386 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3387 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3388 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3389 I915_WRITE(DISP_ARB_CTL,
3390 (I915_READ(DISP_ARB_CTL) |
3392 I915_WRITE(WM3_LP_ILK, 0);
3393 I915_WRITE(WM2_LP_ILK, 0);
3394 I915_WRITE(WM1_LP_ILK, 0);
3397 * Based on the document from hardware guys the following bits
3398 * should be set unconditionally in order to enable FBC.
3399 * The bit 22 of 0x42000
3400 * The bit 22 of 0x42004
3401 * The bit 7,8,9 of 0x42020.
3403 if (IS_IRONLAKE_M(dev)) {
3404 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3405 I915_READ(ILK_DISPLAY_CHICKEN1) |
3407 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3408 I915_READ(ILK_DISPLAY_CHICKEN2) |
3412 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3414 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3415 I915_READ(ILK_DISPLAY_CHICKEN2) |
3416 ILK_ELPIN_409_SELECT);
3417 I915_WRITE(_3D_CHICKEN2,
3418 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3419 _3D_CHICKEN2_WM_READ_PIPELINED);
3421 /* WaDisableRenderCachePipelinedFlush */
3422 I915_WRITE(CACHE_MODE_0,
3423 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3425 ibx_init_clock_gating(dev);
3428 static void cpt_init_clock_gating(struct drm_device *dev)
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3434 * On Ibex Peak and Cougar Point, we need to disable clock
3435 * gating for the panel power sequencer or it will fail to
3436 * start up when no ports are active.
3438 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3439 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3440 DPLS_EDP_PPS_FIX_DIS);
3441 /* WADP0ClockGatingDisable */
3442 for_each_pipe(pipe) {
3443 I915_WRITE(TRANS_CHICKEN1(pipe),
3444 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3448 static void gen6_init_clock_gating(struct drm_device *dev)
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3452 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3454 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3456 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3457 I915_READ(ILK_DISPLAY_CHICKEN2) |
3458 ILK_ELPIN_409_SELECT);
3460 I915_WRITE(WM3_LP_ILK, 0);
3461 I915_WRITE(WM2_LP_ILK, 0);
3462 I915_WRITE(WM1_LP_ILK, 0);
3464 I915_WRITE(CACHE_MODE_0,
3465 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3467 I915_WRITE(GEN6_UCGCTL1,
3468 I915_READ(GEN6_UCGCTL1) |
3469 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3470 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3472 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3473 * gating disable must be set. Failure to set it results in
3474 * flickering pixels due to Z write ordering failures after
3475 * some amount of runtime in the Mesa "fire" demo, and Unigine
3476 * Sanctuary and Tropics, and apparently anything else with
3477 * alpha test or pixel discard.
3479 * According to the spec, bit 11 (RCCUNIT) must also be set,
3480 * but we didn't debug actual testcases to find it out.
3482 * Also apply WaDisableVDSUnitClockGating and
3483 * WaDisableRCPBUnitClockGating.
3485 I915_WRITE(GEN6_UCGCTL2,
3486 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3487 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3488 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3490 /* Bspec says we need to always set all mask bits. */
3491 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3492 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3495 * According to the spec the following bits should be
3496 * set in order to enable memory self-refresh and fbc:
3497 * The bit21 and bit22 of 0x42000
3498 * The bit21 and bit22 of 0x42004
3499 * The bit5 and bit7 of 0x42020
3500 * The bit14 of 0x70180
3501 * The bit14 of 0x71180
3503 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3504 I915_READ(ILK_DISPLAY_CHICKEN1) |
3505 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3506 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3507 I915_READ(ILK_DISPLAY_CHICKEN2) |
3508 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3509 I915_WRITE(ILK_DSPCLK_GATE_D,
3510 I915_READ(ILK_DSPCLK_GATE_D) |
3511 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3512 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3514 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3515 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3517 for_each_pipe(pipe) {
3518 I915_WRITE(DSPCNTR(pipe),
3519 I915_READ(DSPCNTR(pipe)) |
3520 DISPPLANE_TRICKLE_FEED_DISABLE);
3521 intel_flush_display_plane(dev_priv, pipe);
3524 /* The default value should be 0x200 according to docs, but the two
3525 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3526 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3527 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3529 cpt_init_clock_gating(dev);
3532 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3534 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3536 reg &= ~GEN7_FF_SCHED_MASK;
3537 reg |= GEN7_FF_TS_SCHED_HW;
3538 reg |= GEN7_FF_VS_SCHED_HW;
3539 reg |= GEN7_FF_DS_SCHED_HW;
3541 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3544 static void haswell_init_clock_gating(struct drm_device *dev)
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3549 I915_WRITE(WM3_LP_ILK, 0);
3550 I915_WRITE(WM2_LP_ILK, 0);
3551 I915_WRITE(WM1_LP_ILK, 0);
3553 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3554 * This implements the WaDisableRCZUnitClockGating workaround.
3556 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3558 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3559 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3560 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3562 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3563 I915_WRITE(GEN7_L3CNTLREG1,
3564 GEN7_WA_FOR_GEN7_L3_CONTROL);
3565 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3566 GEN7_WA_L3_CHICKEN_MODE);
3568 /* This is required by WaCatErrorRejectionIssue */
3569 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3570 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3571 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3573 for_each_pipe(pipe) {
3574 I915_WRITE(DSPCNTR(pipe),
3575 I915_READ(DSPCNTR(pipe)) |
3576 DISPPLANE_TRICKLE_FEED_DISABLE);
3577 intel_flush_display_plane(dev_priv, pipe);
3580 gen7_setup_fixed_func_scheduler(dev_priv);
3582 /* WaDisable4x2SubspanOptimization */
3583 I915_WRITE(CACHE_MODE_1,
3584 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3586 /* XXX: This is a workaround for early silicon revisions and should be
3591 WM_DBG_DISALLOW_MULTIPLE_LP |
3592 WM_DBG_DISALLOW_SPRITE |
3593 WM_DBG_DISALLOW_MAXFIFO);
3597 static void ivybridge_init_clock_gating(struct drm_device *dev)
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3603 I915_WRITE(WM3_LP_ILK, 0);
3604 I915_WRITE(WM2_LP_ILK, 0);
3605 I915_WRITE(WM1_LP_ILK, 0);
3607 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3609 /* WaDisableEarlyCull */
3610 I915_WRITE(_3D_CHICKEN3,
3611 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3613 /* WaDisableBackToBackFlipFix */
3614 I915_WRITE(IVB_CHICKEN3,
3615 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3616 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3618 /* WaDisablePSDDualDispatchEnable */
3619 if (IS_IVB_GT1(dev))
3620 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3621 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3623 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3624 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3626 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3627 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3628 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3630 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3631 I915_WRITE(GEN7_L3CNTLREG1,
3632 GEN7_WA_FOR_GEN7_L3_CONTROL);
3633 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3634 GEN7_WA_L3_CHICKEN_MODE);
3635 if (IS_IVB_GT1(dev))
3636 I915_WRITE(GEN7_ROW_CHICKEN2,
3637 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3639 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3640 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3643 /* WaForceL3Serialization */
3644 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3645 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3647 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3648 * gating disable must be set. Failure to set it results in
3649 * flickering pixels due to Z write ordering failures after
3650 * some amount of runtime in the Mesa "fire" demo, and Unigine
3651 * Sanctuary and Tropics, and apparently anything else with
3652 * alpha test or pixel discard.
3654 * According to the spec, bit 11 (RCCUNIT) must also be set,
3655 * but we didn't debug actual testcases to find it out.
3657 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3658 * This implements the WaDisableRCZUnitClockGating workaround.
3660 I915_WRITE(GEN6_UCGCTL2,
3661 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3662 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3664 /* This is required by WaCatErrorRejectionIssue */
3665 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3666 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3667 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3669 for_each_pipe(pipe) {
3670 I915_WRITE(DSPCNTR(pipe),
3671 I915_READ(DSPCNTR(pipe)) |
3672 DISPPLANE_TRICKLE_FEED_DISABLE);
3673 intel_flush_display_plane(dev_priv, pipe);
3676 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3677 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3679 gen7_setup_fixed_func_scheduler(dev_priv);
3681 /* WaDisable4x2SubspanOptimization */
3682 I915_WRITE(CACHE_MODE_1,
3683 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3685 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3686 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3687 snpcr |= GEN6_MBC_SNPCR_MED;
3688 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3690 cpt_init_clock_gating(dev);
3693 static void valleyview_init_clock_gating(struct drm_device *dev)
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3698 I915_WRITE(WM3_LP_ILK, 0);
3699 I915_WRITE(WM2_LP_ILK, 0);
3700 I915_WRITE(WM1_LP_ILK, 0);
3702 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3704 /* WaDisableEarlyCull */
3705 I915_WRITE(_3D_CHICKEN3,
3706 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3708 /* WaDisableBackToBackFlipFix */
3709 I915_WRITE(IVB_CHICKEN3,
3710 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3711 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3713 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3714 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3716 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3717 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3718 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3720 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3721 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3722 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3724 /* WaForceL3Serialization */
3725 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3726 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3728 /* WaDisableDopClockGating */
3729 I915_WRITE(GEN7_ROW_CHICKEN2,
3730 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3732 /* WaForceL3Serialization */
3733 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3734 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3736 /* This is required by WaCatErrorRejectionIssue */
3737 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3738 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3739 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3741 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3742 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3745 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3746 * gating disable must be set. Failure to set it results in
3747 * flickering pixels due to Z write ordering failures after
3748 * some amount of runtime in the Mesa "fire" demo, and Unigine
3749 * Sanctuary and Tropics, and apparently anything else with
3750 * alpha test or pixel discard.
3752 * According to the spec, bit 11 (RCCUNIT) must also be set,
3753 * but we didn't debug actual testcases to find it out.
3755 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3756 * This implements the WaDisableRCZUnitClockGating workaround.
3758 * Also apply WaDisableVDSUnitClockGating and
3759 * WaDisableRCPBUnitClockGating.
3761 I915_WRITE(GEN6_UCGCTL2,
3762 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3763 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3764 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3765 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3766 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3768 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3770 for_each_pipe(pipe) {
3771 I915_WRITE(DSPCNTR(pipe),
3772 I915_READ(DSPCNTR(pipe)) |
3773 DISPPLANE_TRICKLE_FEED_DISABLE);
3774 intel_flush_display_plane(dev_priv, pipe);
3777 I915_WRITE(CACHE_MODE_1,
3778 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3781 * On ValleyView, the GUnit needs to signal the GT
3782 * when flip and other events complete. So enable
3783 * all the GUnit->GT interrupts here
3785 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3786 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3787 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3788 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3789 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3790 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3791 PLANEA_FLIPDONE_INT_EN);
3794 * WaDisableVLVClockGating_VBIIssue
3795 * Disable clock gating on th GCFG unit to prevent a delay
3796 * in the reporting of vblank events.
3798 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
3801 static void g4x_init_clock_gating(struct drm_device *dev)
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 uint32_t dspclk_gate;
3806 I915_WRITE(RENCLK_GATE_D1, 0);
3807 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3808 GS_UNIT_CLOCK_GATE_DISABLE |
3809 CL_UNIT_CLOCK_GATE_DISABLE);
3810 I915_WRITE(RAMCLK_GATE_D, 0);
3811 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3812 OVRUNIT_CLOCK_GATE_DISABLE |
3813 OVCUNIT_CLOCK_GATE_DISABLE;
3815 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3816 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3818 /* WaDisableRenderCachePipelinedFlush */
3819 I915_WRITE(CACHE_MODE_0,
3820 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3823 static void crestline_init_clock_gating(struct drm_device *dev)
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3827 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3828 I915_WRITE(RENCLK_GATE_D2, 0);
3829 I915_WRITE(DSPCLK_GATE_D, 0);
3830 I915_WRITE(RAMCLK_GATE_D, 0);
3831 I915_WRITE16(DEUC, 0);
3834 static void broadwater_init_clock_gating(struct drm_device *dev)
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3838 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3839 I965_RCC_CLOCK_GATE_DISABLE |
3840 I965_RCPB_CLOCK_GATE_DISABLE |
3841 I965_ISC_CLOCK_GATE_DISABLE |
3842 I965_FBC_CLOCK_GATE_DISABLE);
3843 I915_WRITE(RENCLK_GATE_D2, 0);
3846 static void gen3_init_clock_gating(struct drm_device *dev)
3848 struct drm_i915_private *dev_priv = dev->dev_private;
3849 u32 dstate = I915_READ(D_STATE);
3851 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3852 DSTATE_DOT_CLOCK_GATING;
3853 I915_WRITE(D_STATE, dstate);
3855 if (IS_PINEVIEW(dev))
3856 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
3858 /* IIR "flip pending" means done if this bit is set */
3859 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
3862 static void i85x_init_clock_gating(struct drm_device *dev)
3864 struct drm_i915_private *dev_priv = dev->dev_private;
3866 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3869 static void i830_init_clock_gating(struct drm_device *dev)
3871 struct drm_i915_private *dev_priv = dev->dev_private;
3873 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3876 void intel_init_clock_gating(struct drm_device *dev)
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3880 dev_priv->display.init_clock_gating(dev);
3883 /* Starting with Haswell, we have different power wells for
3884 * different parts of the GPU. This attempts to enable them all.
3886 void intel_init_power_wells(struct drm_device *dev)
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 unsigned long power_wells[] = {
3896 if (!IS_HASWELL(dev))
3899 mutex_lock(&dev->struct_mutex);
3901 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
3902 int well = I915_READ(power_wells[i]);
3904 if ((well & HSW_PWR_WELL_STATE) == 0) {
3905 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
3906 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
3907 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
3911 mutex_unlock(&dev->struct_mutex);
3914 /* Set up chip specific power management-related functions */
3915 void intel_init_pm(struct drm_device *dev)
3917 struct drm_i915_private *dev_priv = dev->dev_private;
3919 if (I915_HAS_FBC(dev)) {
3920 if (HAS_PCH_SPLIT(dev)) {
3921 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
3922 dev_priv->display.enable_fbc = ironlake_enable_fbc;
3923 dev_priv->display.disable_fbc = ironlake_disable_fbc;
3924 } else if (IS_GM45(dev)) {
3925 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
3926 dev_priv->display.enable_fbc = g4x_enable_fbc;
3927 dev_priv->display.disable_fbc = g4x_disable_fbc;
3928 } else if (IS_CRESTLINE(dev)) {
3929 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
3930 dev_priv->display.enable_fbc = i8xx_enable_fbc;
3931 dev_priv->display.disable_fbc = i8xx_disable_fbc;
3933 /* 855GM needs testing */
3937 if (IS_PINEVIEW(dev))
3938 i915_pineview_get_mem_freq(dev);
3939 else if (IS_GEN5(dev))
3940 i915_ironlake_get_mem_freq(dev);
3942 /* For FIFO watermark updates */
3943 if (HAS_PCH_SPLIT(dev)) {
3945 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
3946 dev_priv->display.update_wm = ironlake_update_wm;
3948 DRM_DEBUG_KMS("Failed to get proper latency. "
3950 dev_priv->display.update_wm = NULL;
3952 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
3953 } else if (IS_GEN6(dev)) {
3954 if (SNB_READ_WM0_LATENCY()) {
3955 dev_priv->display.update_wm = sandybridge_update_wm;
3956 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3958 DRM_DEBUG_KMS("Failed to read display plane latency. "
3960 dev_priv->display.update_wm = NULL;
3962 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
3963 } else if (IS_IVYBRIDGE(dev)) {
3964 /* FIXME: detect B0+ stepping and use auto training */
3965 if (SNB_READ_WM0_LATENCY()) {
3966 dev_priv->display.update_wm = sandybridge_update_wm;
3967 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3969 DRM_DEBUG_KMS("Failed to read display plane latency. "
3971 dev_priv->display.update_wm = NULL;
3973 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
3974 } else if (IS_HASWELL(dev)) {
3975 if (SNB_READ_WM0_LATENCY()) {
3976 dev_priv->display.update_wm = sandybridge_update_wm;
3977 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3978 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
3980 DRM_DEBUG_KMS("Failed to read display plane latency. "
3982 dev_priv->display.update_wm = NULL;
3984 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
3986 dev_priv->display.update_wm = NULL;
3987 } else if (IS_VALLEYVIEW(dev)) {
3988 dev_priv->display.update_wm = valleyview_update_wm;
3989 dev_priv->display.init_clock_gating =
3990 valleyview_init_clock_gating;
3991 } else if (IS_PINEVIEW(dev)) {
3992 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
3995 dev_priv->mem_freq)) {
3996 DRM_INFO("failed to find known CxSR latency "
3997 "(found ddr%s fsb freq %d, mem freq %d), "
3999 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4000 dev_priv->fsb_freq, dev_priv->mem_freq);
4001 /* Disable CxSR and never update its watermark again */
4002 pineview_disable_cxsr(dev);
4003 dev_priv->display.update_wm = NULL;
4005 dev_priv->display.update_wm = pineview_update_wm;
4006 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4007 } else if (IS_G4X(dev)) {
4008 dev_priv->display.update_wm = g4x_update_wm;
4009 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4010 } else if (IS_GEN4(dev)) {
4011 dev_priv->display.update_wm = i965_update_wm;
4012 if (IS_CRESTLINE(dev))
4013 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4014 else if (IS_BROADWATER(dev))
4015 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4016 } else if (IS_GEN3(dev)) {
4017 dev_priv->display.update_wm = i9xx_update_wm;
4018 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4019 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4020 } else if (IS_I865G(dev)) {
4021 dev_priv->display.update_wm = i830_update_wm;
4022 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4023 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4024 } else if (IS_I85X(dev)) {
4025 dev_priv->display.update_wm = i9xx_update_wm;
4026 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4027 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4029 dev_priv->display.update_wm = i830_update_wm;
4030 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4032 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4034 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4038 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4040 u32 gt_thread_status_mask;
4042 if (IS_HASWELL(dev_priv->dev))
4043 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4045 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4047 /* w/a for a sporadic read returning 0 by waiting for the GT
4048 * thread to wake up.
4050 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4051 DRM_ERROR("GT thread status wait timed out\n");
4054 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4056 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4057 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4060 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4064 if (IS_HASWELL(dev_priv->dev))
4065 forcewake_ack = FORCEWAKE_ACK_HSW;
4067 forcewake_ack = FORCEWAKE_ACK;
4069 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4070 FORCEWAKE_ACK_TIMEOUT_MS))
4071 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4073 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4074 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4076 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4077 FORCEWAKE_ACK_TIMEOUT_MS))
4078 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4080 __gen6_gt_wait_for_thread_c0(dev_priv);
4083 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4085 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4086 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4089 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4093 if (IS_HASWELL(dev_priv->dev))
4094 forcewake_ack = FORCEWAKE_ACK_HSW;
4096 forcewake_ack = FORCEWAKE_MT_ACK;
4098 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4099 FORCEWAKE_ACK_TIMEOUT_MS))
4100 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4102 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4103 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4105 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4106 FORCEWAKE_ACK_TIMEOUT_MS))
4107 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4109 __gen6_gt_wait_for_thread_c0(dev_priv);
4113 * Generally this is called implicitly by the register read function. However,
4114 * if some sequence requires the GT to not power down then this function should
4115 * be called at the beginning of the sequence followed by a call to
4116 * gen6_gt_force_wake_put() at the end of the sequence.
4118 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4120 unsigned long irqflags;
4122 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4123 if (dev_priv->forcewake_count++ == 0)
4124 dev_priv->gt.force_wake_get(dev_priv);
4125 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4128 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4131 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4132 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4133 "MMIO read or write has been dropped %x\n", gtfifodbg))
4134 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4137 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4139 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4140 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4141 gen6_gt_check_fifodbg(dev_priv);
4144 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4146 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4147 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4148 gen6_gt_check_fifodbg(dev_priv);
4152 * see gen6_gt_force_wake_get()
4154 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4156 unsigned long irqflags;
4158 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4159 if (--dev_priv->forcewake_count == 0)
4160 dev_priv->gt.force_wake_put(dev_priv);
4161 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4164 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4168 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4170 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4171 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4173 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4175 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4177 dev_priv->gt_fifo_count = fifo;
4179 dev_priv->gt_fifo_count--;
4184 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4186 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4189 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4191 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4192 FORCEWAKE_ACK_TIMEOUT_MS))
4193 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4195 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4197 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4198 FORCEWAKE_ACK_TIMEOUT_MS))
4199 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4201 __gen6_gt_wait_for_thread_c0(dev_priv);
4204 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4206 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4207 /* The below doubles as a POSTING_READ */
4208 gen6_gt_check_fifodbg(dev_priv);
4211 void intel_gt_reset(struct drm_device *dev)
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4215 if (IS_VALLEYVIEW(dev)) {
4216 vlv_force_wake_reset(dev_priv);
4217 } else if (INTEL_INFO(dev)->gen >= 6) {
4218 __gen6_gt_force_wake_reset(dev_priv);
4219 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4220 __gen6_gt_force_wake_mt_reset(dev_priv);
4224 void intel_gt_init(struct drm_device *dev)
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4228 spin_lock_init(&dev_priv->gt_lock);
4230 intel_gt_reset(dev);
4232 if (IS_VALLEYVIEW(dev)) {
4233 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4234 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4235 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4236 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4237 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4238 } else if (IS_GEN6(dev)) {
4239 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4240 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4242 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4243 intel_gen6_powersave_work);
4246 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4248 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
4250 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4251 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4255 I915_WRITE(GEN6_PCODE_DATA, *val);
4256 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4258 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4260 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4264 *val = I915_READ(GEN6_PCODE_DATA);
4265 I915_WRITE(GEN6_PCODE_DATA, 0);
4270 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4272 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
4274 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4275 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4279 I915_WRITE(GEN6_PCODE_DATA, val);
4280 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4282 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4284 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4288 I915_WRITE(GEN6_PCODE_DATA, 0);