2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33 #include <linux/moduleparam.h>
34 #include "intel_drv.h"
36 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
39 intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
40 struct drm_display_mode *adjusted_mode)
42 drm_mode_copy(adjusted_mode, fixed_mode);
44 drm_mode_set_crtcinfo(adjusted_mode, 0);
47 /* adjusted_mode has been preset to be the panel's fixed mode */
49 intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
50 struct intel_crtc_config *pipe_config,
53 struct drm_display_mode *adjusted_mode;
54 int x, y, width, height;
56 adjusted_mode = &pipe_config->adjusted_mode;
58 x = y = width = height = 0;
60 /* Native modes don't need fitting */
61 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
62 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
65 switch (fitting_mode) {
66 case DRM_MODE_SCALE_CENTER:
67 width = pipe_config->pipe_src_w;
68 height = pipe_config->pipe_src_h;
69 x = (adjusted_mode->hdisplay - width + 1)/2;
70 y = (adjusted_mode->vdisplay - height + 1)/2;
73 case DRM_MODE_SCALE_ASPECT:
74 /* Scale but preserve the aspect ratio */
76 u32 scaled_width = adjusted_mode->hdisplay
77 * pipe_config->pipe_src_h;
78 u32 scaled_height = pipe_config->pipe_src_w
79 * adjusted_mode->vdisplay;
80 if (scaled_width > scaled_height) { /* pillar */
81 width = scaled_height / pipe_config->pipe_src_h;
84 x = (adjusted_mode->hdisplay - width + 1) / 2;
86 height = adjusted_mode->vdisplay;
87 } else if (scaled_width < scaled_height) { /* letter */
88 height = scaled_width / pipe_config->pipe_src_w;
91 y = (adjusted_mode->vdisplay - height + 1) / 2;
93 width = adjusted_mode->hdisplay;
96 width = adjusted_mode->hdisplay;
97 height = adjusted_mode->vdisplay;
102 case DRM_MODE_SCALE_FULLSCREEN:
104 width = adjusted_mode->hdisplay;
105 height = adjusted_mode->vdisplay;
109 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
114 pipe_config->pch_pfit.pos = (x << 16) | y;
115 pipe_config->pch_pfit.size = (width << 16) | height;
116 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
120 centre_horizontally(struct drm_display_mode *mode,
123 u32 border, sync_pos, blank_width, sync_width;
125 /* keep the hsync and hblank widths constant */
126 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
127 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
128 sync_pos = (blank_width - sync_width + 1) / 2;
130 border = (mode->hdisplay - width + 1) / 2;
131 border += border & 1; /* make the border even */
133 mode->crtc_hdisplay = width;
134 mode->crtc_hblank_start = width + border;
135 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
137 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
138 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
142 centre_vertically(struct drm_display_mode *mode,
145 u32 border, sync_pos, blank_width, sync_width;
147 /* keep the vsync and vblank widths constant */
148 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
149 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
150 sync_pos = (blank_width - sync_width + 1) / 2;
152 border = (mode->vdisplay - height + 1) / 2;
154 mode->crtc_vdisplay = height;
155 mode->crtc_vblank_start = height + border;
156 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
158 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
159 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
162 static inline u32 panel_fitter_scaling(u32 source, u32 target)
165 * Floating point operation is not supported. So the FACTOR
166 * is defined, which can avoid the floating point computation
167 * when calculating the panel ratio.
170 #define FACTOR (1 << ACCURACY)
171 u32 ratio = source * FACTOR / target;
172 return (FACTOR * ratio + FACTOR/2) / FACTOR;
175 static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
178 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
179 u32 scaled_width = adjusted_mode->hdisplay *
180 pipe_config->pipe_src_h;
181 u32 scaled_height = pipe_config->pipe_src_w *
182 adjusted_mode->vdisplay;
184 /* 965+ is easy, it does everything in hw */
185 if (scaled_width > scaled_height)
186 *pfit_control |= PFIT_ENABLE |
188 else if (scaled_width < scaled_height)
189 *pfit_control |= PFIT_ENABLE |
191 else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
192 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
195 static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
196 u32 *pfit_control, u32 *pfit_pgm_ratios,
199 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
200 u32 scaled_width = adjusted_mode->hdisplay *
201 pipe_config->pipe_src_h;
202 u32 scaled_height = pipe_config->pipe_src_w *
203 adjusted_mode->vdisplay;
207 * For earlier chips we have to calculate the scaling
208 * ratio by hand and program it into the
209 * PFIT_PGM_RATIO register
211 if (scaled_width > scaled_height) { /* pillar */
212 centre_horizontally(adjusted_mode,
214 pipe_config->pipe_src_h);
216 *border = LVDS_BORDER_ENABLE;
217 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
218 bits = panel_fitter_scaling(pipe_config->pipe_src_h,
219 adjusted_mode->vdisplay);
221 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
222 bits << PFIT_VERT_SCALE_SHIFT);
223 *pfit_control |= (PFIT_ENABLE |
224 VERT_INTERP_BILINEAR |
225 HORIZ_INTERP_BILINEAR);
227 } else if (scaled_width < scaled_height) { /* letter */
228 centre_vertically(adjusted_mode,
230 pipe_config->pipe_src_w);
232 *border = LVDS_BORDER_ENABLE;
233 if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
234 bits = panel_fitter_scaling(pipe_config->pipe_src_w,
235 adjusted_mode->hdisplay);
237 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
238 bits << PFIT_VERT_SCALE_SHIFT);
239 *pfit_control |= (PFIT_ENABLE |
240 VERT_INTERP_BILINEAR |
241 HORIZ_INTERP_BILINEAR);
244 /* Aspects match, Let hw scale both directions */
245 *pfit_control |= (PFIT_ENABLE |
246 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
247 VERT_INTERP_BILINEAR |
248 HORIZ_INTERP_BILINEAR);
252 void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
253 struct intel_crtc_config *pipe_config,
256 struct drm_device *dev = intel_crtc->base.dev;
257 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
258 struct drm_display_mode *adjusted_mode;
260 adjusted_mode = &pipe_config->adjusted_mode;
262 /* Native modes don't need fitting */
263 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
264 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
267 switch (fitting_mode) {
268 case DRM_MODE_SCALE_CENTER:
270 * For centered modes, we have to calculate border widths &
271 * heights and modify the values programmed into the CRTC.
273 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
274 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
275 border = LVDS_BORDER_ENABLE;
277 case DRM_MODE_SCALE_ASPECT:
278 /* Scale but preserve the aspect ratio */
279 if (INTEL_INFO(dev)->gen >= 4)
280 i965_scale_aspect(pipe_config, &pfit_control);
282 i9xx_scale_aspect(pipe_config, &pfit_control,
283 &pfit_pgm_ratios, &border);
285 case DRM_MODE_SCALE_FULLSCREEN:
287 * Full scaling, even if it changes the aspect ratio.
288 * Fortunately this is all done for us in hw.
290 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
291 pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
292 pfit_control |= PFIT_ENABLE;
293 if (INTEL_INFO(dev)->gen >= 4)
294 pfit_control |= PFIT_SCALING_AUTO;
296 pfit_control |= (VERT_AUTO_SCALE |
297 VERT_INTERP_BILINEAR |
299 HORIZ_INTERP_BILINEAR);
303 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
307 /* 965+ wants fuzzy fitting */
308 /* FIXME: handle multiple panels by failing gracefully */
309 if (INTEL_INFO(dev)->gen >= 4)
310 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
314 if ((pfit_control & PFIT_ENABLE) == 0) {
319 /* Make sure pre-965 set dither correctly for 18bpp panels. */
320 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
321 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
323 pipe_config->gmch_pfit.control = pfit_control;
324 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
325 pipe_config->gmch_pfit.lvds_border_bits = border;
328 static int is_backlight_combination_mode(struct drm_device *dev)
330 struct drm_i915_private *dev_priv = dev->dev_private;
332 if (INTEL_INFO(dev)->gen >= 4)
333 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
336 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
341 /* XXX: query mode clock or hardware clock and program max PWM appropriately
344 static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
346 struct drm_i915_private *dev_priv = dev->dev_private;
349 WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
351 /* Restore the CTL value if it lost, e.g. GPU reset */
353 if (HAS_PCH_SPLIT(dev_priv->dev)) {
354 val = I915_READ(BLC_PWM_PCH_CTL2);
355 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
356 dev_priv->regfile.saveBLC_PWM_CTL2 = val;
357 } else if (val == 0) {
358 val = dev_priv->regfile.saveBLC_PWM_CTL2;
359 I915_WRITE(BLC_PWM_PCH_CTL2, val);
362 val = I915_READ(BLC_PWM_CTL);
363 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
364 dev_priv->regfile.saveBLC_PWM_CTL = val;
365 if (INTEL_INFO(dev)->gen >= 4)
366 dev_priv->regfile.saveBLC_PWM_CTL2 =
367 I915_READ(BLC_PWM_CTL2);
368 } else if (val == 0) {
369 val = dev_priv->regfile.saveBLC_PWM_CTL;
370 I915_WRITE(BLC_PWM_CTL, val);
371 if (INTEL_INFO(dev)->gen >= 4)
372 I915_WRITE(BLC_PWM_CTL2,
373 dev_priv->regfile.saveBLC_PWM_CTL2);
380 static u32 intel_panel_get_max_backlight(struct drm_device *dev)
384 max = i915_read_blc_pwm_ctl(dev);
386 if (HAS_PCH_SPLIT(dev)) {
389 if (INTEL_INFO(dev)->gen < 4)
394 if (is_backlight_combination_mode(dev))
398 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
403 static int i915_panel_invert_brightness;
404 MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
405 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
406 "report PCI device ID, subsystem vendor and subsystem device ID "
407 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
408 "It will then be included in an upcoming module version.");
409 module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
410 static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
412 struct drm_i915_private *dev_priv = dev->dev_private;
414 if (i915_panel_invert_brightness < 0)
417 if (i915_panel_invert_brightness > 0 ||
418 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
419 u32 max = intel_panel_get_max_backlight(dev);
427 static u32 intel_panel_get_backlight(struct drm_device *dev)
429 struct drm_i915_private *dev_priv = dev->dev_private;
433 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
435 if (HAS_PCH_SPLIT(dev)) {
436 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
438 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
439 if (INTEL_INFO(dev)->gen < 4)
442 if (is_backlight_combination_mode(dev)) {
445 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
450 val = intel_panel_compute_brightness(dev, val);
452 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
454 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
458 static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
460 struct drm_i915_private *dev_priv = dev->dev_private;
461 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
462 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
465 static void intel_panel_actually_set_backlight(struct drm_device *dev,
468 struct drm_i915_private *dev_priv = dev->dev_private;
471 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
472 level = intel_panel_compute_brightness(dev, level);
474 if (HAS_PCH_SPLIT(dev))
475 return intel_pch_panel_set_backlight(dev, level);
477 if (is_backlight_combination_mode(dev)) {
478 u32 max = intel_panel_get_max_backlight(dev);
481 /* we're screwed, but keep behaviour backwards compatible */
485 lbpc = level * 0xfe / max + 1;
487 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
490 tmp = I915_READ(BLC_PWM_CTL);
491 if (INTEL_INFO(dev)->gen < 4)
493 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
494 I915_WRITE(BLC_PWM_CTL, tmp | level);
497 /* set backlight brightness to level in range [0..max] */
498 void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
500 struct drm_i915_private *dev_priv = dev->dev_private;
504 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
506 freq = intel_panel_get_max_backlight(dev);
508 /* we are screwed, bail out */
512 /* scale to hardware, but be careful to not overflow */
514 level = level * freq / max;
516 level = freq / max * level;
518 dev_priv->backlight.level = level;
519 if (dev_priv->backlight.device)
520 dev_priv->backlight.device->props.brightness = level;
522 if (dev_priv->backlight.enabled)
523 intel_panel_actually_set_backlight(dev, level);
525 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
528 void intel_panel_disable_backlight(struct drm_device *dev)
530 struct drm_i915_private *dev_priv = dev->dev_private;
534 * Do not disable backlight on the vgaswitcheroo path. When switching
535 * away from i915, the other client may depend on i915 to handle the
536 * backlight. This will leave the backlight on unnecessarily when
537 * another client is not activated.
539 if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
540 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
544 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
546 dev_priv->backlight.enabled = false;
547 intel_panel_actually_set_backlight(dev, 0);
549 if (INTEL_INFO(dev)->gen >= 4) {
552 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
554 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
556 if (HAS_PCH_SPLIT(dev)) {
557 tmp = I915_READ(BLC_PWM_PCH_CTL1);
558 tmp &= ~BLM_PCH_PWM_ENABLE;
559 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
563 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
566 void intel_panel_enable_backlight(struct drm_device *dev,
569 struct drm_i915_private *dev_priv = dev->dev_private;
570 enum transcoder cpu_transcoder =
571 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
574 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
576 if (dev_priv->backlight.level == 0) {
577 dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
578 if (dev_priv->backlight.device)
579 dev_priv->backlight.device->props.brightness =
580 dev_priv->backlight.level;
583 if (INTEL_INFO(dev)->gen >= 4) {
586 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
589 tmp = I915_READ(reg);
591 /* Note that this can also get called through dpms changes. And
592 * we don't track the backlight dpms state, hence check whether
593 * we have to do anything first. */
594 if (tmp & BLM_PWM_ENABLE)
597 if (INTEL_INFO(dev)->num_pipes == 3)
598 tmp &= ~BLM_PIPE_SELECT_IVB;
600 tmp &= ~BLM_PIPE_SELECT;
602 if (cpu_transcoder == TRANSCODER_EDP)
603 tmp |= BLM_TRANSCODER_EDP;
605 tmp |= BLM_PIPE(cpu_transcoder);
606 tmp &= ~BLM_PWM_ENABLE;
608 I915_WRITE(reg, tmp);
610 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
612 if (HAS_PCH_SPLIT(dev) &&
613 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
614 tmp = I915_READ(BLC_PWM_PCH_CTL1);
615 tmp |= BLM_PCH_PWM_ENABLE;
616 tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
617 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
622 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
623 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
626 dev_priv->backlight.enabled = true;
627 intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
629 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
632 static void intel_panel_init_backlight(struct drm_device *dev)
634 struct drm_i915_private *dev_priv = dev->dev_private;
636 dev_priv->backlight.level = intel_panel_get_backlight(dev);
637 dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
640 enum drm_connector_status
641 intel_panel_detect(struct drm_device *dev)
643 struct drm_i915_private *dev_priv = dev->dev_private;
645 /* Assume that the BIOS does not lie through the OpRegion... */
646 if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
647 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
648 connector_status_connected :
649 connector_status_disconnected;
652 switch (i915_panel_ignore_lid) {
654 return connector_status_connected;
656 return connector_status_disconnected;
658 return connector_status_unknown;
662 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
663 static int intel_panel_update_status(struct backlight_device *bd)
665 struct drm_device *dev = bl_get_data(bd);
666 intel_panel_set_backlight(dev, bd->props.brightness,
667 bd->props.max_brightness);
671 static int intel_panel_get_brightness(struct backlight_device *bd)
673 struct drm_device *dev = bl_get_data(bd);
674 return intel_panel_get_backlight(dev);
677 static const struct backlight_ops intel_panel_bl_ops = {
678 .update_status = intel_panel_update_status,
679 .get_brightness = intel_panel_get_brightness,
682 int intel_panel_setup_backlight(struct drm_connector *connector)
684 struct drm_device *dev = connector->dev;
685 struct drm_i915_private *dev_priv = dev->dev_private;
686 struct backlight_properties props;
689 intel_panel_init_backlight(dev);
691 if (WARN_ON(dev_priv->backlight.device))
694 memset(&props, 0, sizeof(props));
695 props.type = BACKLIGHT_RAW;
696 props.brightness = dev_priv->backlight.level;
698 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
699 props.max_brightness = intel_panel_get_max_backlight(dev);
700 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
702 if (props.max_brightness == 0) {
703 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
706 dev_priv->backlight.device =
707 backlight_device_register("intel_backlight",
708 &connector->kdev, dev,
709 &intel_panel_bl_ops, &props);
711 if (IS_ERR(dev_priv->backlight.device)) {
712 DRM_ERROR("Failed to register backlight: %ld\n",
713 PTR_ERR(dev_priv->backlight.device));
714 dev_priv->backlight.device = NULL;
720 void intel_panel_destroy_backlight(struct drm_device *dev)
722 struct drm_i915_private *dev_priv = dev->dev_private;
723 if (dev_priv->backlight.device) {
724 backlight_device_unregister(dev_priv->backlight.device);
725 dev_priv->backlight.device = NULL;
729 int intel_panel_setup_backlight(struct drm_connector *connector)
731 intel_panel_init_backlight(connector->dev);
735 void intel_panel_destroy_backlight(struct drm_device *dev)
741 int intel_panel_init(struct intel_panel *panel,
742 struct drm_display_mode *fixed_mode)
744 panel->fixed_mode = fixed_mode;
749 void intel_panel_fini(struct intel_panel *panel)
751 struct intel_connector *intel_connector =
752 container_of(panel, struct intel_connector, panel);
754 if (panel->fixed_mode)
755 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);