2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
161 GEN8_CTX_STATUS_PREEMPTED | \
162 GEN8_CTX_STATUS_ELEMENT_SWITCH)
164 #define CTX_LRI_HEADER_0 0x01
165 #define CTX_CONTEXT_CONTROL 0x02
166 #define CTX_RING_HEAD 0x04
167 #define CTX_RING_TAIL 0x06
168 #define CTX_RING_BUFFER_START 0x08
169 #define CTX_RING_BUFFER_CONTROL 0x0a
170 #define CTX_BB_HEAD_U 0x0c
171 #define CTX_BB_HEAD_L 0x0e
172 #define CTX_BB_STATE 0x10
173 #define CTX_SECOND_BB_HEAD_U 0x12
174 #define CTX_SECOND_BB_HEAD_L 0x14
175 #define CTX_SECOND_BB_STATE 0x16
176 #define CTX_BB_PER_CTX_PTR 0x18
177 #define CTX_RCS_INDIRECT_CTX 0x1a
178 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
179 #define CTX_LRI_HEADER_1 0x21
180 #define CTX_CTX_TIMESTAMP 0x22
181 #define CTX_PDP3_UDW 0x24
182 #define CTX_PDP3_LDW 0x26
183 #define CTX_PDP2_UDW 0x28
184 #define CTX_PDP2_LDW 0x2a
185 #define CTX_PDP1_UDW 0x2c
186 #define CTX_PDP1_LDW 0x2e
187 #define CTX_PDP0_UDW 0x30
188 #define CTX_PDP0_LDW 0x32
189 #define CTX_LRI_HEADER_2 0x41
190 #define CTX_R_PWR_CLK_STATE 0x42
191 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
193 #define GEN8_CTX_VALID (1<<0)
194 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
195 #define GEN8_CTX_FORCE_RESTORE (1<<2)
196 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
197 #define GEN8_CTX_PRIVILEGE (1<<8)
199 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
200 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
201 (reg_state)[(pos)+1] = (val); \
204 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
205 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
206 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
207 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
210 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
211 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
212 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
217 FAULT_AND_HALT, /* Debug only */
219 FAULT_AND_CONTINUE /* Unsupported */
221 #define GEN8_CTX_ID_SHIFT 32
222 #define GEN8_CTX_ID_WIDTH 21
223 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
224 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
226 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
227 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
229 #define WA_TAIL_DWORDS 2
231 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
232 struct intel_engine_cs *engine);
233 static int intel_lr_context_pin(struct i915_gem_context *ctx,
234 struct intel_engine_cs *engine);
235 static void execlists_init_reg_state(u32 *reg_state,
236 struct i915_gem_context *ctx,
237 struct intel_engine_cs *engine,
238 struct intel_ring *ring);
241 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
242 * @dev_priv: i915 device private
243 * @enable_execlists: value of i915.enable_execlists module parameter.
245 * Only certain platforms support Execlists (the prerequisites being
246 * support for Logical Ring Contexts and Aliasing PPGTT or better).
248 * Return: 1 if Execlists is supported and has to be enabled.
250 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
252 /* On platforms with execlist available, vGPU will only
253 * support execlist mode, no ring buffer mode.
255 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
258 if (INTEL_GEN(dev_priv) >= 9)
261 if (enable_execlists == 0)
264 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
265 USES_PPGTT(dev_priv) &&
266 i915.use_mmio_flip >= 0)
273 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
275 struct drm_i915_private *dev_priv = engine->i915;
277 engine->disable_lite_restore_wa =
278 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
279 (engine->id == VCS || engine->id == VCS2);
281 engine->ctx_desc_template = GEN8_CTX_VALID;
282 if (IS_GEN8(dev_priv))
283 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
284 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
286 /* TODO: WaDisableLiteRestore when we start using semaphore
287 * signalling between Command Streamers */
288 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
290 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
291 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
292 if (engine->disable_lite_restore_wa)
293 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
297 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
298 * descriptor for a pinned context
299 * @ctx: Context to work on
300 * @engine: Engine the descriptor will be used with
302 * The context descriptor encodes various attributes of a context,
303 * including its GTT address and some flags. Because it's fairly
304 * expensive to calculate, we'll just do it once and cache the result,
305 * which remains valid until the context is unpinned.
307 * This is what a descriptor looks like, from LSB to MSB::
309 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
310 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
311 * bits 32-52: ctx ID, a globally unique tag
312 * bits 53-54: mbz, reserved for use by hardware
313 * bits 55-63: group ID, currently unused and set to 0
316 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
317 struct intel_engine_cs *engine)
319 struct intel_context *ce = &ctx->engine[engine->id];
322 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
324 desc = ctx->desc_template; /* bits 3-4 */
325 desc |= engine->ctx_desc_template; /* bits 0-11 */
326 desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
328 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
333 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
334 struct intel_engine_cs *engine)
336 return ctx->engine[engine->id].lrc_desc;
340 execlists_context_status_change(struct drm_i915_gem_request *rq,
341 unsigned long status)
344 * Only used when GVT-g is enabled now. When GVT-g is disabled,
345 * The compiler should eliminate this function as dead-code.
347 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
350 atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
354 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
356 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
357 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
358 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
359 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
362 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
364 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
365 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
366 u32 *reg_state = ce->lrc_reg_state;
368 reg_state[CTX_RING_TAIL+1] = rq->tail;
370 /* True 32b PPGTT with dynamic page allocation: update PDP
371 * registers and point the unallocated PDPs to scratch page.
372 * PML4 is allocated during ppgtt init, so this is not needed
375 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
376 execlists_update_context_pdps(ppgtt, reg_state);
381 static void execlists_submit_ports(struct intel_engine_cs *engine)
383 struct drm_i915_private *dev_priv = engine->i915;
384 struct execlist_port *port = engine->execlist_port;
386 dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
390 execlists_context_status_change(port[0].request,
391 INTEL_CONTEXT_SCHEDULE_IN);
392 desc[0] = execlists_update_context(port[0].request);
393 engine->preempt_wa = port[0].count++; /* bdw only? fixed on skl? */
395 if (port[1].request) {
396 GEM_BUG_ON(port[1].count);
397 execlists_context_status_change(port[1].request,
398 INTEL_CONTEXT_SCHEDULE_IN);
399 desc[1] = execlists_update_context(port[1].request);
404 GEM_BUG_ON(desc[0] == desc[1]);
406 /* You must always write both descriptors in the order below. */
407 writel(upper_32_bits(desc[1]), elsp);
408 writel(lower_32_bits(desc[1]), elsp);
410 writel(upper_32_bits(desc[0]), elsp);
411 /* The context is automatically loaded after the following */
412 writel(lower_32_bits(desc[0]), elsp);
415 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
417 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
418 ctx->execlists_force_single_submission);
421 static bool can_merge_ctx(const struct i915_gem_context *prev,
422 const struct i915_gem_context *next)
427 if (ctx_single_port_submission(prev))
433 static void execlists_dequeue(struct intel_engine_cs *engine)
435 struct drm_i915_gem_request *last;
436 struct execlist_port *port = engine->execlist_port;
441 last = port->request;
443 /* WaIdleLiteRestore:bdw,skl
444 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
445 * as we resubmit the request. See gen8_emit_breadcrumb()
446 * for where we prepare the padding after the end of the
449 last->tail = last->wa_tail;
451 GEM_BUG_ON(port[1].request);
453 /* Hardware submission is through 2 ports. Conceptually each port
454 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
455 * static for a context, and unique to each, so we only execute
456 * requests belonging to a single context from each ring. RING_HEAD
457 * is maintained by the CS in the context image, it marks the place
458 * where it got up to last time, and through RING_TAIL we tell the CS
459 * where we want to execute up to this time.
461 * In this list the requests are in order of execution. Consecutive
462 * requests from the same context are adjacent in the ringbuffer. We
463 * can combine these requests into a single RING_TAIL update:
465 * RING_HEAD...req1...req2
467 * since to execute req2 the CS must first execute req1.
469 * Our goal then is to point each port to the end of a consecutive
470 * sequence of requests as being the most optimal (fewest wake ups
471 * and context switches) submission.
474 spin_lock_irqsave(&engine->timeline->lock, flags);
475 rb = engine->execlist_first;
477 struct drm_i915_gem_request *cursor =
478 rb_entry(rb, typeof(*cursor), priotree.node);
480 /* Can we combine this request with the current port? It has to
481 * be the same context/ringbuffer and not have any exceptions
482 * (e.g. GVT saying never to combine contexts).
484 * If we can combine the requests, we can execute both by
485 * updating the RING_TAIL to point to the end of the second
486 * request, and so we never need to tell the hardware about
489 if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
490 /* If we are on the second port and cannot combine
491 * this request with the last, then we are done.
493 if (port != engine->execlist_port)
496 /* If GVT overrides us we only ever submit port[0],
497 * leaving port[1] empty. Note that we also have
498 * to be careful that we don't queue the same
499 * context (even though a different request) to
502 if (ctx_single_port_submission(last->ctx) ||
503 ctx_single_port_submission(cursor->ctx))
506 GEM_BUG_ON(last->ctx == cursor->ctx);
508 i915_gem_request_assign(&port->request, last);
513 rb_erase(&cursor->priotree.node, &engine->execlist_queue);
514 RB_CLEAR_NODE(&cursor->priotree.node);
515 cursor->priotree.priority = INT_MAX;
517 /* We keep the previous context alive until we retire the
518 * following request. This ensures that any the context object
519 * is still pinned for any residual writes the HW makes into it
520 * on the context switch into the next object following the
521 * breadcrumb. Otherwise, we may retire the context too early.
523 cursor->previous_context = engine->last_context;
524 engine->last_context = cursor->ctx;
526 __i915_gem_request_submit(cursor);
531 i915_gem_request_assign(&port->request, last);
532 engine->execlist_first = rb;
534 spin_unlock_irqrestore(&engine->timeline->lock, flags);
537 execlists_submit_ports(engine);
540 static bool execlists_elsp_idle(struct intel_engine_cs *engine)
542 return !engine->execlist_port[0].request;
546 * intel_execlists_idle() - Determine if all engine submission ports are idle
547 * @dev_priv: i915 device private
549 * Return true if there are no requests pending on any of the submission ports
552 bool intel_execlists_idle(struct drm_i915_private *dev_priv)
554 struct intel_engine_cs *engine;
555 enum intel_engine_id id;
557 if (!i915.enable_execlists)
560 for_each_engine(engine, dev_priv, id)
561 if (!execlists_elsp_idle(engine))
567 static bool execlists_elsp_ready(struct intel_engine_cs *engine)
571 port = 1; /* wait for a free slot */
572 if (engine->disable_lite_restore_wa || engine->preempt_wa)
573 port = 0; /* wait for GPU to be idle before continuing */
575 return !engine->execlist_port[port].request;
579 * Check the unread Context Status Buffers and manage the submission of new
580 * contexts to the ELSP accordingly.
582 static void intel_lrc_irq_handler(unsigned long data)
584 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
585 struct execlist_port *port = engine->execlist_port;
586 struct drm_i915_private *dev_priv = engine->i915;
588 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
590 if (!execlists_elsp_idle(engine)) {
591 u32 __iomem *csb_mmio =
592 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
594 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
595 unsigned int csb, head, tail;
597 csb = readl(csb_mmio);
598 head = GEN8_CSB_READ_PTR(csb);
599 tail = GEN8_CSB_WRITE_PTR(csb);
601 tail += GEN8_CSB_ENTRIES;
602 while (head < tail) {
603 unsigned int idx = ++head % GEN8_CSB_ENTRIES;
604 unsigned int status = readl(buf + 2 * idx);
606 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
609 GEM_BUG_ON(port[0].count == 0);
610 if (--port[0].count == 0) {
611 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
612 execlists_context_status_change(port[0].request,
613 INTEL_CONTEXT_SCHEDULE_OUT);
615 i915_gem_request_put(port[0].request);
617 memset(&port[1], 0, sizeof(port[1]));
619 engine->preempt_wa = false;
622 GEM_BUG_ON(port[0].count == 0 &&
623 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
626 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
627 GEN8_CSB_WRITE_PTR(csb) << 8),
631 if (execlists_elsp_ready(engine))
632 execlists_dequeue(engine);
634 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
637 static bool insert_request(struct i915_priotree *pt, struct rb_root *root)
639 struct rb_node **p, *rb;
642 /* most positive priority is scheduled first, equal priorities fifo */
646 struct i915_priotree *pos;
649 pos = rb_entry(rb, typeof(*pos), node);
650 if (pt->priority > pos->priority) {
657 rb_link_node(&pt->node, rb, p);
658 rb_insert_color(&pt->node, root);
663 static void execlists_submit_request(struct drm_i915_gem_request *request)
665 struct intel_engine_cs *engine = request->engine;
668 /* Will be called from irq-context when using foreign fences. */
669 spin_lock_irqsave(&engine->timeline->lock, flags);
671 if (insert_request(&request->priotree, &engine->execlist_queue))
672 engine->execlist_first = &request->priotree.node;
673 if (execlists_elsp_idle(engine))
674 tasklet_hi_schedule(&engine->irq_tasklet);
676 spin_unlock_irqrestore(&engine->timeline->lock, flags);
679 static struct intel_engine_cs *
680 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
682 struct intel_engine_cs *engine;
684 engine = container_of(pt,
685 struct drm_i915_gem_request,
687 if (engine != locked) {
689 spin_unlock_irq(&locked->timeline->lock);
690 spin_lock_irq(&engine->timeline->lock);
696 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
698 static DEFINE_MUTEX(lock);
699 struct intel_engine_cs *engine = NULL;
700 struct i915_dependency *dep, *p;
701 struct i915_dependency stack;
704 if (prio <= READ_ONCE(request->priotree.priority))
707 /* Need global lock to use the temporary link inside i915_dependency */
710 stack.signaler = &request->priotree;
711 list_add(&stack.dfs_link, &dfs);
713 /* Recursively bump all dependent priorities to match the new request.
715 * A naive approach would be to use recursion:
716 * static void update_priorities(struct i915_priotree *pt, prio) {
717 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
718 * update_priorities(dep->signal, prio)
719 * insert_request(pt);
721 * but that may have unlimited recursion depth and so runs a very
722 * real risk of overunning the kernel stack. Instead, we build
723 * a flat list of all dependencies starting with the current request.
724 * As we walk the list of dependencies, we add all of its dependencies
725 * to the end of the list (this may include an already visited
726 * request) and continue to walk onwards onto the new dependencies. The
727 * end result is a topological list of requests in reverse order, the
728 * last element in the list is the request we must execute first.
730 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
731 struct i915_priotree *pt = dep->signaler;
733 list_for_each_entry(p, &pt->signalers_list, signal_link)
734 if (prio > READ_ONCE(p->signaler->priority))
735 list_move_tail(&p->dfs_link, &dfs);
737 p = list_next_entry(dep, dfs_link);
738 if (!RB_EMPTY_NODE(&pt->node))
741 engine = pt_lock_engine(pt, engine);
743 /* If it is not already in the rbtree, we can update the
744 * priority inplace and skip over it (and its dependencies)
745 * if it is referenced *again* as we descend the dfs.
747 if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) {
749 list_del_init(&dep->dfs_link);
753 /* Fifo and depth-first replacement ensure our deps execute before us */
754 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
755 struct i915_priotree *pt = dep->signaler;
757 INIT_LIST_HEAD(&dep->dfs_link);
759 engine = pt_lock_engine(pt, engine);
761 if (prio <= pt->priority)
764 GEM_BUG_ON(RB_EMPTY_NODE(&pt->node));
767 rb_erase(&pt->node, &engine->execlist_queue);
768 if (insert_request(pt, &engine->execlist_queue))
769 engine->execlist_first = &pt->node;
773 spin_unlock_irq(&engine->timeline->lock);
777 /* XXX Do we need to preempt to make room for us and our deps? */
780 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
782 struct intel_engine_cs *engine = request->engine;
783 struct intel_context *ce = &request->ctx->engine[engine->id];
786 /* Flush enough space to reduce the likelihood of waiting after
787 * we start building the request - in which case we will just
788 * have to repeat work.
790 request->reserved_space += EXECLISTS_REQUEST_SIZE;
793 ret = execlists_context_deferred_alloc(request->ctx, engine);
798 request->ring = ce->ring;
800 ret = intel_lr_context_pin(request->ctx, engine);
804 if (i915.enable_guc_submission) {
806 * Check that the GuC has space for the request before
807 * going any further, as the i915_add_request() call
808 * later on mustn't fail ...
810 ret = i915_guc_wq_reserve(request);
815 ret = intel_ring_begin(request, 0);
819 if (!ce->initialised) {
820 ret = engine->init_context(request);
824 ce->initialised = true;
827 /* Note that after this point, we have committed to using
828 * this request as it is being used to both track the
829 * state of engine initialisation and liveness of the
830 * golden renderstate above. Think twice before you try
831 * to cancel/unwind this request now.
834 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
838 if (i915.enable_guc_submission)
839 i915_guc_wq_unreserve(request);
841 intel_lr_context_unpin(request->ctx, engine);
845 static int intel_lr_context_pin(struct i915_gem_context *ctx,
846 struct intel_engine_cs *engine)
848 struct intel_context *ce = &ctx->engine[engine->id];
852 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
857 ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN,
858 PIN_OFFSET_BIAS | GUC_WOPCM_TOP | PIN_GLOBAL);
862 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
864 ret = PTR_ERR(vaddr);
868 ret = intel_ring_pin(ce->ring);
872 intel_lr_context_descriptor_update(ctx, engine);
874 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
875 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
876 i915_ggtt_offset(ce->ring->vma);
878 ce->state->obj->mm.dirty = true;
880 /* Invalidate GuC TLB. */
881 if (i915.enable_guc_submission) {
882 struct drm_i915_private *dev_priv = ctx->i915;
883 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
886 i915_gem_context_get(ctx);
890 i915_gem_object_unpin_map(ce->state->obj);
892 __i915_vma_unpin(ce->state);
898 void intel_lr_context_unpin(struct i915_gem_context *ctx,
899 struct intel_engine_cs *engine)
901 struct intel_context *ce = &ctx->engine[engine->id];
903 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
904 GEM_BUG_ON(ce->pin_count == 0);
909 intel_ring_unpin(ce->ring);
911 i915_gem_object_unpin_map(ce->state->obj);
912 i915_vma_unpin(ce->state);
914 i915_gem_context_put(ctx);
917 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
920 struct intel_ring *ring = req->ring;
921 struct i915_workarounds *w = &req->i915->workarounds;
926 ret = req->engine->emit_flush(req, EMIT_BARRIER);
930 ret = intel_ring_begin(req, w->count * 2 + 2);
934 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
935 for (i = 0; i < w->count; i++) {
936 intel_ring_emit_reg(ring, w->reg[i].addr);
937 intel_ring_emit(ring, w->reg[i].value);
939 intel_ring_emit(ring, MI_NOOP);
941 intel_ring_advance(ring);
943 ret = req->engine->emit_flush(req, EMIT_BARRIER);
950 #define wa_ctx_emit(batch, index, cmd) \
952 int __index = (index)++; \
953 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
956 batch[__index] = (cmd); \
959 #define wa_ctx_emit_reg(batch, index, reg) \
960 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
963 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
964 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
965 * but there is a slight complication as this is applied in WA batch where the
966 * values are only initialized once so we cannot take register value at the
967 * beginning and reuse it further; hence we save its value to memory, upload a
968 * constant value with bit21 set and then we restore it back with the saved value.
969 * To simplify the WA, a constant value is formed by using the default value
970 * of this register. This shouldn't be a problem because we are only modifying
971 * it for a short period and this batch in non-premptible. We can ofcourse
972 * use additional instructions that read the actual value of the register
973 * at that time and set our bit of interest but it makes the WA complicated.
975 * This WA is also required for Gen9 so extracting as a function avoids
978 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
982 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
984 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
985 MI_SRM_LRM_GLOBAL_GTT));
986 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
987 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
988 wa_ctx_emit(batch, index, 0);
990 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
991 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
992 wa_ctx_emit(batch, index, l3sqc4_flush);
994 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
995 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
996 PIPE_CONTROL_DC_FLUSH_ENABLE));
997 wa_ctx_emit(batch, index, 0);
998 wa_ctx_emit(batch, index, 0);
999 wa_ctx_emit(batch, index, 0);
1000 wa_ctx_emit(batch, index, 0);
1002 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1003 MI_SRM_LRM_GLOBAL_GTT));
1004 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1005 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
1006 wa_ctx_emit(batch, index, 0);
1011 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1013 uint32_t start_alignment)
1015 return wa_ctx->offset = ALIGN(offset, start_alignment);
1018 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1020 uint32_t size_alignment)
1022 wa_ctx->size = offset - wa_ctx->offset;
1024 WARN(wa_ctx->size % size_alignment,
1025 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1026 wa_ctx->size, size_alignment);
1031 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1032 * initialized at the beginning and shared across all contexts but this field
1033 * helps us to have multiple batches at different offsets and select them based
1034 * on a criteria. At the moment this batch always start at the beginning of the page
1035 * and at this point we don't have multiple wa_ctx batch buffers.
1037 * The number of WA applied are not known at the beginning; we use this field
1038 * to return the no of DWORDS written.
1040 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1041 * so it adds NOOPs as padding to make it cacheline aligned.
1042 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1043 * makes a complete batch buffer.
1045 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1046 struct i915_wa_ctx_bb *wa_ctx,
1050 uint32_t scratch_addr;
1051 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1053 /* WaDisableCtxRestoreArbitration:bdw,chv */
1054 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1056 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1057 if (IS_BROADWELL(engine->i915)) {
1058 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1064 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1065 /* Actual scratch location is at 128 bytes offset */
1066 scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1068 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1069 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1070 PIPE_CONTROL_GLOBAL_GTT_IVB |
1071 PIPE_CONTROL_CS_STALL |
1072 PIPE_CONTROL_QW_WRITE));
1073 wa_ctx_emit(batch, index, scratch_addr);
1074 wa_ctx_emit(batch, index, 0);
1075 wa_ctx_emit(batch, index, 0);
1076 wa_ctx_emit(batch, index, 0);
1078 /* Pad to end of cacheline */
1079 while (index % CACHELINE_DWORDS)
1080 wa_ctx_emit(batch, index, MI_NOOP);
1083 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1084 * execution depends on the length specified in terms of cache lines
1085 * in the register CTX_RCS_INDIRECT_CTX
1088 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1092 * This batch is started immediately after indirect_ctx batch. Since we ensure
1093 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1095 * The number of DWORDS written are returned using this field.
1097 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1098 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1100 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1101 struct i915_wa_ctx_bb *wa_ctx,
1105 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1107 /* WaDisableCtxRestoreArbitration:bdw,chv */
1108 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1110 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1112 return wa_ctx_end(wa_ctx, *offset = index, 1);
1115 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1116 struct i915_wa_ctx_bb *wa_ctx,
1121 struct drm_i915_private *dev_priv = engine->i915;
1122 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1124 /* WaDisableCtxRestoreArbitration:bxt */
1125 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1126 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1128 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1129 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1134 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
1135 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1136 wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
1137 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
1138 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
1139 wa_ctx_emit(batch, index, MI_NOOP);
1141 /* WaClearSlmSpaceAtContextSwitch:kbl */
1142 /* Actual scratch location is at 128 bytes offset */
1143 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1145 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1147 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1148 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1149 PIPE_CONTROL_GLOBAL_GTT_IVB |
1150 PIPE_CONTROL_CS_STALL |
1151 PIPE_CONTROL_QW_WRITE));
1152 wa_ctx_emit(batch, index, scratch_addr);
1153 wa_ctx_emit(batch, index, 0);
1154 wa_ctx_emit(batch, index, 0);
1155 wa_ctx_emit(batch, index, 0);
1158 /* WaMediaPoolStateCmdInWABB:bxt */
1159 if (HAS_POOLED_EU(engine->i915)) {
1161 * EU pool configuration is setup along with golden context
1162 * during context initialization. This value depends on
1163 * device type (2x6 or 3x6) and needs to be updated based
1164 * on which subslice is disabled especially for 2x6
1165 * devices, however it is safe to load default
1166 * configuration of 3x6 device instead of masking off
1167 * corresponding bits because HW ignores bits of a disabled
1168 * subslice and drops down to appropriate config. Please
1169 * see render_state_setup() in i915_gem_render_state.c for
1170 * possible configurations, to avoid duplication they are
1171 * not shown here again.
1173 u32 eu_pool_config = 0x00777000;
1174 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
1175 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
1176 wa_ctx_emit(batch, index, eu_pool_config);
1177 wa_ctx_emit(batch, index, 0);
1178 wa_ctx_emit(batch, index, 0);
1179 wa_ctx_emit(batch, index, 0);
1182 /* Pad to end of cacheline */
1183 while (index % CACHELINE_DWORDS)
1184 wa_ctx_emit(batch, index, MI_NOOP);
1186 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1189 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1190 struct i915_wa_ctx_bb *wa_ctx,
1194 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1196 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
1197 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
1198 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1199 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1200 wa_ctx_emit(batch, index,
1201 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1202 wa_ctx_emit(batch, index, MI_NOOP);
1205 /* WaClearTdlStateAckDirtyBits:bxt */
1206 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
1207 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
1209 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
1210 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1212 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
1213 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1215 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
1216 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1218 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
1219 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1220 wa_ctx_emit(batch, index, 0x0);
1221 wa_ctx_emit(batch, index, MI_NOOP);
1224 /* WaDisableCtxRestoreArbitration:bxt */
1225 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1226 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1228 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1230 return wa_ctx_end(wa_ctx, *offset = index, 1);
1233 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1235 struct drm_i915_gem_object *obj;
1236 struct i915_vma *vma;
1239 obj = i915_gem_object_create(&engine->i915->drm, PAGE_ALIGN(size));
1241 return PTR_ERR(obj);
1243 vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
1249 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1253 engine->wa_ctx.vma = vma;
1257 i915_gem_object_put(obj);
1261 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1263 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1266 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1268 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1274 WARN_ON(engine->id != RCS);
1276 /* update this when WA for higher Gen are added */
1277 if (INTEL_GEN(engine->i915) > 9) {
1278 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1279 INTEL_GEN(engine->i915));
1283 /* some WA perform writes to scratch page, ensure it is valid */
1284 if (!engine->scratch) {
1285 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1289 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1291 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1295 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1296 batch = kmap_atomic(page);
1299 if (IS_GEN8(engine->i915)) {
1300 ret = gen8_init_indirectctx_bb(engine,
1301 &wa_ctx->indirect_ctx,
1307 ret = gen8_init_perctx_bb(engine,
1313 } else if (IS_GEN9(engine->i915)) {
1314 ret = gen9_init_indirectctx_bb(engine,
1315 &wa_ctx->indirect_ctx,
1321 ret = gen9_init_perctx_bb(engine,
1330 kunmap_atomic(batch);
1332 lrc_destroy_wa_ctx_obj(engine);
1337 static void lrc_init_hws(struct intel_engine_cs *engine)
1339 struct drm_i915_private *dev_priv = engine->i915;
1341 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1342 engine->status_page.ggtt_offset);
1343 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1346 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1348 struct drm_i915_private *dev_priv = engine->i915;
1351 ret = intel_mocs_init_engine(engine);
1355 lrc_init_hws(engine);
1357 intel_engine_reset_breadcrumbs(engine);
1359 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1361 I915_WRITE(RING_MODE_GEN7(engine),
1362 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1363 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1365 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1367 intel_engine_init_hangcheck(engine);
1369 /* After a GPU reset, we may have requests to replay */
1370 if (!execlists_elsp_idle(engine)) {
1371 engine->execlist_port[0].count = 0;
1372 engine->execlist_port[1].count = 0;
1373 execlists_submit_ports(engine);
1379 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1381 struct drm_i915_private *dev_priv = engine->i915;
1384 ret = gen8_init_common_ring(engine);
1388 /* We need to disable the AsyncFlip performance optimisations in order
1389 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1390 * programmed to '1' on all products.
1392 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1394 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1396 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1398 return init_workarounds_ring(engine);
1401 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1405 ret = gen8_init_common_ring(engine);
1409 return init_workarounds_ring(engine);
1412 static void reset_common_ring(struct intel_engine_cs *engine,
1413 struct drm_i915_gem_request *request)
1415 struct drm_i915_private *dev_priv = engine->i915;
1416 struct execlist_port *port = engine->execlist_port;
1417 struct intel_context *ce = &request->ctx->engine[engine->id];
1419 /* We want a simple context + ring to execute the breadcrumb update.
1420 * We cannot rely on the context being intact across the GPU hang,
1421 * so clear it and rebuild just what we need for the breadcrumb.
1422 * All pending requests for this context will be zapped, and any
1423 * future request will be after userspace has had the opportunity
1424 * to recreate its own state.
1426 execlists_init_reg_state(ce->lrc_reg_state,
1427 request->ctx, engine, ce->ring);
1429 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1430 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1431 i915_ggtt_offset(ce->ring->vma);
1432 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1434 request->ring->head = request->postfix;
1435 request->ring->last_retired_head = -1;
1436 intel_ring_update_space(request->ring);
1438 if (i915.enable_guc_submission)
1441 /* Catch up with any missed context-switch interrupts */
1442 I915_WRITE(RING_CONTEXT_STATUS_PTR(engine), _MASKED_FIELD(0xffff, 0));
1443 if (request->ctx != port[0].request->ctx) {
1444 i915_gem_request_put(port[0].request);
1446 memset(&port[1], 0, sizeof(port[1]));
1449 GEM_BUG_ON(request->ctx != port[0].request->ctx);
1451 /* Reset WaIdleLiteRestore:bdw,skl as well */
1452 request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
1455 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1457 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1458 struct intel_ring *ring = req->ring;
1459 struct intel_engine_cs *engine = req->engine;
1460 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1463 ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1467 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1468 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1469 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1471 intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i));
1472 intel_ring_emit(ring, upper_32_bits(pd_daddr));
1473 intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i));
1474 intel_ring_emit(ring, lower_32_bits(pd_daddr));
1477 intel_ring_emit(ring, MI_NOOP);
1478 intel_ring_advance(ring);
1483 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1484 u64 offset, u32 len,
1485 unsigned int dispatch_flags)
1487 struct intel_ring *ring = req->ring;
1488 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1491 /* Don't rely in hw updating PDPs, specially in lite-restore.
1492 * Ideally, we should set Force PD Restore in ctx descriptor,
1493 * but we can't. Force Restore would be a second option, but
1494 * it is unsafe in case of lite-restore (because the ctx is
1495 * not idle). PML4 is allocated during ppgtt init so this is
1496 * not needed in 48-bit.*/
1497 if (req->ctx->ppgtt &&
1498 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1499 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1500 !intel_vgpu_active(req->i915)) {
1501 ret = intel_logical_ring_emit_pdps(req);
1506 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1509 ret = intel_ring_begin(req, 4);
1513 /* FIXME(BDW): Address space and security selectors. */
1514 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
1516 (dispatch_flags & I915_DISPATCH_RS ?
1517 MI_BATCH_RESOURCE_STREAMER : 0));
1518 intel_ring_emit(ring, lower_32_bits(offset));
1519 intel_ring_emit(ring, upper_32_bits(offset));
1520 intel_ring_emit(ring, MI_NOOP);
1521 intel_ring_advance(ring);
1526 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1528 struct drm_i915_private *dev_priv = engine->i915;
1529 I915_WRITE_IMR(engine,
1530 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1531 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1534 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1536 struct drm_i915_private *dev_priv = engine->i915;
1537 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1540 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1542 struct intel_ring *ring = request->ring;
1546 ret = intel_ring_begin(request, 4);
1550 cmd = MI_FLUSH_DW + 1;
1552 /* We always require a command barrier so that subsequent
1553 * commands, such as breadcrumb interrupts, are strictly ordered
1554 * wrt the contents of the write cache being flushed to memory
1555 * (and thus being coherent from the CPU).
1557 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1559 if (mode & EMIT_INVALIDATE) {
1560 cmd |= MI_INVALIDATE_TLB;
1561 if (request->engine->id == VCS)
1562 cmd |= MI_INVALIDATE_BSD;
1565 intel_ring_emit(ring, cmd);
1566 intel_ring_emit(ring,
1567 I915_GEM_HWS_SCRATCH_ADDR |
1568 MI_FLUSH_DW_USE_GTT);
1569 intel_ring_emit(ring, 0); /* upper addr */
1570 intel_ring_emit(ring, 0); /* value */
1571 intel_ring_advance(ring);
1576 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1579 struct intel_ring *ring = request->ring;
1580 struct intel_engine_cs *engine = request->engine;
1582 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1583 bool vf_flush_wa = false, dc_flush_wa = false;
1588 flags |= PIPE_CONTROL_CS_STALL;
1590 if (mode & EMIT_FLUSH) {
1591 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1592 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1593 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1594 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1597 if (mode & EMIT_INVALIDATE) {
1598 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1599 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1600 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1601 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1602 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1603 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1604 flags |= PIPE_CONTROL_QW_WRITE;
1605 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1608 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1611 if (IS_GEN9(request->i915))
1614 /* WaForGAMHang:kbl */
1615 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1627 ret = intel_ring_begin(request, len);
1632 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1633 intel_ring_emit(ring, 0);
1634 intel_ring_emit(ring, 0);
1635 intel_ring_emit(ring, 0);
1636 intel_ring_emit(ring, 0);
1637 intel_ring_emit(ring, 0);
1641 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1642 intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE);
1643 intel_ring_emit(ring, 0);
1644 intel_ring_emit(ring, 0);
1645 intel_ring_emit(ring, 0);
1646 intel_ring_emit(ring, 0);
1649 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1650 intel_ring_emit(ring, flags);
1651 intel_ring_emit(ring, scratch_addr);
1652 intel_ring_emit(ring, 0);
1653 intel_ring_emit(ring, 0);
1654 intel_ring_emit(ring, 0);
1657 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1658 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL);
1659 intel_ring_emit(ring, 0);
1660 intel_ring_emit(ring, 0);
1661 intel_ring_emit(ring, 0);
1662 intel_ring_emit(ring, 0);
1665 intel_ring_advance(ring);
1670 static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1673 * On BXT A steppings there is a HW coherency issue whereby the
1674 * MI_STORE_DATA_IMM storing the completed request's seqno
1675 * occasionally doesn't invalidate the CPU cache. Work around this by
1676 * clflushing the corresponding cacheline whenever the caller wants
1677 * the coherency to be guaranteed. Note that this cacheline is known
1678 * to be clean at this point, since we only write it in
1679 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1680 * this clflush in practice becomes an invalidate operation.
1682 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1686 * Reserve space for 2 NOOPs at the end of each request to be
1687 * used as a workaround for not being allowed to do lite
1688 * restore with HEAD==TAIL (WaIdleLiteRestore).
1690 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *out)
1694 request->wa_tail = intel_ring_offset(request->ring, out);
1697 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request,
1700 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1701 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1703 *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1704 *out++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
1706 *out++ = request->global_seqno;
1707 *out++ = MI_USER_INTERRUPT;
1709 request->tail = intel_ring_offset(request->ring, out);
1711 gen8_emit_wa_tail(request, out);
1714 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1716 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
1719 /* We're using qword write, seqno should be aligned to 8 bytes. */
1720 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1722 /* w/a for post sync ops following a GPGPU operation we
1723 * need a prior CS_STALL, which is emitted by the flush
1724 * following the batch.
1726 *out++ = GFX_OP_PIPE_CONTROL(6);
1727 *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB |
1728 PIPE_CONTROL_CS_STALL |
1729 PIPE_CONTROL_QW_WRITE);
1730 *out++ = intel_hws_seqno_address(request->engine);
1732 *out++ = request->global_seqno;
1733 /* We're thrashing one dword of HWS. */
1735 *out++ = MI_USER_INTERRUPT;
1737 request->tail = intel_ring_offset(request->ring, out);
1739 gen8_emit_wa_tail(request, out);
1742 static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
1744 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1748 ret = intel_logical_ring_workarounds_emit(req);
1752 ret = intel_rcs_context_init_mocs(req);
1754 * Failing to program the MOCS is non-fatal.The system will not
1755 * run at peak performance. So generate an error and carry on.
1758 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1760 return i915_gem_render_state_emit(req);
1764 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1765 * @engine: Engine Command Streamer.
1767 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1769 struct drm_i915_private *dev_priv;
1772 * Tasklet cannot be active at this point due intel_mark_active/idle
1773 * so this is just for documentation.
1775 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1776 tasklet_kill(&engine->irq_tasklet);
1778 dev_priv = engine->i915;
1780 if (engine->buffer) {
1781 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1784 if (engine->cleanup)
1785 engine->cleanup(engine);
1787 intel_engine_cleanup_common(engine);
1789 if (engine->status_page.vma) {
1790 i915_gem_object_unpin_map(engine->status_page.vma->obj);
1791 engine->status_page.vma = NULL;
1793 intel_lr_context_unpin(dev_priv->kernel_context, engine);
1795 lrc_destroy_wa_ctx_obj(engine);
1796 engine->i915 = NULL;
1797 dev_priv->engine[engine->id] = NULL;
1801 void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
1803 struct intel_engine_cs *engine;
1804 enum intel_engine_id id;
1806 for_each_engine(engine, dev_priv, id) {
1807 engine->submit_request = execlists_submit_request;
1808 engine->schedule = execlists_schedule;
1813 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1815 /* Default vfuncs which can be overriden by each engine. */
1816 engine->init_hw = gen8_init_common_ring;
1817 engine->reset_hw = reset_common_ring;
1818 engine->emit_flush = gen8_emit_flush;
1819 engine->emit_breadcrumb = gen8_emit_breadcrumb;
1820 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1821 engine->submit_request = execlists_submit_request;
1822 engine->schedule = execlists_schedule;
1824 engine->irq_enable = gen8_logical_ring_enable_irq;
1825 engine->irq_disable = gen8_logical_ring_disable_irq;
1826 engine->emit_bb_start = gen8_emit_bb_start;
1827 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1828 engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1832 logical_ring_default_irqs(struct intel_engine_cs *engine)
1834 unsigned shift = engine->irq_shift;
1835 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1836 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1840 lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1842 const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1845 /* The HWSP is part of the default context object in LRC mode. */
1846 hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1848 return PTR_ERR(hws);
1850 engine->status_page.page_addr = hws + hws_offset;
1851 engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
1852 engine->status_page.vma = vma;
1858 logical_ring_setup(struct intel_engine_cs *engine)
1860 struct drm_i915_private *dev_priv = engine->i915;
1861 enum forcewake_domains fw_domains;
1863 intel_engine_setup_common(engine);
1865 /* Intentionally left blank. */
1866 engine->buffer = NULL;
1868 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1872 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1873 RING_CONTEXT_STATUS_PTR(engine),
1874 FW_REG_READ | FW_REG_WRITE);
1876 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1877 RING_CONTEXT_STATUS_BUF_BASE(engine),
1880 engine->fw_domains = fw_domains;
1882 tasklet_init(&engine->irq_tasklet,
1883 intel_lrc_irq_handler, (unsigned long)engine);
1885 logical_ring_init_platform_invariants(engine);
1886 logical_ring_default_vfuncs(engine);
1887 logical_ring_default_irqs(engine);
1891 logical_ring_init(struct intel_engine_cs *engine)
1893 struct i915_gem_context *dctx = engine->i915->kernel_context;
1896 ret = intel_engine_init_common(engine);
1900 ret = execlists_context_deferred_alloc(dctx, engine);
1904 /* As this is the default context, always pin it */
1905 ret = intel_lr_context_pin(dctx, engine);
1907 DRM_ERROR("Failed to pin context for %s: %d\n",
1912 /* And setup the hardware status page. */
1913 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1915 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1922 intel_logical_ring_cleanup(engine);
1926 int logical_render_ring_init(struct intel_engine_cs *engine)
1928 struct drm_i915_private *dev_priv = engine->i915;
1931 logical_ring_setup(engine);
1933 if (HAS_L3_DPF(dev_priv))
1934 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1936 /* Override some for render ring. */
1937 if (INTEL_GEN(dev_priv) >= 9)
1938 engine->init_hw = gen9_init_render_ring;
1940 engine->init_hw = gen8_init_render_ring;
1941 engine->init_context = gen8_init_rcs_context;
1942 engine->emit_flush = gen8_emit_flush_render;
1943 engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
1944 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
1946 ret = intel_engine_create_scratch(engine, 4096);
1950 ret = intel_init_workaround_bb(engine);
1953 * We continue even if we fail to initialize WA batch
1954 * because we only expect rare glitches but nothing
1955 * critical to prevent us from using GPU
1957 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1961 return logical_ring_init(engine);
1964 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1966 logical_ring_setup(engine);
1968 return logical_ring_init(engine);
1972 make_rpcs(struct drm_i915_private *dev_priv)
1977 * No explicit RPCS request is needed to ensure full
1978 * slice/subslice/EU enablement prior to Gen9.
1980 if (INTEL_GEN(dev_priv) < 9)
1984 * Starting in Gen9, render power gating can leave
1985 * slice/subslice/EU in a partially enabled state. We
1986 * must make an explicit request through RPCS for full
1989 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
1990 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1991 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
1992 GEN8_RPCS_S_CNT_SHIFT;
1993 rpcs |= GEN8_RPCS_ENABLE;
1996 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
1997 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1998 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
1999 GEN8_RPCS_SS_CNT_SHIFT;
2000 rpcs |= GEN8_RPCS_ENABLE;
2003 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2004 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2005 GEN8_RPCS_EU_MIN_SHIFT;
2006 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2007 GEN8_RPCS_EU_MAX_SHIFT;
2008 rpcs |= GEN8_RPCS_ENABLE;
2014 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2016 u32 indirect_ctx_offset;
2018 switch (INTEL_GEN(engine->i915)) {
2020 MISSING_CASE(INTEL_GEN(engine->i915));
2023 indirect_ctx_offset =
2024 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2027 indirect_ctx_offset =
2028 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2032 return indirect_ctx_offset;
2035 static void execlists_init_reg_state(u32 *reg_state,
2036 struct i915_gem_context *ctx,
2037 struct intel_engine_cs *engine,
2038 struct intel_ring *ring)
2040 struct drm_i915_private *dev_priv = engine->i915;
2041 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2043 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2044 * commands followed by (reg, value) pairs. The values we are setting here are
2045 * only for the first context restore: on a subsequent save, the GPU will
2046 * recreate this batchbuffer with new values (including all the missing
2047 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2048 reg_state[CTX_LRI_HEADER_0] =
2049 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2050 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2051 RING_CONTEXT_CONTROL(engine),
2052 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2053 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2054 (HAS_RESOURCE_STREAMER(dev_priv) ?
2055 CTX_CTRL_RS_CTX_ENABLE : 0)));
2056 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2058 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2060 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2061 RING_START(engine->mmio_base), 0);
2062 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2063 RING_CTL(engine->mmio_base),
2064 RING_CTL_SIZE(ring->size) | RING_VALID);
2065 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2066 RING_BBADDR_UDW(engine->mmio_base), 0);
2067 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2068 RING_BBADDR(engine->mmio_base), 0);
2069 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2070 RING_BBSTATE(engine->mmio_base),
2072 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2073 RING_SBBADDR_UDW(engine->mmio_base), 0);
2074 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2075 RING_SBBADDR(engine->mmio_base), 0);
2076 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2077 RING_SBBSTATE(engine->mmio_base), 0);
2078 if (engine->id == RCS) {
2079 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2080 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2081 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2082 RING_INDIRECT_CTX(engine->mmio_base), 0);
2083 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2084 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2085 if (engine->wa_ctx.vma) {
2086 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2087 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2089 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2090 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2091 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2093 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2094 intel_lr_indirect_ctx_offset(engine) << 6;
2096 reg_state[CTX_BB_PER_CTX_PTR+1] =
2097 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2101 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2102 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2103 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2104 /* PDP values well be assigned later if needed */
2105 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2107 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2109 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2111 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2113 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2115 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2117 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2119 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2122 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2123 /* 64b PPGTT (48bit canonical)
2124 * PDP0_DESCRIPTOR contains the base address to PML4 and
2125 * other PDP Descriptors are ignored.
2127 ASSIGN_CTX_PML4(ppgtt, reg_state);
2130 * PDP*_DESCRIPTOR contains the base address of space supported.
2131 * With dynamic page allocation, PDPs may not be allocated at
2132 * this point. Point the unallocated PDPs to the scratch page
2134 execlists_update_context_pdps(ppgtt, reg_state);
2137 if (engine->id == RCS) {
2138 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2139 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2140 make_rpcs(dev_priv));
2145 populate_lr_context(struct i915_gem_context *ctx,
2146 struct drm_i915_gem_object *ctx_obj,
2147 struct intel_engine_cs *engine,
2148 struct intel_ring *ring)
2153 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2155 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2159 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2160 if (IS_ERR(vaddr)) {
2161 ret = PTR_ERR(vaddr);
2162 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2165 ctx_obj->mm.dirty = true;
2167 /* The second page of the context object contains some fields which must
2168 * be set up prior to the first execution. */
2170 execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
2173 i915_gem_object_unpin_map(ctx_obj);
2179 * intel_lr_context_size() - return the size of the context for an engine
2180 * @engine: which engine to find the context size for
2182 * Each engine may require a different amount of space for a context image,
2183 * so when allocating (or copying) an image, this function can be used to
2184 * find the right size for the specific engine.
2186 * Return: size (in bytes) of an engine-specific context image
2188 * Note: this size includes the HWSP, which is part of the context image
2189 * in LRC mode, but does not include the "shared data page" used with
2190 * GuC submission. The caller should account for this if using the GuC.
2192 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2196 WARN_ON(INTEL_GEN(engine->i915) < 8);
2198 switch (engine->id) {
2200 if (INTEL_GEN(engine->i915) >= 9)
2201 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2203 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2209 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2216 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2217 struct intel_engine_cs *engine)
2219 struct drm_i915_gem_object *ctx_obj;
2220 struct intel_context *ce = &ctx->engine[engine->id];
2221 struct i915_vma *vma;
2222 uint32_t context_size;
2223 struct intel_ring *ring;
2228 context_size = round_up(intel_lr_context_size(engine), 4096);
2230 /* One extra page as the sharing data between driver and GuC */
2231 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2233 ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size);
2234 if (IS_ERR(ctx_obj)) {
2235 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2236 return PTR_ERR(ctx_obj);
2239 vma = i915_vma_create(ctx_obj, &ctx->i915->ggtt.base, NULL);
2242 goto error_deref_obj;
2245 ring = intel_engine_create_ring(engine, ctx->ring_size);
2247 ret = PTR_ERR(ring);
2248 goto error_deref_obj;
2251 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2253 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2254 goto error_ring_free;
2259 ce->initialised = engine->init_context == NULL;
2264 intel_ring_free(ring);
2266 i915_gem_object_put(ctx_obj);
2270 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2272 struct intel_engine_cs *engine;
2273 struct i915_gem_context *ctx;
2274 enum intel_engine_id id;
2276 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2277 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2278 * that stored in context. As we only write new commands from
2279 * ce->ring->tail onwards, everything before that is junk. If the GPU
2280 * starts reading from its RING_HEAD from the context, it may try to
2281 * execute that junk and die.
2283 * So to avoid that we reset the context images upon resume. For
2284 * simplicity, we just zero everything out.
2286 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2287 for_each_engine(engine, dev_priv, id) {
2288 struct intel_context *ce = &ctx->engine[engine->id];
2294 reg = i915_gem_object_pin_map(ce->state->obj,
2296 if (WARN_ON(IS_ERR(reg)))
2299 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2300 reg[CTX_RING_HEAD+1] = 0;
2301 reg[CTX_RING_TAIL+1] = 0;
2303 ce->state->obj->mm.dirty = true;
2304 i915_gem_object_unpin_map(ce->state->obj);
2306 ce->ring->head = ce->ring->tail = 0;
2307 ce->ring->last_retired_head = -1;
2308 intel_ring_update_space(ce->ring);