2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
161 GEN8_CTX_STATUS_PREEMPTED | \
162 GEN8_CTX_STATUS_ELEMENT_SWITCH)
164 #define CTX_LRI_HEADER_0 0x01
165 #define CTX_CONTEXT_CONTROL 0x02
166 #define CTX_RING_HEAD 0x04
167 #define CTX_RING_TAIL 0x06
168 #define CTX_RING_BUFFER_START 0x08
169 #define CTX_RING_BUFFER_CONTROL 0x0a
170 #define CTX_BB_HEAD_U 0x0c
171 #define CTX_BB_HEAD_L 0x0e
172 #define CTX_BB_STATE 0x10
173 #define CTX_SECOND_BB_HEAD_U 0x12
174 #define CTX_SECOND_BB_HEAD_L 0x14
175 #define CTX_SECOND_BB_STATE 0x16
176 #define CTX_BB_PER_CTX_PTR 0x18
177 #define CTX_RCS_INDIRECT_CTX 0x1a
178 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
179 #define CTX_LRI_HEADER_1 0x21
180 #define CTX_CTX_TIMESTAMP 0x22
181 #define CTX_PDP3_UDW 0x24
182 #define CTX_PDP3_LDW 0x26
183 #define CTX_PDP2_UDW 0x28
184 #define CTX_PDP2_LDW 0x2a
185 #define CTX_PDP1_UDW 0x2c
186 #define CTX_PDP1_LDW 0x2e
187 #define CTX_PDP0_UDW 0x30
188 #define CTX_PDP0_LDW 0x32
189 #define CTX_LRI_HEADER_2 0x41
190 #define CTX_R_PWR_CLK_STATE 0x42
191 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
193 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
194 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 (reg_state)[(pos)+1] = (val); \
198 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
199 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
200 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
201 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
204 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
206 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
209 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
210 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
212 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
213 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
215 #define WA_TAIL_DWORDS 2
217 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
218 struct intel_engine_cs *engine);
219 static void execlists_init_reg_state(u32 *reg_state,
220 struct i915_gem_context *ctx,
221 struct intel_engine_cs *engine,
222 struct intel_ring *ring);
225 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
226 * @dev_priv: i915 device private
227 * @enable_execlists: value of i915.enable_execlists module parameter.
229 * Only certain platforms support Execlists (the prerequisites being
230 * support for Logical Ring Contexts and Aliasing PPGTT or better).
232 * Return: 1 if Execlists is supported and has to be enabled.
234 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
236 /* On platforms with execlist available, vGPU will only
237 * support execlist mode, no ring buffer mode.
239 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
242 if (INTEL_GEN(dev_priv) >= 9)
245 if (enable_execlists == 0)
248 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
249 USES_PPGTT(dev_priv) &&
250 i915.use_mmio_flip >= 0)
257 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
258 * descriptor for a pinned context
259 * @ctx: Context to work on
260 * @engine: Engine the descriptor will be used with
262 * The context descriptor encodes various attributes of a context,
263 * including its GTT address and some flags. Because it's fairly
264 * expensive to calculate, we'll just do it once and cache the result,
265 * which remains valid until the context is unpinned.
267 * This is what a descriptor looks like, from LSB to MSB::
269 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
270 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
271 * bits 32-52: ctx ID, a globally unique tag
272 * bits 53-54: mbz, reserved for use by hardware
273 * bits 55-63: group ID, currently unused and set to 0
276 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
277 struct intel_engine_cs *engine)
279 struct intel_context *ce = &ctx->engine[engine->id];
282 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
284 desc = ctx->desc_template; /* bits 0-11 */
285 desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
287 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
292 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
293 struct intel_engine_cs *engine)
295 return ctx->engine[engine->id].lrc_desc;
299 execlists_context_status_change(struct drm_i915_gem_request *rq,
300 unsigned long status)
303 * Only used when GVT-g is enabled now. When GVT-g is disabled,
304 * The compiler should eliminate this function as dead-code.
306 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
309 atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
313 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
315 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
316 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
317 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
318 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
321 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
323 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
324 struct i915_hw_ppgtt *ppgtt =
325 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
326 u32 *reg_state = ce->lrc_reg_state;
328 GEM_BUG_ON(!IS_ALIGNED(rq->tail, 8));
329 reg_state[CTX_RING_TAIL+1] = rq->tail;
331 /* True 32b PPGTT with dynamic page allocation: update PDP
332 * registers and point the unallocated PDPs to scratch page.
333 * PML4 is allocated during ppgtt init, so this is not needed
336 if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
337 execlists_update_context_pdps(ppgtt, reg_state);
342 static void execlists_submit_ports(struct intel_engine_cs *engine)
344 struct drm_i915_private *dev_priv = engine->i915;
345 struct execlist_port *port = engine->execlist_port;
347 dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
350 GEM_BUG_ON(port[0].count > 1);
352 execlists_context_status_change(port[0].request,
353 INTEL_CONTEXT_SCHEDULE_IN);
354 desc[0] = execlists_update_context(port[0].request);
355 GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
358 if (port[1].request) {
359 GEM_BUG_ON(port[1].count);
360 execlists_context_status_change(port[1].request,
361 INTEL_CONTEXT_SCHEDULE_IN);
362 desc[1] = execlists_update_context(port[1].request);
363 GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
368 GEM_BUG_ON(desc[0] == desc[1]);
370 /* You must always write both descriptors in the order below. */
371 writel(upper_32_bits(desc[1]), elsp);
372 writel(lower_32_bits(desc[1]), elsp);
374 writel(upper_32_bits(desc[0]), elsp);
375 /* The context is automatically loaded after the following */
376 writel(lower_32_bits(desc[0]), elsp);
379 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
381 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
382 i915_gem_context_force_single_submission(ctx));
385 static bool can_merge_ctx(const struct i915_gem_context *prev,
386 const struct i915_gem_context *next)
391 if (ctx_single_port_submission(prev))
397 static void execlists_dequeue(struct intel_engine_cs *engine)
399 struct drm_i915_gem_request *last;
400 struct execlist_port *port = engine->execlist_port;
405 last = port->request;
407 /* WaIdleLiteRestore:bdw,skl
408 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
409 * as we resubmit the request. See gen8_emit_breadcrumb()
410 * for where we prepare the padding after the end of the
413 last->tail = last->wa_tail;
415 GEM_BUG_ON(port[1].request);
417 /* Hardware submission is through 2 ports. Conceptually each port
418 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
419 * static for a context, and unique to each, so we only execute
420 * requests belonging to a single context from each ring. RING_HEAD
421 * is maintained by the CS in the context image, it marks the place
422 * where it got up to last time, and through RING_TAIL we tell the CS
423 * where we want to execute up to this time.
425 * In this list the requests are in order of execution. Consecutive
426 * requests from the same context are adjacent in the ringbuffer. We
427 * can combine these requests into a single RING_TAIL update:
429 * RING_HEAD...req1...req2
431 * since to execute req2 the CS must first execute req1.
433 * Our goal then is to point each port to the end of a consecutive
434 * sequence of requests as being the most optimal (fewest wake ups
435 * and context switches) submission.
438 spin_lock_irqsave(&engine->timeline->lock, flags);
439 rb = engine->execlist_first;
441 struct drm_i915_gem_request *cursor =
442 rb_entry(rb, typeof(*cursor), priotree.node);
444 /* Can we combine this request with the current port? It has to
445 * be the same context/ringbuffer and not have any exceptions
446 * (e.g. GVT saying never to combine contexts).
448 * If we can combine the requests, we can execute both by
449 * updating the RING_TAIL to point to the end of the second
450 * request, and so we never need to tell the hardware about
453 if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
454 /* If we are on the second port and cannot combine
455 * this request with the last, then we are done.
457 if (port != engine->execlist_port)
460 /* If GVT overrides us we only ever submit port[0],
461 * leaving port[1] empty. Note that we also have
462 * to be careful that we don't queue the same
463 * context (even though a different request) to
466 if (ctx_single_port_submission(last->ctx) ||
467 ctx_single_port_submission(cursor->ctx))
470 GEM_BUG_ON(last->ctx == cursor->ctx);
472 i915_gem_request_assign(&port->request, last);
477 rb_erase(&cursor->priotree.node, &engine->execlist_queue);
478 RB_CLEAR_NODE(&cursor->priotree.node);
479 cursor->priotree.priority = INT_MAX;
481 __i915_gem_request_submit(cursor);
486 i915_gem_request_assign(&port->request, last);
487 engine->execlist_first = rb;
489 spin_unlock_irqrestore(&engine->timeline->lock, flags);
492 execlists_submit_ports(engine);
495 static bool execlists_elsp_idle(struct intel_engine_cs *engine)
497 return !engine->execlist_port[0].request;
501 * intel_execlists_idle() - Determine if all engine submission ports are idle
502 * @dev_priv: i915 device private
504 * Return true if there are no requests pending on any of the submission ports
507 bool intel_execlists_idle(struct drm_i915_private *dev_priv)
509 struct intel_engine_cs *engine;
510 enum intel_engine_id id;
512 if (!i915.enable_execlists)
515 for_each_engine(engine, dev_priv, id) {
516 /* Interrupt/tasklet pending? */
517 if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted))
520 /* Both ports drained, no more ELSP submission? */
521 if (!execlists_elsp_idle(engine))
528 static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
530 const struct execlist_port *port = engine->execlist_port;
532 return port[0].count + port[1].count < 2;
536 * Check the unread Context Status Buffers and manage the submission of new
537 * contexts to the ELSP accordingly.
539 static void intel_lrc_irq_handler(unsigned long data)
541 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
542 struct execlist_port *port = engine->execlist_port;
543 struct drm_i915_private *dev_priv = engine->i915;
545 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
547 while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
548 u32 __iomem *csb_mmio =
549 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
551 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
552 unsigned int csb, head, tail;
554 csb = readl(csb_mmio);
555 head = GEN8_CSB_READ_PTR(csb);
556 tail = GEN8_CSB_WRITE_PTR(csb);
561 tail += GEN8_CSB_ENTRIES;
563 unsigned int idx = ++head % GEN8_CSB_ENTRIES;
564 unsigned int status = readl(buf + 2 * idx);
566 /* We are flying near dragons again.
568 * We hold a reference to the request in execlist_port[]
569 * but no more than that. We are operating in softirq
570 * context and so cannot hold any mutex or sleep. That
571 * prevents us stopping the requests we are processing
572 * in port[] from being retired simultaneously (the
573 * breadcrumb will be complete before we see the
574 * context-switch). As we only hold the reference to the
575 * request, any pointer chasing underneath the request
576 * is subject to a potential use-after-free. Thus we
577 * store all of the bookkeeping within port[] as
578 * required, and avoid using unguarded pointers beneath
579 * request itself. The same applies to the atomic
583 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
586 /* Check the context/desc id for this event matches */
587 GEM_DEBUG_BUG_ON(readl(buf + 2 * idx + 1) !=
590 GEM_BUG_ON(port[0].count == 0);
591 if (--port[0].count == 0) {
592 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
593 execlists_context_status_change(port[0].request,
594 INTEL_CONTEXT_SCHEDULE_OUT);
596 i915_gem_request_put(port[0].request);
598 memset(&port[1], 0, sizeof(port[1]));
601 GEM_BUG_ON(port[0].count == 0 &&
602 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
603 } while (head < tail);
605 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
606 GEN8_CSB_WRITE_PTR(csb) << 8),
610 if (execlists_elsp_ready(engine))
611 execlists_dequeue(engine);
613 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
616 static bool insert_request(struct i915_priotree *pt, struct rb_root *root)
618 struct rb_node **p, *rb;
621 /* most positive priority is scheduled first, equal priorities fifo */
625 struct i915_priotree *pos;
628 pos = rb_entry(rb, typeof(*pos), node);
629 if (pt->priority > pos->priority) {
636 rb_link_node(&pt->node, rb, p);
637 rb_insert_color(&pt->node, root);
642 static void execlists_submit_request(struct drm_i915_gem_request *request)
644 struct intel_engine_cs *engine = request->engine;
647 /* Will be called from irq-context when using foreign fences. */
648 spin_lock_irqsave(&engine->timeline->lock, flags);
650 if (insert_request(&request->priotree, &engine->execlist_queue)) {
651 engine->execlist_first = &request->priotree.node;
652 if (execlists_elsp_ready(engine))
653 tasklet_hi_schedule(&engine->irq_tasklet);
656 spin_unlock_irqrestore(&engine->timeline->lock, flags);
659 static struct intel_engine_cs *
660 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
662 struct intel_engine_cs *engine;
664 engine = container_of(pt,
665 struct drm_i915_gem_request,
667 if (engine != locked) {
669 spin_unlock_irq(&locked->timeline->lock);
670 spin_lock_irq(&engine->timeline->lock);
676 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
678 struct intel_engine_cs *engine = NULL;
679 struct i915_dependency *dep, *p;
680 struct i915_dependency stack;
683 if (prio <= READ_ONCE(request->priotree.priority))
686 /* Need BKL in order to use the temporary link inside i915_dependency */
687 lockdep_assert_held(&request->i915->drm.struct_mutex);
689 stack.signaler = &request->priotree;
690 list_add(&stack.dfs_link, &dfs);
692 /* Recursively bump all dependent priorities to match the new request.
694 * A naive approach would be to use recursion:
695 * static void update_priorities(struct i915_priotree *pt, prio) {
696 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
697 * update_priorities(dep->signal, prio)
698 * insert_request(pt);
700 * but that may have unlimited recursion depth and so runs a very
701 * real risk of overunning the kernel stack. Instead, we build
702 * a flat list of all dependencies starting with the current request.
703 * As we walk the list of dependencies, we add all of its dependencies
704 * to the end of the list (this may include an already visited
705 * request) and continue to walk onwards onto the new dependencies. The
706 * end result is a topological list of requests in reverse order, the
707 * last element in the list is the request we must execute first.
709 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
710 struct i915_priotree *pt = dep->signaler;
712 list_for_each_entry(p, &pt->signalers_list, signal_link)
713 if (prio > READ_ONCE(p->signaler->priority))
714 list_move_tail(&p->dfs_link, &dfs);
716 list_safe_reset_next(dep, p, dfs_link);
717 if (!RB_EMPTY_NODE(&pt->node))
720 engine = pt_lock_engine(pt, engine);
722 /* If it is not already in the rbtree, we can update the
723 * priority inplace and skip over it (and its dependencies)
724 * if it is referenced *again* as we descend the dfs.
726 if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) {
728 list_del_init(&dep->dfs_link);
732 /* Fifo and depth-first replacement ensure our deps execute before us */
733 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
734 struct i915_priotree *pt = dep->signaler;
736 INIT_LIST_HEAD(&dep->dfs_link);
738 engine = pt_lock_engine(pt, engine);
740 if (prio <= pt->priority)
743 GEM_BUG_ON(RB_EMPTY_NODE(&pt->node));
746 rb_erase(&pt->node, &engine->execlist_queue);
747 if (insert_request(pt, &engine->execlist_queue))
748 engine->execlist_first = &pt->node;
752 spin_unlock_irq(&engine->timeline->lock);
754 /* XXX Do we need to preempt to make room for us and our deps? */
757 static int execlists_context_pin(struct intel_engine_cs *engine,
758 struct i915_gem_context *ctx)
760 struct intel_context *ce = &ctx->engine[engine->id];
765 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
771 ret = execlists_context_deferred_alloc(ctx, engine);
775 GEM_BUG_ON(!ce->state);
777 flags = PIN_GLOBAL | PIN_HIGH;
778 if (ctx->ggtt_offset_bias)
779 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
781 ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
785 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
787 ret = PTR_ERR(vaddr);
791 ret = intel_ring_pin(ce->ring, ctx->ggtt_offset_bias);
795 intel_lr_context_descriptor_update(ctx, engine);
797 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
798 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
799 i915_ggtt_offset(ce->ring->vma);
801 ce->state->obj->mm.dirty = true;
803 i915_gem_context_get(ctx);
807 i915_gem_object_unpin_map(ce->state->obj);
809 __i915_vma_unpin(ce->state);
815 static void execlists_context_unpin(struct intel_engine_cs *engine,
816 struct i915_gem_context *ctx)
818 struct intel_context *ce = &ctx->engine[engine->id];
820 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
821 GEM_BUG_ON(ce->pin_count == 0);
826 intel_ring_unpin(ce->ring);
828 i915_gem_object_unpin_map(ce->state->obj);
829 i915_vma_unpin(ce->state);
831 i915_gem_context_put(ctx);
834 static int execlists_request_alloc(struct drm_i915_gem_request *request)
836 struct intel_engine_cs *engine = request->engine;
837 struct intel_context *ce = &request->ctx->engine[engine->id];
841 GEM_BUG_ON(!ce->pin_count);
843 /* Flush enough space to reduce the likelihood of waiting after
844 * we start building the request - in which case we will just
845 * have to repeat work.
847 request->reserved_space += EXECLISTS_REQUEST_SIZE;
849 GEM_BUG_ON(!ce->ring);
850 request->ring = ce->ring;
852 if (i915.enable_guc_submission) {
854 * Check that the GuC has space for the request before
855 * going any further, as the i915_add_request() call
856 * later on mustn't fail ...
858 ret = i915_guc_wq_reserve(request);
863 cs = intel_ring_begin(request, 0);
869 if (!ce->initialised) {
870 ret = engine->init_context(request);
874 ce->initialised = true;
877 /* Note that after this point, we have committed to using
878 * this request as it is being used to both track the
879 * state of engine initialisation and liveness of the
880 * golden renderstate above. Think twice before you try
881 * to cancel/unwind this request now.
884 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
888 if (i915.enable_guc_submission)
889 i915_guc_wq_unreserve(request);
895 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
896 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
897 * but there is a slight complication as this is applied in WA batch where the
898 * values are only initialized once so we cannot take register value at the
899 * beginning and reuse it further; hence we save its value to memory, upload a
900 * constant value with bit21 set and then we restore it back with the saved value.
901 * To simplify the WA, a constant value is formed by using the default value
902 * of this register. This shouldn't be a problem because we are only modifying
903 * it for a short period and this batch in non-premptible. We can ofcourse
904 * use additional instructions that read the actual value of the register
905 * at that time and set our bit of interest but it makes the WA complicated.
907 * This WA is also required for Gen9 so extracting as a function avoids
911 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
913 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
914 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
915 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
918 *batch++ = MI_LOAD_REGISTER_IMM(1);
919 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
920 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
922 batch = gen8_emit_pipe_control(batch,
923 PIPE_CONTROL_CS_STALL |
924 PIPE_CONTROL_DC_FLUSH_ENABLE,
927 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
928 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
929 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
936 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
937 * initialized at the beginning and shared across all contexts but this field
938 * helps us to have multiple batches at different offsets and select them based
939 * on a criteria. At the moment this batch always start at the beginning of the page
940 * and at this point we don't have multiple wa_ctx batch buffers.
942 * The number of WA applied are not known at the beginning; we use this field
943 * to return the no of DWORDS written.
945 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
946 * so it adds NOOPs as padding to make it cacheline aligned.
947 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
948 * makes a complete batch buffer.
950 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
952 /* WaDisableCtxRestoreArbitration:bdw,chv */
953 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
955 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
956 if (IS_BROADWELL(engine->i915))
957 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
959 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
960 /* Actual scratch location is at 128 bytes offset */
961 batch = gen8_emit_pipe_control(batch,
962 PIPE_CONTROL_FLUSH_L3 |
963 PIPE_CONTROL_GLOBAL_GTT_IVB |
964 PIPE_CONTROL_CS_STALL |
965 PIPE_CONTROL_QW_WRITE,
966 i915_ggtt_offset(engine->scratch) +
967 2 * CACHELINE_BYTES);
969 /* Pad to end of cacheline */
970 while ((unsigned long)batch % CACHELINE_BYTES)
974 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
975 * execution depends on the length specified in terms of cache lines
976 * in the register CTX_RCS_INDIRECT_CTX
983 * This batch is started immediately after indirect_ctx batch. Since we ensure
984 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
986 * The number of DWORDS written are returned using this field.
988 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
989 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
991 static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
993 /* WaDisableCtxRestoreArbitration:bdw,chv */
994 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
995 *batch++ = MI_BATCH_BUFFER_END;
1000 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1002 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1003 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1005 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1006 *batch++ = MI_LOAD_REGISTER_IMM(1);
1007 *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
1008 *batch++ = _MASKED_BIT_DISABLE(
1009 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
1012 /* WaClearSlmSpaceAtContextSwitch:kbl */
1013 /* Actual scratch location is at 128 bytes offset */
1014 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1015 batch = gen8_emit_pipe_control(batch,
1016 PIPE_CONTROL_FLUSH_L3 |
1017 PIPE_CONTROL_GLOBAL_GTT_IVB |
1018 PIPE_CONTROL_CS_STALL |
1019 PIPE_CONTROL_QW_WRITE,
1020 i915_ggtt_offset(engine->scratch)
1021 + 2 * CACHELINE_BYTES);
1024 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1025 if (HAS_POOLED_EU(engine->i915)) {
1027 * EU pool configuration is setup along with golden context
1028 * during context initialization. This value depends on
1029 * device type (2x6 or 3x6) and needs to be updated based
1030 * on which subslice is disabled especially for 2x6
1031 * devices, however it is safe to load default
1032 * configuration of 3x6 device instead of masking off
1033 * corresponding bits because HW ignores bits of a disabled
1034 * subslice and drops down to appropriate config. Please
1035 * see render_state_setup() in i915_gem_render_state.c for
1036 * possible configurations, to avoid duplication they are
1037 * not shown here again.
1039 *batch++ = GEN9_MEDIA_POOL_STATE;
1040 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1041 *batch++ = 0x00777000;
1047 /* Pad to end of cacheline */
1048 while ((unsigned long)batch % CACHELINE_BYTES)
1054 static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
1056 *batch++ = MI_BATCH_BUFFER_END;
1061 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1063 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1065 struct drm_i915_gem_object *obj;
1066 struct i915_vma *vma;
1069 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1071 return PTR_ERR(obj);
1073 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1079 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1083 engine->wa_ctx.vma = vma;
1087 i915_gem_object_put(obj);
1091 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1093 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1096 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1098 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1100 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1101 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1103 wa_bb_func_t wa_bb_fn[2];
1105 void *batch, *batch_ptr;
1109 if (WARN_ON(engine->id != RCS || !engine->scratch))
1112 switch (INTEL_GEN(engine->i915)) {
1114 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1115 wa_bb_fn[1] = gen9_init_perctx_bb;
1118 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1119 wa_bb_fn[1] = gen8_init_perctx_bb;
1122 MISSING_CASE(INTEL_GEN(engine->i915));
1126 ret = lrc_setup_wa_ctx(engine);
1128 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1132 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1133 batch = batch_ptr = kmap_atomic(page);
1136 * Emit the two workaround batch buffers, recording the offset from the
1137 * start of the workaround batch buffer object for each and their
1140 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1141 wa_bb[i]->offset = batch_ptr - batch;
1142 if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) {
1146 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1147 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1150 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1152 kunmap_atomic(batch);
1154 lrc_destroy_wa_ctx(engine);
1159 static u32 port_seqno(struct execlist_port *port)
1161 return port->request ? port->request->global_seqno : 0;
1164 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1166 struct drm_i915_private *dev_priv = engine->i915;
1169 ret = intel_mocs_init_engine(engine);
1173 intel_engine_reset_breadcrumbs(engine);
1174 intel_engine_init_hangcheck(engine);
1176 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1177 I915_WRITE(RING_MODE_GEN7(engine),
1178 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1179 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1180 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1181 engine->status_page.ggtt_offset);
1182 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1184 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1186 /* After a GPU reset, we may have requests to replay */
1187 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1188 if (!execlists_elsp_idle(engine)) {
1189 DRM_DEBUG_DRIVER("Restarting %s from requests [0x%x, 0x%x]\n",
1191 port_seqno(&engine->execlist_port[0]),
1192 port_seqno(&engine->execlist_port[1]));
1193 engine->execlist_port[0].count = 0;
1194 engine->execlist_port[1].count = 0;
1195 execlists_submit_ports(engine);
1201 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1203 struct drm_i915_private *dev_priv = engine->i915;
1206 ret = gen8_init_common_ring(engine);
1210 /* We need to disable the AsyncFlip performance optimisations in order
1211 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1212 * programmed to '1' on all products.
1214 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1216 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1218 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1220 return init_workarounds_ring(engine);
1223 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1227 ret = gen8_init_common_ring(engine);
1231 return init_workarounds_ring(engine);
1234 static void reset_common_ring(struct intel_engine_cs *engine,
1235 struct drm_i915_gem_request *request)
1237 struct execlist_port *port = engine->execlist_port;
1238 struct intel_context *ce;
1240 /* If the request was innocent, we leave the request in the ELSP
1241 * and will try to replay it on restarting. The context image may
1242 * have been corrupted by the reset, in which case we may have
1243 * to service a new GPU hang, but more likely we can continue on
1246 * If the request was guilty, we presume the context is corrupt
1247 * and have to at least restore the RING register in the context
1248 * image back to the expected values to skip over the guilty request.
1250 if (!request || request->fence.error != -EIO)
1253 /* We want a simple context + ring to execute the breadcrumb update.
1254 * We cannot rely on the context being intact across the GPU hang,
1255 * so clear it and rebuild just what we need for the breadcrumb.
1256 * All pending requests for this context will be zapped, and any
1257 * future request will be after userspace has had the opportunity
1258 * to recreate its own state.
1260 ce = &request->ctx->engine[engine->id];
1261 execlists_init_reg_state(ce->lrc_reg_state,
1262 request->ctx, engine, ce->ring);
1264 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1265 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1266 i915_ggtt_offset(ce->ring->vma);
1267 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1269 request->ring->head = request->postfix;
1270 request->ring->last_retired_head = -1;
1271 intel_ring_update_space(request->ring);
1273 if (i915.enable_guc_submission)
1276 /* Catch up with any missed context-switch interrupts */
1277 if (request->ctx != port[0].request->ctx) {
1278 i915_gem_request_put(port[0].request);
1280 memset(&port[1], 0, sizeof(port[1]));
1283 GEM_BUG_ON(request->ctx != port[0].request->ctx);
1285 /* Reset WaIdleLiteRestore:bdw,skl as well */
1286 request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
1287 GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
1290 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1292 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1293 struct intel_engine_cs *engine = req->engine;
1294 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1298 cs = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1302 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1303 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1304 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1306 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1307 *cs++ = upper_32_bits(pd_daddr);
1308 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1309 *cs++ = lower_32_bits(pd_daddr);
1313 intel_ring_advance(req, cs);
1318 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1319 u64 offset, u32 len,
1320 unsigned int dispatch_flags)
1322 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1326 /* Don't rely in hw updating PDPs, specially in lite-restore.
1327 * Ideally, we should set Force PD Restore in ctx descriptor,
1328 * but we can't. Force Restore would be a second option, but
1329 * it is unsafe in case of lite-restore (because the ctx is
1330 * not idle). PML4 is allocated during ppgtt init so this is
1331 * not needed in 48-bit.*/
1332 if (req->ctx->ppgtt &&
1333 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1334 if (!i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
1335 !intel_vgpu_active(req->i915)) {
1336 ret = intel_logical_ring_emit_pdps(req);
1341 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1344 cs = intel_ring_begin(req, 4);
1348 /* FIXME(BDW): Address space and security selectors. */
1349 *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags &
1350 I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
1351 *cs++ = lower_32_bits(offset);
1352 *cs++ = upper_32_bits(offset);
1354 intel_ring_advance(req, cs);
1359 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1361 struct drm_i915_private *dev_priv = engine->i915;
1362 I915_WRITE_IMR(engine,
1363 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1364 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1367 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1369 struct drm_i915_private *dev_priv = engine->i915;
1370 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1373 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1377 cs = intel_ring_begin(request, 4);
1381 cmd = MI_FLUSH_DW + 1;
1383 /* We always require a command barrier so that subsequent
1384 * commands, such as breadcrumb interrupts, are strictly ordered
1385 * wrt the contents of the write cache being flushed to memory
1386 * (and thus being coherent from the CPU).
1388 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1390 if (mode & EMIT_INVALIDATE) {
1391 cmd |= MI_INVALIDATE_TLB;
1392 if (request->engine->id == VCS)
1393 cmd |= MI_INVALIDATE_BSD;
1397 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1398 *cs++ = 0; /* upper addr */
1399 *cs++ = 0; /* value */
1400 intel_ring_advance(request, cs);
1405 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1408 struct intel_engine_cs *engine = request->engine;
1410 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1411 bool vf_flush_wa = false, dc_flush_wa = false;
1415 flags |= PIPE_CONTROL_CS_STALL;
1417 if (mode & EMIT_FLUSH) {
1418 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1419 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1420 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1421 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1424 if (mode & EMIT_INVALIDATE) {
1425 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1426 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1427 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1428 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1429 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1430 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1431 flags |= PIPE_CONTROL_QW_WRITE;
1432 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1435 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1438 if (IS_GEN9(request->i915))
1441 /* WaForGAMHang:kbl */
1442 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1454 cs = intel_ring_begin(request, len);
1459 cs = gen8_emit_pipe_control(cs, 0, 0);
1462 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
1465 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
1468 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
1470 intel_ring_advance(request, cs);
1476 * Reserve space for 2 NOOPs at the end of each request to be
1477 * used as a workaround for not being allowed to do lite
1478 * restore with HEAD==TAIL (WaIdleLiteRestore).
1480 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs)
1484 request->wa_tail = intel_ring_offset(request, cs);
1487 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
1489 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1490 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1492 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1493 *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
1495 *cs++ = request->global_seqno;
1496 *cs++ = MI_USER_INTERRUPT;
1498 request->tail = intel_ring_offset(request, cs);
1499 GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
1501 gen8_emit_wa_tail(request, cs);
1504 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1506 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
1509 /* We're using qword write, seqno should be aligned to 8 bytes. */
1510 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1512 /* w/a for post sync ops following a GPGPU operation we
1513 * need a prior CS_STALL, which is emitted by the flush
1514 * following the batch.
1516 *cs++ = GFX_OP_PIPE_CONTROL(6);
1517 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
1518 PIPE_CONTROL_QW_WRITE;
1519 *cs++ = intel_hws_seqno_address(request->engine);
1521 *cs++ = request->global_seqno;
1522 /* We're thrashing one dword of HWS. */
1524 *cs++ = MI_USER_INTERRUPT;
1526 request->tail = intel_ring_offset(request, cs);
1527 GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
1529 gen8_emit_wa_tail(request, cs);
1532 static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
1534 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1538 ret = intel_ring_workarounds_emit(req);
1542 ret = intel_rcs_context_init_mocs(req);
1544 * Failing to program the MOCS is non-fatal.The system will not
1545 * run at peak performance. So generate an error and carry on.
1548 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1550 return i915_gem_render_state_emit(req);
1554 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1555 * @engine: Engine Command Streamer.
1557 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1559 struct drm_i915_private *dev_priv;
1562 * Tasklet cannot be active at this point due intel_mark_active/idle
1563 * so this is just for documentation.
1565 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1566 tasklet_kill(&engine->irq_tasklet);
1568 dev_priv = engine->i915;
1570 if (engine->buffer) {
1571 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1574 if (engine->cleanup)
1575 engine->cleanup(engine);
1577 if (engine->status_page.vma) {
1578 i915_gem_object_unpin_map(engine->status_page.vma->obj);
1579 engine->status_page.vma = NULL;
1582 intel_engine_cleanup_common(engine);
1584 lrc_destroy_wa_ctx(engine);
1585 engine->i915 = NULL;
1586 dev_priv->engine[engine->id] = NULL;
1590 void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
1592 struct intel_engine_cs *engine;
1593 enum intel_engine_id id;
1595 for_each_engine(engine, dev_priv, id) {
1596 engine->submit_request = execlists_submit_request;
1597 engine->schedule = execlists_schedule;
1602 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1604 /* Default vfuncs which can be overriden by each engine. */
1605 engine->init_hw = gen8_init_common_ring;
1606 engine->reset_hw = reset_common_ring;
1608 engine->context_pin = execlists_context_pin;
1609 engine->context_unpin = execlists_context_unpin;
1611 engine->request_alloc = execlists_request_alloc;
1613 engine->emit_flush = gen8_emit_flush;
1614 engine->emit_breadcrumb = gen8_emit_breadcrumb;
1615 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1616 engine->submit_request = execlists_submit_request;
1617 engine->schedule = execlists_schedule;
1619 engine->irq_enable = gen8_logical_ring_enable_irq;
1620 engine->irq_disable = gen8_logical_ring_disable_irq;
1621 engine->emit_bb_start = gen8_emit_bb_start;
1625 logical_ring_default_irqs(struct intel_engine_cs *engine)
1627 unsigned shift = engine->irq_shift;
1628 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1629 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1633 lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1635 const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1638 /* The HWSP is part of the default context object in LRC mode. */
1639 hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1641 return PTR_ERR(hws);
1643 engine->status_page.page_addr = hws + hws_offset;
1644 engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
1645 engine->status_page.vma = vma;
1651 logical_ring_setup(struct intel_engine_cs *engine)
1653 struct drm_i915_private *dev_priv = engine->i915;
1654 enum forcewake_domains fw_domains;
1656 intel_engine_setup_common(engine);
1658 /* Intentionally left blank. */
1659 engine->buffer = NULL;
1661 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1665 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1666 RING_CONTEXT_STATUS_PTR(engine),
1667 FW_REG_READ | FW_REG_WRITE);
1669 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1670 RING_CONTEXT_STATUS_BUF_BASE(engine),
1673 engine->fw_domains = fw_domains;
1675 tasklet_init(&engine->irq_tasklet,
1676 intel_lrc_irq_handler, (unsigned long)engine);
1678 logical_ring_default_vfuncs(engine);
1679 logical_ring_default_irqs(engine);
1683 logical_ring_init(struct intel_engine_cs *engine)
1685 struct i915_gem_context *dctx = engine->i915->kernel_context;
1688 ret = intel_engine_init_common(engine);
1692 /* And setup the hardware status page. */
1693 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1695 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1702 intel_logical_ring_cleanup(engine);
1706 int logical_render_ring_init(struct intel_engine_cs *engine)
1708 struct drm_i915_private *dev_priv = engine->i915;
1711 logical_ring_setup(engine);
1713 if (HAS_L3_DPF(dev_priv))
1714 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1716 /* Override some for render ring. */
1717 if (INTEL_GEN(dev_priv) >= 9)
1718 engine->init_hw = gen9_init_render_ring;
1720 engine->init_hw = gen8_init_render_ring;
1721 engine->init_context = gen8_init_rcs_context;
1722 engine->emit_flush = gen8_emit_flush_render;
1723 engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
1724 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
1726 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
1730 ret = intel_init_workaround_bb(engine);
1733 * We continue even if we fail to initialize WA batch
1734 * because we only expect rare glitches but nothing
1735 * critical to prevent us from using GPU
1737 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1741 return logical_ring_init(engine);
1744 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1746 logical_ring_setup(engine);
1748 return logical_ring_init(engine);
1752 make_rpcs(struct drm_i915_private *dev_priv)
1757 * No explicit RPCS request is needed to ensure full
1758 * slice/subslice/EU enablement prior to Gen9.
1760 if (INTEL_GEN(dev_priv) < 9)
1764 * Starting in Gen9, render power gating can leave
1765 * slice/subslice/EU in a partially enabled state. We
1766 * must make an explicit request through RPCS for full
1769 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
1770 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1771 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
1772 GEN8_RPCS_S_CNT_SHIFT;
1773 rpcs |= GEN8_RPCS_ENABLE;
1776 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
1777 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1778 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
1779 GEN8_RPCS_SS_CNT_SHIFT;
1780 rpcs |= GEN8_RPCS_ENABLE;
1783 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
1784 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1785 GEN8_RPCS_EU_MIN_SHIFT;
1786 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1787 GEN8_RPCS_EU_MAX_SHIFT;
1788 rpcs |= GEN8_RPCS_ENABLE;
1794 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1796 u32 indirect_ctx_offset;
1798 switch (INTEL_GEN(engine->i915)) {
1800 MISSING_CASE(INTEL_GEN(engine->i915));
1803 indirect_ctx_offset =
1804 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1807 indirect_ctx_offset =
1808 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1812 return indirect_ctx_offset;
1815 static void execlists_init_reg_state(u32 *reg_state,
1816 struct i915_gem_context *ctx,
1817 struct intel_engine_cs *engine,
1818 struct intel_ring *ring)
1820 struct drm_i915_private *dev_priv = engine->i915;
1821 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
1823 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1824 * commands followed by (reg, value) pairs. The values we are setting here are
1825 * only for the first context restore: on a subsequent save, the GPU will
1826 * recreate this batchbuffer with new values (including all the missing
1827 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1828 reg_state[CTX_LRI_HEADER_0] =
1829 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
1830 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
1831 RING_CONTEXT_CONTROL(engine),
1832 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1833 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
1834 (HAS_RESOURCE_STREAMER(dev_priv) ?
1835 CTX_CTRL_RS_CTX_ENABLE : 0)));
1836 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
1838 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
1840 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
1841 RING_START(engine->mmio_base), 0);
1842 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
1843 RING_CTL(engine->mmio_base),
1844 RING_CTL_SIZE(ring->size) | RING_VALID);
1845 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
1846 RING_BBADDR_UDW(engine->mmio_base), 0);
1847 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
1848 RING_BBADDR(engine->mmio_base), 0);
1849 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
1850 RING_BBSTATE(engine->mmio_base),
1852 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
1853 RING_SBBADDR_UDW(engine->mmio_base), 0);
1854 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
1855 RING_SBBADDR(engine->mmio_base), 0);
1856 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
1857 RING_SBBSTATE(engine->mmio_base), 0);
1858 if (engine->id == RCS) {
1859 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
1860 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
1861 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
1862 RING_INDIRECT_CTX(engine->mmio_base), 0);
1863 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
1864 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
1865 if (engine->wa_ctx.vma) {
1866 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1867 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
1869 reg_state[CTX_RCS_INDIRECT_CTX+1] =
1870 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
1871 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
1873 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
1874 intel_lr_indirect_ctx_offset(engine) << 6;
1876 reg_state[CTX_BB_PER_CTX_PTR+1] =
1877 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
1880 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
1881 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
1882 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
1883 /* PDP values well be assigned later if needed */
1884 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
1886 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
1888 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
1890 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
1892 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
1894 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
1896 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
1898 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
1901 if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
1902 /* 64b PPGTT (48bit canonical)
1903 * PDP0_DESCRIPTOR contains the base address to PML4 and
1904 * other PDP Descriptors are ignored.
1906 ASSIGN_CTX_PML4(ppgtt, reg_state);
1909 if (engine->id == RCS) {
1910 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1911 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
1912 make_rpcs(dev_priv));
1917 populate_lr_context(struct i915_gem_context *ctx,
1918 struct drm_i915_gem_object *ctx_obj,
1919 struct intel_engine_cs *engine,
1920 struct intel_ring *ring)
1925 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1927 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1931 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
1932 if (IS_ERR(vaddr)) {
1933 ret = PTR_ERR(vaddr);
1934 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
1937 ctx_obj->mm.dirty = true;
1939 /* The second page of the context object contains some fields which must
1940 * be set up prior to the first execution. */
1942 execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
1945 i915_gem_object_unpin_map(ctx_obj);
1951 * intel_lr_context_size() - return the size of the context for an engine
1952 * @engine: which engine to find the context size for
1954 * Each engine may require a different amount of space for a context image,
1955 * so when allocating (or copying) an image, this function can be used to
1956 * find the right size for the specific engine.
1958 * Return: size (in bytes) of an engine-specific context image
1960 * Note: this size includes the HWSP, which is part of the context image
1961 * in LRC mode, but does not include the "shared data page" used with
1962 * GuC submission. The caller should account for this if using the GuC.
1964 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
1968 WARN_ON(INTEL_GEN(engine->i915) < 8);
1970 switch (engine->id) {
1972 if (INTEL_GEN(engine->i915) >= 9)
1973 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1975 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1981 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1988 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
1989 struct intel_engine_cs *engine)
1991 struct drm_i915_gem_object *ctx_obj;
1992 struct intel_context *ce = &ctx->engine[engine->id];
1993 struct i915_vma *vma;
1994 uint32_t context_size;
1995 struct intel_ring *ring;
2000 context_size = round_up(intel_lr_context_size(engine),
2001 I915_GTT_PAGE_SIZE);
2003 /* One extra page as the sharing data between driver and GuC */
2004 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2006 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2007 if (IS_ERR(ctx_obj)) {
2008 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2009 return PTR_ERR(ctx_obj);
2012 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2015 goto error_deref_obj;
2018 ring = intel_engine_create_ring(engine, ctx->ring_size);
2020 ret = PTR_ERR(ring);
2021 goto error_deref_obj;
2024 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2026 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2027 goto error_ring_free;
2032 ce->initialised = engine->init_context == NULL;
2037 intel_ring_free(ring);
2039 i915_gem_object_put(ctx_obj);
2043 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2045 struct intel_engine_cs *engine;
2046 struct i915_gem_context *ctx;
2047 enum intel_engine_id id;
2049 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2050 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2051 * that stored in context. As we only write new commands from
2052 * ce->ring->tail onwards, everything before that is junk. If the GPU
2053 * starts reading from its RING_HEAD from the context, it may try to
2054 * execute that junk and die.
2056 * So to avoid that we reset the context images upon resume. For
2057 * simplicity, we just zero everything out.
2059 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2060 for_each_engine(engine, dev_priv, id) {
2061 struct intel_context *ce = &ctx->engine[engine->id];
2067 reg = i915_gem_object_pin_map(ce->state->obj,
2069 if (WARN_ON(IS_ERR(reg)))
2072 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2073 reg[CTX_RING_HEAD+1] = 0;
2074 reg[CTX_RING_TAIL+1] = 0;
2076 ce->state->obj->mm.dirty = true;
2077 i915_gem_object_unpin_map(ce->state->obj);
2079 ce->ring->head = ce->ring->tail = 0;
2080 ce->ring->last_retired_head = -1;
2081 intel_ring_update_space(ce->ring);