2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "i915_vgpu.h"
141 #include "intel_lrc_reg.h"
142 #include "intel_mocs.h"
143 #include "intel_workarounds.h"
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
162 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
163 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
164 #define WA_TAIL_DWORDS 2
165 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
167 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
168 struct intel_engine_cs *engine,
169 struct intel_context *ce);
170 static void execlists_init_reg_state(u32 *reg_state,
171 struct i915_gem_context *ctx,
172 struct intel_engine_cs *engine,
173 struct intel_ring *ring);
175 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
177 return rb_entry(rb, struct i915_priolist, node);
180 static inline int rq_prio(const struct i915_request *rq)
182 return rq->sched.attr.priority;
185 static inline bool need_preempt(const struct intel_engine_cs *engine,
186 const struct i915_request *last,
189 return (intel_engine_has_preemption(engine) &&
190 __execlists_need_preempt(prio, rq_prio(last)) &&
191 !i915_request_completed(last));
195 * The context descriptor encodes various attributes of a context,
196 * including its GTT address and some flags. Because it's fairly
197 * expensive to calculate, we'll just do it once and cache the result,
198 * which remains valid until the context is unpinned.
200 * This is what a descriptor looks like, from LSB to MSB::
202 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
203 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
204 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
205 * bits 53-54: mbz, reserved for use by hardware
206 * bits 55-63: group ID, currently unused and set to 0
208 * Starting from Gen11, the upper dword of the descriptor has a new format:
210 * bits 32-36: reserved
211 * bits 37-47: SW context ID
212 * bits 48:53: engine instance
213 * bit 54: mbz, reserved for use by hardware
214 * bits 55-60: SW counter
215 * bits 61-63: engine class
217 * engine info, SW context ID and SW counter need to form a unique number
218 * (Context ID) per lrc.
221 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
222 struct intel_engine_cs *engine,
223 struct intel_context *ce)
227 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
228 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
230 desc = ctx->desc_template; /* bits 0-11 */
231 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
233 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
235 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
238 * The following 32bits are copied into the OA reports (dword 2).
239 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
242 if (INTEL_GEN(ctx->i915) >= 11) {
243 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
244 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
247 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
250 /* TODO: decide what to do with SW counter (bits 55-60) */
252 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
255 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
256 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
262 static struct i915_priolist *
263 lookup_priolist(struct intel_engine_cs *engine, int prio)
265 struct intel_engine_execlists * const execlists = &engine->execlists;
266 struct i915_priolist *p;
267 struct rb_node **parent, *rb;
270 if (unlikely(execlists->no_priolist))
271 prio = I915_PRIORITY_NORMAL;
274 /* most positive priority is scheduled first, equal priorities fifo */
276 parent = &execlists->queue.rb_root.rb_node;
280 if (prio > p->priority) {
281 parent = &rb->rb_left;
282 } else if (prio < p->priority) {
283 parent = &rb->rb_right;
290 if (prio == I915_PRIORITY_NORMAL) {
291 p = &execlists->default_priolist;
293 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
294 /* Convert an allocation failure to a priority bump */
296 prio = I915_PRIORITY_NORMAL; /* recurses just once */
298 /* To maintain ordering with all rendering, after an
299 * allocation failure we have to disable all scheduling.
300 * Requests will then be executed in fifo, and schedule
301 * will ensure that dependencies are emitted in fifo.
302 * There will be still some reordering with existing
303 * requests, so if userspace lied about their
304 * dependencies that reordering may be visible.
306 execlists->no_priolist = true;
312 INIT_LIST_HEAD(&p->requests);
313 rb_link_node(&p->node, rb, parent);
314 rb_insert_color_cached(&p->node, &execlists->queue, first);
319 static void unwind_wa_tail(struct i915_request *rq)
321 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
322 assert_ring_tail_valid(rq->ring, rq->tail);
325 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
327 struct i915_request *rq, *rn;
328 struct i915_priolist *uninitialized_var(p);
329 int last_prio = I915_PRIORITY_INVALID;
331 lockdep_assert_held(&engine->timeline.lock);
333 list_for_each_entry_safe_reverse(rq, rn,
334 &engine->timeline.requests,
336 if (i915_request_completed(rq))
339 __i915_request_unsubmit(rq);
342 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
343 if (rq_prio(rq) != last_prio) {
344 last_prio = rq_prio(rq);
345 p = lookup_priolist(engine, last_prio);
348 GEM_BUG_ON(p->priority != rq_prio(rq));
349 list_add(&rq->sched.link, &p->requests);
354 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
356 struct intel_engine_cs *engine =
357 container_of(execlists, typeof(*engine), execlists);
360 spin_lock_irqsave(&engine->timeline.lock, flags);
362 __unwind_incomplete_requests(engine);
364 spin_unlock_irqrestore(&engine->timeline.lock, flags);
368 execlists_context_status_change(struct i915_request *rq, unsigned long status)
371 * Only used when GVT-g is enabled now. When GVT-g is disabled,
372 * The compiler should eliminate this function as dead-code.
374 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
377 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
382 execlists_user_begin(struct intel_engine_execlists *execlists,
383 const struct execlist_port *port)
385 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
389 execlists_user_end(struct intel_engine_execlists *execlists)
391 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
395 execlists_context_schedule_in(struct i915_request *rq)
397 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
398 intel_engine_context_in(rq->engine);
402 execlists_context_schedule_out(struct i915_request *rq, unsigned long status)
404 intel_engine_context_out(rq->engine);
405 execlists_context_status_change(rq, status);
406 trace_i915_request_out(rq);
410 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
412 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
413 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
414 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
415 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
418 static u64 execlists_update_context(struct i915_request *rq)
420 struct intel_context *ce = rq->hw_context;
421 struct i915_hw_ppgtt *ppgtt =
422 rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
423 u32 *reg_state = ce->lrc_reg_state;
425 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
427 /* True 32b PPGTT with dynamic page allocation: update PDP
428 * registers and point the unallocated PDPs to scratch page.
429 * PML4 is allocated during ppgtt init, so this is not needed
432 if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
433 execlists_update_context_pdps(ppgtt, reg_state);
438 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
440 if (execlists->ctrl_reg) {
441 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
442 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
444 writel(upper_32_bits(desc), execlists->submit_reg);
445 writel(lower_32_bits(desc), execlists->submit_reg);
449 static void execlists_submit_ports(struct intel_engine_cs *engine)
451 struct intel_engine_execlists *execlists = &engine->execlists;
452 struct execlist_port *port = execlists->port;
456 * We can skip acquiring intel_runtime_pm_get() here as it was taken
457 * on our behalf by the request (see i915_gem_mark_busy()) and it will
458 * not be relinquished until the device is idle (see
459 * i915_gem_idle_work_handler()). As a precaution, we make sure
460 * that all ELSP are drained i.e. we have processed the CSB,
461 * before allowing ourselves to idle and calling intel_runtime_pm_put().
463 GEM_BUG_ON(!engine->i915->gt.awake);
466 * ELSQ note: the submit queue is not cleared after being submitted
467 * to the HW so we need to make sure we always clean it up. This is
468 * currently ensured by the fact that we always write the same number
469 * of elsq entries, keep this in mind before changing the loop below.
471 for (n = execlists_num_ports(execlists); n--; ) {
472 struct i915_request *rq;
476 rq = port_unpack(&port[n], &count);
478 GEM_BUG_ON(count > !n);
480 execlists_context_schedule_in(rq);
481 port_set(&port[n], port_pack(rq, count));
482 desc = execlists_update_context(rq);
483 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
485 GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
487 port[n].context_id, count,
489 rq->fence.context, rq->fence.seqno,
490 intel_engine_get_seqno(engine),
497 write_desc(execlists, desc, n);
500 /* we need to manually load the submit queue */
501 if (execlists->ctrl_reg)
502 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
504 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
507 static bool ctx_single_port_submission(const struct intel_context *ce)
509 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
510 i915_gem_context_force_single_submission(ce->gem_context));
513 static bool can_merge_ctx(const struct intel_context *prev,
514 const struct intel_context *next)
519 if (ctx_single_port_submission(prev))
525 static void port_assign(struct execlist_port *port, struct i915_request *rq)
527 GEM_BUG_ON(rq == port_request(port));
529 if (port_isset(port))
530 i915_request_put(port_request(port));
532 port_set(port, port_pack(i915_request_get(rq), port_count(port)));
535 static void inject_preempt_context(struct intel_engine_cs *engine)
537 struct intel_engine_execlists *execlists = &engine->execlists;
538 struct intel_context *ce =
539 to_intel_context(engine->i915->preempt_context, engine);
542 GEM_BUG_ON(execlists->preempt_complete_status !=
543 upper_32_bits(ce->lrc_desc));
546 * Switch to our empty preempt context so
547 * the state of the GPU is known (idle).
549 GEM_TRACE("%s\n", engine->name);
550 for (n = execlists_num_ports(execlists); --n; )
551 write_desc(execlists, 0, n);
553 write_desc(execlists, ce->lrc_desc, n);
555 /* we need to manually load the submit queue */
556 if (execlists->ctrl_reg)
557 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
559 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
560 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
563 static void complete_preempt_context(struct intel_engine_execlists *execlists)
565 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
567 if (inject_preempt_hang(execlists))
570 execlists_cancel_port_requests(execlists);
571 __unwind_incomplete_requests(container_of(execlists,
572 struct intel_engine_cs,
576 static void execlists_dequeue(struct intel_engine_cs *engine)
578 struct intel_engine_execlists * const execlists = &engine->execlists;
579 struct execlist_port *port = execlists->port;
580 const struct execlist_port * const last_port =
581 &execlists->port[execlists->port_mask];
582 struct i915_request *last = port_request(port);
587 * Hardware submission is through 2 ports. Conceptually each port
588 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
589 * static for a context, and unique to each, so we only execute
590 * requests belonging to a single context from each ring. RING_HEAD
591 * is maintained by the CS in the context image, it marks the place
592 * where it got up to last time, and through RING_TAIL we tell the CS
593 * where we want to execute up to this time.
595 * In this list the requests are in order of execution. Consecutive
596 * requests from the same context are adjacent in the ringbuffer. We
597 * can combine these requests into a single RING_TAIL update:
599 * RING_HEAD...req1...req2
601 * since to execute req2 the CS must first execute req1.
603 * Our goal then is to point each port to the end of a consecutive
604 * sequence of requests as being the most optimal (fewest wake ups
605 * and context switches) submission.
610 * Don't resubmit or switch until all outstanding
611 * preemptions (lite-restore) are seen. Then we
612 * know the next preemption status we see corresponds
613 * to this ELSP update.
615 GEM_BUG_ON(!execlists_is_active(execlists,
616 EXECLISTS_ACTIVE_USER));
617 GEM_BUG_ON(!port_count(&port[0]));
620 * If we write to ELSP a second time before the HW has had
621 * a chance to respond to the previous write, we can confuse
622 * the HW and hit "undefined behaviour". After writing to ELSP,
623 * we must then wait until we see a context-switch event from
624 * the HW to indicate that it has had a chance to respond.
626 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
629 if (need_preempt(engine, last, execlists->queue_priority)) {
630 inject_preempt_context(engine);
635 * In theory, we could coalesce more requests onto
636 * the second port (the first port is active, with
637 * no preemptions pending). However, that means we
638 * then have to deal with the possible lite-restore
639 * of the second port (as we submit the ELSP, there
640 * may be a context-switch) but also we may complete
641 * the resubmission before the context-switch. Ergo,
642 * coalescing onto the second port will cause a
643 * preemption event, but we cannot predict whether
644 * that will affect port[0] or port[1].
646 * If the second port is already active, we can wait
647 * until the next context-switch before contemplating
648 * new requests. The GPU will be busy and we should be
649 * able to resubmit the new ELSP before it idles,
650 * avoiding pipeline bubbles (momentary pauses where
651 * the driver is unable to keep up the supply of new
652 * work). However, we have to double check that the
653 * priorities of the ports haven't been switch.
655 if (port_count(&port[1]))
659 * WaIdleLiteRestore:bdw,skl
660 * Apply the wa NOOPs to prevent
661 * ring:HEAD == rq:TAIL as we resubmit the
662 * request. See gen8_emit_breadcrumb() for
663 * where we prepare the padding after the
664 * end of the request.
666 last->tail = last->wa_tail;
669 while ((rb = rb_first_cached(&execlists->queue))) {
670 struct i915_priolist *p = to_priolist(rb);
671 struct i915_request *rq, *rn;
673 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
675 * Can we combine this request with the current port?
676 * It has to be the same context/ringbuffer and not
677 * have any exceptions (e.g. GVT saying never to
680 * If we can combine the requests, we can execute both
681 * by updating the RING_TAIL to point to the end of the
682 * second request, and so we never need to tell the
683 * hardware about the first.
686 !can_merge_ctx(rq->hw_context, last->hw_context)) {
688 * If we are on the second port and cannot
689 * combine this request with the last, then we
692 if (port == last_port) {
693 __list_del_many(&p->requests,
699 * If GVT overrides us we only ever submit
700 * port[0], leaving port[1] empty. Note that we
701 * also have to be careful that we don't queue
702 * the same context (even though a different
703 * request) to the second port.
705 if (ctx_single_port_submission(last->hw_context) ||
706 ctx_single_port_submission(rq->hw_context)) {
707 __list_del_many(&p->requests,
712 GEM_BUG_ON(last->hw_context == rq->hw_context);
715 port_assign(port, last);
718 GEM_BUG_ON(port_isset(port));
721 INIT_LIST_HEAD(&rq->sched.link);
722 __i915_request_submit(rq);
723 trace_i915_request_in(rq, port_index(port, execlists));
728 rb_erase_cached(&p->node, &execlists->queue);
729 INIT_LIST_HEAD(&p->requests);
730 if (p->priority != I915_PRIORITY_NORMAL)
731 kmem_cache_free(engine->i915->priorities, p);
736 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
738 * We choose queue_priority such that if we add a request of greater
739 * priority than this, we kick the submission tasklet to decide on
740 * the right order of submitting the requests to hardware. We must
741 * also be prepared to reorder requests as they are in-flight on the
742 * HW. We derive the queue_priority then as the first "hole" in
743 * the HW submission ports and if there are no available slots,
744 * the priority of the lowest executing request, i.e. last.
746 * When we do receive a higher priority request ready to run from the
747 * user, see queue_request(), the queue_priority is bumped to that
748 * request triggering preemption on the next dequeue (or subsequent
749 * interrupt for secondary ports).
751 execlists->queue_priority =
752 port != execlists->port ? rq_prio(last) : INT_MIN;
755 port_assign(port, last);
756 execlists_submit_ports(engine);
759 /* We must always keep the beast fed if we have work piled up */
760 GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
761 !port_isset(execlists->port));
763 /* Re-evaluate the executing context setup after each preemptive kick */
765 execlists_user_begin(execlists, execlists->port);
767 /* If the engine is now idle, so should be the flag; and vice versa. */
768 GEM_BUG_ON(execlists_is_active(&engine->execlists,
769 EXECLISTS_ACTIVE_USER) ==
770 !port_isset(engine->execlists.port));
774 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
776 struct execlist_port *port = execlists->port;
777 unsigned int num_ports = execlists_num_ports(execlists);
779 while (num_ports-- && port_isset(port)) {
780 struct i915_request *rq = port_request(port);
782 GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n",
784 (unsigned int)(port - execlists->port),
786 rq->fence.context, rq->fence.seqno,
787 intel_engine_get_seqno(rq->engine));
789 GEM_BUG_ON(!execlists->active);
790 execlists_context_schedule_out(rq,
791 i915_request_completed(rq) ?
792 INTEL_CONTEXT_SCHEDULE_OUT :
793 INTEL_CONTEXT_SCHEDULE_PREEMPTED);
795 i915_request_put(rq);
797 memset(port, 0, sizeof(*port));
801 execlists_clear_all_active(execlists);
804 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
807 * After a reset, the HW starts writing into CSB entry [0]. We
808 * therefore have to set our HEAD pointer back one entry so that
809 * the *first* entry we check is entry 0. To complicate this further,
810 * as we don't wait for the first interrupt after reset, we have to
811 * fake the HW write to point back to the last entry so that our
812 * inline comparison of our cached head position against the last HW
813 * write works even before the first interrupt.
815 execlists->csb_head = execlists->csb_write_reset;
816 WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
819 static void nop_submission_tasklet(unsigned long data)
821 /* The driver is wedged; don't process any more events. */
824 static void execlists_cancel_requests(struct intel_engine_cs *engine)
826 struct intel_engine_execlists * const execlists = &engine->execlists;
827 struct i915_request *rq, *rn;
831 GEM_TRACE("%s current %d\n",
832 engine->name, intel_engine_get_seqno(engine));
835 * Before we call engine->cancel_requests(), we should have exclusive
836 * access to the submission state. This is arranged for us by the
837 * caller disabling the interrupt generation, the tasklet and other
838 * threads that may then access the same state, giving us a free hand
839 * to reset state. However, we still need to let lockdep be aware that
840 * we know this state may be accessed in hardirq context, so we
841 * disable the irq around this manipulation and we want to keep
842 * the spinlock focused on its duties and not accidentally conflate
843 * coverage to the submission's irq state. (Similarly, although we
844 * shouldn't need to disable irq around the manipulation of the
845 * submission's irq state, we also wish to remind ourselves that
848 spin_lock_irqsave(&engine->timeline.lock, flags);
850 /* Cancel the requests on the HW and clear the ELSP tracker. */
851 execlists_cancel_port_requests(execlists);
852 execlists_user_end(execlists);
854 /* Mark all executing requests as skipped. */
855 list_for_each_entry(rq, &engine->timeline.requests, link) {
856 GEM_BUG_ON(!rq->global_seqno);
857 if (!i915_request_completed(rq))
858 dma_fence_set_error(&rq->fence, -EIO);
861 /* Flush the queued requests to the timeline list (for retiring). */
862 while ((rb = rb_first_cached(&execlists->queue))) {
863 struct i915_priolist *p = to_priolist(rb);
865 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
866 INIT_LIST_HEAD(&rq->sched.link);
868 dma_fence_set_error(&rq->fence, -EIO);
869 __i915_request_submit(rq);
872 rb_erase_cached(&p->node, &execlists->queue);
873 INIT_LIST_HEAD(&p->requests);
874 if (p->priority != I915_PRIORITY_NORMAL)
875 kmem_cache_free(engine->i915->priorities, p);
878 /* Remaining _unready_ requests will be nop'ed when submitted */
880 execlists->queue_priority = INT_MIN;
881 execlists->queue = RB_ROOT_CACHED;
882 GEM_BUG_ON(port_isset(execlists->port));
884 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
885 execlists->tasklet.func = nop_submission_tasklet;
887 spin_unlock_irqrestore(&engine->timeline.lock, flags);
891 reset_in_progress(const struct intel_engine_execlists *execlists)
893 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
896 static void process_csb(struct intel_engine_cs *engine)
898 struct intel_engine_execlists * const execlists = &engine->execlists;
899 struct execlist_port *port = execlists->port;
900 const u32 * const buf = execlists->csb_status;
904 * Note that csb_write, csb_status may be either in HWSP or mmio.
905 * When reading from the csb_write mmio register, we have to be
906 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
907 * the low 4bits. As it happens we know the next 4bits are always
908 * zero and so we can simply masked off the low u8 of the register
909 * and treat it identically to reading from the HWSP (without having
910 * to use explicit shifting and masking, and probably bifurcating
911 * the code to handle the legacy mmio read).
913 head = execlists->csb_head;
914 tail = READ_ONCE(*execlists->csb_write);
915 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
916 if (unlikely(head == tail))
920 * Hopefully paired with a wmb() in HW!
922 * We must complete the read of the write pointer before any reads
923 * from the CSB, so that we do not see stale values. Without an rmb
924 * (lfence) the HW may speculatively perform the CSB[] reads *before*
925 * we perform the READ_ONCE(*csb_write).
930 struct i915_request *rq;
934 if (++head == GEN8_CSB_ENTRIES)
938 * We are flying near dragons again.
940 * We hold a reference to the request in execlist_port[]
941 * but no more than that. We are operating in softirq
942 * context and so cannot hold any mutex or sleep. That
943 * prevents us stopping the requests we are processing
944 * in port[] from being retired simultaneously (the
945 * breadcrumb will be complete before we see the
946 * context-switch). As we only hold the reference to the
947 * request, any pointer chasing underneath the request
948 * is subject to a potential use-after-free. Thus we
949 * store all of the bookkeeping within port[] as
950 * required, and avoid using unguarded pointers beneath
951 * request itself. The same applies to the atomic
955 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
957 buf[2 * head + 0], buf[2 * head + 1],
960 status = buf[2 * head];
961 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
962 GEN8_CTX_STATUS_PREEMPTED))
963 execlists_set_active(execlists,
964 EXECLISTS_ACTIVE_HWACK);
965 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
966 execlists_clear_active(execlists,
967 EXECLISTS_ACTIVE_HWACK);
969 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
972 /* We should never get a COMPLETED | IDLE_ACTIVE! */
973 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
975 if (status & GEN8_CTX_STATUS_COMPLETE &&
976 buf[2*head + 1] == execlists->preempt_complete_status) {
977 GEM_TRACE("%s preempt-idle\n", engine->name);
978 complete_preempt_context(execlists);
982 if (status & GEN8_CTX_STATUS_PREEMPTED &&
983 execlists_is_active(execlists,
984 EXECLISTS_ACTIVE_PREEMPT))
987 GEM_BUG_ON(!execlists_is_active(execlists,
988 EXECLISTS_ACTIVE_USER));
990 rq = port_unpack(port, &count);
991 GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
993 port->context_id, count,
994 rq ? rq->global_seqno : 0,
995 rq ? rq->fence.context : 0,
996 rq ? rq->fence.seqno : 0,
997 intel_engine_get_seqno(engine),
998 rq ? rq_prio(rq) : 0);
1000 /* Check the context/desc id for this event matches */
1001 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
1003 GEM_BUG_ON(count == 0);
1006 * On the final event corresponding to the
1007 * submission of this context, we expect either
1008 * an element-switch event or a completion
1009 * event (and on completion, the active-idle
1010 * marker). No more preemptions, lite-restore
1013 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
1014 GEM_BUG_ON(port_isset(&port[1]) &&
1015 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
1016 GEM_BUG_ON(!port_isset(&port[1]) &&
1017 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
1020 * We rely on the hardware being strongly
1021 * ordered, that the breadcrumb write is
1022 * coherent (visible from the CPU) before the
1023 * user interrupt and CSB is processed.
1025 GEM_BUG_ON(!i915_request_completed(rq));
1027 execlists_context_schedule_out(rq,
1028 INTEL_CONTEXT_SCHEDULE_OUT);
1029 i915_request_put(rq);
1031 GEM_TRACE("%s completed ctx=%d\n",
1032 engine->name, port->context_id);
1034 port = execlists_port_complete(execlists, port);
1035 if (port_isset(port))
1036 execlists_user_begin(execlists, port);
1038 execlists_user_end(execlists);
1040 port_set(port, port_pack(rq, count));
1042 } while (head != tail);
1044 execlists->csb_head = head;
1047 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1049 lockdep_assert_held(&engine->timeline.lock);
1051 process_csb(engine);
1052 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
1053 execlists_dequeue(engine);
1057 * Check the unread Context Status Buffers and manage the submission of new
1058 * contexts to the ELSP accordingly.
1060 static void execlists_submission_tasklet(unsigned long data)
1062 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1063 unsigned long flags;
1065 GEM_TRACE("%s awake?=%d, active=%x\n",
1067 engine->i915->gt.awake,
1068 engine->execlists.active);
1070 spin_lock_irqsave(&engine->timeline.lock, flags);
1071 __execlists_submission_tasklet(engine);
1072 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1075 static void queue_request(struct intel_engine_cs *engine,
1076 struct i915_sched_node *node,
1079 list_add_tail(&node->link,
1080 &lookup_priolist(engine, prio)->requests);
1083 static void __update_queue(struct intel_engine_cs *engine, int prio)
1085 engine->execlists.queue_priority = prio;
1088 static void __submit_queue_imm(struct intel_engine_cs *engine)
1090 struct intel_engine_execlists * const execlists = &engine->execlists;
1092 if (reset_in_progress(execlists))
1093 return; /* defer until we restart the engine following reset */
1095 if (execlists->tasklet.func == execlists_submission_tasklet)
1096 __execlists_submission_tasklet(engine);
1098 tasklet_hi_schedule(&execlists->tasklet);
1101 static void submit_queue(struct intel_engine_cs *engine, int prio)
1103 if (prio > engine->execlists.queue_priority) {
1104 __update_queue(engine, prio);
1105 __submit_queue_imm(engine);
1109 static void execlists_submit_request(struct i915_request *request)
1111 struct intel_engine_cs *engine = request->engine;
1112 unsigned long flags;
1114 /* Will be called from irq-context when using foreign fences. */
1115 spin_lock_irqsave(&engine->timeline.lock, flags);
1117 queue_request(engine, &request->sched, rq_prio(request));
1119 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1120 GEM_BUG_ON(list_empty(&request->sched.link));
1122 submit_queue(engine, rq_prio(request));
1124 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1127 static struct i915_request *sched_to_request(struct i915_sched_node *node)
1129 return container_of(node, struct i915_request, sched);
1132 static struct intel_engine_cs *
1133 sched_lock_engine(struct i915_sched_node *node, struct intel_engine_cs *locked)
1135 struct intel_engine_cs *engine = sched_to_request(node)->engine;
1137 GEM_BUG_ON(!locked);
1139 if (engine != locked) {
1140 spin_unlock(&locked->timeline.lock);
1141 spin_lock(&engine->timeline.lock);
1147 static void execlists_schedule(struct i915_request *request,
1148 const struct i915_sched_attr *attr)
1150 struct i915_priolist *uninitialized_var(pl);
1151 struct intel_engine_cs *engine, *last;
1152 struct i915_dependency *dep, *p;
1153 struct i915_dependency stack;
1154 const int prio = attr->priority;
1157 GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
1159 if (i915_request_completed(request))
1162 if (prio <= READ_ONCE(request->sched.attr.priority))
1165 /* Need BKL in order to use the temporary link inside i915_dependency */
1166 lockdep_assert_held(&request->i915->drm.struct_mutex);
1168 stack.signaler = &request->sched;
1169 list_add(&stack.dfs_link, &dfs);
1172 * Recursively bump all dependent priorities to match the new request.
1174 * A naive approach would be to use recursion:
1175 * static void update_priorities(struct i915_sched_node *node, prio) {
1176 * list_for_each_entry(dep, &node->signalers_list, signal_link)
1177 * update_priorities(dep->signal, prio)
1178 * queue_request(node);
1180 * but that may have unlimited recursion depth and so runs a very
1181 * real risk of overunning the kernel stack. Instead, we build
1182 * a flat list of all dependencies starting with the current request.
1183 * As we walk the list of dependencies, we add all of its dependencies
1184 * to the end of the list (this may include an already visited
1185 * request) and continue to walk onwards onto the new dependencies. The
1186 * end result is a topological list of requests in reverse order, the
1187 * last element in the list is the request we must execute first.
1189 list_for_each_entry(dep, &dfs, dfs_link) {
1190 struct i915_sched_node *node = dep->signaler;
1193 * Within an engine, there can be no cycle, but we may
1194 * refer to the same dependency chain multiple times
1195 * (redundant dependencies are not eliminated) and across
1198 list_for_each_entry(p, &node->signalers_list, signal_link) {
1199 GEM_BUG_ON(p == dep); /* no cycles! */
1201 if (i915_sched_node_signaled(p->signaler))
1204 GEM_BUG_ON(p->signaler->attr.priority < node->attr.priority);
1205 if (prio > READ_ONCE(p->signaler->attr.priority))
1206 list_move_tail(&p->dfs_link, &dfs);
1211 * If we didn't need to bump any existing priorities, and we haven't
1212 * yet submitted this request (i.e. there is no potential race with
1213 * execlists_submit_request()), we can set our own priority and skip
1214 * acquiring the engine locks.
1216 if (request->sched.attr.priority == I915_PRIORITY_INVALID) {
1217 GEM_BUG_ON(!list_empty(&request->sched.link));
1218 request->sched.attr = *attr;
1219 if (stack.dfs_link.next == stack.dfs_link.prev)
1221 __list_del_entry(&stack.dfs_link);
1225 engine = request->engine;
1226 spin_lock_irq(&engine->timeline.lock);
1228 /* Fifo and depth-first replacement ensure our deps execute before us */
1229 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
1230 struct i915_sched_node *node = dep->signaler;
1232 INIT_LIST_HEAD(&dep->dfs_link);
1234 engine = sched_lock_engine(node, engine);
1236 if (prio <= node->attr.priority)
1239 node->attr.priority = prio;
1240 if (!list_empty(&node->link)) {
1241 if (last != engine) {
1242 pl = lookup_priolist(engine, prio);
1245 GEM_BUG_ON(pl->priority != prio);
1246 list_move_tail(&node->link, &pl->requests);
1249 if (prio > engine->execlists.queue_priority &&
1250 i915_sw_fence_done(&sched_to_request(node)->submit)) {
1251 /* defer submission until after all of our updates */
1252 __update_queue(engine, prio);
1253 tasklet_hi_schedule(&engine->execlists.tasklet);
1257 spin_unlock_irq(&engine->timeline.lock);
1260 static void execlists_context_destroy(struct intel_context *ce)
1262 GEM_BUG_ON(ce->pin_count);
1267 intel_ring_free(ce->ring);
1269 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1270 i915_gem_object_put(ce->state->obj);
1273 static void execlists_context_unpin(struct intel_context *ce)
1275 i915_gem_context_unpin_hw_id(ce->gem_context);
1277 intel_ring_unpin(ce->ring);
1279 ce->state->obj->pin_global--;
1280 i915_gem_object_unpin_map(ce->state->obj);
1281 i915_vma_unpin(ce->state);
1283 i915_gem_context_put(ce->gem_context);
1286 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1292 * Clear this page out of any CPU caches for coherent swap-in/out.
1293 * We only want to do this on the first bind so that we do not stall
1294 * on an active context (which by nature is already on the GPU).
1296 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1297 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1302 flags = PIN_GLOBAL | PIN_HIGH;
1303 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1305 return i915_vma_pin(vma, 0, 0, flags);
1308 static struct intel_context *
1309 __execlists_context_pin(struct intel_engine_cs *engine,
1310 struct i915_gem_context *ctx,
1311 struct intel_context *ce)
1316 ret = execlists_context_deferred_alloc(ctx, engine, ce);
1319 GEM_BUG_ON(!ce->state);
1321 ret = __context_pin(ctx, ce->state);
1325 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
1326 if (IS_ERR(vaddr)) {
1327 ret = PTR_ERR(vaddr);
1331 ret = intel_ring_pin(ce->ring);
1335 ret = i915_gem_context_pin_hw_id(ctx);
1339 intel_lr_context_descriptor_update(ctx, engine, ce);
1341 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1342 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1343 i915_ggtt_offset(ce->ring->vma);
1344 GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
1345 ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
1347 ce->state->obj->pin_global++;
1348 i915_gem_context_get(ctx);
1352 intel_ring_unpin(ce->ring);
1354 i915_gem_object_unpin_map(ce->state->obj);
1356 __i915_vma_unpin(ce->state);
1359 return ERR_PTR(ret);
1362 static const struct intel_context_ops execlists_context_ops = {
1363 .unpin = execlists_context_unpin,
1364 .destroy = execlists_context_destroy,
1367 static struct intel_context *
1368 execlists_context_pin(struct intel_engine_cs *engine,
1369 struct i915_gem_context *ctx)
1371 struct intel_context *ce = to_intel_context(ctx, engine);
1373 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1375 if (likely(ce->pin_count++))
1377 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1379 ce->ops = &execlists_context_ops;
1381 return __execlists_context_pin(engine, ctx, ce);
1384 static int execlists_request_alloc(struct i915_request *request)
1388 GEM_BUG_ON(!request->hw_context->pin_count);
1390 /* Flush enough space to reduce the likelihood of waiting after
1391 * we start building the request - in which case we will just
1392 * have to repeat work.
1394 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1396 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1400 /* Note that after this point, we have committed to using
1401 * this request as it is being used to both track the
1402 * state of engine initialisation and liveness of the
1403 * golden renderstate above. Think twice before you try
1404 * to cancel/unwind this request now.
1407 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1412 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1413 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1414 * but there is a slight complication as this is applied in WA batch where the
1415 * values are only initialized once so we cannot take register value at the
1416 * beginning and reuse it further; hence we save its value to memory, upload a
1417 * constant value with bit21 set and then we restore it back with the saved value.
1418 * To simplify the WA, a constant value is formed by using the default value
1419 * of this register. This shouldn't be a problem because we are only modifying
1420 * it for a short period and this batch in non-premptible. We can ofcourse
1421 * use additional instructions that read the actual value of the register
1422 * at that time and set our bit of interest but it makes the WA complicated.
1424 * This WA is also required for Gen9 so extracting as a function avoids
1428 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1430 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1431 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1432 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1435 *batch++ = MI_LOAD_REGISTER_IMM(1);
1436 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1437 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1439 batch = gen8_emit_pipe_control(batch,
1440 PIPE_CONTROL_CS_STALL |
1441 PIPE_CONTROL_DC_FLUSH_ENABLE,
1444 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1445 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1446 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1453 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1454 * initialized at the beginning and shared across all contexts but this field
1455 * helps us to have multiple batches at different offsets and select them based
1456 * on a criteria. At the moment this batch always start at the beginning of the page
1457 * and at this point we don't have multiple wa_ctx batch buffers.
1459 * The number of WA applied are not known at the beginning; we use this field
1460 * to return the no of DWORDS written.
1462 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1463 * so it adds NOOPs as padding to make it cacheline aligned.
1464 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1465 * makes a complete batch buffer.
1467 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1469 /* WaDisableCtxRestoreArbitration:bdw,chv */
1470 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1472 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1473 if (IS_BROADWELL(engine->i915))
1474 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1476 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1477 /* Actual scratch location is at 128 bytes offset */
1478 batch = gen8_emit_pipe_control(batch,
1479 PIPE_CONTROL_FLUSH_L3 |
1480 PIPE_CONTROL_GLOBAL_GTT_IVB |
1481 PIPE_CONTROL_CS_STALL |
1482 PIPE_CONTROL_QW_WRITE,
1483 i915_ggtt_offset(engine->scratch) +
1484 2 * CACHELINE_BYTES);
1486 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1488 /* Pad to end of cacheline */
1489 while ((unsigned long)batch % CACHELINE_BYTES)
1493 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1494 * execution depends on the length specified in terms of cache lines
1495 * in the register CTX_RCS_INDIRECT_CTX
1506 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1508 GEM_BUG_ON(!count || count > 63);
1510 *batch++ = MI_LOAD_REGISTER_IMM(count);
1512 *batch++ = i915_mmio_reg_offset(lri->reg);
1513 *batch++ = lri->value;
1514 } while (lri++, --count);
1520 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1522 static const struct lri lri[] = {
1523 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1525 COMMON_SLICE_CHICKEN2,
1526 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1533 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1534 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1540 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1541 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1545 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1547 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1548 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1550 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1552 /* WaClearSlmSpaceAtContextSwitch:kbl */
1553 /* Actual scratch location is at 128 bytes offset */
1554 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1555 batch = gen8_emit_pipe_control(batch,
1556 PIPE_CONTROL_FLUSH_L3 |
1557 PIPE_CONTROL_GLOBAL_GTT_IVB |
1558 PIPE_CONTROL_CS_STALL |
1559 PIPE_CONTROL_QW_WRITE,
1560 i915_ggtt_offset(engine->scratch)
1561 + 2 * CACHELINE_BYTES);
1564 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1565 if (HAS_POOLED_EU(engine->i915)) {
1567 * EU pool configuration is setup along with golden context
1568 * during context initialization. This value depends on
1569 * device type (2x6 or 3x6) and needs to be updated based
1570 * on which subslice is disabled especially for 2x6
1571 * devices, however it is safe to load default
1572 * configuration of 3x6 device instead of masking off
1573 * corresponding bits because HW ignores bits of a disabled
1574 * subslice and drops down to appropriate config. Please
1575 * see render_state_setup() in i915_gem_render_state.c for
1576 * possible configurations, to avoid duplication they are
1577 * not shown here again.
1579 *batch++ = GEN9_MEDIA_POOL_STATE;
1580 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1581 *batch++ = 0x00777000;
1587 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1589 /* Pad to end of cacheline */
1590 while ((unsigned long)batch % CACHELINE_BYTES)
1597 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1602 * WaPipeControlBefore3DStateSamplePattern: cnl
1604 * Ensure the engine is idle prior to programming a
1605 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1607 batch = gen8_emit_pipe_control(batch,
1608 PIPE_CONTROL_CS_STALL,
1611 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1612 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1613 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1614 * confusing. Since gen8_emit_pipe_control() already advances the
1615 * batch by 6 dwords, we advance the other 10 here, completing a
1616 * cacheline. It's not clear if the workaround requires this padding
1617 * before other commands, or if it's just the regular padding we would
1618 * already have for the workaround bb, so leave it here for now.
1620 for (i = 0; i < 10; i++)
1623 /* Pad to end of cacheline */
1624 while ((unsigned long)batch % CACHELINE_BYTES)
1630 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1632 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1634 struct drm_i915_gem_object *obj;
1635 struct i915_vma *vma;
1638 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1640 return PTR_ERR(obj);
1642 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
1648 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1652 engine->wa_ctx.vma = vma;
1656 i915_gem_object_put(obj);
1660 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1662 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1665 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1667 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1669 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1670 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1672 wa_bb_func_t wa_bb_fn[2];
1674 void *batch, *batch_ptr;
1678 if (GEM_WARN_ON(engine->id != RCS))
1681 switch (INTEL_GEN(engine->i915)) {
1685 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1689 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1693 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1697 MISSING_CASE(INTEL_GEN(engine->i915));
1701 ret = lrc_setup_wa_ctx(engine);
1703 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1707 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1708 batch = batch_ptr = kmap_atomic(page);
1711 * Emit the two workaround batch buffers, recording the offset from the
1712 * start of the workaround batch buffer object for each and their
1715 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1716 wa_bb[i]->offset = batch_ptr - batch;
1717 if (GEM_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1718 CACHELINE_BYTES))) {
1723 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1724 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1727 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1729 kunmap_atomic(batch);
1731 lrc_destroy_wa_ctx(engine);
1736 static void enable_execlists(struct intel_engine_cs *engine)
1738 struct drm_i915_private *dev_priv = engine->i915;
1740 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1743 * Make sure we're not enabling the new 12-deep CSB
1744 * FIFO as that requires a slightly updated handling
1745 * in the ctx switch irq. Since we're currently only
1746 * using only 2 elements of the enhanced execlists the
1747 * deeper FIFO it's not needed and it's not worth adding
1748 * more statements to the irq handler to support it.
1750 if (INTEL_GEN(dev_priv) >= 11)
1751 I915_WRITE(RING_MODE_GEN7(engine),
1752 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1754 I915_WRITE(RING_MODE_GEN7(engine),
1755 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1757 I915_WRITE(RING_MI_MODE(engine->mmio_base),
1758 _MASKED_BIT_DISABLE(STOP_RING));
1760 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1761 engine->status_page.ggtt_offset);
1762 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1765 static bool unexpected_starting_state(struct intel_engine_cs *engine)
1767 struct drm_i915_private *dev_priv = engine->i915;
1768 bool unexpected = false;
1770 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
1771 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
1778 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1780 intel_mocs_init_engine(engine);
1782 intel_engine_reset_breadcrumbs(engine);
1784 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
1785 struct drm_printer p = drm_debug_printer(__func__);
1787 intel_engine_dump(engine, &p, NULL);
1790 enable_execlists(engine);
1795 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1797 struct drm_i915_private *dev_priv = engine->i915;
1800 ret = gen8_init_common_ring(engine);
1804 intel_whitelist_workarounds_apply(engine);
1806 /* We need to disable the AsyncFlip performance optimisations in order
1807 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1808 * programmed to '1' on all products.
1810 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1812 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1814 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1819 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1823 ret = gen8_init_common_ring(engine);
1827 intel_whitelist_workarounds_apply(engine);
1832 static struct i915_request *
1833 execlists_reset_prepare(struct intel_engine_cs *engine)
1835 struct intel_engine_execlists * const execlists = &engine->execlists;
1836 struct i915_request *request, *active;
1837 unsigned long flags;
1839 GEM_TRACE("%s: depth<-%d\n", engine->name,
1840 atomic_read(&execlists->tasklet.count));
1843 * Prevent request submission to the hardware until we have
1844 * completed the reset in i915_gem_reset_finish(). If a request
1845 * is completed by one engine, it may then queue a request
1846 * to a second via its execlists->tasklet *just* as we are
1847 * calling engine->init_hw() and also writing the ELSP.
1848 * Turning off the execlists->tasklet until the reset is over
1849 * prevents the race.
1851 __tasklet_disable_sync_once(&execlists->tasklet);
1853 spin_lock_irqsave(&engine->timeline.lock, flags);
1856 * We want to flush the pending context switches, having disabled
1857 * the tasklet above, we can assume exclusive access to the execlists.
1858 * For this allows us to catch up with an inflight preemption event,
1859 * and avoid blaming an innocent request if the stall was due to the
1860 * preemption itself.
1862 process_csb(engine);
1865 * The last active request can then be no later than the last request
1866 * now in ELSP[0]. So search backwards from there, so that if the GPU
1867 * has advanced beyond the last CSB update, it will be pardoned.
1870 request = port_request(execlists->port);
1873 * Prevent the breadcrumb from advancing before we decide
1874 * which request is currently active.
1876 intel_engine_stop_cs(engine);
1878 list_for_each_entry_from_reverse(request,
1879 &engine->timeline.requests,
1881 if (__i915_request_completed(request,
1882 request->global_seqno))
1889 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1894 static void execlists_reset(struct intel_engine_cs *engine,
1895 struct i915_request *request)
1897 struct intel_engine_execlists * const execlists = &engine->execlists;
1898 unsigned long flags;
1901 GEM_TRACE("%s request global=%x, current=%d\n",
1902 engine->name, request ? request->global_seqno : 0,
1903 intel_engine_get_seqno(engine));
1905 spin_lock_irqsave(&engine->timeline.lock, flags);
1908 * Catch up with any missed context-switch interrupts.
1910 * Ideally we would just read the remaining CSB entries now that we
1911 * know the gpu is idle. However, the CSB registers are sometimes^W
1912 * often trashed across a GPU reset! Instead we have to rely on
1913 * guessing the missed context-switch events by looking at what
1914 * requests were completed.
1916 execlists_cancel_port_requests(execlists);
1918 /* Push back any incomplete requests for replay after the reset. */
1919 __unwind_incomplete_requests(engine);
1921 /* Following the reset, we need to reload the CSB read/write pointers */
1922 reset_csb_pointers(&engine->execlists);
1924 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1927 * If the request was innocent, we leave the request in the ELSP
1928 * and will try to replay it on restarting. The context image may
1929 * have been corrupted by the reset, in which case we may have
1930 * to service a new GPU hang, but more likely we can continue on
1933 * If the request was guilty, we presume the context is corrupt
1934 * and have to at least restore the RING register in the context
1935 * image back to the expected values to skip over the guilty request.
1937 if (!request || request->fence.error != -EIO)
1941 * We want a simple context + ring to execute the breadcrumb update.
1942 * We cannot rely on the context being intact across the GPU hang,
1943 * so clear it and rebuild just what we need for the breadcrumb.
1944 * All pending requests for this context will be zapped, and any
1945 * future request will be after userspace has had the opportunity
1946 * to recreate its own state.
1948 regs = request->hw_context->lrc_reg_state;
1949 if (engine->pinned_default_state) {
1950 memcpy(regs, /* skip restoring the vanilla PPHWSP */
1951 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
1952 engine->context_size - PAGE_SIZE);
1954 execlists_init_reg_state(regs,
1955 request->gem_context, engine, request->ring);
1957 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1958 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
1960 request->ring->head = intel_ring_wrap(request->ring, request->postfix);
1961 regs[CTX_RING_HEAD + 1] = request->ring->head;
1963 intel_ring_update_space(request->ring);
1965 /* Reset WaIdleLiteRestore:bdw,skl as well */
1966 unwind_wa_tail(request);
1969 static void execlists_reset_finish(struct intel_engine_cs *engine)
1971 struct intel_engine_execlists * const execlists = &engine->execlists;
1974 * After a GPU reset, we may have requests to replay. Do so now while
1975 * we still have the forcewake to be sure that the GPU is not allowed
1976 * to sleep before we restart and reload a context.
1979 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
1980 execlists->tasklet.func(execlists->tasklet.data);
1982 tasklet_enable(&execlists->tasklet);
1983 GEM_TRACE("%s: depth->%d\n", engine->name,
1984 atomic_read(&execlists->tasklet.count));
1987 static int intel_logical_ring_emit_pdps(struct i915_request *rq)
1989 struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
1990 struct intel_engine_cs *engine = rq->engine;
1991 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1995 cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2);
1999 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
2000 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
2001 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
2003 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
2004 *cs++ = upper_32_bits(pd_daddr);
2005 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
2006 *cs++ = lower_32_bits(pd_daddr);
2010 intel_ring_advance(rq, cs);
2015 static int gen8_emit_bb_start(struct i915_request *rq,
2016 u64 offset, u32 len,
2017 const unsigned int flags)
2022 /* Don't rely in hw updating PDPs, specially in lite-restore.
2023 * Ideally, we should set Force PD Restore in ctx descriptor,
2024 * but we can't. Force Restore would be a second option, but
2025 * it is unsafe in case of lite-restore (because the ctx is
2026 * not idle). PML4 is allocated during ppgtt init so this is
2027 * not needed in 48-bit.*/
2028 if (rq->gem_context->ppgtt &&
2029 (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
2030 !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
2031 !intel_vgpu_active(rq->i915)) {
2032 ret = intel_logical_ring_emit_pdps(rq);
2036 rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
2039 cs = intel_ring_begin(rq, 6);
2044 * WaDisableCtxRestoreArbitration:bdw,chv
2046 * We don't need to perform MI_ARB_ENABLE as often as we do (in
2047 * particular all the gen that do not need the w/a at all!), if we
2048 * took care to make sure that on every switch into this context
2049 * (both ordinary and for preemption) that arbitrartion was enabled
2050 * we would be fine. However, there doesn't seem to be a downside to
2051 * being paranoid and making sure it is set before each batch and
2052 * every context-switch.
2054 * Note that if we fail to enable arbitration before the request
2055 * is complete, then we do not see the context-switch interrupt and
2056 * the engine hangs (with RING_HEAD == RING_TAIL).
2058 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
2060 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2062 /* FIXME(BDW): Address space and security selectors. */
2063 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2064 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2065 *cs++ = lower_32_bits(offset);
2066 *cs++ = upper_32_bits(offset);
2068 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2070 intel_ring_advance(rq, cs);
2075 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
2077 struct drm_i915_private *dev_priv = engine->i915;
2078 I915_WRITE_IMR(engine,
2079 ~(engine->irq_enable_mask | engine->irq_keep_mask));
2080 POSTING_READ_FW(RING_IMR(engine->mmio_base));
2083 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
2085 struct drm_i915_private *dev_priv = engine->i915;
2086 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
2089 static int gen8_emit_flush(struct i915_request *request, u32 mode)
2093 cs = intel_ring_begin(request, 4);
2097 cmd = MI_FLUSH_DW + 1;
2099 /* We always require a command barrier so that subsequent
2100 * commands, such as breadcrumb interrupts, are strictly ordered
2101 * wrt the contents of the write cache being flushed to memory
2102 * (and thus being coherent from the CPU).
2104 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2106 if (mode & EMIT_INVALIDATE) {
2107 cmd |= MI_INVALIDATE_TLB;
2108 if (request->engine->id == VCS)
2109 cmd |= MI_INVALIDATE_BSD;
2113 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2114 *cs++ = 0; /* upper addr */
2115 *cs++ = 0; /* value */
2116 intel_ring_advance(request, cs);
2121 static int gen8_emit_flush_render(struct i915_request *request,
2124 struct intel_engine_cs *engine = request->engine;
2126 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
2127 bool vf_flush_wa = false, dc_flush_wa = false;
2131 flags |= PIPE_CONTROL_CS_STALL;
2133 if (mode & EMIT_FLUSH) {
2134 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2135 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2136 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2137 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2140 if (mode & EMIT_INVALIDATE) {
2141 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2142 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2143 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2144 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2145 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2146 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2147 flags |= PIPE_CONTROL_QW_WRITE;
2148 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2151 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2154 if (IS_GEN9(request->i915))
2157 /* WaForGAMHang:kbl */
2158 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2170 cs = intel_ring_begin(request, len);
2175 cs = gen8_emit_pipe_control(cs, 0, 0);
2178 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2181 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2184 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2186 intel_ring_advance(request, cs);
2192 * Reserve space for 2 NOOPs at the end of each request to be
2193 * used as a workaround for not being allowed to do lite
2194 * restore with HEAD==TAIL (WaIdleLiteRestore).
2196 static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2198 /* Ensure there's always at least one preemption point per-request. */
2199 *cs++ = MI_ARB_CHECK;
2201 request->wa_tail = intel_ring_offset(request, cs);
2204 static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
2206 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
2207 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
2209 cs = gen8_emit_ggtt_write(cs, request->global_seqno,
2210 intel_hws_seqno_address(request->engine));
2211 *cs++ = MI_USER_INTERRUPT;
2212 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2213 request->tail = intel_ring_offset(request, cs);
2214 assert_ring_tail_valid(request->ring, request->tail);
2216 gen8_emit_wa_tail(request, cs);
2218 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
2220 static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2222 /* We're using qword write, seqno should be aligned to 8 bytes. */
2223 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
2225 cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
2226 intel_hws_seqno_address(request->engine));
2227 *cs++ = MI_USER_INTERRUPT;
2228 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2229 request->tail = intel_ring_offset(request, cs);
2230 assert_ring_tail_valid(request->ring, request->tail);
2232 gen8_emit_wa_tail(request, cs);
2234 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
2236 static int gen8_init_rcs_context(struct i915_request *rq)
2240 ret = intel_ctx_workarounds_emit(rq);
2244 ret = intel_rcs_context_init_mocs(rq);
2246 * Failing to program the MOCS is non-fatal.The system will not
2247 * run at peak performance. So generate an error and carry on.
2250 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2252 return i915_gem_render_state_emit(rq);
2256 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2257 * @engine: Engine Command Streamer.
2259 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2261 struct drm_i915_private *dev_priv;
2264 * Tasklet cannot be active at this point due intel_mark_active/idle
2265 * so this is just for documentation.
2267 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
2268 &engine->execlists.tasklet.state)))
2269 tasklet_kill(&engine->execlists.tasklet);
2271 dev_priv = engine->i915;
2273 if (engine->buffer) {
2274 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2277 if (engine->cleanup)
2278 engine->cleanup(engine);
2280 intel_engine_cleanup_common(engine);
2282 lrc_destroy_wa_ctx(engine);
2284 engine->i915 = NULL;
2285 dev_priv->engine[engine->id] = NULL;
2289 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2291 engine->submit_request = execlists_submit_request;
2292 engine->cancel_requests = execlists_cancel_requests;
2293 engine->schedule = execlists_schedule;
2294 engine->execlists.tasklet.func = execlists_submission_tasklet;
2296 engine->reset.prepare = execlists_reset_prepare;
2298 engine->park = NULL;
2299 engine->unpark = NULL;
2301 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2302 if (engine->i915->preempt_context)
2303 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2305 engine->i915->caps.scheduler =
2306 I915_SCHEDULER_CAP_ENABLED |
2307 I915_SCHEDULER_CAP_PRIORITY;
2308 if (intel_engine_has_preemption(engine))
2309 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
2313 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2315 /* Default vfuncs which can be overriden by each engine. */
2316 engine->init_hw = gen8_init_common_ring;
2318 engine->reset.prepare = execlists_reset_prepare;
2319 engine->reset.reset = execlists_reset;
2320 engine->reset.finish = execlists_reset_finish;
2322 engine->context_pin = execlists_context_pin;
2323 engine->request_alloc = execlists_request_alloc;
2325 engine->emit_flush = gen8_emit_flush;
2326 engine->emit_breadcrumb = gen8_emit_breadcrumb;
2327 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
2329 engine->set_default_submission = intel_execlists_set_default_submission;
2331 if (INTEL_GEN(engine->i915) < 11) {
2332 engine->irq_enable = gen8_logical_ring_enable_irq;
2333 engine->irq_disable = gen8_logical_ring_disable_irq;
2336 * TODO: On Gen11 interrupt masks need to be clear
2337 * to allow C6 entry. Keep interrupts enabled at
2338 * and take the hit of generating extra interrupts
2339 * until a more refined solution exists.
2342 engine->emit_bb_start = gen8_emit_bb_start;
2346 logical_ring_default_irqs(struct intel_engine_cs *engine)
2348 unsigned int shift = 0;
2350 if (INTEL_GEN(engine->i915) < 11) {
2351 const u8 irq_shifts[] = {
2352 [RCS] = GEN8_RCS_IRQ_SHIFT,
2353 [BCS] = GEN8_BCS_IRQ_SHIFT,
2354 [VCS] = GEN8_VCS1_IRQ_SHIFT,
2355 [VCS2] = GEN8_VCS2_IRQ_SHIFT,
2356 [VECS] = GEN8_VECS_IRQ_SHIFT,
2359 shift = irq_shifts[engine->id];
2362 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2363 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2367 logical_ring_setup(struct intel_engine_cs *engine)
2369 intel_engine_setup_common(engine);
2371 /* Intentionally left blank. */
2372 engine->buffer = NULL;
2374 tasklet_init(&engine->execlists.tasklet,
2375 execlists_submission_tasklet, (unsigned long)engine);
2377 logical_ring_default_vfuncs(engine);
2378 logical_ring_default_irqs(engine);
2381 static bool csb_force_mmio(struct drm_i915_private *i915)
2383 /* Older GVT emulation depends upon intercepting CSB mmio */
2384 return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
2387 static int logical_ring_init(struct intel_engine_cs *engine)
2389 struct drm_i915_private *i915 = engine->i915;
2390 struct intel_engine_execlists * const execlists = &engine->execlists;
2393 ret = intel_engine_init_common(engine);
2397 if (HAS_LOGICAL_RING_ELSQ(i915)) {
2398 execlists->submit_reg = i915->regs +
2399 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
2400 execlists->ctrl_reg = i915->regs +
2401 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
2403 execlists->submit_reg = i915->regs +
2404 i915_mmio_reg_offset(RING_ELSP(engine));
2407 execlists->preempt_complete_status = ~0u;
2408 if (i915->preempt_context) {
2409 struct intel_context *ce =
2410 to_intel_context(i915->preempt_context, engine);
2412 execlists->preempt_complete_status =
2413 upper_32_bits(ce->lrc_desc);
2416 execlists->csb_read =
2417 i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
2418 if (csb_force_mmio(i915)) {
2419 execlists->csb_status = (u32 __force *)
2420 (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
2422 execlists->csb_write = (u32 __force *)execlists->csb_read;
2423 execlists->csb_write_reset =
2424 _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
2425 GEN8_CSB_ENTRIES - 1);
2427 execlists->csb_status =
2428 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
2430 execlists->csb_write =
2431 &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
2432 execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
2434 reset_csb_pointers(execlists);
2439 intel_logical_ring_cleanup(engine);
2443 int logical_render_ring_init(struct intel_engine_cs *engine)
2445 struct drm_i915_private *dev_priv = engine->i915;
2448 logical_ring_setup(engine);
2450 if (HAS_L3_DPF(dev_priv))
2451 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2453 /* Override some for render ring. */
2454 if (INTEL_GEN(dev_priv) >= 9)
2455 engine->init_hw = gen9_init_render_ring;
2457 engine->init_hw = gen8_init_render_ring;
2458 engine->init_context = gen8_init_rcs_context;
2459 engine->emit_flush = gen8_emit_flush_render;
2460 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2461 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2463 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2467 ret = intel_init_workaround_bb(engine);
2470 * We continue even if we fail to initialize WA batch
2471 * because we only expect rare glitches but nothing
2472 * critical to prevent us from using GPU
2474 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2478 return logical_ring_init(engine);
2481 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2483 logical_ring_setup(engine);
2485 return logical_ring_init(engine);
2489 make_rpcs(struct drm_i915_private *dev_priv)
2491 bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
2492 u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
2493 u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
2497 * No explicit RPCS request is needed to ensure full
2498 * slice/subslice/EU enablement prior to Gen9.
2500 if (INTEL_GEN(dev_priv) < 9)
2504 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
2505 * wide and Icelake has up to eight subslices, specfial programming is
2506 * needed in order to correctly enable all subslices.
2508 * According to documentation software must consider the configuration
2509 * as 2x4x8 and hardware will translate this to 1x8x8.
2511 * Furthemore, even though SScount is three bits, maximum documented
2512 * value for it is four. From this some rules/restrictions follow:
2515 * If enabled subslice count is greater than four, two whole slices must
2516 * be enabled instead.
2519 * When more than one slice is enabled, hardware ignores the subslice
2522 * From these restrictions it follows that it is not possible to enable
2523 * a count of subslices between the SScount maximum of four restriction,
2524 * and the maximum available number on a particular SKU. Either all
2525 * subslices are enabled, or a count between one and four on the first
2528 if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) {
2529 GEM_BUG_ON(subslices & 1);
2531 subslice_pg = false;
2536 * Starting in Gen9, render power gating can leave
2537 * slice/subslice/EU in a partially enabled state. We
2538 * must make an explicit request through RPCS for full
2541 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2542 u32 mask, val = slices;
2544 if (INTEL_GEN(dev_priv) >= 11) {
2545 mask = GEN11_RPCS_S_CNT_MASK;
2546 val <<= GEN11_RPCS_S_CNT_SHIFT;
2548 mask = GEN8_RPCS_S_CNT_MASK;
2549 val <<= GEN8_RPCS_S_CNT_SHIFT;
2552 GEM_BUG_ON(val & ~mask);
2555 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
2559 u32 val = subslices;
2561 val <<= GEN8_RPCS_SS_CNT_SHIFT;
2563 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
2564 val &= GEN8_RPCS_SS_CNT_MASK;
2566 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
2569 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2572 val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2573 GEN8_RPCS_EU_MIN_SHIFT;
2574 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
2575 val &= GEN8_RPCS_EU_MIN_MASK;
2579 val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2580 GEN8_RPCS_EU_MAX_SHIFT;
2581 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
2582 val &= GEN8_RPCS_EU_MAX_MASK;
2586 rpcs |= GEN8_RPCS_ENABLE;
2592 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2594 u32 indirect_ctx_offset;
2596 switch (INTEL_GEN(engine->i915)) {
2598 MISSING_CASE(INTEL_GEN(engine->i915));
2601 indirect_ctx_offset =
2602 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2605 indirect_ctx_offset =
2606 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2609 indirect_ctx_offset =
2610 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2613 indirect_ctx_offset =
2614 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2618 return indirect_ctx_offset;
2621 static void execlists_init_reg_state(u32 *regs,
2622 struct i915_gem_context *ctx,
2623 struct intel_engine_cs *engine,
2624 struct intel_ring *ring)
2626 struct drm_i915_private *dev_priv = engine->i915;
2627 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2628 u32 base = engine->mmio_base;
2629 bool rcs = engine->class == RENDER_CLASS;
2631 /* A context is actually a big batch buffer with several
2632 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2633 * values we are setting here are only for the first context restore:
2634 * on a subsequent save, the GPU will recreate this batchbuffer with new
2635 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2636 * we are not initializing here).
2638 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2639 MI_LRI_FORCE_POSTED;
2641 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2642 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
2643 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
2644 if (INTEL_GEN(dev_priv) < 11) {
2645 regs[CTX_CONTEXT_CONTROL + 1] |=
2646 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
2647 CTX_CTRL_RS_CTX_ENABLE);
2649 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2650 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2651 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2652 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2653 RING_CTL_SIZE(ring->size) | RING_VALID);
2654 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2655 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2656 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2657 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2658 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2659 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2661 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2663 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2664 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2665 RING_INDIRECT_CTX_OFFSET(base), 0);
2666 if (wa_ctx->indirect_ctx.size) {
2667 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2669 regs[CTX_RCS_INDIRECT_CTX + 1] =
2670 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2671 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2673 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2674 intel_lr_indirect_ctx_offset(engine) << 6;
2677 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2678 if (wa_ctx->per_ctx.size) {
2679 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2681 regs[CTX_BB_PER_CTX_PTR + 1] =
2682 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2686 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2688 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2689 /* PDP values well be assigned later if needed */
2690 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2691 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2692 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2693 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2694 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2695 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2696 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2697 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2699 if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
2700 /* 64b PPGTT (48bit canonical)
2701 * PDP0_DESCRIPTOR contains the base address to PML4 and
2702 * other PDP Descriptors are ignored.
2704 ASSIGN_CTX_PML4(ppgtt, regs);
2708 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2709 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2710 make_rpcs(dev_priv));
2712 i915_oa_init_reg_state(engine, ctx, regs);
2715 regs[CTX_END] = MI_BATCH_BUFFER_END;
2716 if (INTEL_GEN(dev_priv) >= 10)
2717 regs[CTX_END] |= BIT(0);
2721 populate_lr_context(struct i915_gem_context *ctx,
2722 struct drm_i915_gem_object *ctx_obj,
2723 struct intel_engine_cs *engine,
2724 struct intel_ring *ring)
2730 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2732 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2736 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2737 if (IS_ERR(vaddr)) {
2738 ret = PTR_ERR(vaddr);
2739 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2742 ctx_obj->mm.dirty = true;
2744 if (engine->default_state) {
2746 * We only want to copy over the template context state;
2747 * skipping over the headers reserved for GuC communication,
2748 * leaving those as zero.
2750 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2753 defaults = i915_gem_object_pin_map(engine->default_state,
2755 if (IS_ERR(defaults)) {
2756 ret = PTR_ERR(defaults);
2760 memcpy(vaddr + start, defaults + start, engine->context_size);
2761 i915_gem_object_unpin_map(engine->default_state);
2764 /* The second page of the context object contains some fields which must
2765 * be set up prior to the first execution. */
2766 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2767 execlists_init_reg_state(regs, ctx, engine, ring);
2768 if (!engine->default_state)
2769 regs[CTX_CONTEXT_CONTROL + 1] |=
2770 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2771 if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
2772 regs[CTX_CONTEXT_CONTROL + 1] |=
2773 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2774 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2777 i915_gem_object_unpin_map(ctx_obj);
2781 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2782 struct intel_engine_cs *engine,
2783 struct intel_context *ce)
2785 struct drm_i915_gem_object *ctx_obj;
2786 struct i915_vma *vma;
2787 uint32_t context_size;
2788 struct intel_ring *ring;
2789 struct i915_timeline *timeline;
2795 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2798 * Before the actual start of the context image, we insert a few pages
2799 * for our own use and for sharing with the GuC.
2801 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2803 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2804 if (IS_ERR(ctx_obj))
2805 return PTR_ERR(ctx_obj);
2807 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.vm, NULL);
2810 goto error_deref_obj;
2813 timeline = i915_timeline_create(ctx->i915, ctx->name);
2814 if (IS_ERR(timeline)) {
2815 ret = PTR_ERR(timeline);
2816 goto error_deref_obj;
2819 ring = intel_engine_create_ring(engine, timeline, ctx->ring_size);
2820 i915_timeline_put(timeline);
2822 ret = PTR_ERR(ring);
2823 goto error_deref_obj;
2826 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2828 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2829 goto error_ring_free;
2838 intel_ring_free(ring);
2840 i915_gem_object_put(ctx_obj);
2844 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2846 struct intel_engine_cs *engine;
2847 struct i915_gem_context *ctx;
2848 enum intel_engine_id id;
2850 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2851 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2852 * that stored in context. As we only write new commands from
2853 * ce->ring->tail onwards, everything before that is junk. If the GPU
2854 * starts reading from its RING_HEAD from the context, it may try to
2855 * execute that junk and die.
2857 * So to avoid that we reset the context images upon resume. For
2858 * simplicity, we just zero everything out.
2860 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
2861 for_each_engine(engine, dev_priv, id) {
2862 struct intel_context *ce =
2863 to_intel_context(ctx, engine);
2869 reg = i915_gem_object_pin_map(ce->state->obj,
2871 if (WARN_ON(IS_ERR(reg)))
2874 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2875 reg[CTX_RING_HEAD+1] = 0;
2876 reg[CTX_RING_TAIL+1] = 0;
2878 ce->state->obj->mm.dirty = true;
2879 i915_gem_object_unpin_map(ce->state->obj);
2881 intel_ring_reset(ce->ring, 0);
2886 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2887 #include "selftests/intel_lrc.c"