2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include <drm/drm_hdcp.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
43 /* Map gmbus pin pairs to names and registers. */
44 static const struct gmbus_pin gmbus_pins[] = {
45 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
46 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
47 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
48 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
49 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
50 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
53 static const struct gmbus_pin gmbus_pins_bdw[] = {
54 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
55 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
56 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
57 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
60 static const struct gmbus_pin gmbus_pins_skl[] = {
61 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
62 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
63 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
66 static const struct gmbus_pin gmbus_pins_bxt[] = {
67 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
68 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
69 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
72 static const struct gmbus_pin gmbus_pins_cnp[] = {
73 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
74 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
75 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
76 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
79 static const struct gmbus_pin gmbus_pins_icp[] = {
80 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
81 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
82 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
83 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
84 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
85 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
88 /* pin is expected to be valid */
89 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
92 if (HAS_PCH_ICP(dev_priv))
93 return &gmbus_pins_icp[pin];
94 else if (HAS_PCH_CNP(dev_priv))
95 return &gmbus_pins_cnp[pin];
96 else if (IS_GEN9_LP(dev_priv))
97 return &gmbus_pins_bxt[pin];
98 else if (IS_GEN9_BC(dev_priv))
99 return &gmbus_pins_skl[pin];
100 else if (IS_BROADWELL(dev_priv))
101 return &gmbus_pins_bdw[pin];
103 return &gmbus_pins[pin];
106 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
111 if (HAS_PCH_ICP(dev_priv))
112 size = ARRAY_SIZE(gmbus_pins_icp);
113 else if (HAS_PCH_CNP(dev_priv))
114 size = ARRAY_SIZE(gmbus_pins_cnp);
115 else if (IS_GEN9_LP(dev_priv))
116 size = ARRAY_SIZE(gmbus_pins_bxt);
117 else if (IS_GEN9_BC(dev_priv))
118 size = ARRAY_SIZE(gmbus_pins_skl);
119 else if (IS_BROADWELL(dev_priv))
120 size = ARRAY_SIZE(gmbus_pins_bdw);
122 size = ARRAY_SIZE(gmbus_pins);
124 return pin < size && get_gmbus_pin(dev_priv, pin)->name;
127 /* Intel GPIO access functions */
129 #define I2C_RISEFALL_TIME 10
131 static inline struct intel_gmbus *
132 to_intel_gmbus(struct i2c_adapter *i2c)
134 return container_of(i2c, struct intel_gmbus, adapter);
138 intel_i2c_reset(struct drm_i915_private *dev_priv)
140 I915_WRITE(GMBUS0, 0);
141 I915_WRITE(GMBUS4, 0);
144 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
149 /* When using bit bashing for I2C, this bit needs to be set to 1 */
150 val = I915_READ(DSPCLK_GATE_D);
152 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
154 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
155 I915_WRITE(DSPCLK_GATE_D, val);
158 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
163 val = I915_READ(SOUTH_DSPCLK_GATE_D);
165 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
167 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
168 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
171 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
176 val = I915_READ(GEN9_CLKGATE_DIS_4);
178 val |= BXT_GMBUS_GATING_DIS;
180 val &= ~BXT_GMBUS_GATING_DIS;
181 I915_WRITE(GEN9_CLKGATE_DIS_4, val);
184 static u32 get_reserved(struct intel_gmbus *bus)
186 struct drm_i915_private *dev_priv = bus->dev_priv;
189 /* On most chips, these bits must be preserved in software. */
190 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
191 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
192 (GPIO_DATA_PULLUP_DISABLE |
193 GPIO_CLOCK_PULLUP_DISABLE);
198 static int get_clock(void *data)
200 struct intel_gmbus *bus = data;
201 struct drm_i915_private *dev_priv = bus->dev_priv;
202 u32 reserved = get_reserved(bus);
203 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
204 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
205 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
208 static int get_data(void *data)
210 struct intel_gmbus *bus = data;
211 struct drm_i915_private *dev_priv = bus->dev_priv;
212 u32 reserved = get_reserved(bus);
213 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
214 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
215 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
218 static void set_clock(void *data, int state_high)
220 struct intel_gmbus *bus = data;
221 struct drm_i915_private *dev_priv = bus->dev_priv;
222 u32 reserved = get_reserved(bus);
226 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
228 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
231 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
232 POSTING_READ(bus->gpio_reg);
235 static void set_data(void *data, int state_high)
237 struct intel_gmbus *bus = data;
238 struct drm_i915_private *dev_priv = bus->dev_priv;
239 u32 reserved = get_reserved(bus);
243 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
245 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
248 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
249 POSTING_READ(bus->gpio_reg);
253 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
255 struct intel_gmbus *bus = container_of(adapter,
258 struct drm_i915_private *dev_priv = bus->dev_priv;
260 intel_i2c_reset(dev_priv);
262 if (IS_PINEVIEW(dev_priv))
263 pnv_gmbus_clock_gating(dev_priv, false);
267 udelay(I2C_RISEFALL_TIME);
272 intel_gpio_post_xfer(struct i2c_adapter *adapter)
274 struct intel_gmbus *bus = container_of(adapter,
277 struct drm_i915_private *dev_priv = bus->dev_priv;
282 if (IS_PINEVIEW(dev_priv))
283 pnv_gmbus_clock_gating(dev_priv, true);
287 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
289 struct drm_i915_private *dev_priv = bus->dev_priv;
290 struct i2c_algo_bit_data *algo;
292 algo = &bus->bit_algo;
294 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
295 bus->adapter.algo_data = algo;
296 algo->setsda = set_data;
297 algo->setscl = set_clock;
298 algo->getsda = get_data;
299 algo->getscl = get_clock;
300 algo->pre_xfer = intel_gpio_pre_xfer;
301 algo->post_xfer = intel_gpio_post_xfer;
302 algo->udelay = I2C_RISEFALL_TIME;
303 algo->timeout = usecs_to_jiffies(2200);
307 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
313 /* Important: The hw handles only the first bit, so set only one! Since
314 * we also need to check for NAKs besides the hw ready/idle signal, we
315 * need to wake up periodically and check that ourselves.
317 if (!HAS_GMBUS_IRQ(dev_priv))
320 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
321 I915_WRITE_FW(GMBUS4, irq_en);
323 status |= GMBUS_SATOER;
324 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
326 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
328 I915_WRITE_FW(GMBUS4, 0);
329 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
331 if (gmbus2 & GMBUS_SATOER)
338 gmbus_wait_idle(struct drm_i915_private *dev_priv)
344 /* Important: The hw handles only the first bit, so set only one! */
346 if (HAS_GMBUS_IRQ(dev_priv))
347 irq_enable = GMBUS_IDLE_EN;
349 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
350 I915_WRITE_FW(GMBUS4, irq_enable);
352 ret = intel_wait_for_register_fw(dev_priv,
353 GMBUS2, GMBUS_ACTIVE, 0,
356 I915_WRITE_FW(GMBUS4, 0);
357 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
363 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
365 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
366 GMBUS_BYTE_COUNT_MAX;
370 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
371 unsigned short addr, u8 *buf, unsigned int len,
372 u32 gmbus0_reg, u32 gmbus1_index)
374 unsigned int size = len;
375 bool burst_read = len > gmbus_max_xfer_size(dev_priv);
376 bool extra_byte_added = false;
380 * As per HW Spec, for 512Bytes need to read extra Byte and
381 * Ignore the extra byte read.
384 extra_byte_added = true;
387 size = len % 256 + 256;
388 I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
391 I915_WRITE_FW(GMBUS1,
394 (size << GMBUS_BYTE_COUNT_SHIFT) |
395 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
396 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
401 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
405 val = I915_READ_FW(GMBUS3);
407 if (extra_byte_added && len == 1)
412 } while (--len && ++loop < 4);
414 if (burst_read && len == size - 4)
415 /* Reset the override bit */
416 I915_WRITE_FW(GMBUS0, gmbus0_reg);
423 * HW spec says that 512Bytes in Burst read need special treatment.
424 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
425 * an I2C slave, which supports such a lengthy burst read too for experiments.
427 * So until things get clarified on HW support, to avoid the burst read length
428 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
430 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
433 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
434 u32 gmbus0_reg, u32 gmbus1_index)
437 unsigned int rx_size = msg->len;
442 if (HAS_GMBUS_BURST_READ(dev_priv))
443 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
445 len = min(rx_size, gmbus_max_xfer_size(dev_priv));
447 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
448 gmbus0_reg, gmbus1_index);
454 } while (rx_size != 0);
460 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
461 unsigned short addr, u8 *buf, unsigned int len,
464 unsigned int chunk_size = len;
468 while (len && loop < 4) {
469 val |= *buf++ << (8 * loop++);
473 I915_WRITE_FW(GMBUS3, val);
474 I915_WRITE_FW(GMBUS1,
475 gmbus1_index | GMBUS_CYCLE_WAIT |
476 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
477 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
478 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
484 val |= *buf++ << (8 * loop);
485 } while (--len && ++loop < 4);
487 I915_WRITE_FW(GMBUS3, val);
489 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
498 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
502 unsigned int tx_size = msg->len;
507 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
509 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
516 } while (tx_size != 0);
522 * The gmbus controller can combine a 1 or 2 byte write with another read/write
523 * that immediately follows it by using an "INDEX" cycle.
526 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
528 return (i + 1 < num &&
529 msgs[i].addr == msgs[i + 1].addr &&
530 !(msgs[i].flags & I2C_M_RD) &&
531 (msgs[i].len == 1 || msgs[i].len == 2) &&
532 msgs[i + 1].len > 0);
536 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
539 u32 gmbus1_index = 0;
543 if (msgs[0].len == 2)
544 gmbus5 = GMBUS_2BYTE_INDEX_EN |
545 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
546 if (msgs[0].len == 1)
547 gmbus1_index = GMBUS_CYCLE_INDEX |
548 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
550 /* GMBUS5 holds 16-bit index */
552 I915_WRITE_FW(GMBUS5, gmbus5);
554 if (msgs[1].flags & I2C_M_RD)
555 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
558 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
560 /* Clear GMBUS5 after each index transfer */
562 I915_WRITE_FW(GMBUS5, 0);
568 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
571 struct intel_gmbus *bus = container_of(adapter,
574 struct drm_i915_private *dev_priv = bus->dev_priv;
575 int i = 0, inc, try = 0;
578 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
579 if (IS_GEN9_LP(dev_priv))
580 bxt_gmbus_clock_gating(dev_priv, false);
581 else if (HAS_PCH_SPT(dev_priv) ||
582 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
583 pch_gmbus_clock_gating(dev_priv, false);
586 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
588 for (; i < num; i += inc) {
590 if (gmbus_is_index_xfer(msgs, i, num)) {
591 ret = gmbus_index_xfer(dev_priv, &msgs[i],
592 gmbus0_source | bus->reg0);
593 inc = 2; /* an index transmission is two msgs */
594 } else if (msgs[i].flags & I2C_M_RD) {
595 ret = gmbus_xfer_read(dev_priv, &msgs[i],
596 gmbus0_source | bus->reg0, 0);
598 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
602 ret = gmbus_wait(dev_priv,
603 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
604 if (ret == -ETIMEDOUT)
610 /* Generate a STOP condition on the bus. Note that gmbus can't generata
611 * a STOP on the very first cycle. To simplify the code we
612 * unconditionally generate the STOP condition with an additional gmbus
614 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
616 /* Mark the GMBUS interface as disabled after waiting for idle.
617 * We will re-enable it at the start of the next xfer,
618 * till then let it sleep.
620 if (gmbus_wait_idle(dev_priv)) {
621 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
625 I915_WRITE_FW(GMBUS0, 0);
631 * Wait for bus to IDLE before clearing NAK.
632 * If we clear the NAK while bus is still active, then it will stay
633 * active and the next transaction may fail.
635 * If no ACK is received during the address phase of a transaction, the
636 * adapter must report -ENXIO. It is not clear what to return if no ACK
637 * is received at other times. But we have to be careful to not return
638 * spurious -ENXIO because that will prevent i2c and drm edid functions
639 * from retrying. So return -ENXIO only when gmbus properly quiescents -
640 * timing out seems to happen when there _is_ a ddc chip present, but
641 * it's slow responding and only answers on the 2nd retry.
644 if (gmbus_wait_idle(dev_priv)) {
645 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
650 /* Toggle the Software Clear Interrupt bit. This has the effect
651 * of resetting the GMBUS controller and so clearing the
652 * BUS_ERROR raised by the slave's NAK.
654 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
655 I915_WRITE_FW(GMBUS1, 0);
656 I915_WRITE_FW(GMBUS0, 0);
658 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
659 adapter->name, msgs[i].addr,
660 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
663 * Passive adapters sometimes NAK the first probe. Retry the first
664 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
665 * has retries internally. See also the retry loop in
666 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
668 if (ret == -ENXIO && i == 0 && try++ == 0) {
669 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
677 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
678 bus->adapter.name, bus->reg0 & 0xff);
679 I915_WRITE_FW(GMBUS0, 0);
682 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
683 * instead. Use EAGAIN to have i2c core retry.
688 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
689 if (IS_GEN9_LP(dev_priv))
690 bxt_gmbus_clock_gating(dev_priv, true);
691 else if (HAS_PCH_SPT(dev_priv) ||
692 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
693 pch_gmbus_clock_gating(dev_priv, true);
699 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
701 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
703 struct drm_i915_private *dev_priv = bus->dev_priv;
706 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
708 if (bus->force_bit) {
709 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
711 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
713 ret = do_gmbus_xfer(adapter, msgs, num, 0);
715 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
718 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
723 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
725 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
727 struct drm_i915_private *dev_priv = bus->dev_priv;
729 u8 cmd = DRM_HDCP_DDC_AKSV;
730 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
731 struct i2c_msg msgs[] = {
733 .addr = DRM_HDCP_DDC_ADDR,
739 .addr = DRM_HDCP_DDC_ADDR,
746 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
747 mutex_lock(&dev_priv->gmbus_mutex);
750 * In order to output Aksv to the receiver, use an indexed write to
751 * pass the i2c command, and tell GMBUS to use the HW-provided value
752 * instead of sourcing GMBUS3 for the data.
754 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
756 mutex_unlock(&dev_priv->gmbus_mutex);
757 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
762 static u32 gmbus_func(struct i2c_adapter *adapter)
764 return i2c_bit_algo.functionality(adapter) &
765 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
766 /* I2C_FUNC_10BIT_ADDR | */
767 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
768 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
771 static const struct i2c_algorithm gmbus_algorithm = {
772 .master_xfer = gmbus_xfer,
773 .functionality = gmbus_func
776 static void gmbus_lock_bus(struct i2c_adapter *adapter,
779 struct intel_gmbus *bus = to_intel_gmbus(adapter);
780 struct drm_i915_private *dev_priv = bus->dev_priv;
782 mutex_lock(&dev_priv->gmbus_mutex);
785 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
788 struct intel_gmbus *bus = to_intel_gmbus(adapter);
789 struct drm_i915_private *dev_priv = bus->dev_priv;
791 return mutex_trylock(&dev_priv->gmbus_mutex);
794 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
797 struct intel_gmbus *bus = to_intel_gmbus(adapter);
798 struct drm_i915_private *dev_priv = bus->dev_priv;
800 mutex_unlock(&dev_priv->gmbus_mutex);
803 static const struct i2c_lock_operations gmbus_lock_ops = {
804 .lock_bus = gmbus_lock_bus,
805 .trylock_bus = gmbus_trylock_bus,
806 .unlock_bus = gmbus_unlock_bus,
810 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
811 * @dev_priv: i915 device private
813 int intel_setup_gmbus(struct drm_i915_private *dev_priv)
815 struct pci_dev *pdev = dev_priv->drm.pdev;
816 struct intel_gmbus *bus;
820 if (INTEL_INFO(dev_priv)->num_pipes == 0)
823 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
824 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
825 else if (!HAS_GMCH_DISPLAY(dev_priv))
827 * Broxton uses the same PCH offsets for South Display Engine,
828 * even though it doesn't have a PCH.
830 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
832 mutex_init(&dev_priv->gmbus_mutex);
833 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
835 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
836 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
839 bus = &dev_priv->gmbus[pin];
841 bus->adapter.owner = THIS_MODULE;
842 bus->adapter.class = I2C_CLASS_DDC;
843 snprintf(bus->adapter.name,
844 sizeof(bus->adapter.name),
846 get_gmbus_pin(dev_priv, pin)->name);
848 bus->adapter.dev.parent = &pdev->dev;
849 bus->dev_priv = dev_priv;
851 bus->adapter.algo = &gmbus_algorithm;
852 bus->adapter.lock_ops = &gmbus_lock_ops;
855 * We wish to retry with bit banging
856 * after a timed out GMBUS attempt.
858 bus->adapter.retries = 1;
860 /* By default use a conservative clock rate */
861 bus->reg0 = pin | GMBUS_RATE_100KHZ;
863 /* gmbus seems to be broken on i830 */
864 if (IS_I830(dev_priv))
867 intel_gpio_setup(bus, pin);
869 ret = i2c_add_adapter(&bus->adapter);
874 intel_i2c_reset(dev_priv);
880 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
883 bus = &dev_priv->gmbus[pin];
884 i2c_del_adapter(&bus->adapter);
889 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
892 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
895 return &dev_priv->gmbus[pin].adapter;
898 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
900 struct intel_gmbus *bus = to_intel_gmbus(adapter);
902 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
905 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
907 struct intel_gmbus *bus = to_intel_gmbus(adapter);
908 struct drm_i915_private *dev_priv = bus->dev_priv;
910 mutex_lock(&dev_priv->gmbus_mutex);
912 bus->force_bit += force_bit ? 1 : -1;
913 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
914 force_bit ? "en" : "dis", adapter->name,
917 mutex_unlock(&dev_priv->gmbus_mutex);
920 void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
922 struct intel_gmbus *bus;
925 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
926 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
929 bus = &dev_priv->gmbus[pin];
930 i2c_del_adapter(&bus->adapter);