2 * Copyright © 2014 Intel Corporation
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25 #include <linux/circ_buf.h>
26 #include <trace/events/dma_fence.h>
28 #include "intel_guc_submission.h"
29 #include "intel_lrc_reg.h"
32 #define GUC_PREEMPT_FINISHED 0x1
33 #define GUC_PREEMPT_BREADCRUMB_DWORDS 0x8
34 #define GUC_PREEMPT_BREADCRUMB_BYTES \
35 (sizeof(u32) * GUC_PREEMPT_BREADCRUMB_DWORDS)
38 * DOC: GuC-based command submission
41 * A intel_guc_client refers to a submission path through GuC. Currently, there
42 * are two clients. One of them (the execbuf_client) is charged with all
43 * submissions to the GuC, the other one (preempt_client) is responsible for
44 * preempting the execbuf_client. This struct is the owner of a doorbell, a
45 * process descriptor and a workqueue (all of them inside a single gem object
46 * that contains all required pages for these elements).
48 * GuC stage descriptor:
49 * During initialization, the driver allocates a static pool of 1024 such
50 * descriptors, and shares them with the GuC.
51 * Currently, there exists a 1:1 mapping between a intel_guc_client and a
52 * guc_stage_desc (via the client's stage_id), so effectively only one
53 * gets used. This stage descriptor lets the GuC know about the doorbell,
54 * workqueue and process descriptor. Theoretically, it also lets the GuC
55 * know about our HW contexts (context ID, etc...), but we actually
56 * employ a kind of submission where the GuC uses the LRCA sent via the work
57 * item instead (the single guc_stage_desc associated to execbuf client
58 * contains information about the default kernel context only, but this is
59 * essentially unused). This is called a "proxy" submission.
61 * The Scratch registers:
62 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
63 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
64 * triggers an interrupt on the GuC via another register write (0xC4C8).
65 * Firmware writes a success/fail code back to the action register after
66 * processes the request. The kernel driver polls waiting for this update and
68 * See intel_guc_send()
71 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
72 * mapped into process space.
75 * There are several types of work items that the host may place into a
76 * workqueue, each with its own requirements and limitations. Currently only
77 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
78 * represents in-order queue. The kernel driver packs ring tail pointer and an
79 * ELSP context descriptor dword into Work Item.
80 * See guc_add_request()
84 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
86 return rb_entry(rb, struct i915_priolist, node);
89 static inline bool is_high_priority(struct intel_guc_client *client)
91 return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
92 client->priority == GUC_CLIENT_PRIORITY_HIGH);
95 static int reserve_doorbell(struct intel_guc_client *client)
101 GEM_BUG_ON(client->doorbell_id != GUC_DOORBELL_INVALID);
104 * The bitmap tracks which doorbell registers are currently in use.
105 * It is split into two halves; the first half is used for normal
106 * priority contexts, the second half for high-priority ones.
109 end = GUC_NUM_DOORBELLS / 2;
110 if (is_high_priority(client)) {
115 id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset);
119 __set_bit(id, client->guc->doorbell_bitmap);
120 client->doorbell_id = id;
121 DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
122 client->stage_id, yesno(is_high_priority(client)),
127 static bool has_doorbell(struct intel_guc_client *client)
129 if (client->doorbell_id == GUC_DOORBELL_INVALID)
132 return test_bit(client->doorbell_id, client->guc->doorbell_bitmap);
135 static void unreserve_doorbell(struct intel_guc_client *client)
137 GEM_BUG_ON(!has_doorbell(client));
139 __clear_bit(client->doorbell_id, client->guc->doorbell_bitmap);
140 client->doorbell_id = GUC_DOORBELL_INVALID;
144 * Tell the GuC to allocate or deallocate a specific doorbell
147 static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id)
150 INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
154 return intel_guc_send(guc, action, ARRAY_SIZE(action));
157 static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id)
160 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
164 return intel_guc_send(guc, action, ARRAY_SIZE(action));
167 static struct guc_stage_desc *__get_stage_desc(struct intel_guc_client *client)
169 struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr;
171 return &base[client->stage_id];
175 * Initialise, update, or clear doorbell data shared with the GuC
177 * These functions modify shared data and so need access to the mapped
178 * client object which contains the page being used for the doorbell
181 static void __update_doorbell_desc(struct intel_guc_client *client, u16 new_id)
183 struct guc_stage_desc *desc;
185 /* Update the GuC's idea of the doorbell ID */
186 desc = __get_stage_desc(client);
187 desc->db_id = new_id;
190 static struct guc_doorbell_info *__get_doorbell(struct intel_guc_client *client)
192 return client->vaddr + client->doorbell_offset;
195 static void __create_doorbell(struct intel_guc_client *client)
197 struct guc_doorbell_info *doorbell;
199 doorbell = __get_doorbell(client);
200 doorbell->db_status = GUC_DOORBELL_ENABLED;
201 doorbell->cookie = 0;
204 static void __destroy_doorbell(struct intel_guc_client *client)
206 struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
207 struct guc_doorbell_info *doorbell;
208 u16 db_id = client->doorbell_id;
210 doorbell = __get_doorbell(client);
211 doorbell->db_status = GUC_DOORBELL_DISABLED;
212 doorbell->cookie = 0;
214 /* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit
215 * to go to zero after updating db_status before we call the GuC to
216 * release the doorbell
218 if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID), 10))
219 WARN_ONCE(true, "Doorbell never became invalid after disable\n");
222 static int create_doorbell(struct intel_guc_client *client)
226 if (WARN_ON(!has_doorbell(client)))
227 return -ENODEV; /* internal setup error, should never happen */
229 __update_doorbell_desc(client, client->doorbell_id);
230 __create_doorbell(client);
232 ret = __guc_allocate_doorbell(client->guc, client->stage_id);
234 __destroy_doorbell(client);
235 __update_doorbell_desc(client, GUC_DOORBELL_INVALID);
236 DRM_DEBUG_DRIVER("Couldn't create client %u doorbell: %d\n",
237 client->stage_id, ret);
244 static int destroy_doorbell(struct intel_guc_client *client)
248 GEM_BUG_ON(!has_doorbell(client));
250 __destroy_doorbell(client);
251 ret = __guc_deallocate_doorbell(client->guc, client->stage_id);
253 DRM_ERROR("Couldn't destroy client %u doorbell: %d\n",
254 client->stage_id, ret);
256 __update_doorbell_desc(client, GUC_DOORBELL_INVALID);
261 static unsigned long __select_cacheline(struct intel_guc *guc)
263 unsigned long offset;
265 /* Doorbell uses a single cache line within a page */
266 offset = offset_in_page(guc->db_cacheline);
268 /* Moving to next cache line to reduce contention */
269 guc->db_cacheline += cache_line_size();
271 DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n",
272 offset, guc->db_cacheline, cache_line_size());
276 static inline struct guc_process_desc *
277 __get_process_desc(struct intel_guc_client *client)
279 return client->vaddr + client->proc_desc_offset;
283 * Initialise the process descriptor shared with the GuC firmware.
285 static void guc_proc_desc_init(struct intel_guc *guc,
286 struct intel_guc_client *client)
288 struct guc_process_desc *desc;
290 desc = memset(__get_process_desc(client), 0, sizeof(*desc));
293 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
294 * space for ring3 clients (set them as in mmap_ioctl) or kernel
295 * space for kernel clients (map on demand instead? May make debug
296 * easier to have it mapped).
298 desc->wq_base_addr = 0;
299 desc->db_base_addr = 0;
301 desc->stage_id = client->stage_id;
302 desc->wq_size_bytes = GUC_WQ_SIZE;
303 desc->wq_status = WQ_STATUS_ACTIVE;
304 desc->priority = client->priority;
307 static int guc_stage_desc_pool_create(struct intel_guc *guc)
309 struct i915_vma *vma;
312 vma = intel_guc_allocate_vma(guc,
313 PAGE_ALIGN(sizeof(struct guc_stage_desc) *
314 GUC_MAX_STAGE_DESCRIPTORS));
318 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
320 i915_vma_unpin_and_release(&vma);
321 return PTR_ERR(vaddr);
324 guc->stage_desc_pool = vma;
325 guc->stage_desc_pool_vaddr = vaddr;
326 ida_init(&guc->stage_ids);
331 static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
333 ida_destroy(&guc->stage_ids);
334 i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
335 i915_vma_unpin_and_release(&guc->stage_desc_pool);
339 * Initialise/clear the stage descriptor shared with the GuC firmware.
341 * This descriptor tells the GuC where (in GGTT space) to find the important
342 * data structures relating to this client (doorbell, process descriptor,
345 static void guc_stage_desc_init(struct intel_guc *guc,
346 struct intel_guc_client *client)
348 struct drm_i915_private *dev_priv = guc_to_i915(guc);
349 struct intel_engine_cs *engine;
350 struct i915_gem_context *ctx = client->owner;
351 struct guc_stage_desc *desc;
355 desc = __get_stage_desc(client);
356 memset(desc, 0, sizeof(*desc));
358 desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE |
359 GUC_STAGE_DESC_ATTR_KERNEL;
360 if (is_high_priority(client))
361 desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT;
362 desc->stage_id = client->stage_id;
363 desc->priority = client->priority;
364 desc->db_id = client->doorbell_id;
366 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
367 struct intel_context *ce = to_intel_context(ctx, engine);
368 u32 guc_engine_id = engine->guc_id;
369 struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id];
371 /* TODO: We have a design issue to be solved here. Only when we
372 * receive the first batch, we know which engine is used by the
373 * user. But here GuC expects the lrc and ring to be pinned. It
374 * is not an issue for default context, which is the only one
375 * for now who owns a GuC client. But for future owner of GuC
376 * client, need to make sure lrc is pinned prior to enter here.
379 break; /* XXX: continue? */
382 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
383 * submission or, in other words, not using a direct submission
384 * model) the KMD's LRCA is not used for any work submission.
385 * Instead, the GuC uses the LRCA of the user mode context (see
386 * guc_add_request below).
388 lrc->context_desc = lower_32_bits(ce->lrc_desc);
390 /* The state page is after PPHWSP */
391 lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
392 LRC_STATE_PN * PAGE_SIZE;
394 /* XXX: In direct submission, the GuC wants the HW context id
395 * here. In proxy submission, it wants the stage id
397 lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
398 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
400 lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
401 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
402 lrc->ring_next_free_location = lrc->ring_begin;
403 lrc->ring_current_tail_pointer_value = 0;
405 desc->engines_used |= (1 << guc_engine_id);
408 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
409 client->engines, desc->engines_used);
410 WARN_ON(desc->engines_used == 0);
413 * The doorbell, process descriptor, and workqueue are all parts
414 * of the client object, which the GuC will reference via the GGTT
416 gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
417 desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
418 client->doorbell_offset;
419 desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
420 desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
421 desc->process_desc = gfx_addr + client->proc_desc_offset;
422 desc->wq_addr = gfx_addr + GUC_DB_SIZE;
423 desc->wq_size = GUC_WQ_SIZE;
425 desc->desc_private = ptr_to_u64(client);
428 static void guc_stage_desc_fini(struct intel_guc *guc,
429 struct intel_guc_client *client)
431 struct guc_stage_desc *desc;
433 desc = __get_stage_desc(client);
434 memset(desc, 0, sizeof(*desc));
437 /* Construct a Work Item and append it to the GuC's Work Queue */
438 static void guc_wq_item_append(struct intel_guc_client *client,
439 u32 target_engine, u32 context_desc,
440 u32 ring_tail, u32 fence_id)
442 /* wqi_len is in DWords, and does not include the one-word header */
443 const size_t wqi_size = sizeof(struct guc_wq_item);
444 const u32 wqi_len = wqi_size / sizeof(u32) - 1;
445 struct guc_process_desc *desc = __get_process_desc(client);
446 struct guc_wq_item *wqi;
449 lockdep_assert_held(&client->wq_lock);
451 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
452 * should not have the case where structure wqi is across page, neither
453 * wrapped to the beginning. This simplifies the implementation below.
455 * XXX: if not the case, we need save data to a temp wqi and copy it to
456 * workqueue buffer dw by dw.
458 BUILD_BUG_ON(wqi_size != 16);
460 /* Free space is guaranteed. */
461 wq_off = READ_ONCE(desc->tail);
462 GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
463 GUC_WQ_SIZE) < wqi_size);
464 GEM_BUG_ON(wq_off & (wqi_size - 1));
466 /* WQ starts from the page after doorbell / process_desc */
467 wqi = client->vaddr + wq_off + GUC_DB_SIZE;
469 /* Now fill in the 4-word work queue item */
470 wqi->header = WQ_TYPE_INORDER |
471 (wqi_len << WQ_LEN_SHIFT) |
472 (target_engine << WQ_TARGET_SHIFT) |
474 wqi->context_desc = context_desc;
475 wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
476 GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
477 wqi->fence_id = fence_id;
479 /* Make the update visible to GuC */
480 WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
483 static void guc_reset_wq(struct intel_guc_client *client)
485 struct guc_process_desc *desc = __get_process_desc(client);
491 static void guc_ring_doorbell(struct intel_guc_client *client)
493 struct guc_doorbell_info *db;
496 lockdep_assert_held(&client->wq_lock);
498 /* pointer of current doorbell cacheline */
499 db = __get_doorbell(client);
502 * We're not expecting the doorbell cookie to change behind our back,
503 * we also need to treat 0 as a reserved value.
505 cookie = READ_ONCE(db->cookie);
506 WARN_ON_ONCE(xchg(&db->cookie, cookie + 1 ?: cookie + 2) != cookie);
508 /* XXX: doorbell was lost and need to acquire it again */
509 GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
512 static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
514 struct intel_guc_client *client = guc->execbuf_client;
515 struct intel_engine_cs *engine = rq->engine;
516 u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);
517 u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
519 spin_lock(&client->wq_lock);
521 guc_wq_item_append(client, engine->guc_id, ctx_desc,
522 ring_tail, rq->global_seqno);
523 guc_ring_doorbell(client);
525 client->submissions[engine->id] += 1;
527 spin_unlock(&client->wq_lock);
531 * When we're doing submissions using regular execlists backend, writing to
532 * ELSP from CPU side is enough to make sure that writes to ringbuffer pages
533 * pinned in mappable aperture portion of GGTT are visible to command streamer.
534 * Writes done by GuC on our behalf are not guaranteeing such ordering,
535 * therefore, to ensure the flush, we're issuing a POSTING READ.
537 static void flush_ggtt_writes(struct i915_vma *vma)
539 struct drm_i915_private *dev_priv = vma->vm->i915;
541 if (i915_vma_is_map_and_fenceable(vma))
542 POSTING_READ_FW(GUC_STATUS);
545 static void inject_preempt_context(struct work_struct *work)
547 struct guc_preempt_work *preempt_work =
548 container_of(work, typeof(*preempt_work), work);
549 struct intel_engine_cs *engine = preempt_work->engine;
550 struct intel_guc *guc = container_of(preempt_work, typeof(*guc),
551 preempt_work[engine->id]);
552 struct intel_guc_client *client = guc->preempt_client;
553 struct guc_stage_desc *stage_desc = __get_stage_desc(client);
554 u32 ctx_desc = lower_32_bits(to_intel_context(client->owner,
559 * The ring contains commands to write GUC_PREEMPT_FINISHED into HWSP.
560 * See guc_fill_preempt_context().
562 spin_lock_irq(&client->wq_lock);
563 guc_wq_item_append(client, engine->guc_id, ctx_desc,
564 GUC_PREEMPT_BREADCRUMB_BYTES / sizeof(u64), 0);
565 spin_unlock_irq(&client->wq_lock);
568 * If GuC firmware performs an engine reset while that engine had
569 * a preemption pending, it will set the terminated attribute bit
570 * on our preemption stage descriptor. GuC firmware retains all
571 * pending work items for a high-priority GuC client, unlike the
572 * normal-priority GuC client where work items are dropped. It
573 * wants to make sure the preempt-to-idle work doesn't run when
574 * scheduling resumes, and uses this bit to inform its scheduler
575 * and presumably us as well. Our job is to clear it for the next
576 * preemption after reset, otherwise that and future preemptions
577 * will never complete. We'll just clear it every time.
579 stage_desc->attribute &= ~GUC_STAGE_DESC_ATTR_TERMINATED;
581 data[0] = INTEL_GUC_ACTION_REQUEST_PREEMPTION;
582 data[1] = client->stage_id;
583 data[2] = INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q |
584 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q;
585 data[3] = engine->guc_id;
586 data[4] = guc->execbuf_client->priority;
587 data[5] = guc->execbuf_client->stage_id;
588 data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
590 if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
591 execlists_clear_active(&engine->execlists,
592 EXECLISTS_ACTIVE_PREEMPT);
593 tasklet_schedule(&engine->execlists.tasklet);
598 * We're using user interrupt and HWSP value to mark that preemption has
599 * finished and GPU is idle. Normally, we could unwind and continue similar to
600 * execlists submission path. Unfortunately, with GuC we also need to wait for
601 * it to finish its own postprocessing, before attempting to submit. Otherwise
602 * GuC may silently ignore our submissions, and thus we risk losing request at
603 * best, executing out-of-order and causing kernel panic at worst.
605 #define GUC_PREEMPT_POSTPROCESS_DELAY_MS 10
606 static void wait_for_guc_preempt_report(struct intel_engine_cs *engine)
608 struct intel_guc *guc = &engine->i915->guc;
609 struct guc_shared_ctx_data *data = guc->shared_data_vaddr;
610 struct guc_ctx_report *report =
611 &data->preempt_ctx_report[engine->guc_id];
613 WARN_ON(wait_for_atomic(report->report_return_status ==
614 INTEL_GUC_REPORT_STATUS_COMPLETE,
615 GUC_PREEMPT_POSTPROCESS_DELAY_MS));
617 * GuC is expecting that we're also going to clear the affected context
618 * counter, let's also reset the return status to not depend on GuC
619 * resetting it after recieving another preempt action
621 report->affected_count = 0;
622 report->report_return_status = INTEL_GUC_REPORT_STATUS_UNKNOWN;
625 static void complete_preempt_context(struct intel_engine_cs *engine)
627 struct intel_engine_execlists *execlists = &engine->execlists;
629 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
631 execlists_cancel_port_requests(execlists);
632 execlists_unwind_incomplete_requests(execlists);
634 wait_for_guc_preempt_report(engine);
635 intel_write_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX, 0);
637 execlists_clear_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
641 * guc_submit() - Submit commands through GuC
642 * @engine: engine associated with the commands
644 * The only error here arises if the doorbell hardware isn't functioning
645 * as expected, which really shouln't happen.
647 static void guc_submit(struct intel_engine_cs *engine)
649 struct intel_guc *guc = &engine->i915->guc;
650 struct intel_engine_execlists * const execlists = &engine->execlists;
651 struct execlist_port *port = execlists->port;
654 for (n = 0; n < execlists_num_ports(execlists); n++) {
655 struct i915_request *rq;
658 rq = port_unpack(&port[n], &count);
659 if (rq && count == 0) {
660 port_set(&port[n], port_pack(rq, ++count));
662 flush_ggtt_writes(rq->ring->vma);
664 guc_add_request(guc, rq);
669 static void port_assign(struct execlist_port *port, struct i915_request *rq)
671 GEM_BUG_ON(port_isset(port));
673 port_set(port, i915_request_get(rq));
676 static inline int rq_prio(const struct i915_request *rq)
678 return rq->sched.attr.priority;
681 static inline int port_prio(const struct execlist_port *port)
683 return rq_prio(port_request(port));
686 static bool __guc_dequeue(struct intel_engine_cs *engine)
688 struct intel_engine_execlists * const execlists = &engine->execlists;
689 struct execlist_port *port = execlists->port;
690 struct i915_request *last = NULL;
691 const struct execlist_port * const last_port =
692 &execlists->port[execlists->port_mask];
696 lockdep_assert_held(&engine->timeline.lock);
698 if (port_isset(port)) {
699 if (intel_engine_has_preemption(engine)) {
700 struct guc_preempt_work *preempt_work =
701 &engine->i915->guc.preempt_work[engine->id];
702 int prio = execlists->queue_priority;
704 if (__execlists_need_preempt(prio, port_prio(port))) {
705 execlists_set_active(execlists,
706 EXECLISTS_ACTIVE_PREEMPT);
707 queue_work(engine->i915->guc.preempt_wq,
708 &preempt_work->work);
714 if (port_isset(port))
717 GEM_BUG_ON(port_isset(port));
719 while ((rb = rb_first_cached(&execlists->queue))) {
720 struct i915_priolist *p = to_priolist(rb);
721 struct i915_request *rq, *rn;
723 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
724 if (last && rq->hw_context != last->hw_context) {
725 if (port == last_port) {
726 __list_del_many(&p->requests,
732 port_assign(port, last);
736 INIT_LIST_HEAD(&rq->sched.link);
738 __i915_request_submit(rq);
739 trace_i915_request_in(rq, port_index(port, execlists));
744 rb_erase_cached(&p->node, &execlists->queue);
745 INIT_LIST_HEAD(&p->requests);
746 if (p->priority != I915_PRIORITY_NORMAL)
747 kmem_cache_free(engine->i915->priorities, p);
750 execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
752 port_assign(port, last);
754 execlists_user_begin(execlists, execlists->port);
756 /* We must always keep the beast fed if we have work piled up */
757 GEM_BUG_ON(port_isset(execlists->port) &&
758 !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
759 GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
760 !port_isset(execlists->port));
765 static void guc_dequeue(struct intel_engine_cs *engine)
770 local_irq_save(flags);
772 spin_lock(&engine->timeline.lock);
773 submit = __guc_dequeue(engine);
774 spin_unlock(&engine->timeline.lock);
779 local_irq_restore(flags);
782 static void guc_submission_tasklet(unsigned long data)
784 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
785 struct intel_engine_execlists * const execlists = &engine->execlists;
786 struct execlist_port *port = execlists->port;
787 struct i915_request *rq;
789 rq = port_request(port);
790 while (rq && i915_request_completed(rq)) {
791 trace_i915_request_out(rq);
792 i915_request_put(rq);
794 port = execlists_port_complete(execlists, port);
795 if (port_isset(port)) {
796 execlists_user_begin(execlists, port);
797 rq = port_request(port);
799 execlists_user_end(execlists);
804 if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) &&
805 intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) ==
806 GUC_PREEMPT_FINISHED)
807 complete_preempt_context(engine);
809 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
813 static struct i915_request *
814 guc_reset_prepare(struct intel_engine_cs *engine)
816 struct intel_engine_execlists * const execlists = &engine->execlists;
818 GEM_TRACE("%s\n", engine->name);
821 * Prevent request submission to the hardware until we have
822 * completed the reset in i915_gem_reset_finish(). If a request
823 * is completed by one engine, it may then queue a request
824 * to a second via its execlists->tasklet *just* as we are
825 * calling engine->init_hw() and also writing the ELSP.
826 * Turning off the execlists->tasklet until the reset is over
829 __tasklet_disable_sync_once(&execlists->tasklet);
832 * We're using worker to queue preemption requests from the tasklet in
833 * GuC submission mode.
834 * Even though tasklet was disabled, we may still have a worker queued.
835 * Let's make sure that all workers scheduled before disabling the
836 * tasklet are completed before continuing with the reset.
838 if (engine->i915->guc.preempt_wq)
839 flush_workqueue(engine->i915->guc.preempt_wq);
841 return i915_gem_find_active_request(engine);
845 * Everything below here is concerned with setup & teardown, and is
846 * therefore not part of the somewhat time-critical batch-submission
847 * path of guc_submit() above.
850 /* Check that a doorbell register is in the expected state */
851 static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
853 struct drm_i915_private *dev_priv = guc_to_i915(guc);
857 GEM_BUG_ON(db_id >= GUC_DOORBELL_INVALID);
859 drbregl = I915_READ(GEN8_DRBREGL(db_id));
860 valid = drbregl & GEN8_DRB_VALID;
862 if (test_bit(db_id, guc->doorbell_bitmap) == valid)
865 DRM_DEBUG_DRIVER("Doorbell %d has unexpected state (0x%x): valid=%s\n",
866 db_id, drbregl, yesno(valid));
871 static bool guc_verify_doorbells(struct intel_guc *guc)
875 for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id)
876 if (!doorbell_ok(guc, db_id))
882 static int guc_clients_doorbell_init(struct intel_guc *guc)
886 ret = create_doorbell(guc->execbuf_client);
890 if (guc->preempt_client) {
891 ret = create_doorbell(guc->preempt_client);
893 destroy_doorbell(guc->execbuf_client);
901 static void guc_clients_doorbell_fini(struct intel_guc *guc)
904 * By the time we're here, GuC has already been reset.
905 * Instead of trying (in vain) to communicate with it, let's just
906 * cleanup the doorbell HW and our internal state.
908 if (guc->preempt_client) {
909 __destroy_doorbell(guc->preempt_client);
910 __update_doorbell_desc(guc->preempt_client,
911 GUC_DOORBELL_INVALID);
914 if (guc->execbuf_client) {
915 __destroy_doorbell(guc->execbuf_client);
916 __update_doorbell_desc(guc->execbuf_client,
917 GUC_DOORBELL_INVALID);
922 * guc_client_alloc() - Allocate an intel_guc_client
923 * @dev_priv: driver private data structure
924 * @engines: The set of engines to enable for this client
925 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
926 * The kernel client to replace ExecList submission is created with
927 * NORMAL priority. Priority of a client for scheduler can be HIGH,
928 * while a preemption context can use CRITICAL.
929 * @ctx: the context that owns the client (we use the default render
932 * Return: An intel_guc_client object if success, else NULL.
934 static struct intel_guc_client *
935 guc_client_alloc(struct drm_i915_private *dev_priv,
938 struct i915_gem_context *ctx)
940 struct intel_guc_client *client;
941 struct intel_guc *guc = &dev_priv->guc;
942 struct i915_vma *vma;
946 client = kzalloc(sizeof(*client), GFP_KERNEL);
948 return ERR_PTR(-ENOMEM);
952 client->engines = engines;
953 client->priority = priority;
954 client->doorbell_id = GUC_DOORBELL_INVALID;
955 spin_lock_init(&client->wq_lock);
957 ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
962 client->stage_id = ret;
964 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
965 vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
971 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
974 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
976 ret = PTR_ERR(vaddr);
979 client->vaddr = vaddr;
981 client->doorbell_offset = __select_cacheline(guc);
984 * Since the doorbell only requires a single cacheline, we can save
985 * space by putting the application process descriptor in the same
986 * page. Use the half of the page that doesn't include the doorbell.
988 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
989 client->proc_desc_offset = 0;
991 client->proc_desc_offset = (GUC_DB_SIZE / 2);
993 guc_proc_desc_init(guc, client);
994 guc_stage_desc_init(guc, client);
996 ret = reserve_doorbell(client);
1000 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
1001 priority, client, client->engines, client->stage_id);
1002 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
1003 client->doorbell_id, client->doorbell_offset);
1008 i915_gem_object_unpin_map(client->vma->obj);
1010 i915_vma_unpin_and_release(&client->vma);
1012 ida_simple_remove(&guc->stage_ids, client->stage_id);
1015 return ERR_PTR(ret);
1018 static void guc_client_free(struct intel_guc_client *client)
1020 unreserve_doorbell(client);
1021 guc_stage_desc_fini(client->guc, client);
1022 i915_gem_object_unpin_map(client->vma->obj);
1023 i915_vma_unpin_and_release(&client->vma);
1024 ida_simple_remove(&client->guc->stage_ids, client->stage_id);
1028 static inline bool ctx_save_restore_disabled(struct intel_context *ce)
1030 u32 sr = ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1];
1032 #define SR_DISABLED \
1033 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \
1034 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)
1036 return (sr & SR_DISABLED) == SR_DISABLED;
1041 static void guc_fill_preempt_context(struct intel_guc *guc)
1043 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1044 struct intel_guc_client *client = guc->preempt_client;
1045 struct intel_engine_cs *engine;
1046 enum intel_engine_id id;
1048 for_each_engine(engine, dev_priv, id) {
1049 struct intel_context *ce =
1050 to_intel_context(client->owner, engine);
1051 u32 addr = intel_hws_preempt_done_address(engine);
1054 GEM_BUG_ON(!ce->pin_count);
1057 * We rely on this context image *not* being saved after
1058 * preemption. This ensures that the RING_HEAD / RING_TAIL
1059 * remain pointing at initial values forever.
1061 GEM_BUG_ON(!ctx_save_restore_disabled(ce));
1063 cs = ce->ring->vaddr;
1065 cs = gen8_emit_ggtt_write_rcs(cs,
1066 GUC_PREEMPT_FINISHED,
1069 cs = gen8_emit_ggtt_write(cs,
1070 GUC_PREEMPT_FINISHED,
1075 *cs++ = MI_USER_INTERRUPT;
1078 GEM_BUG_ON((void *)cs - ce->ring->vaddr !=
1079 GUC_PREEMPT_BREADCRUMB_BYTES);
1081 flush_ggtt_writes(ce->ring->vma);
1085 static int guc_clients_create(struct intel_guc *guc)
1087 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1088 struct intel_guc_client *client;
1090 GEM_BUG_ON(guc->execbuf_client);
1091 GEM_BUG_ON(guc->preempt_client);
1093 client = guc_client_alloc(dev_priv,
1094 INTEL_INFO(dev_priv)->ring_mask,
1095 GUC_CLIENT_PRIORITY_KMD_NORMAL,
1096 dev_priv->kernel_context);
1097 if (IS_ERR(client)) {
1098 DRM_ERROR("Failed to create GuC client for submission!\n");
1099 return PTR_ERR(client);
1101 guc->execbuf_client = client;
1103 if (dev_priv->preempt_context) {
1104 client = guc_client_alloc(dev_priv,
1105 INTEL_INFO(dev_priv)->ring_mask,
1106 GUC_CLIENT_PRIORITY_KMD_HIGH,
1107 dev_priv->preempt_context);
1108 if (IS_ERR(client)) {
1109 DRM_ERROR("Failed to create GuC client for preemption!\n");
1110 guc_client_free(guc->execbuf_client);
1111 guc->execbuf_client = NULL;
1112 return PTR_ERR(client);
1114 guc->preempt_client = client;
1116 guc_fill_preempt_context(guc);
1122 static void guc_clients_destroy(struct intel_guc *guc)
1124 struct intel_guc_client *client;
1126 client = fetch_and_zero(&guc->preempt_client);
1128 guc_client_free(client);
1130 client = fetch_and_zero(&guc->execbuf_client);
1132 guc_client_free(client);
1136 * Set up the memory resources to be shared with the GuC (via the GGTT)
1137 * at firmware loading time.
1139 int intel_guc_submission_init(struct intel_guc *guc)
1141 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1142 struct intel_engine_cs *engine;
1143 enum intel_engine_id id;
1146 if (guc->stage_desc_pool)
1149 ret = guc_stage_desc_pool_create(guc);
1153 * Keep static analysers happy, let them know that we allocated the
1154 * vma after testing that it didn't exist earlier.
1156 GEM_BUG_ON(!guc->stage_desc_pool);
1158 WARN_ON(!guc_verify_doorbells(guc));
1159 ret = guc_clients_create(guc);
1163 for_each_engine(engine, dev_priv, id) {
1164 guc->preempt_work[id].engine = engine;
1165 INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context);
1171 guc_stage_desc_pool_destroy(guc);
1175 void intel_guc_submission_fini(struct intel_guc *guc)
1177 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1178 struct intel_engine_cs *engine;
1179 enum intel_engine_id id;
1181 for_each_engine(engine, dev_priv, id)
1182 cancel_work_sync(&guc->preempt_work[id].work);
1184 guc_clients_destroy(guc);
1185 WARN_ON(!guc_verify_doorbells(guc));
1187 guc_stage_desc_pool_destroy(guc);
1190 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
1192 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1193 struct intel_engine_cs *engine;
1194 enum intel_engine_id id;
1197 /* tell all command streamers to forward interrupts (but not vblank)
1200 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
1201 for_each_engine(engine, dev_priv, id)
1202 I915_WRITE(RING_MODE_GEN7(engine), irqs);
1204 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
1205 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
1206 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1207 /* These three registers have the same bit definitions */
1208 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
1209 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
1210 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
1213 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
1214 * (unmasked) PM interrupts to the GuC. All other bits of this
1215 * register *disable* generation of a specific interrupt.
1217 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
1218 * writing to the PM interrupt mask register, i.e. interrupts
1219 * that must not be disabled.
1221 * If the GuC is handling these interrupts, then we must not let
1222 * the PM code disable ANY interrupt that the GuC is expecting.
1223 * So for each ENABLED (0) bit in this register, we must SET the
1224 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
1225 * GuC needs ARAT expired interrupt unmasked hence it is set in
1228 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
1229 * result in the register bit being left SET!
1231 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
1232 rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
1235 static void guc_interrupts_release(struct drm_i915_private *dev_priv)
1237 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1238 struct intel_engine_cs *engine;
1239 enum intel_engine_id id;
1243 * tell all command streamers NOT to forward interrupts or vblank
1246 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
1247 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
1248 for_each_engine(engine, dev_priv, id)
1249 I915_WRITE(RING_MODE_GEN7(engine), irqs);
1251 /* route all GT interrupts to the host */
1252 I915_WRITE(GUC_BCS_RCS_IER, 0);
1253 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
1254 I915_WRITE(GUC_WD_VECS_IER, 0);
1256 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
1257 rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
1260 static void guc_submission_park(struct intel_engine_cs *engine)
1262 intel_engine_unpin_breadcrumbs_irq(engine);
1265 static void guc_submission_unpark(struct intel_engine_cs *engine)
1267 intel_engine_pin_breadcrumbs_irq(engine);
1270 int intel_guc_submission_enable(struct intel_guc *guc)
1272 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1273 struct intel_engine_cs *engine;
1274 enum intel_engine_id id;
1278 * We're using GuC work items for submitting work through GuC. Since
1279 * we're coalescing multiple requests from a single context into a
1280 * single work item prior to assigning it to execlist_port, we can
1281 * never have more work items than the total number of ports (for all
1282 * engines). The GuC firmware is controlling the HEAD of work queue,
1283 * and it is guaranteed that it will remove the work item from the
1284 * queue before our request is completed.
1286 BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
1287 sizeof(struct guc_wq_item) *
1288 I915_NUM_ENGINES > GUC_WQ_SIZE);
1290 GEM_BUG_ON(!guc->execbuf_client);
1292 guc_reset_wq(guc->execbuf_client);
1293 if (guc->preempt_client)
1294 guc_reset_wq(guc->preempt_client);
1296 err = intel_guc_sample_forcewake(guc);
1300 err = guc_clients_doorbell_init(guc);
1304 /* Take over from manual control of ELSP (execlists) */
1305 guc_interrupts_capture(dev_priv);
1307 for_each_engine(engine, dev_priv, id) {
1308 struct intel_engine_execlists * const execlists =
1311 execlists->tasklet.func = guc_submission_tasklet;
1313 engine->reset.prepare = guc_reset_prepare;
1315 engine->park = guc_submission_park;
1316 engine->unpark = guc_submission_unpark;
1318 engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
1324 void intel_guc_submission_disable(struct intel_guc *guc)
1326 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1328 GEM_BUG_ON(dev_priv->gt.awake); /* GT should be parked first */
1330 guc_interrupts_release(dev_priv);
1331 guc_clients_doorbell_fini(guc);
1333 /* Revert back to manual ELSP submission */
1334 intel_engines_reset_default_submission(dev_priv);
1337 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1338 #include "selftests/intel_guc.c"