2 * Copyright © 2014 Intel Corporation
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include <linux/circ_buf.h>
26 #include <trace/events/dma_fence.h>
28 #include "intel_guc_submission.h"
29 #include "intel_lrc_reg.h"
32 #define GUC_PREEMPT_FINISHED 0x1
33 #define GUC_PREEMPT_BREADCRUMB_DWORDS 0x8
34 #define GUC_PREEMPT_BREADCRUMB_BYTES \
35 (sizeof(u32) * GUC_PREEMPT_BREADCRUMB_DWORDS)
38 * DOC: GuC-based command submission
41 * A intel_guc_client refers to a submission path through GuC. Currently, there
42 * are two clients. One of them (the execbuf_client) is charged with all
43 * submissions to the GuC, the other one (preempt_client) is responsible for
44 * preempting the execbuf_client. This struct is the owner of a doorbell, a
45 * process descriptor and a workqueue (all of them inside a single gem object
46 * that contains all required pages for these elements).
48 * GuC stage descriptor:
49 * During initialization, the driver allocates a static pool of 1024 such
50 * descriptors, and shares them with the GuC.
51 * Currently, there exists a 1:1 mapping between a intel_guc_client and a
52 * guc_stage_desc (via the client's stage_id), so effectively only one
53 * gets used. This stage descriptor lets the GuC know about the doorbell,
54 * workqueue and process descriptor. Theoretically, it also lets the GuC
55 * know about our HW contexts (context ID, etc...), but we actually
56 * employ a kind of submission where the GuC uses the LRCA sent via the work
57 * item instead (the single guc_stage_desc associated to execbuf client
58 * contains information about the default kernel context only, but this is
59 * essentially unused). This is called a "proxy" submission.
61 * The Scratch registers:
62 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
63 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
64 * triggers an interrupt on the GuC via another register write (0xC4C8).
65 * Firmware writes a success/fail code back to the action register after
66 * processes the request. The kernel driver polls waiting for this update and
68 * See intel_guc_send()
71 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
72 * mapped into process space.
75 * There are several types of work items that the host may place into a
76 * workqueue, each with its own requirements and limitations. Currently only
77 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
78 * represents in-order queue. The kernel driver packs ring tail pointer and an
79 * ELSP context descriptor dword into Work Item.
80 * See guc_add_request()
84 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
86 return rb_entry(rb, struct i915_priolist, node);
89 static inline bool is_high_priority(struct intel_guc_client *client)
91 return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
92 client->priority == GUC_CLIENT_PRIORITY_HIGH);
95 static int reserve_doorbell(struct intel_guc_client *client)
101 GEM_BUG_ON(client->doorbell_id != GUC_DOORBELL_INVALID);
104 * The bitmap tracks which doorbell registers are currently in use.
105 * It is split into two halves; the first half is used for normal
106 * priority contexts, the second half for high-priority ones.
109 end = GUC_NUM_DOORBELLS / 2;
110 if (is_high_priority(client)) {
115 id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset);
119 __set_bit(id, client->guc->doorbell_bitmap);
120 client->doorbell_id = id;
121 DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
122 client->stage_id, yesno(is_high_priority(client)),
127 static bool has_doorbell(struct intel_guc_client *client)
129 if (client->doorbell_id == GUC_DOORBELL_INVALID)
132 return test_bit(client->doorbell_id, client->guc->doorbell_bitmap);
135 static void unreserve_doorbell(struct intel_guc_client *client)
137 GEM_BUG_ON(!has_doorbell(client));
139 __clear_bit(client->doorbell_id, client->guc->doorbell_bitmap);
140 client->doorbell_id = GUC_DOORBELL_INVALID;
144 * Tell the GuC to allocate or deallocate a specific doorbell
147 static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id)
150 INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
154 return intel_guc_send(guc, action, ARRAY_SIZE(action));
157 static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id)
160 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
164 return intel_guc_send(guc, action, ARRAY_SIZE(action));
167 static struct guc_stage_desc *__get_stage_desc(struct intel_guc_client *client)
169 struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr;
171 return &base[client->stage_id];
175 * Initialise, update, or clear doorbell data shared with the GuC
177 * These functions modify shared data and so need access to the mapped
178 * client object which contains the page being used for the doorbell
181 static void __update_doorbell_desc(struct intel_guc_client *client, u16 new_id)
183 struct guc_stage_desc *desc;
185 /* Update the GuC's idea of the doorbell ID */
186 desc = __get_stage_desc(client);
187 desc->db_id = new_id;
190 static struct guc_doorbell_info *__get_doorbell(struct intel_guc_client *client)
192 return client->vaddr + client->doorbell_offset;
195 static void __create_doorbell(struct intel_guc_client *client)
197 struct guc_doorbell_info *doorbell;
199 doorbell = __get_doorbell(client);
200 doorbell->db_status = GUC_DOORBELL_ENABLED;
201 doorbell->cookie = 0;
204 static void __destroy_doorbell(struct intel_guc_client *client)
206 struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
207 struct guc_doorbell_info *doorbell;
208 u16 db_id = client->doorbell_id;
210 doorbell = __get_doorbell(client);
211 doorbell->db_status = GUC_DOORBELL_DISABLED;
212 doorbell->cookie = 0;
214 /* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit
215 * to go to zero after updating db_status before we call the GuC to
216 * release the doorbell
218 if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID), 10))
219 WARN_ONCE(true, "Doorbell never became invalid after disable\n");
222 static int create_doorbell(struct intel_guc_client *client)
226 if (WARN_ON(!has_doorbell(client)))
227 return -ENODEV; /* internal setup error, should never happen */
229 __update_doorbell_desc(client, client->doorbell_id);
230 __create_doorbell(client);
232 ret = __guc_allocate_doorbell(client->guc, client->stage_id);
234 __destroy_doorbell(client);
235 __update_doorbell_desc(client, GUC_DOORBELL_INVALID);
236 DRM_DEBUG_DRIVER("Couldn't create client %u doorbell: %d\n",
237 client->stage_id, ret);
244 static int destroy_doorbell(struct intel_guc_client *client)
248 GEM_BUG_ON(!has_doorbell(client));
250 __destroy_doorbell(client);
251 ret = __guc_deallocate_doorbell(client->guc, client->stage_id);
253 DRM_ERROR("Couldn't destroy client %u doorbell: %d\n",
254 client->stage_id, ret);
256 __update_doorbell_desc(client, GUC_DOORBELL_INVALID);
261 static unsigned long __select_cacheline(struct intel_guc *guc)
263 unsigned long offset;
265 /* Doorbell uses a single cache line within a page */
266 offset = offset_in_page(guc->db_cacheline);
268 /* Moving to next cache line to reduce contention */
269 guc->db_cacheline += cache_line_size();
271 DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n",
272 offset, guc->db_cacheline, cache_line_size());
276 static inline struct guc_process_desc *
277 __get_process_desc(struct intel_guc_client *client)
279 return client->vaddr + client->proc_desc_offset;
283 * Initialise the process descriptor shared with the GuC firmware.
285 static void guc_proc_desc_init(struct intel_guc *guc,
286 struct intel_guc_client *client)
288 struct guc_process_desc *desc;
290 desc = memset(__get_process_desc(client), 0, sizeof(*desc));
293 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
294 * space for ring3 clients (set them as in mmap_ioctl) or kernel
295 * space for kernel clients (map on demand instead? May make debug
296 * easier to have it mapped).
298 desc->wq_base_addr = 0;
299 desc->db_base_addr = 0;
301 desc->stage_id = client->stage_id;
302 desc->wq_size_bytes = GUC_WQ_SIZE;
303 desc->wq_status = WQ_STATUS_ACTIVE;
304 desc->priority = client->priority;
307 static int guc_stage_desc_pool_create(struct intel_guc *guc)
309 struct i915_vma *vma;
312 vma = intel_guc_allocate_vma(guc,
313 PAGE_ALIGN(sizeof(struct guc_stage_desc) *
314 GUC_MAX_STAGE_DESCRIPTORS));
318 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
320 i915_vma_unpin_and_release(&vma, 0);
321 return PTR_ERR(vaddr);
324 guc->stage_desc_pool = vma;
325 guc->stage_desc_pool_vaddr = vaddr;
326 ida_init(&guc->stage_ids);
331 static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
333 ida_destroy(&guc->stage_ids);
334 i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP);
338 * Initialise/clear the stage descriptor shared with the GuC firmware.
340 * This descriptor tells the GuC where (in GGTT space) to find the important
341 * data structures relating to this client (doorbell, process descriptor,
344 static void guc_stage_desc_init(struct intel_guc *guc,
345 struct intel_guc_client *client)
347 struct drm_i915_private *dev_priv = guc_to_i915(guc);
348 struct intel_engine_cs *engine;
349 struct i915_gem_context *ctx = client->owner;
350 struct guc_stage_desc *desc;
354 desc = __get_stage_desc(client);
355 memset(desc, 0, sizeof(*desc));
357 desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE |
358 GUC_STAGE_DESC_ATTR_KERNEL;
359 if (is_high_priority(client))
360 desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT;
361 desc->stage_id = client->stage_id;
362 desc->priority = client->priority;
363 desc->db_id = client->doorbell_id;
365 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
366 struct intel_context *ce = to_intel_context(ctx, engine);
367 u32 guc_engine_id = engine->guc_id;
368 struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id];
370 /* TODO: We have a design issue to be solved here. Only when we
371 * receive the first batch, we know which engine is used by the
372 * user. But here GuC expects the lrc and ring to be pinned. It
373 * is not an issue for default context, which is the only one
374 * for now who owns a GuC client. But for future owner of GuC
375 * client, need to make sure lrc is pinned prior to enter here.
378 break; /* XXX: continue? */
381 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
382 * submission or, in other words, not using a direct submission
383 * model) the KMD's LRCA is not used for any work submission.
384 * Instead, the GuC uses the LRCA of the user mode context (see
385 * guc_add_request below).
387 lrc->context_desc = lower_32_bits(ce->lrc_desc);
389 /* The state page is after PPHWSP */
390 lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
391 LRC_STATE_PN * PAGE_SIZE;
393 /* XXX: In direct submission, the GuC wants the HW context id
394 * here. In proxy submission, it wants the stage id
396 lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
397 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
399 lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
400 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
401 lrc->ring_next_free_location = lrc->ring_begin;
402 lrc->ring_current_tail_pointer_value = 0;
404 desc->engines_used |= (1 << guc_engine_id);
407 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
408 client->engines, desc->engines_used);
409 WARN_ON(desc->engines_used == 0);
412 * The doorbell, process descriptor, and workqueue are all parts
413 * of the client object, which the GuC will reference via the GGTT
415 gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
416 desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
417 client->doorbell_offset;
418 desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
419 desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
420 desc->process_desc = gfx_addr + client->proc_desc_offset;
421 desc->wq_addr = gfx_addr + GUC_DB_SIZE;
422 desc->wq_size = GUC_WQ_SIZE;
424 desc->desc_private = ptr_to_u64(client);
427 static void guc_stage_desc_fini(struct intel_guc *guc,
428 struct intel_guc_client *client)
430 struct guc_stage_desc *desc;
432 desc = __get_stage_desc(client);
433 memset(desc, 0, sizeof(*desc));
436 /* Construct a Work Item and append it to the GuC's Work Queue */
437 static void guc_wq_item_append(struct intel_guc_client *client,
438 u32 target_engine, u32 context_desc,
439 u32 ring_tail, u32 fence_id)
441 /* wqi_len is in DWords, and does not include the one-word header */
442 const size_t wqi_size = sizeof(struct guc_wq_item);
443 const u32 wqi_len = wqi_size / sizeof(u32) - 1;
444 struct guc_process_desc *desc = __get_process_desc(client);
445 struct guc_wq_item *wqi;
448 lockdep_assert_held(&client->wq_lock);
450 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
451 * should not have the case where structure wqi is across page, neither
452 * wrapped to the beginning. This simplifies the implementation below.
454 * XXX: if not the case, we need save data to a temp wqi and copy it to
455 * workqueue buffer dw by dw.
457 BUILD_BUG_ON(wqi_size != 16);
459 /* We expect the WQ to be active if we're appending items to it */
460 GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE);
462 /* Free space is guaranteed. */
463 wq_off = READ_ONCE(desc->tail);
464 GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
465 GUC_WQ_SIZE) < wqi_size);
466 GEM_BUG_ON(wq_off & (wqi_size - 1));
468 /* WQ starts from the page after doorbell / process_desc */
469 wqi = client->vaddr + wq_off + GUC_DB_SIZE;
471 if (I915_SELFTEST_ONLY(client->use_nop_wqi)) {
472 wqi->header = WQ_TYPE_NOOP | (wqi_len << WQ_LEN_SHIFT);
474 /* Now fill in the 4-word work queue item */
475 wqi->header = WQ_TYPE_INORDER |
476 (wqi_len << WQ_LEN_SHIFT) |
477 (target_engine << WQ_TARGET_SHIFT) |
479 wqi->context_desc = context_desc;
480 wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
481 GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
482 wqi->fence_id = fence_id;
485 /* Make the update visible to GuC */
486 WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
489 static void guc_reset_wq(struct intel_guc_client *client)
491 struct guc_process_desc *desc = __get_process_desc(client);
497 static void guc_ring_doorbell(struct intel_guc_client *client)
499 struct guc_doorbell_info *db;
502 lockdep_assert_held(&client->wq_lock);
504 /* pointer of current doorbell cacheline */
505 db = __get_doorbell(client);
508 * We're not expecting the doorbell cookie to change behind our back,
509 * we also need to treat 0 as a reserved value.
511 cookie = READ_ONCE(db->cookie);
512 WARN_ON_ONCE(xchg(&db->cookie, cookie + 1 ?: cookie + 2) != cookie);
514 /* XXX: doorbell was lost and need to acquire it again */
515 GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
518 static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
520 struct intel_guc_client *client = guc->execbuf_client;
521 struct intel_engine_cs *engine = rq->engine;
522 u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);
523 u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
525 spin_lock(&client->wq_lock);
527 guc_wq_item_append(client, engine->guc_id, ctx_desc,
528 ring_tail, rq->global_seqno);
529 guc_ring_doorbell(client);
531 client->submissions[engine->id] += 1;
533 spin_unlock(&client->wq_lock);
537 * When we're doing submissions using regular execlists backend, writing to
538 * ELSP from CPU side is enough to make sure that writes to ringbuffer pages
539 * pinned in mappable aperture portion of GGTT are visible to command streamer.
540 * Writes done by GuC on our behalf are not guaranteeing such ordering,
541 * therefore, to ensure the flush, we're issuing a POSTING READ.
543 static void flush_ggtt_writes(struct i915_vma *vma)
545 struct drm_i915_private *dev_priv = vma->vm->i915;
547 if (i915_vma_is_map_and_fenceable(vma))
548 POSTING_READ_FW(GUC_STATUS);
551 static void inject_preempt_context(struct work_struct *work)
553 struct guc_preempt_work *preempt_work =
554 container_of(work, typeof(*preempt_work), work);
555 struct intel_engine_cs *engine = preempt_work->engine;
556 struct intel_guc *guc = container_of(preempt_work, typeof(*guc),
557 preempt_work[engine->id]);
558 struct intel_guc_client *client = guc->preempt_client;
559 struct guc_stage_desc *stage_desc = __get_stage_desc(client);
560 u32 ctx_desc = lower_32_bits(to_intel_context(client->owner,
565 * The ring contains commands to write GUC_PREEMPT_FINISHED into HWSP.
566 * See guc_fill_preempt_context().
568 spin_lock_irq(&client->wq_lock);
569 guc_wq_item_append(client, engine->guc_id, ctx_desc,
570 GUC_PREEMPT_BREADCRUMB_BYTES / sizeof(u64), 0);
571 spin_unlock_irq(&client->wq_lock);
574 * If GuC firmware performs an engine reset while that engine had
575 * a preemption pending, it will set the terminated attribute bit
576 * on our preemption stage descriptor. GuC firmware retains all
577 * pending work items for a high-priority GuC client, unlike the
578 * normal-priority GuC client where work items are dropped. It
579 * wants to make sure the preempt-to-idle work doesn't run when
580 * scheduling resumes, and uses this bit to inform its scheduler
581 * and presumably us as well. Our job is to clear it for the next
582 * preemption after reset, otherwise that and future preemptions
583 * will never complete. We'll just clear it every time.
585 stage_desc->attribute &= ~GUC_STAGE_DESC_ATTR_TERMINATED;
587 data[0] = INTEL_GUC_ACTION_REQUEST_PREEMPTION;
588 data[1] = client->stage_id;
589 data[2] = INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q |
590 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q;
591 data[3] = engine->guc_id;
592 data[4] = guc->execbuf_client->priority;
593 data[5] = guc->execbuf_client->stage_id;
594 data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
596 if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
597 execlists_clear_active(&engine->execlists,
598 EXECLISTS_ACTIVE_PREEMPT);
599 tasklet_schedule(&engine->execlists.tasklet);
604 * We're using user interrupt and HWSP value to mark that preemption has
605 * finished and GPU is idle. Normally, we could unwind and continue similar to
606 * execlists submission path. Unfortunately, with GuC we also need to wait for
607 * it to finish its own postprocessing, before attempting to submit. Otherwise
608 * GuC may silently ignore our submissions, and thus we risk losing request at
609 * best, executing out-of-order and causing kernel panic at worst.
611 #define GUC_PREEMPT_POSTPROCESS_DELAY_MS 10
612 static void wait_for_guc_preempt_report(struct intel_engine_cs *engine)
614 struct intel_guc *guc = &engine->i915->guc;
615 struct guc_shared_ctx_data *data = guc->shared_data_vaddr;
616 struct guc_ctx_report *report =
617 &data->preempt_ctx_report[engine->guc_id];
619 WARN_ON(wait_for_atomic(report->report_return_status ==
620 INTEL_GUC_REPORT_STATUS_COMPLETE,
621 GUC_PREEMPT_POSTPROCESS_DELAY_MS));
623 * GuC is expecting that we're also going to clear the affected context
624 * counter, let's also reset the return status to not depend on GuC
625 * resetting it after recieving another preempt action
627 report->affected_count = 0;
628 report->report_return_status = INTEL_GUC_REPORT_STATUS_UNKNOWN;
631 static void complete_preempt_context(struct intel_engine_cs *engine)
633 struct intel_engine_execlists *execlists = &engine->execlists;
635 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
637 if (inject_preempt_hang(execlists))
640 execlists_cancel_port_requests(execlists);
641 execlists_unwind_incomplete_requests(execlists);
643 wait_for_guc_preempt_report(engine);
644 intel_write_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX, 0);
648 * guc_submit() - Submit commands through GuC
649 * @engine: engine associated with the commands
651 * The only error here arises if the doorbell hardware isn't functioning
652 * as expected, which really shouln't happen.
654 static void guc_submit(struct intel_engine_cs *engine)
656 struct intel_guc *guc = &engine->i915->guc;
657 struct intel_engine_execlists * const execlists = &engine->execlists;
658 struct execlist_port *port = execlists->port;
661 for (n = 0; n < execlists_num_ports(execlists); n++) {
662 struct i915_request *rq;
665 rq = port_unpack(&port[n], &count);
666 if (rq && count == 0) {
667 port_set(&port[n], port_pack(rq, ++count));
669 flush_ggtt_writes(rq->ring->vma);
671 guc_add_request(guc, rq);
676 static void port_assign(struct execlist_port *port, struct i915_request *rq)
678 GEM_BUG_ON(port_isset(port));
680 port_set(port, i915_request_get(rq));
683 static inline int rq_prio(const struct i915_request *rq)
685 return rq->sched.attr.priority;
688 static inline int port_prio(const struct execlist_port *port)
690 return rq_prio(port_request(port));
693 static bool __guc_dequeue(struct intel_engine_cs *engine)
695 struct intel_engine_execlists * const execlists = &engine->execlists;
696 struct execlist_port *port = execlists->port;
697 struct i915_request *last = NULL;
698 const struct execlist_port * const last_port =
699 &execlists->port[execlists->port_mask];
703 lockdep_assert_held(&engine->timeline.lock);
705 if (port_isset(port)) {
706 if (intel_engine_has_preemption(engine)) {
707 struct guc_preempt_work *preempt_work =
708 &engine->i915->guc.preempt_work[engine->id];
709 int prio = execlists->queue_priority;
711 if (__execlists_need_preempt(prio, port_prio(port))) {
712 execlists_set_active(execlists,
713 EXECLISTS_ACTIVE_PREEMPT);
714 queue_work(engine->i915->guc.preempt_wq,
715 &preempt_work->work);
721 if (port_isset(port))
724 GEM_BUG_ON(port_isset(port));
726 while ((rb = rb_first_cached(&execlists->queue))) {
727 struct i915_priolist *p = to_priolist(rb);
728 struct i915_request *rq, *rn;
730 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
731 if (last && rq->hw_context != last->hw_context) {
732 if (port == last_port) {
733 __list_del_many(&p->requests,
739 port_assign(port, last);
743 INIT_LIST_HEAD(&rq->sched.link);
745 __i915_request_submit(rq);
746 trace_i915_request_in(rq, port_index(port, execlists));
751 rb_erase_cached(&p->node, &execlists->queue);
752 INIT_LIST_HEAD(&p->requests);
753 if (p->priority != I915_PRIORITY_NORMAL)
754 kmem_cache_free(engine->i915->priorities, p);
757 execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
759 port_assign(port, last);
761 execlists_user_begin(execlists, execlists->port);
763 /* We must always keep the beast fed if we have work piled up */
764 GEM_BUG_ON(port_isset(execlists->port) &&
765 !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
766 GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
767 !port_isset(execlists->port));
772 static void guc_dequeue(struct intel_engine_cs *engine)
777 local_irq_save(flags);
779 spin_lock(&engine->timeline.lock);
780 submit = __guc_dequeue(engine);
781 spin_unlock(&engine->timeline.lock);
786 local_irq_restore(flags);
789 static void guc_submission_tasklet(unsigned long data)
791 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
792 struct intel_engine_execlists * const execlists = &engine->execlists;
793 struct execlist_port *port = execlists->port;
794 struct i915_request *rq;
796 rq = port_request(port);
797 while (rq && i915_request_completed(rq)) {
798 trace_i915_request_out(rq);
799 i915_request_put(rq);
801 port = execlists_port_complete(execlists, port);
802 if (port_isset(port)) {
803 execlists_user_begin(execlists, port);
804 rq = port_request(port);
806 execlists_user_end(execlists);
811 if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) &&
812 intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) ==
813 GUC_PREEMPT_FINISHED)
814 complete_preempt_context(engine);
816 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
820 static struct i915_request *
821 guc_reset_prepare(struct intel_engine_cs *engine)
823 struct intel_engine_execlists * const execlists = &engine->execlists;
825 GEM_TRACE("%s\n", engine->name);
828 * Prevent request submission to the hardware until we have
829 * completed the reset in i915_gem_reset_finish(). If a request
830 * is completed by one engine, it may then queue a request
831 * to a second via its execlists->tasklet *just* as we are
832 * calling engine->init_hw() and also writing the ELSP.
833 * Turning off the execlists->tasklet until the reset is over
836 __tasklet_disable_sync_once(&execlists->tasklet);
839 * We're using worker to queue preemption requests from the tasklet in
840 * GuC submission mode.
841 * Even though tasklet was disabled, we may still have a worker queued.
842 * Let's make sure that all workers scheduled before disabling the
843 * tasklet are completed before continuing with the reset.
845 if (engine->i915->guc.preempt_wq)
846 flush_workqueue(engine->i915->guc.preempt_wq);
848 return i915_gem_find_active_request(engine);
852 * Everything below here is concerned with setup & teardown, and is
853 * therefore not part of the somewhat time-critical batch-submission
854 * path of guc_submit() above.
857 /* Check that a doorbell register is in the expected state */
858 static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
860 struct drm_i915_private *dev_priv = guc_to_i915(guc);
864 GEM_BUG_ON(db_id >= GUC_DOORBELL_INVALID);
866 drbregl = I915_READ(GEN8_DRBREGL(db_id));
867 valid = drbregl & GEN8_DRB_VALID;
869 if (test_bit(db_id, guc->doorbell_bitmap) == valid)
872 DRM_DEBUG_DRIVER("Doorbell %d has unexpected state (0x%x): valid=%s\n",
873 db_id, drbregl, yesno(valid));
878 static bool guc_verify_doorbells(struct intel_guc *guc)
882 for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id)
883 if (!doorbell_ok(guc, db_id))
889 static int guc_clients_doorbell_init(struct intel_guc *guc)
893 ret = create_doorbell(guc->execbuf_client);
897 if (guc->preempt_client) {
898 ret = create_doorbell(guc->preempt_client);
900 destroy_doorbell(guc->execbuf_client);
908 static void guc_clients_doorbell_fini(struct intel_guc *guc)
911 * By the time we're here, GuC has already been reset.
912 * Instead of trying (in vain) to communicate with it, let's just
913 * cleanup the doorbell HW and our internal state.
915 if (guc->preempt_client) {
916 __destroy_doorbell(guc->preempt_client);
917 __update_doorbell_desc(guc->preempt_client,
918 GUC_DOORBELL_INVALID);
921 if (guc->execbuf_client) {
922 __destroy_doorbell(guc->execbuf_client);
923 __update_doorbell_desc(guc->execbuf_client,
924 GUC_DOORBELL_INVALID);
929 * guc_client_alloc() - Allocate an intel_guc_client
930 * @dev_priv: driver private data structure
931 * @engines: The set of engines to enable for this client
932 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
933 * The kernel client to replace ExecList submission is created with
934 * NORMAL priority. Priority of a client for scheduler can be HIGH,
935 * while a preemption context can use CRITICAL.
936 * @ctx: the context that owns the client (we use the default render
939 * Return: An intel_guc_client object if success, else NULL.
941 static struct intel_guc_client *
942 guc_client_alloc(struct drm_i915_private *dev_priv,
945 struct i915_gem_context *ctx)
947 struct intel_guc_client *client;
948 struct intel_guc *guc = &dev_priv->guc;
949 struct i915_vma *vma;
953 client = kzalloc(sizeof(*client), GFP_KERNEL);
955 return ERR_PTR(-ENOMEM);
959 client->engines = engines;
960 client->priority = priority;
961 client->doorbell_id = GUC_DOORBELL_INVALID;
962 spin_lock_init(&client->wq_lock);
964 ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
969 client->stage_id = ret;
971 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
972 vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
978 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
981 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
983 ret = PTR_ERR(vaddr);
986 client->vaddr = vaddr;
988 client->doorbell_offset = __select_cacheline(guc);
991 * Since the doorbell only requires a single cacheline, we can save
992 * space by putting the application process descriptor in the same
993 * page. Use the half of the page that doesn't include the doorbell.
995 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
996 client->proc_desc_offset = 0;
998 client->proc_desc_offset = (GUC_DB_SIZE / 2);
1000 guc_proc_desc_init(guc, client);
1001 guc_stage_desc_init(guc, client);
1003 ret = reserve_doorbell(client);
1007 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
1008 priority, client, client->engines, client->stage_id);
1009 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
1010 client->doorbell_id, client->doorbell_offset);
1015 i915_gem_object_unpin_map(client->vma->obj);
1017 i915_vma_unpin_and_release(&client->vma, 0);
1019 ida_simple_remove(&guc->stage_ids, client->stage_id);
1022 return ERR_PTR(ret);
1025 static void guc_client_free(struct intel_guc_client *client)
1027 unreserve_doorbell(client);
1028 guc_stage_desc_fini(client->guc, client);
1029 i915_vma_unpin_and_release(&client->vma, I915_VMA_RELEASE_MAP);
1030 ida_simple_remove(&client->guc->stage_ids, client->stage_id);
1034 static inline bool ctx_save_restore_disabled(struct intel_context *ce)
1036 u32 sr = ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1];
1038 #define SR_DISABLED \
1039 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \
1040 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)
1042 return (sr & SR_DISABLED) == SR_DISABLED;
1047 static void guc_fill_preempt_context(struct intel_guc *guc)
1049 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1050 struct intel_guc_client *client = guc->preempt_client;
1051 struct intel_engine_cs *engine;
1052 enum intel_engine_id id;
1054 for_each_engine(engine, dev_priv, id) {
1055 struct intel_context *ce =
1056 to_intel_context(client->owner, engine);
1057 u32 addr = intel_hws_preempt_done_address(engine);
1060 GEM_BUG_ON(!ce->pin_count);
1063 * We rely on this context image *not* being saved after
1064 * preemption. This ensures that the RING_HEAD / RING_TAIL
1065 * remain pointing at initial values forever.
1067 GEM_BUG_ON(!ctx_save_restore_disabled(ce));
1069 cs = ce->ring->vaddr;
1071 cs = gen8_emit_ggtt_write_rcs(cs,
1072 GUC_PREEMPT_FINISHED,
1075 cs = gen8_emit_ggtt_write(cs,
1076 GUC_PREEMPT_FINISHED,
1081 *cs++ = MI_USER_INTERRUPT;
1084 GEM_BUG_ON((void *)cs - ce->ring->vaddr !=
1085 GUC_PREEMPT_BREADCRUMB_BYTES);
1087 flush_ggtt_writes(ce->ring->vma);
1091 static int guc_clients_create(struct intel_guc *guc)
1093 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1094 struct intel_guc_client *client;
1096 GEM_BUG_ON(guc->execbuf_client);
1097 GEM_BUG_ON(guc->preempt_client);
1099 client = guc_client_alloc(dev_priv,
1100 INTEL_INFO(dev_priv)->ring_mask,
1101 GUC_CLIENT_PRIORITY_KMD_NORMAL,
1102 dev_priv->kernel_context);
1103 if (IS_ERR(client)) {
1104 DRM_ERROR("Failed to create GuC client for submission!\n");
1105 return PTR_ERR(client);
1107 guc->execbuf_client = client;
1109 if (dev_priv->preempt_context) {
1110 client = guc_client_alloc(dev_priv,
1111 INTEL_INFO(dev_priv)->ring_mask,
1112 GUC_CLIENT_PRIORITY_KMD_HIGH,
1113 dev_priv->preempt_context);
1114 if (IS_ERR(client)) {
1115 DRM_ERROR("Failed to create GuC client for preemption!\n");
1116 guc_client_free(guc->execbuf_client);
1117 guc->execbuf_client = NULL;
1118 return PTR_ERR(client);
1120 guc->preempt_client = client;
1122 guc_fill_preempt_context(guc);
1128 static void guc_clients_destroy(struct intel_guc *guc)
1130 struct intel_guc_client *client;
1132 client = fetch_and_zero(&guc->preempt_client);
1134 guc_client_free(client);
1136 client = fetch_and_zero(&guc->execbuf_client);
1138 guc_client_free(client);
1142 * Set up the memory resources to be shared with the GuC (via the GGTT)
1143 * at firmware loading time.
1145 int intel_guc_submission_init(struct intel_guc *guc)
1147 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1148 struct intel_engine_cs *engine;
1149 enum intel_engine_id id;
1152 if (guc->stage_desc_pool)
1155 ret = guc_stage_desc_pool_create(guc);
1159 * Keep static analysers happy, let them know that we allocated the
1160 * vma after testing that it didn't exist earlier.
1162 GEM_BUG_ON(!guc->stage_desc_pool);
1164 WARN_ON(!guc_verify_doorbells(guc));
1165 ret = guc_clients_create(guc);
1169 for_each_engine(engine, dev_priv, id) {
1170 guc->preempt_work[id].engine = engine;
1171 INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context);
1177 guc_stage_desc_pool_destroy(guc);
1181 void intel_guc_submission_fini(struct intel_guc *guc)
1183 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1184 struct intel_engine_cs *engine;
1185 enum intel_engine_id id;
1187 for_each_engine(engine, dev_priv, id)
1188 cancel_work_sync(&guc->preempt_work[id].work);
1190 guc_clients_destroy(guc);
1191 WARN_ON(!guc_verify_doorbells(guc));
1193 if (guc->stage_desc_pool)
1194 guc_stage_desc_pool_destroy(guc);
1197 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
1199 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1200 struct intel_engine_cs *engine;
1201 enum intel_engine_id id;
1204 /* tell all command streamers to forward interrupts (but not vblank)
1207 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
1208 for_each_engine(engine, dev_priv, id)
1209 I915_WRITE(RING_MODE_GEN7(engine), irqs);
1211 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
1212 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
1213 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1214 /* These three registers have the same bit definitions */
1215 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
1216 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
1217 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
1220 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
1221 * (unmasked) PM interrupts to the GuC. All other bits of this
1222 * register *disable* generation of a specific interrupt.
1224 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
1225 * writing to the PM interrupt mask register, i.e. interrupts
1226 * that must not be disabled.
1228 * If the GuC is handling these interrupts, then we must not let
1229 * the PM code disable ANY interrupt that the GuC is expecting.
1230 * So for each ENABLED (0) bit in this register, we must SET the
1231 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
1232 * GuC needs ARAT expired interrupt unmasked hence it is set in
1235 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
1236 * result in the register bit being left SET!
1238 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
1239 rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
1242 static void guc_interrupts_release(struct drm_i915_private *dev_priv)
1244 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1245 struct intel_engine_cs *engine;
1246 enum intel_engine_id id;
1250 * tell all command streamers NOT to forward interrupts or vblank
1253 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
1254 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
1255 for_each_engine(engine, dev_priv, id)
1256 I915_WRITE(RING_MODE_GEN7(engine), irqs);
1258 /* route all GT interrupts to the host */
1259 I915_WRITE(GUC_BCS_RCS_IER, 0);
1260 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
1261 I915_WRITE(GUC_WD_VECS_IER, 0);
1263 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
1264 rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
1267 static void guc_submission_park(struct intel_engine_cs *engine)
1269 intel_engine_unpin_breadcrumbs_irq(engine);
1272 static void guc_submission_unpark(struct intel_engine_cs *engine)
1274 intel_engine_pin_breadcrumbs_irq(engine);
1277 static void guc_set_default_submission(struct intel_engine_cs *engine)
1280 * We inherit a bunch of functions from execlists that we'd like
1283 * engine->submit_request = execlists_submit_request;
1284 * engine->cancel_requests = execlists_cancel_requests;
1285 * engine->schedule = execlists_schedule;
1287 * But we need to override the actual submission backend in order
1288 * to talk to the GuC.
1290 intel_execlists_set_default_submission(engine);
1292 engine->execlists.tasklet.func = guc_submission_tasklet;
1294 engine->park = guc_submission_park;
1295 engine->unpark = guc_submission_unpark;
1297 engine->reset.prepare = guc_reset_prepare;
1299 engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
1302 int intel_guc_submission_enable(struct intel_guc *guc)
1304 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1305 struct intel_engine_cs *engine;
1306 enum intel_engine_id id;
1310 * We're using GuC work items for submitting work through GuC. Since
1311 * we're coalescing multiple requests from a single context into a
1312 * single work item prior to assigning it to execlist_port, we can
1313 * never have more work items than the total number of ports (for all
1314 * engines). The GuC firmware is controlling the HEAD of work queue,
1315 * and it is guaranteed that it will remove the work item from the
1316 * queue before our request is completed.
1318 BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
1319 sizeof(struct guc_wq_item) *
1320 I915_NUM_ENGINES > GUC_WQ_SIZE);
1322 GEM_BUG_ON(!guc->execbuf_client);
1324 guc_reset_wq(guc->execbuf_client);
1325 if (guc->preempt_client)
1326 guc_reset_wq(guc->preempt_client);
1328 err = intel_guc_sample_forcewake(guc);
1332 err = guc_clients_doorbell_init(guc);
1336 /* Take over from manual control of ELSP (execlists) */
1337 guc_interrupts_capture(dev_priv);
1339 for_each_engine(engine, dev_priv, id) {
1340 engine->set_default_submission = guc_set_default_submission;
1341 engine->set_default_submission(engine);
1347 void intel_guc_submission_disable(struct intel_guc *guc)
1349 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1351 GEM_BUG_ON(dev_priv->gt.awake); /* GT should be parked first */
1353 guc_interrupts_release(dev_priv);
1354 guc_clients_doorbell_fini(guc);
1357 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1358 #include "selftests/intel_guc.c"