drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_INFO(dev_priv)->gen < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_INFO(dev_priv)->gen <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  73 {
  74         return crtc->base.y - crtc->adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         int w, h;
  86
  87         if (drm_rotation_90_or_270(cache->plane.rotation)) {
  88                 w = cache->plane.src_h;
  89                 h = cache->plane.src_w;
  90         } else {
  91                 w = cache->plane.src_w;
  92                 h = cache->plane.src_h;
  93         }
  94
  95         if (width)
  96                 *width = w;
  97         if (height)
  98                 *height = h;
  99 }
 100
 101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 102                                         struct intel_fbc_state_cache *cache)
 103 {
 104         int lines;
 105
 106         intel_fbc_get_plane_source_size(cache, NULL, &lines);
 107         if (INTEL_INFO(dev_priv)->gen >= 7)
 108                 lines = min(lines, 2048);
 109
 110         /* Hardware needs the full buffer stride, not just the active area. */
 111         return lines * cache->fb.stride;
 112 }
 113
 114 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 115 {
 116         u32 fbc_ctl;
 117
 118         /* Disable compression */
 119         fbc_ctl = I915_READ(FBC_CONTROL);
 120         if ((fbc_ctl & FBC_CTL_EN) == 0)
 121                 return;
 122
 123         fbc_ctl &= ~FBC_CTL_EN;
 124         I915_WRITE(FBC_CONTROL, fbc_ctl);
 125
 126         /* Wait for compressing bit to clear */
 127         if (intel_wait_for_register(dev_priv,
 128                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 129                                     10)) {
 130                 DRM_DEBUG_KMS("FBC idle timed out\n");
 131                 return;
 132         }
 133 }
 134
 135 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 136 {
 137         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 138         int cfb_pitch;
 139         int i;
 140         u32 fbc_ctl;
 141
 142         /* Note: fbc.threshold == 1 for i8xx */
 143         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 144         if (params->fb.stride < cfb_pitch)
 145                 cfb_pitch = params->fb.stride;
 146
 147         /* FBC_CTL wants 32B or 64B units */
 148         if (IS_GEN2(dev_priv))
 149                 cfb_pitch = (cfb_pitch / 32) - 1;
 150         else
 151                 cfb_pitch = (cfb_pitch / 64) - 1;
 152
 153         /* Clear old tags */
 154         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 155                 I915_WRITE(FBC_TAG(i), 0);
 156
 157         if (IS_GEN4(dev_priv)) {
 158                 u32 fbc_ctl2;
 159
 160                 /* Set it up... */
 161                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 162                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
 163                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 164                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 165         }
 166
 167         /* enable it... */
 168         fbc_ctl = I915_READ(FBC_CONTROL);
 169         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 170         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 171         if (IS_I945GM(dev_priv))
 172                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 173         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 174         fbc_ctl |= params->fb.fence_reg;
 175         I915_WRITE(FBC_CONTROL, fbc_ctl);
 176 }
 177
 178 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 179 {
 180         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 181 }
 182
 183 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 184 {
 185         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 186         u32 dpfc_ctl;
 187
 188         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
 189         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 190                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 191         else
 192                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 193
 194         if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
 195                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
 196                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 197         } else {
 198                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 199         }
 200
 201         /* enable it... */
 202         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 203 }
 204
 205 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 206 {
 207         u32 dpfc_ctl;
 208
 209         /* Disable compression */
 210         dpfc_ctl = I915_READ(DPFC_CONTROL);
 211         if (dpfc_ctl & DPFC_CTL_EN) {
 212                 dpfc_ctl &= ~DPFC_CTL_EN;
 213                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 214         }
 215 }
 216
 217 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 218 {
 219         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 220 }
 221
 222 /* This function forces a CFB recompression through the nuke operation. */
 223 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 224 {
 225         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 226         POSTING_READ(MSG_FBC_REND_STATE);
 227 }
 228
 229 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 230 {
 231         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 232         u32 dpfc_ctl;
 233         int threshold = dev_priv->fbc.threshold;
 234
 235         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
 236         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 237                 threshold++;
 238
 239         switch (threshold) {
 240         case 4:
 241         case 3:
 242                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 243                 break;
 244         case 2:
 245                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 246                 break;
 247         case 1:
 248                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 249                 break;
 250         }
 251
 252         if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
 253                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 254                 if (IS_GEN5(dev_priv))
 255                         dpfc_ctl |= params->fb.fence_reg;
 256                 if (IS_GEN6(dev_priv)) {
 257                         I915_WRITE(SNB_DPFC_CTL_SA,
 258                                    SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 259                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 260                                    params->crtc.fence_y_offset);
 261                 }
 262         } else {
 263                 if (IS_GEN6(dev_priv)) {
 264                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 265                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 266                 }
 267         }
 268
 269         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 270         I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
 271         /* enable it... */
 272         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 273
 274         intel_fbc_recompress(dev_priv);
 275 }
 276
 277 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 278 {
 279         u32 dpfc_ctl;
 280
 281         /* Disable compression */
 282         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 283         if (dpfc_ctl & DPFC_CTL_EN) {
 284                 dpfc_ctl &= ~DPFC_CTL_EN;
 285                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 286         }
 287 }
 288
 289 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 290 {
 291         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 292 }
 293
 294 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 295 {
 296         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 297         u32 dpfc_ctl;
 298         int threshold = dev_priv->fbc.threshold;
 299
 300         dpfc_ctl = 0;
 301         if (IS_IVYBRIDGE(dev_priv))
 302                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
 303
 304         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 305                 threshold++;
 306
 307         switch (threshold) {
 308         case 4:
 309         case 3:
 310                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 311                 break;
 312         case 2:
 313                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 314                 break;
 315         case 1:
 316                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 317                 break;
 318         }
 319
 320         if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
 321                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 322                 I915_WRITE(SNB_DPFC_CTL_SA,
 323                            SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 324                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 325         } else {
 326                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 327                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 328         }
 329
 330         if (dev_priv->fbc.false_color)
 331                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 332
 333         if (IS_IVYBRIDGE(dev_priv)) {
 334                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 335                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 336                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 337                            ILK_FBCQ_DIS);
 338         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 339                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 340                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 341                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 342                            HSW_FBCQ_DIS);
 343         }
 344
 345         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 346
 347         intel_fbc_recompress(dev_priv);
 348 }
 349
 350 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 351 {
 352         if (INTEL_INFO(dev_priv)->gen >= 5)
 353                 return ilk_fbc_is_active(dev_priv);
 354         else if (IS_GM45(dev_priv))
 355                 return g4x_fbc_is_active(dev_priv);
 356         else
 357                 return i8xx_fbc_is_active(dev_priv);
 358 }
 359
 360 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 361 {
 362         struct intel_fbc *fbc = &dev_priv->fbc;
 363
 364         fbc->active = true;
 365
 366         if (INTEL_INFO(dev_priv)->gen >= 7)
 367                 gen7_fbc_activate(dev_priv);
 368         else if (INTEL_INFO(dev_priv)->gen >= 5)
 369                 ilk_fbc_activate(dev_priv);
 370         else if (IS_GM45(dev_priv))
 371                 g4x_fbc_activate(dev_priv);
 372         else
 373                 i8xx_fbc_activate(dev_priv);
 374 }
 375
 376 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 377 {
 378         struct intel_fbc *fbc = &dev_priv->fbc;
 379
 380         fbc->active = false;
 381
 382         if (INTEL_INFO(dev_priv)->gen >= 5)
 383                 ilk_fbc_deactivate(dev_priv);
 384         else if (IS_GM45(dev_priv))
 385                 g4x_fbc_deactivate(dev_priv);
 386         else
 387                 i8xx_fbc_deactivate(dev_priv);
 388 }
 389
 390 /**
 391  * intel_fbc_is_active - Is FBC active?
 392  * @dev_priv: i915 device instance
 393  *
 394  * This function is used to verify the current state of FBC.
 395  *
 396  * FIXME: This should be tracked in the plane config eventually
 397  * instead of queried at runtime for most callers.
 398  */
 399 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 400 {
 401         return dev_priv->fbc.active;
 402 }
 403
 404 static void intel_fbc_work_fn(struct work_struct *__work)
 405 {
 406         struct drm_i915_private *dev_priv =
 407                 container_of(__work, struct drm_i915_private, fbc.work.work);
 408         struct intel_fbc *fbc = &dev_priv->fbc;
 409         struct intel_fbc_work *work = &fbc->work;
 410         struct intel_crtc *crtc = fbc->crtc;
 411         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 412
 413         if (drm_crtc_vblank_get(&crtc->base)) {
 414                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 415                           pipe_name(crtc->pipe));
 416
 417                 mutex_lock(&fbc->lock);
 418                 work->scheduled = false;
 419                 mutex_unlock(&fbc->lock);
 420                 return;
 421         }
 422
 423 retry:
 424         /* Delay the actual enabling to let pageflipping cease and the
 425          * display to settle before starting the compression. Note that
 426          * this delay also serves a second purpose: it allows for a
 427          * vblank to pass after disabling the FBC before we attempt
 428          * to modify the control registers.
 429          *
 430          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 431          *
 432          * It is also worth mentioning that since work->scheduled_vblank can be
 433          * updated multiple times by the other threads, hitting the timeout is
 434          * not an error condition. We'll just end up hitting the "goto retry"
 435          * case below.
 436          */
 437         wait_event_timeout(vblank->queue,
 438                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 439                 msecs_to_jiffies(50));
 440
 441         mutex_lock(&fbc->lock);
 442
 443         /* Were we cancelled? */
 444         if (!work->scheduled)
 445                 goto out;
 446
 447         /* Were we delayed again while this function was sleeping? */
 448         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 449                 mutex_unlock(&fbc->lock);
 450                 goto retry;
 451         }
 452
 453         intel_fbc_hw_activate(dev_priv);
 454
 455         work->scheduled = false;
 456
 457 out:
 458         mutex_unlock(&fbc->lock);
 459         drm_crtc_vblank_put(&crtc->base);
 460 }
 461
 462 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 463 {
 464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 465         struct intel_fbc *fbc = &dev_priv->fbc;
 466         struct intel_fbc_work *work = &fbc->work;
 467
 468         WARN_ON(!mutex_is_locked(&fbc->lock));
 469
 470         if (drm_crtc_vblank_get(&crtc->base)) {
 471                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 472                           pipe_name(crtc->pipe));
 473                 return;
 474         }
 475
 476         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 477          * this function since we're not releasing fbc.lock, so it won't have an
 478          * opportunity to grab it to discover that it was cancelled. So we just
 479          * update the expected jiffy count. */
 480         work->scheduled = true;
 481         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 482         drm_crtc_vblank_put(&crtc->base);
 483
 484         schedule_work(&work->work);
 485 }
 486
 487 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 488 {
 489         struct intel_fbc *fbc = &dev_priv->fbc;
 490
 491         WARN_ON(!mutex_is_locked(&fbc->lock));
 492
 493         /* Calling cancel_work() here won't help due to the fact that the work
 494          * function grabs fbc->lock. Just set scheduled to false so the work
 495          * function can know it was cancelled. */
 496         fbc->work.scheduled = false;
 497
 498         if (fbc->active)
 499                 intel_fbc_hw_deactivate(dev_priv);
 500 }
 501
 502 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 503                               struct intel_plane_state *plane_state)
 504 {
 505         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 506         struct intel_fbc *fbc = &dev_priv->fbc;
 507         enum pipe pipe = crtc->pipe;
 508
 509         /* Don't even bother tracking anything we don't need. */
 510         if (!no_fbc_on_multiple_pipes(dev_priv))
 511                 return true;
 512
 513         if (plane_state->base.visible)
 514                 fbc->visible_pipes_mask |= (1 << pipe);
 515         else
 516                 fbc->visible_pipes_mask &= ~(1 << pipe);
 517
 518         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 519 }
 520
 521 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 522                                       struct drm_mm_node *node,
 523                                       int size,
 524                                       int fb_cpp)
 525 {
 526         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 527         int compression_threshold = 1;
 528         int ret;
 529         u64 end;
 530
 531         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 532          * reserved range size, so it always assumes the maximum (8mb) is used.
 533          * If we enable FBC using a CFB on that memory range we'll get FIFO
 534          * underruns, even if that range is not reserved by the BIOS. */
 535         if (IS_BROADWELL(dev_priv) ||
 536             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 537                 end = ggtt->stolen_size - 8 * 1024 * 1024;
 538         else
 539                 end = ggtt->stolen_usable_size;
 540
 541         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 542          * code changes, this code needs to change as well.
 543          *
 544          * The enable_fbc code will attempt to use one of our 2 compression
 545          * thresholds, therefore, in that case, we only have 1 resort.
 546          */
 547
 548         /* Try to over-allocate to reduce reallocations and fragmentation. */
 549         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 550                                                    4096, 0, end);
 551         if (ret == 0)
 552                 return compression_threshold;
 553
 554 again:
 555         /* HW's ability to limit the CFB is 1:4 */
 556         if (compression_threshold > 4 ||
 557             (fb_cpp == 2 && compression_threshold == 2))
 558                 return 0;
 559
 560         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 561                                                    4096, 0, end);
 562         if (ret && INTEL_INFO(dev_priv)->gen <= 4) {
 563                 return 0;
 564         } else if (ret) {
 565                 compression_threshold <<= 1;
 566                 goto again;
 567         } else {
 568                 return compression_threshold;
 569         }
 570 }
 571
 572 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 573 {
 574         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 575         struct intel_fbc *fbc = &dev_priv->fbc;
 576         struct drm_mm_node *uninitialized_var(compressed_llb);
 577         int size, fb_cpp, ret;
 578
 579         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 580
 581         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 582         fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0);
 583
 584         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 585                                          size, fb_cpp);
 586         if (!ret)
 587                 goto err_llb;
 588         else if (ret > 1) {
 589                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 590
 591         }
 592
 593         fbc->threshold = ret;
 594
 595         if (INTEL_INFO(dev_priv)->gen >= 5)
 596                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 597         else if (IS_GM45(dev_priv)) {
 598                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 599         } else {
 600                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 601                 if (!compressed_llb)
 602                         goto err_fb;
 603
 604                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 605                                                   4096, 4096);
 606                 if (ret)
 607                         goto err_fb;
 608
 609                 fbc->compressed_llb = compressed_llb;
 610
 611                 I915_WRITE(FBC_CFB_BASE,
 612                            dev_priv->mm.stolen_base + fbc->compressed_fb.start);
 613                 I915_WRITE(FBC_LL_BASE,
 614                            dev_priv->mm.stolen_base + compressed_llb->start);
 615         }
 616
 617         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 618                       fbc->compressed_fb.size, fbc->threshold);
 619
 620         return 0;
 621
 622 err_fb:
 623         kfree(compressed_llb);
 624         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 625 err_llb:
 626         pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 627         return -ENOSPC;
 628 }
 629
 630 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 631 {
 632         struct intel_fbc *fbc = &dev_priv->fbc;
 633
 634         if (drm_mm_node_allocated(&fbc->compressed_fb))
 635                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 636
 637         if (fbc->compressed_llb) {
 638                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 639                 kfree(fbc->compressed_llb);
 640         }
 641 }
 642
 643 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 644 {
 645         struct intel_fbc *fbc = &dev_priv->fbc;
 646
 647         if (!fbc_supported(dev_priv))
 648                 return;
 649
 650         mutex_lock(&fbc->lock);
 651         __intel_fbc_cleanup_cfb(dev_priv);
 652         mutex_unlock(&fbc->lock);
 653 }
 654
 655 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 656                             unsigned int stride)
 657 {
 658         /* These should have been caught earlier. */
 659         WARN_ON(stride < 512);
 660         WARN_ON((stride & (64 - 1)) != 0);
 661
 662         /* Below are the additional FBC restrictions. */
 663
 664         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 665                 return stride == 4096 || stride == 8192;
 666
 667         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 668                 return false;
 669
 670         if (stride > 16384)
 671                 return false;
 672
 673         return true;
 674 }
 675
 676 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 677                                   uint32_t pixel_format)
 678 {
 679         switch (pixel_format) {
 680         case DRM_FORMAT_XRGB8888:
 681         case DRM_FORMAT_XBGR8888:
 682                 return true;
 683         case DRM_FORMAT_XRGB1555:
 684         case DRM_FORMAT_RGB565:
 685                 /* 16bpp not supported on gen2 */
 686                 if (IS_GEN2(dev_priv))
 687                         return false;
 688                 /* WaFbcOnly1to1Ratio:ctg */
 689                 if (IS_G4X(dev_priv))
 690                         return false;
 691                 return true;
 692         default:
 693                 return false;
 694         }
 695 }
 696
 697 /*
 698  * For some reason, the hardware tracking starts looking at whatever we
 699  * programmed as the display plane base address register. It does not look at
 700  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 701  * variables instead of just looking at the pipe/plane size.
 702  */
 703 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 704 {
 705         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 706         struct intel_fbc *fbc = &dev_priv->fbc;
 707         unsigned int effective_w, effective_h, max_w, max_h;
 708
 709         if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) {
 710                 max_w = 4096;
 711                 max_h = 4096;
 712         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
 713                 max_w = 4096;
 714                 max_h = 2048;
 715         } else {
 716                 max_w = 2048;
 717                 max_h = 1536;
 718         }
 719
 720         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 721                                         &effective_h);
 722         effective_w += crtc->adjusted_x;
 723         effective_h += crtc->adjusted_y;
 724
 725         return effective_w <= max_w && effective_h <= max_h;
 726 }
 727
 728 /* XXX replace me when we have VMA tracking for intel_plane_state */
 729 static int get_fence_id(struct drm_framebuffer *fb)
 730 {
 731         struct i915_vma *vma = i915_gem_object_to_ggtt(intel_fb_obj(fb), NULL);
 732
 733         return vma && vma->fence ? vma->fence->id : I915_FENCE_REG_NONE;
 734 }
 735
 736 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 737                                          struct intel_crtc_state *crtc_state,
 738                                          struct intel_plane_state *plane_state)
 739 {
 740         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 741         struct intel_fbc *fbc = &dev_priv->fbc;
 742         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 743         struct drm_framebuffer *fb = plane_state->base.fb;
 744         struct drm_i915_gem_object *obj;
 745
 746         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 747         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 748                 cache->crtc.hsw_bdw_pixel_rate =
 749                         ilk_pipe_pixel_rate(crtc_state);
 750
 751         cache->plane.rotation = plane_state->base.rotation;
 752         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 753         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 754         cache->plane.visible = plane_state->base.visible;
 755
 756         if (!cache->plane.visible)
 757                 return;
 758
 759         obj = intel_fb_obj(fb);
 760
 761         /* FIXME: We lack the proper locking here, so only run this on the
 762          * platforms that need. */
 763         if (IS_GEN(dev_priv, 5, 6))
 764                 cache->fb.ilk_ggtt_offset = i915_gem_object_ggtt_offset(obj, NULL);
 765         cache->fb.pixel_format = fb->pixel_format;
 766         cache->fb.stride = fb->pitches[0];
 767         cache->fb.fence_reg = get_fence_id(fb);
 768         cache->fb.tiling_mode = i915_gem_object_get_tiling(obj);
 769 }
 770
 771 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 772 {
 773         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 774         struct intel_fbc *fbc = &dev_priv->fbc;
 775         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 776
 777         /* We don't need to use a state cache here since this information is
 778          * global for all CRTC.
 779          */
 780         if (fbc->underrun_detected) {
 781                 fbc->no_fbc_reason = "underrun detected";
 782                 return false;
 783         }
 784
 785         if (!cache->plane.visible) {
 786                 fbc->no_fbc_reason = "primary plane not visible";
 787                 return false;
 788         }
 789
 790         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 791             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 792                 fbc->no_fbc_reason = "incompatible mode";
 793                 return false;
 794         }
 795
 796         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 797                 fbc->no_fbc_reason = "mode too large for compression";
 798                 return false;
 799         }
 800
 801         /* The use of a CPU fence is mandatory in order to detect writes
 802          * by the CPU to the scanout and trigger updates to the FBC.
 803          *
 804          * Note that is possible for a tiled surface to be unmappable (and
 805          * so have no fence associated with it) due to aperture constaints
 806          * at the time of pinning.
 807          */
 808         if (cache->fb.tiling_mode != I915_TILING_X ||
 809             cache->fb.fence_reg == I915_FENCE_REG_NONE) {
 810                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 811                 return false;
 812         }
 813         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
 814             cache->plane.rotation != DRM_ROTATE_0) {
 815                 fbc->no_fbc_reason = "rotation unsupported";
 816                 return false;
 817         }
 818
 819         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 820                 fbc->no_fbc_reason = "framebuffer stride not supported";
 821                 return false;
 822         }
 823
 824         if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) {
 825                 fbc->no_fbc_reason = "pixel format is invalid";
 826                 return false;
 827         }
 828
 829         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 830         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 831             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) {
 832                 fbc->no_fbc_reason = "pixel rate is too big";
 833                 return false;
 834         }
 835
 836         /* It is possible for the required CFB size change without a
 837          * crtc->disable + crtc->enable since it is possible to change the
 838          * stride without triggering a full modeset. Since we try to
 839          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 840          * if this happens, but if we exceed the current CFB size we'll have to
 841          * disable FBC. Notice that it would be possible to disable FBC, wait
 842          * for a frame, free the stolen node, then try to reenable FBC in case
 843          * we didn't get any invalidate/deactivate calls, but this would require
 844          * a lot of tracking just for a specific case. If we conclude it's an
 845          * important case, we can implement it later. */
 846         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 847             fbc->compressed_fb.size * fbc->threshold) {
 848                 fbc->no_fbc_reason = "CFB requirements changed";
 849                 return false;
 850         }
 851
 852         return true;
 853 }
 854
 855 static bool intel_fbc_can_choose(struct intel_crtc *crtc)
 856 {
 857         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 858         struct intel_fbc *fbc = &dev_priv->fbc;
 859
 860         if (intel_vgpu_active(dev_priv)) {
 861                 fbc->no_fbc_reason = "VGPU is active";
 862                 return false;
 863         }
 864
 865         if (!i915.enable_fbc) {
 866                 fbc->no_fbc_reason = "disabled per module param or by default";
 867                 return false;
 868         }
 869
 870         if (fbc->underrun_detected) {
 871                 fbc->no_fbc_reason = "underrun detected";
 872                 return false;
 873         }
 874
 875         if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) {
 876                 fbc->no_fbc_reason = "no enabled pipes can have FBC";
 877                 return false;
 878         }
 879
 880         if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) {
 881                 fbc->no_fbc_reason = "no enabled planes can have FBC";
 882                 return false;
 883         }
 884
 885         return true;
 886 }
 887
 888 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 889                                      struct intel_fbc_reg_params *params)
 890 {
 891         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 892         struct intel_fbc *fbc = &dev_priv->fbc;
 893         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 894
 895         /* Since all our fields are integer types, use memset here so the
 896          * comparison function can rely on memcmp because the padding will be
 897          * zero. */
 898         memset(params, 0, sizeof(*params));
 899
 900         params->crtc.pipe = crtc->pipe;
 901         params->crtc.plane = crtc->plane;
 902         params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 903
 904         params->fb.pixel_format = cache->fb.pixel_format;
 905         params->fb.stride = cache->fb.stride;
 906         params->fb.fence_reg = cache->fb.fence_reg;
 907
 908         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 909
 910         params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset;
 911 }
 912
 913 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 914                                        struct intel_fbc_reg_params *params2)
 915 {
 916         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 917         return memcmp(params1, params2, sizeof(*params1)) == 0;
 918 }
 919
 920 void intel_fbc_pre_update(struct intel_crtc *crtc,
 921                           struct intel_crtc_state *crtc_state,
 922                           struct intel_plane_state *plane_state)
 923 {
 924         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 925         struct intel_fbc *fbc = &dev_priv->fbc;
 926
 927         if (!fbc_supported(dev_priv))
 928                 return;
 929
 930         mutex_lock(&fbc->lock);
 931
 932         if (!multiple_pipes_ok(crtc, plane_state)) {
 933                 fbc->no_fbc_reason = "more than one pipe active";
 934                 goto deactivate;
 935         }
 936
 937         if (!fbc->enabled || fbc->crtc != crtc)
 938                 goto unlock;
 939
 940         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 941
 942 deactivate:
 943         intel_fbc_deactivate(dev_priv);
 944 unlock:
 945         mutex_unlock(&fbc->lock);
 946 }
 947
 948 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 949 {
 950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 951         struct intel_fbc *fbc = &dev_priv->fbc;
 952         struct intel_fbc_reg_params old_params;
 953
 954         WARN_ON(!mutex_is_locked(&fbc->lock));
 955
 956         if (!fbc->enabled || fbc->crtc != crtc)
 957                 return;
 958
 959         if (!intel_fbc_can_activate(crtc)) {
 960                 WARN_ON(fbc->active);
 961                 return;
 962         }
 963
 964         old_params = fbc->params;
 965         intel_fbc_get_reg_params(crtc, &fbc->params);
 966
 967         /* If the scanout has not changed, don't modify the FBC settings.
 968          * Note that we make the fundamental assumption that the fb->obj
 969          * cannot be unpinned (and have its GTT offset and fence revoked)
 970          * without first being decoupled from the scanout and FBC disabled.
 971          */
 972         if (fbc->active &&
 973             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 974                 return;
 975
 976         intel_fbc_deactivate(dev_priv);
 977         intel_fbc_schedule_activation(crtc);
 978         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 979 }
 980
 981 void intel_fbc_post_update(struct intel_crtc *crtc)
 982 {
 983         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 984         struct intel_fbc *fbc = &dev_priv->fbc;
 985
 986         if (!fbc_supported(dev_priv))
 987                 return;
 988
 989         mutex_lock(&fbc->lock);
 990         __intel_fbc_post_update(crtc);
 991         mutex_unlock(&fbc->lock);
 992 }
 993
 994 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 995 {
 996         if (fbc->enabled)
 997                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 998         else
 999                 return fbc->possible_framebuffer_bits;
1000 }
1001
1002 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1003                           unsigned int frontbuffer_bits,
1004                           enum fb_op_origin origin)
1005 {
1006         struct intel_fbc *fbc = &dev_priv->fbc;
1007
1008         if (!fbc_supported(dev_priv))
1009                 return;
1010
1011         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1012                 return;
1013
1014         mutex_lock(&fbc->lock);
1015
1016         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1017
1018         if (fbc->enabled && fbc->busy_bits)
1019                 intel_fbc_deactivate(dev_priv);
1020
1021         mutex_unlock(&fbc->lock);
1022 }
1023
1024 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1025                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1026 {
1027         struct intel_fbc *fbc = &dev_priv->fbc;
1028
1029         if (!fbc_supported(dev_priv))
1030                 return;
1031
1032         mutex_lock(&fbc->lock);
1033
1034         fbc->busy_bits &= ~frontbuffer_bits;
1035
1036         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1037                 goto out;
1038
1039         if (!fbc->busy_bits && fbc->enabled &&
1040             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1041                 if (fbc->active)
1042                         intel_fbc_recompress(dev_priv);
1043                 else
1044                         __intel_fbc_post_update(fbc->crtc);
1045         }
1046
1047 out:
1048         mutex_unlock(&fbc->lock);
1049 }
1050
1051 /**
1052  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1053  * @dev_priv: i915 device instance
1054  * @state: the atomic state structure
1055  *
1056  * This function looks at the proposed state for CRTCs and planes, then chooses
1057  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1058  * true.
1059  *
1060  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1061  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1062  */
1063 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1064                            struct drm_atomic_state *state)
1065 {
1066         struct intel_fbc *fbc = &dev_priv->fbc;
1067         struct drm_crtc *crtc;
1068         struct drm_crtc_state *crtc_state;
1069         struct drm_plane *plane;
1070         struct drm_plane_state *plane_state;
1071         bool fbc_crtc_present = false;
1072         int i, j;
1073
1074         mutex_lock(&fbc->lock);
1075
1076         for_each_crtc_in_state(state, crtc, crtc_state, i) {
1077                 if (fbc->crtc == to_intel_crtc(crtc)) {
1078                         fbc_crtc_present = true;
1079                         break;
1080                 }
1081         }
1082         /* This atomic commit doesn't involve the CRTC currently tied to FBC. */
1083         if (!fbc_crtc_present && fbc->crtc != NULL)
1084                 goto out;
1085
1086         /* Simply choose the first CRTC that is compatible and has a visible
1087          * plane. We could go for fancier schemes such as checking the plane
1088          * size, but this would just affect the few platforms that don't tie FBC
1089          * to pipe or plane A. */
1090         for_each_plane_in_state(state, plane, plane_state, i) {
1091                 struct intel_plane_state *intel_plane_state =
1092                         to_intel_plane_state(plane_state);
1093
1094                 if (!intel_plane_state->base.visible)
1095                         continue;
1096
1097                 for_each_crtc_in_state(state, crtc, crtc_state, j) {
1098                         struct intel_crtc_state *intel_crtc_state =
1099                                 to_intel_crtc_state(crtc_state);
1100
1101                         if (plane_state->crtc != crtc)
1102                                 continue;
1103
1104                         if (!intel_fbc_can_choose(to_intel_crtc(crtc)))
1105                                 break;
1106
1107                         intel_crtc_state->enable_fbc = true;
1108                         goto out;
1109                 }
1110         }
1111
1112 out:
1113         mutex_unlock(&fbc->lock);
1114 }
1115
1116 /**
1117  * intel_fbc_enable: tries to enable FBC on the CRTC
1118  * @crtc: the CRTC
1119  * @crtc_state: corresponding &drm_crtc_state for @crtc
1120  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1121  *
1122  * This function checks if the given CRTC was chosen for FBC, then enables it if
1123  * possible. Notice that it doesn't activate FBC. It is valid to call
1124  * intel_fbc_enable multiple times for the same pipe without an
1125  * intel_fbc_disable in the middle, as long as it is deactivated.
1126  */
1127 void intel_fbc_enable(struct intel_crtc *crtc,
1128                       struct intel_crtc_state *crtc_state,
1129                       struct intel_plane_state *plane_state)
1130 {
1131         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1132         struct intel_fbc *fbc = &dev_priv->fbc;
1133
1134         if (!fbc_supported(dev_priv))
1135                 return;
1136
1137         mutex_lock(&fbc->lock);
1138
1139         if (fbc->enabled) {
1140                 WARN_ON(fbc->crtc == NULL);
1141                 if (fbc->crtc == crtc) {
1142                         WARN_ON(!crtc_state->enable_fbc);
1143                         WARN_ON(fbc->active);
1144                 }
1145                 goto out;
1146         }
1147
1148         if (!crtc_state->enable_fbc)
1149                 goto out;
1150
1151         WARN_ON(fbc->active);
1152         WARN_ON(fbc->crtc != NULL);
1153
1154         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1155         if (intel_fbc_alloc_cfb(crtc)) {
1156                 fbc->no_fbc_reason = "not enough stolen memory";
1157                 goto out;
1158         }
1159
1160         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1161         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1162
1163         fbc->enabled = true;
1164         fbc->crtc = crtc;
1165 out:
1166         mutex_unlock(&fbc->lock);
1167 }
1168
1169 /**
1170  * __intel_fbc_disable - disable FBC
1171  * @dev_priv: i915 device instance
1172  *
1173  * This is the low level function that actually disables FBC. Callers should
1174  * grab the FBC lock.
1175  */
1176 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1177 {
1178         struct intel_fbc *fbc = &dev_priv->fbc;
1179         struct intel_crtc *crtc = fbc->crtc;
1180
1181         WARN_ON(!mutex_is_locked(&fbc->lock));
1182         WARN_ON(!fbc->enabled);
1183         WARN_ON(fbc->active);
1184         WARN_ON(crtc->active);
1185
1186         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1187
1188         __intel_fbc_cleanup_cfb(dev_priv);
1189
1190         fbc->enabled = false;
1191         fbc->crtc = NULL;
1192 }
1193
1194 /**
1195  * intel_fbc_disable - disable FBC if it's associated with crtc
1196  * @crtc: the CRTC
1197  *
1198  * This function disables FBC if it's associated with the provided CRTC.
1199  */
1200 void intel_fbc_disable(struct intel_crtc *crtc)
1201 {
1202         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1203         struct intel_fbc *fbc = &dev_priv->fbc;
1204
1205         if (!fbc_supported(dev_priv))
1206                 return;
1207
1208         mutex_lock(&fbc->lock);
1209         if (fbc->crtc == crtc)
1210                 __intel_fbc_disable(dev_priv);
1211         mutex_unlock(&fbc->lock);
1212
1213         cancel_work_sync(&fbc->work.work);
1214 }
1215
1216 /**
1217  * intel_fbc_global_disable - globally disable FBC
1218  * @dev_priv: i915 device instance
1219  *
1220  * This function disables FBC regardless of which CRTC is associated with it.
1221  */
1222 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1223 {
1224         struct intel_fbc *fbc = &dev_priv->fbc;
1225
1226         if (!fbc_supported(dev_priv))
1227                 return;
1228
1229         mutex_lock(&fbc->lock);
1230         if (fbc->enabled)
1231                 __intel_fbc_disable(dev_priv);
1232         mutex_unlock(&fbc->lock);
1233
1234         cancel_work_sync(&fbc->work.work);
1235 }
1236
1237 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1238 {
1239         struct drm_i915_private *dev_priv =
1240                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1241         struct intel_fbc *fbc = &dev_priv->fbc;
1242
1243         mutex_lock(&fbc->lock);
1244
1245         /* Maybe we were scheduled twice. */
1246         if (fbc->underrun_detected)
1247                 goto out;
1248
1249         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1250         fbc->underrun_detected = true;
1251
1252         intel_fbc_deactivate(dev_priv);
1253 out:
1254         mutex_unlock(&fbc->lock);
1255 }
1256
1257 /**
1258  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1259  * @dev_priv: i915 device instance
1260  *
1261  * Without FBC, most underruns are harmless and don't really cause too many
1262  * problems, except for an annoying message on dmesg. With FBC, underruns can
1263  * become black screens or even worse, especially when paired with bad
1264  * watermarks. So in order for us to be on the safe side, completely disable FBC
1265  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1266  * already suggests that watermarks may be bad, so try to be as safe as
1267  * possible.
1268  *
1269  * This function is called from the IRQ handler.
1270  */
1271 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1272 {
1273         struct intel_fbc *fbc = &dev_priv->fbc;
1274
1275         if (!fbc_supported(dev_priv))
1276                 return;
1277
1278         /* There's no guarantee that underrun_detected won't be set to true
1279          * right after this check and before the work is scheduled, but that's
1280          * not a problem since we'll check it again under the work function
1281          * while FBC is locked. This check here is just to prevent us from
1282          * unnecessarily scheduling the work, and it relies on the fact that we
1283          * never switch underrun_detect back to false after it's true. */
1284         if (READ_ONCE(fbc->underrun_detected))
1285                 return;
1286
1287         schedule_work(&fbc->underrun_work);
1288 }
1289
1290 /**
1291  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1292  * @dev_priv: i915 device instance
1293  *
1294  * The FBC code needs to track CRTC visibility since the older platforms can't
1295  * have FBC enabled while multiple pipes are used. This function does the
1296  * initial setup at driver load to make sure FBC is matching the real hardware.
1297  */
1298 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1299 {
1300         struct intel_crtc *crtc;
1301
1302         /* Don't even bother tracking anything if we don't need. */
1303         if (!no_fbc_on_multiple_pipes(dev_priv))
1304                 return;
1305
1306         for_each_intel_crtc(&dev_priv->drm, crtc)
1307                 if (intel_crtc_active(&crtc->base) &&
1308                     to_intel_plane_state(crtc->base.primary->state)->base.visible)
1309                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1310 }
1311
1312 /*
1313  * The DDX driver changes its behavior depending on the value it reads from
1314  * i915.enable_fbc, so sanitize it by translating the default value into either
1315  * 0 or 1 in order to allow it to know what's going on.
1316  *
1317  * Notice that this is done at driver initialization and we still allow user
1318  * space to change the value during runtime without sanitizing it again. IGT
1319  * relies on being able to change i915.enable_fbc at runtime.
1320  */
1321 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1322 {
1323         if (i915.enable_fbc >= 0)
1324                 return !!i915.enable_fbc;
1325
1326         if (!HAS_FBC(dev_priv))
1327                 return 0;
1328
1329         if (IS_BROADWELL(dev_priv))
1330                 return 1;
1331
1332         return 0;
1333 }
1334
1335 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1336 {
1337 #ifdef CONFIG_INTEL_IOMMU
1338         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1339         if (intel_iommu_gfx_mapped &&
1340             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1341                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1342                 return true;
1343         }
1344 #endif
1345
1346         return false;
1347 }
1348
1349 /**
1350  * intel_fbc_init - Initialize FBC
1351  * @dev_priv: the i915 device
1352  *
1353  * This function might be called during PM init process.
1354  */
1355 void intel_fbc_init(struct drm_i915_private *dev_priv)
1356 {
1357         struct intel_fbc *fbc = &dev_priv->fbc;
1358         enum pipe pipe;
1359
1360         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1361         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1362         mutex_init(&fbc->lock);
1363         fbc->enabled = false;
1364         fbc->active = false;
1365         fbc->work.scheduled = false;
1366
1367         if (need_fbc_vtd_wa(dev_priv))
1368                 mkwrite_device_info(dev_priv)->has_fbc = false;
1369
1370         i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1371         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1372
1373         if (!HAS_FBC(dev_priv)) {
1374                 fbc->no_fbc_reason = "unsupported by this chipset";
1375                 return;
1376         }
1377
1378         for_each_pipe(dev_priv, pipe) {
1379                 fbc->possible_framebuffer_bits |=
1380                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1381
1382                 if (fbc_on_pipe_a_only(dev_priv))
1383                         break;
1384         }
1385
1386         /* This value was pulled out of someone's hat */
1387         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_GM45(dev_priv))
1388                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1389
1390         /* We still don't have any sort of hardware state readout for FBC, so
1391          * deactivate it in case the BIOS activated it to make sure software
1392          * matches the hardware state. */
1393         if (intel_fbc_hw_is_active(dev_priv))
1394                 intel_fbc_hw_deactivate(dev_priv);
1395 }