2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
28 #include <linux/kernel.h>
29 #include "intel_drv.h"
31 #include "intel_dsi.h"
38 static const u32 lfsr_converts[] = {
39 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
40 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
41 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
42 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
45 /* Get DSI clock from pixel clock */
46 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
50 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
52 /* DSI data rate = pixel clock * bits per pixel / lane count
53 pixel clock is converted from KHz to Hz */
54 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
59 static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
60 struct dsi_mnp *dsi_mnp, int target_dsi_clk)
62 unsigned int calc_m = 0, calc_p = 0;
63 unsigned int m_min, m_max, p_min = 2, p_max = 6;
66 int delta = target_dsi_clk;
69 /* target_dsi_clk is expected in kHz */
70 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
71 DRM_ERROR("DSI CLK Out of Range\n");
75 if (IS_CHERRYVIEW(dev_priv)) {
87 for (m = m_min; m <= m_max && delta; m++) {
88 for (p = p_min; p <= p_max && delta; p++) {
90 * Find the optimal m and p divisors with minimal delta
91 * +/- the required clock
93 int calc_dsi_clk = (m * ref_clk) / (p * n);
94 int d = abs(target_dsi_clk - calc_dsi_clk);
103 /* register has log2(N1), this works fine for powers of two */
105 m_seed = lfsr_converts[calc_m - 62];
106 dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
107 dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT |
108 m_seed << DSI_PLL_M1_DIV_SHIFT;
114 * XXX: The muxing and gating is hard coded for now. Need to add support for
115 * sharing PLLs with two DSI outputs.
117 static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
119 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
120 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
122 struct dsi_mnp dsi_mnp;
125 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
126 intel_dsi->lane_count);
128 ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
130 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
134 if (intel_dsi->ports & (1 << PORT_A))
135 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
137 if (intel_dsi->ports & (1 << PORT_C))
138 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
140 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
141 dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
143 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
144 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
145 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
148 static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
150 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
155 mutex_lock(&dev_priv->sb_lock);
157 vlv_configure_dsi_pll(encoder);
159 /* wait at least 0.5 us after ungating before enabling VCO */
162 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
163 tmp |= DSI_PLL_VCO_EN;
164 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
166 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
169 mutex_unlock(&dev_priv->sb_lock);
170 DRM_ERROR("DSI PLL lock failed\n");
173 mutex_unlock(&dev_priv->sb_lock);
175 DRM_DEBUG_KMS("DSI PLL locked\n");
178 static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
180 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
185 mutex_lock(&dev_priv->sb_lock);
187 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
188 tmp &= ~DSI_PLL_VCO_EN;
189 tmp |= DSI_PLL_LDO_GATE;
190 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
192 mutex_unlock(&dev_priv->sb_lock);
195 static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
201 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
202 val = I915_READ(BXT_DSI_PLL_ENABLE);
203 enabled = (val & mask) == mask;
209 * Both dividers must be programmed with valid values even if only one
210 * of the PLL is used, see BSpec/Broxton Clocks. Check this here for
211 * paranoia, since BIOS is known to misconfigure PLLs in this way at
212 * times, and since accessing DSI registers with invalid dividers
213 * causes a system hang.
215 val = I915_READ(BXT_DSI_PLL_CTL);
216 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
217 DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",
225 static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
227 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
232 val = I915_READ(BXT_DSI_PLL_ENABLE);
233 val &= ~BXT_DSI_PLL_DO_ENABLE;
234 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
237 * PLL lock should deassert within 200us.
238 * Wait up to 1ms before timing out.
240 if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
241 & BXT_DSI_PLL_LOCKED) == 0, 1))
242 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
245 static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
247 int bpp = mipi_dsi_pixel_format_to_bpp(fmt);
249 WARN(bpp != pipe_bpp,
250 "bpp match assertion failure (expected %d, current %d)\n",
254 static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
256 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
257 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
259 u32 pll_ctl, pll_div;
266 mutex_lock(&dev_priv->sb_lock);
267 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
268 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
269 mutex_unlock(&dev_priv->sb_lock);
271 /* mask out other bits and extract the P1 divisor */
272 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
273 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
276 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
277 n = 1 << n; /* register has log2(N1) */
279 /* mask out the other bits and extract the M1 divisor */
280 pll_div &= DSI_PLL_M1_DIV_MASK;
281 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
284 pll_ctl = pll_ctl >> 1;
290 DRM_ERROR("wrong P1 divisor\n");
294 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
295 if (lfsr_converts[i] == pll_div)
299 if (i == ARRAY_SIZE(lfsr_converts)) {
300 DRM_ERROR("wrong m_seed programmed\n");
306 dsi_clock = (m * refclk) / (p * n);
308 /* pixel_format and pipe_bpp should agree */
309 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
311 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
316 static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
321 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
322 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
326 DRM_ERROR("Invalid BPP(0)\n");
330 dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
331 BXT_DSI_PLL_RATIO_MASK;
333 /* Invalid DSI ratio ? */
334 if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
335 dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
336 DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
340 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
342 /* pixel_format and pipe_bpp should agree */
343 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
345 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
347 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
351 u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
353 if (IS_BROXTON(encoder->base.dev))
354 return bxt_dsi_get_pclk(encoder, pipe_bpp);
356 return vlv_dsi_get_pclk(encoder, pipe_bpp);
359 static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
362 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
365 temp = I915_READ(MIPI_CTRL(port));
366 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
367 I915_WRITE(MIPI_CTRL(port), temp |
368 intel_dsi->escape_clk_div <<
369 ESCAPE_CLOCK_DIVIDER_SHIFT);
372 /* Program BXT Mipi clocks and dividers */
373 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
375 struct drm_i915_private *dev_priv = dev->dev_private;
383 u32 mipi_8by3_divider;
385 /* Clear old configurations */
386 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
387 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
388 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
389 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
390 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
392 /* Get the current DSI rate(actual) */
393 pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
394 BXT_DSI_PLL_RATIO_MASK;
395 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
398 * tx clock should be <= 20MHz and the div value must be
399 * subtracted by 1 as per bspec
401 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
403 * rx clock should be <= 150MHz and the div value must be
404 * subtracted by 1 as per bspec
406 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
409 * rx divider value needs to be updated in the
410 * two differnt bit fields in the register hence splitting the
411 * rx divider value accordingly
413 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
414 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
416 /* As per bpsec program the 8/3X clock divider to the below value */
417 if (dev_priv->vbt.dsi.config->is_cmd_mode)
418 mipi_8by3_divider = 0x2;
420 mipi_8by3_divider = 0x3;
422 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
423 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
424 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
425 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
427 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
430 static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
432 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
433 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
438 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
439 intel_dsi->lane_count);
442 * From clock diagram, to get PLL ratio divider, divide double of DSI
443 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
444 * round 'up' the result
446 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
447 if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
448 dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
449 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
454 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
455 * Spec says both have to be programmed, even if one is not getting
456 * used. Configure MIPI_CLOCK_CTL dividers in modeset
458 val = I915_READ(BXT_DSI_PLL_CTL);
459 val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
460 val &= ~BXT_DSI_FREQ_SEL_MASK;
461 val &= ~BXT_DSI_PLL_RATIO_MASK;
462 val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
464 /* As per recommendation from hardware team,
465 * Prog PVD ratio =1 if dsi ratio <= 50
467 if (dsi_ratio <= 50) {
468 val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
469 val |= BXT_DSI_PLL_PVD_RATIO_1;
472 I915_WRITE(BXT_DSI_PLL_CTL, val);
473 POSTING_READ(BXT_DSI_PLL_CTL);
478 static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
480 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
481 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
487 val = I915_READ(BXT_DSI_PLL_ENABLE);
489 if (val & BXT_DSI_PLL_DO_ENABLE) {
490 WARN(1, "DSI PLL already enabled. Disabling it.\n");
491 val &= ~BXT_DSI_PLL_DO_ENABLE;
492 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
495 /* Configure PLL vales */
496 if (!bxt_configure_dsi_pll(encoder)) {
497 DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
501 /* Program TX, RX, Dphy clocks */
502 for_each_dsi_port(port, intel_dsi->ports)
503 bxt_dsi_program_clocks(encoder->base.dev, port);
506 val = I915_READ(BXT_DSI_PLL_ENABLE);
507 val |= BXT_DSI_PLL_DO_ENABLE;
508 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
510 /* Timeout and fail if PLL not locked */
511 if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
512 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
516 DRM_DEBUG_KMS("DSI PLL locked\n");
519 bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
521 if (IS_BROXTON(dev_priv))
522 return bxt_dsi_pll_is_enabled(dev_priv);
524 MISSING_CASE(INTEL_DEVID(dev_priv));
529 void intel_enable_dsi_pll(struct intel_encoder *encoder)
531 struct drm_device *dev = encoder->base.dev;
533 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
534 vlv_enable_dsi_pll(encoder);
535 else if (IS_BROXTON(dev))
536 bxt_enable_dsi_pll(encoder);
539 void intel_disable_dsi_pll(struct intel_encoder *encoder)
541 struct drm_device *dev = encoder->base.dev;
543 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
544 vlv_disable_dsi_pll(encoder);
545 else if (IS_BROXTON(dev))
546 bxt_disable_dsi_pll(encoder);
549 static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
552 struct drm_device *dev = encoder->base.dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
555 /* Clear old configurations */
556 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
557 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
558 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
559 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
560 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
561 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
562 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
565 void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
567 struct drm_device *dev = encoder->base.dev;
570 bxt_dsi_reset_clocks(encoder, port);
571 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
572 vlv_dsi_reset_clocks(encoder, port);