2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/slab.h>
34 #include <video/mipi_display.h>
35 #include <asm/intel-mid.h>
36 #include <video/mipi_display.h>
38 #include "intel_drv.h"
39 #include "intel_dsi.h"
42 struct drm_panel panel;
43 struct intel_dsi *intel_dsi;
46 static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
48 return container_of(panel, struct vbt_panel, panel);
51 #define MIPI_TRANSFER_MODE_SHIFT 0
52 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
53 #define MIPI_PORT_SHIFT 3
55 #define PREPARE_CNT_MAX 0x3F
56 #define EXIT_ZERO_CNT_MAX 0x3F
57 #define CLK_ZERO_CNT_MAX 0xFF
58 #define TRAIL_CNT_MAX 0x1F
60 #define NS_KHZ_RATIO 1000000
62 /* base offsets for gpio pads */
63 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
64 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
65 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
66 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
67 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
68 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
69 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
70 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
71 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
72 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
73 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
74 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
76 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
77 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
84 static struct gpio_map vlv_gpio_table[] = {
85 { VLV_GPIO_NC_0_HV_DDI0_HPD },
86 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
87 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
88 { VLV_GPIO_NC_3_PANEL0_VDDEN },
89 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
90 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
91 { VLV_GPIO_NC_6_HV_DDI1_HPD },
92 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
93 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
94 { VLV_GPIO_NC_9_PANEL1_VDDEN },
95 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
96 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
99 #define CHV_GPIO_IDX_START_N 0
100 #define CHV_GPIO_IDX_START_E 73
101 #define CHV_GPIO_IDX_START_SW 100
102 #define CHV_GPIO_IDX_START_SE 198
104 #define CHV_VBT_MAX_PINS_PER_FMLY 15
106 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
107 #define CHV_GPIO_GPIOEN (1 << 15)
108 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
109 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
110 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
111 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
112 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
114 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
115 #define CHV_GPIO_CFGLOCK (1 << 31)
117 static inline enum port intel_dsi_seq_port_to_port(u8 port)
119 return port ? PORT_C : PORT_A;
122 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
125 struct mipi_dsi_device *dsi_device;
126 u8 type, flags, seq_port;
135 len = *((u16 *) data);
138 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
140 /* For DSI single link on Port A & C, the seq_port value which is
141 * parsed from Sequence Block#53 of VBT has been set to 0
142 * Now, read/write of packets for the DSI single link on Port A and
143 * Port C will based on the DVO port from VBT block 2.
145 if (intel_dsi->ports == (1 << PORT_C))
148 port = intel_dsi_seq_port_to_port(seq_port);
150 dsi_device = intel_dsi->dsi_hosts[port]->device;
152 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
156 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
157 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
159 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
161 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
164 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
165 mipi_dsi_generic_write(dsi_device, NULL, 0);
167 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
168 mipi_dsi_generic_write(dsi_device, data, 1);
170 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
171 mipi_dsi_generic_write(dsi_device, data, 2);
173 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
174 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
175 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
176 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
178 case MIPI_DSI_GENERIC_LONG_WRITE:
179 mipi_dsi_generic_write(dsi_device, data, len);
181 case MIPI_DSI_DCS_SHORT_WRITE:
182 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
184 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
185 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
187 case MIPI_DSI_DCS_READ:
188 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
190 case MIPI_DSI_DCS_LONG_WRITE:
191 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
201 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
203 u32 delay = *((const u32 *) data);
207 usleep_range(delay, delay + 10);
213 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
214 u8 gpio_source, u8 gpio_index, bool value)
216 struct gpio_map *map;
221 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
222 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
226 map = &vlv_gpio_table[gpio_index];
228 if (dev_priv->vbt.dsi.seq_version >= 3) {
229 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
230 port = IOSF_PORT_GPIO_NC;
232 if (gpio_source == 0) {
233 port = IOSF_PORT_GPIO_NC;
234 } else if (gpio_source == 1) {
235 DRM_DEBUG_KMS("SC gpio not supported\n");
238 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
243 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
244 padval = VLV_GPIO_PAD_VAL(map->base_offset);
246 mutex_lock(&dev_priv->sb_lock);
248 /* FIXME: remove constant below */
249 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
254 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
255 mutex_unlock(&dev_priv->sb_lock);
258 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
259 u8 gpio_source, u8 gpio_index, bool value)
265 if (dev_priv->vbt.dsi.seq_version >= 3) {
266 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
267 /* XXX: it's unclear whether 255->57 is part of SE. */
268 gpio_index -= CHV_GPIO_IDX_START_SE;
269 port = CHV_IOSF_PORT_GPIO_SE;
270 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
271 gpio_index -= CHV_GPIO_IDX_START_SW;
272 port = CHV_IOSF_PORT_GPIO_SW;
273 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
274 gpio_index -= CHV_GPIO_IDX_START_E;
275 port = CHV_IOSF_PORT_GPIO_E;
277 port = CHV_IOSF_PORT_GPIO_N;
280 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
281 if (gpio_source != 0) {
282 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
286 if (gpio_index >= CHV_GPIO_IDX_START_E) {
287 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
292 port = CHV_IOSF_PORT_GPIO_N;
295 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
296 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
298 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
299 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
301 mutex_lock(&dev_priv->sb_lock);
302 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
303 vlv_iosf_sb_write(dev_priv, port, cfg0,
304 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
305 CHV_GPIO_GPIOTXSTATE(value));
306 mutex_unlock(&dev_priv->sb_lock);
309 static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
310 u8 gpio_source, u8 gpio_index, bool value)
312 /* XXX: this table is a quick ugly hack. */
313 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
314 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
317 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
319 value ? GPIOD_OUT_LOW :
322 if (IS_ERR_OR_NULL(gpio_desc)) {
323 DRM_ERROR("GPIO index %u request failed (%ld)\n",
324 gpio_index, PTR_ERR(gpio_desc));
328 bxt_gpio_table[gpio_index] = gpio_desc;
331 gpiod_set_value(gpio_desc, value);
334 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
336 struct drm_device *dev = intel_dsi->base.base.dev;
337 struct drm_i915_private *dev_priv = to_i915(dev);
338 u8 gpio_source, gpio_index = 0, gpio_number;
343 if (dev_priv->vbt.dsi.seq_version >= 3)
344 gpio_index = *data++;
346 gpio_number = *data++;
348 /* gpio source in sequence v2 only */
349 if (dev_priv->vbt.dsi.seq_version == 2)
350 gpio_source = (*data >> 1) & 3;
357 if (IS_VALLEYVIEW(dev_priv))
358 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
359 else if (IS_CHERRYVIEW(dev_priv))
360 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
362 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
367 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
369 DRM_DEBUG_KMS("Skipping I2C element execution\n");
371 return data + *(data + 6) + 7;
374 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
376 DRM_DEBUG_KMS("Skipping SPI element execution\n");
378 return data + *(data + 5) + 6;
381 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
383 DRM_DEBUG_KMS("Skipping PMIC element execution\n");
388 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
390 static const fn_mipi_elem_exec exec_elem[] = {
391 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
392 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
393 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
394 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
395 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
396 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
400 * MIPI Sequence from VBT #53 parsing logic
401 * We have already separated each seqence during bios parsing
402 * Following is generic execution function for any sequence
405 static const char * const seq_name[] = {
406 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
407 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
408 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
409 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
410 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
411 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
412 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
413 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
414 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
415 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
416 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
419 static const char *sequence_name(enum mipi_seq seq_id)
421 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
422 return seq_name[seq_id];
427 static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
429 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
430 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
431 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
433 fn_mipi_elem_exec mipi_elem_exec;
435 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
438 data = dev_priv->vbt.dsi.sequence[seq_id];
442 WARN_ON(*data != seq_id);
444 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
445 seq_id, sequence_name(seq_id));
447 /* Skip Sequence Byte. */
450 /* Skip Size of Sequence. */
451 if (dev_priv->vbt.dsi.seq_version >= 3)
455 u8 operation_byte = *data++;
456 u8 operation_size = 0;
458 if (operation_byte == MIPI_SEQ_ELEM_END)
461 if (operation_byte < ARRAY_SIZE(exec_elem))
462 mipi_elem_exec = exec_elem[operation_byte];
464 mipi_elem_exec = NULL;
466 /* Size of Operation. */
467 if (dev_priv->vbt.dsi.seq_version >= 3)
468 operation_size = *data++;
470 if (mipi_elem_exec) {
471 const u8 *next = data + operation_size;
473 data = mipi_elem_exec(intel_dsi, data);
475 /* Consistency check if we have size. */
476 if (operation_size && data != next) {
477 DRM_ERROR("Inconsistent operation size\n");
480 } else if (operation_size) {
481 /* We have size, skip. */
482 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
484 data += operation_size;
486 /* No size, can't skip without parsing. */
487 DRM_ERROR("Unsupported MIPI operation byte %u\n",
494 static int vbt_panel_prepare(struct drm_panel *panel)
496 generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
497 generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
498 generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
499 generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
504 static int vbt_panel_unprepare(struct drm_panel *panel)
506 generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
507 generic_exec_sequence(panel, MIPI_SEQ_POWER_OFF);
512 static int vbt_panel_enable(struct drm_panel *panel)
514 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON);
515 generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_ON);
520 static int vbt_panel_disable(struct drm_panel *panel)
522 generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_OFF);
523 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF);
528 static int vbt_panel_get_modes(struct drm_panel *panel)
530 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
531 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
532 struct drm_device *dev = intel_dsi->base.base.dev;
533 struct drm_i915_private *dev_priv = to_i915(dev);
534 struct drm_display_mode *mode;
536 if (!panel->connector)
539 mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
543 mode->type |= DRM_MODE_TYPE_PREFERRED;
545 drm_mode_probed_add(panel->connector, mode);
550 static const struct drm_panel_funcs vbt_panel_funcs = {
551 .disable = vbt_panel_disable,
552 .unprepare = vbt_panel_unprepare,
553 .prepare = vbt_panel_prepare,
554 .enable = vbt_panel_enable,
555 .get_modes = vbt_panel_get_modes,
558 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
560 struct drm_device *dev = intel_dsi->base.base.dev;
561 struct drm_i915_private *dev_priv = to_i915(dev);
562 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
563 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
564 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
565 struct vbt_panel *vbt_panel;
567 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
569 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
570 u32 ths_prepare_ns, tclk_trail_ns;
571 u32 tclk_prepare_clkzero, ths_prepare_hszero;
572 u32 lp_to_hs_switch, hs_to_lp_switch;
573 u32 pclk, computed_ddr;
574 u16 burst_mode_ratio;
579 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
580 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
581 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
582 intel_dsi->pixel_format =
583 pixel_format_from_register_bits(
584 mipi_config->videomode_color_format << 7);
585 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
587 intel_dsi->dual_link = mipi_config->dual_link;
588 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
589 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
590 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
591 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
592 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
593 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
594 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
595 intel_dsi->init_count = mipi_config->master_init_timer;
596 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
597 intel_dsi->video_frmt_cfg_bits =
598 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
602 /* In dual link mode each port needs half of pixel clock */
603 if (intel_dsi->dual_link) {
606 /* we can enable pixel_overlap if needed by panel. In this
607 * case we need to increase the pixelclock for extra pixels
609 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
610 pclk += DIV_ROUND_UP(mode->vtotal *
611 intel_dsi->pixel_overlap *
617 * Target ddr frequency from VBT / non burst ddr freq
618 * multiply by 100 to preserve remainder
620 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
621 if (mipi_config->target_burst_mode_freq) {
622 computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
624 if (mipi_config->target_burst_mode_freq <
626 DRM_ERROR("Burst mode freq is less than computed\n");
630 burst_mode_ratio = DIV_ROUND_UP(
631 mipi_config->target_burst_mode_freq * 100,
634 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
636 DRM_ERROR("Burst mode target is not set\n");
640 burst_mode_ratio = 100;
642 intel_dsi->burst_mode_ratio = burst_mode_ratio;
643 intel_dsi->pclk = pclk;
645 bitrate = (pclk * bpp) / intel_dsi->lane_count;
647 switch (intel_dsi->escape_clk_div) {
663 switch (intel_dsi->lane_count) {
666 extra_byte_count = 2;
669 extra_byte_count = 4;
673 extra_byte_count = 3;
678 * ui(s) = 1/f [f in hz]
679 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
683 ui_num = NS_KHZ_RATIO;
686 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
687 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
691 * LP byte clock = TLPX/ (8UI)
693 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
695 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
697 * Since txddrclkhs_i is 2xUI, all the count values programmed in
698 * DPHY param register are divided by 2
702 ths_prepare_ns = max(mipi_config->ths_prepare,
703 mipi_config->tclk_prepare);
704 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
706 /* exit zero count */
707 exit_zero_cnt = DIV_ROUND_UP(
708 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
713 * Exit zero is unified val ths_zero and ths_exit
714 * minimum value for ths_exit = 110ns
715 * min (exit_zero_cnt * 2) = 110/UI
716 * exit_zero_cnt = 55/UI
718 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
722 clk_zero_cnt = DIV_ROUND_UP(
723 (tclk_prepare_clkzero - ths_prepare_ns)
724 * ui_den, 2 * ui_num);
727 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
728 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
730 if (prepare_cnt > PREPARE_CNT_MAX ||
731 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
732 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
733 trail_cnt > TRAIL_CNT_MAX)
734 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
736 if (prepare_cnt > PREPARE_CNT_MAX)
737 prepare_cnt = PREPARE_CNT_MAX;
739 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
740 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
742 if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
743 clk_zero_cnt = CLK_ZERO_CNT_MAX;
745 if (trail_cnt > TRAIL_CNT_MAX)
746 trail_cnt = TRAIL_CNT_MAX;
749 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
750 clk_zero_cnt << 8 | prepare_cnt;
753 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
754 * + 10UI + Extra Byte Count
756 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
757 * Extra Byte Count is calculated according to number of lanes.
758 * High Low Switch Count is the Max of LP to HS and
759 * HS to LP switch count
762 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
766 * The comment above does not match with the code */
767 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
768 exit_zero_cnt * 2 + 10, 8);
770 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
772 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
773 intel_dsi->hs_to_lp_count += extra_byte_count;
776 /* LP -> HS for clock lanes
777 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
779 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
780 * 2(in UI) + extra byte count
781 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
782 * 8 + extra byte count
784 intel_dsi->clk_lp_to_hs_count =
786 4 * tlpx_ui + prepare_cnt * 2 +
790 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
792 /* HS->LP for Clock Lanes
793 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
795 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
796 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
799 intel_dsi->clk_hs_to_lp_count =
800 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
802 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
804 DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
805 DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
806 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
807 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
808 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
809 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
810 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
812 DRM_DEBUG_KMS("Dual link: NONE\n");
813 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
814 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
815 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
816 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
817 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
818 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
819 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
820 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
821 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
822 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
823 DRM_DEBUG_KMS("BTA %s\n",
824 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
826 /* delays in VBT are in unit of 100us, so need to convert
828 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
829 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
830 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
831 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
832 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
833 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
835 /* This is cheating a bit with the cleanup. */
836 vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
840 vbt_panel->intel_dsi = intel_dsi;
841 drm_panel_init(&vbt_panel->panel);
842 vbt_panel->panel.funcs = &vbt_panel_funcs;
843 drm_panel_add(&vbt_panel->panel);
845 /* a regular driver would get the device in probe */
846 for_each_dsi_port(port, intel_dsi->ports) {
847 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
850 return &vbt_panel->panel;