drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72
  73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  76 #else
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  78 #endif
  79
  80 #define _wait_for_atomic(COND, US, ATOMIC) \
  81 ({ \
  82         int cpu, ret, timeout = (US) * 1000; \
  83         u64 base; \
  84         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  85         BUILD_BUG_ON((US) > 50000); \
  86         if (!(ATOMIC)) { \
  87                 preempt_disable(); \
  88                 cpu = smp_processor_id(); \
  89         } \
  90         base = local_clock(); \
  91         for (;;) { \
  92                 u64 now = local_clock(); \
  93                 if (!(ATOMIC)) \
  94                         preempt_enable(); \
  95                 if (COND) { \
  96                         ret = 0; \
  97                         break; \
  98                 } \
  99                 if (now - base >= timeout) { \
 100                         ret = -ETIMEDOUT; \
 101                         break; \
 102                 } \
 103                 cpu_relax(); \
 104                 if (!(ATOMIC)) { \
 105                         preempt_disable(); \
 106                         if (unlikely(cpu != smp_processor_id())) { \
 107                                 timeout -= now - base; \
 108                                 cpu = smp_processor_id(); \
 109                                 base = local_clock(); \
 110                         } \
 111                 } \
 112         } \
 113         ret; \
 114 })
 115
 116 #define wait_for_us(COND, US) \
 117 ({ \
 118         int ret__; \
 119         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 120         if ((US) > 10) \
 121                 ret__ = _wait_for((COND), (US), 10); \
 122         else \
 123                 ret__ = _wait_for_atomic((COND), (US), 0); \
 124         ret__; \
 125 })
 126
 127 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 128 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 129
 130 #define KHz(x) (1000 * (x))
 131 #define MHz(x) KHz(1000 * (x))
 132
 133 /*
 134  * Display related stuff
 135  */
 136
 137 /* store information about an Ixxx DVO */
 138 /* The i830->i865 use multiple DVOs with multiple i2cs */
 139 /* the i915, i945 have a single sDVO i2c bus - which is different */
 140 #define MAX_OUTPUTS 6
 141 /* maximum connectors per crtcs in the mode set */
 142
 143 /* Maximum cursor sizes */
 144 #define GEN2_CURSOR_WIDTH 64
 145 #define GEN2_CURSOR_HEIGHT 64
 146 #define MAX_CURSOR_WIDTH 256
 147 #define MAX_CURSOR_HEIGHT 256
 148
 149 #define INTEL_I2C_BUS_DVO 1
 150 #define INTEL_I2C_BUS_SDVO 2
 151
 152 /* these are outputs from the chip - integrated only
 153    external chips are via DVO or SDVO output */
 154 enum intel_output_type {
 155         INTEL_OUTPUT_UNUSED = 0,
 156         INTEL_OUTPUT_ANALOG = 1,
 157         INTEL_OUTPUT_DVO = 2,
 158         INTEL_OUTPUT_SDVO = 3,
 159         INTEL_OUTPUT_LVDS = 4,
 160         INTEL_OUTPUT_TVOUT = 5,
 161         INTEL_OUTPUT_HDMI = 6,
 162         INTEL_OUTPUT_DP = 7,
 163         INTEL_OUTPUT_EDP = 8,
 164         INTEL_OUTPUT_DSI = 9,
 165         INTEL_OUTPUT_UNKNOWN = 10,
 166         INTEL_OUTPUT_DP_MST = 11,
 167 };
 168
 169 #define INTEL_DVO_CHIP_NONE 0
 170 #define INTEL_DVO_CHIP_LVDS 1
 171 #define INTEL_DVO_CHIP_TMDS 2
 172 #define INTEL_DVO_CHIP_TVOUT 4
 173
 174 #define INTEL_DSI_VIDEO_MODE    0
 175 #define INTEL_DSI_COMMAND_MODE  1
 176
 177 struct intel_framebuffer {
 178         struct drm_framebuffer base;
 179         struct drm_i915_gem_object *obj;
 180         struct intel_rotation_info rot_info;
 181
 182         /* for each plane in the normal GTT view */
 183         struct {
 184                 unsigned int x, y;
 185         } normal[2];
 186         /* for each plane in the rotated GTT view */
 187         struct {
 188                 unsigned int x, y;
 189                 unsigned int pitch; /* pixels */
 190         } rotated[2];
 191 };
 192
 193 struct intel_fbdev {
 194         struct drm_fb_helper helper;
 195         struct intel_framebuffer *fb;
 196         async_cookie_t cookie;
 197         int preferred_bpp;
 198 };
 199
 200 struct intel_encoder {
 201         struct drm_encoder base;
 202
 203         enum intel_output_type type;
 204         unsigned int cloneable;
 205         void (*hot_plug)(struct intel_encoder *);
 206         bool (*compute_config)(struct intel_encoder *,
 207                                struct intel_crtc_state *);
 208         void (*pre_pll_enable)(struct intel_encoder *);
 209         void (*pre_enable)(struct intel_encoder *);
 210         void (*enable)(struct intel_encoder *);
 211         void (*mode_set)(struct intel_encoder *intel_encoder);
 212         void (*disable)(struct intel_encoder *);
 213         void (*post_disable)(struct intel_encoder *);
 214         void (*post_pll_disable)(struct intel_encoder *);
 215         /* Read out the current hw state of this connector, returning true if
 216          * the encoder is active. If the encoder is enabled it also set the pipe
 217          * it is connected to in the pipe parameter. */
 218         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 219         /* Reconstructs the equivalent mode flags for the current hardware
 220          * state. This must be called _after_ display->get_pipe_config has
 221          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 222          * be set correctly before calling this function. */
 223         void (*get_config)(struct intel_encoder *,
 224                            struct intel_crtc_state *pipe_config);
 225         /*
 226          * Called during system suspend after all pending requests for the
 227          * encoder are flushed (for example for DP AUX transactions) and
 228          * device interrupts are disabled.
 229          */
 230         void (*suspend)(struct intel_encoder *);
 231         int crtc_mask;
 232         enum hpd_pin hpd_pin;
 233 };
 234
 235 struct intel_panel {
 236         struct drm_display_mode *fixed_mode;
 237         struct drm_display_mode *downclock_mode;
 238         int fitting_mode;
 239
 240         /* backlight */
 241         struct {
 242                 bool present;
 243                 u32 level;
 244                 u32 min;
 245                 u32 max;
 246                 bool enabled;
 247                 bool combination_mode;  /* gen 2/4 only */
 248                 bool active_low_pwm;
 249
 250                 /* PWM chip */
 251                 bool util_pin_active_low;       /* bxt+ */
 252                 u8 controller;          /* bxt+ only */
 253                 struct pwm_device *pwm;
 254
 255                 struct backlight_device *device;
 256
 257                 /* Connector and platform specific backlight functions */
 258                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 259                 uint32_t (*get)(struct intel_connector *connector);
 260                 void (*set)(struct intel_connector *connector, uint32_t level);
 261                 void (*disable)(struct intel_connector *connector);
 262                 void (*enable)(struct intel_connector *connector);
 263                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 264                                       uint32_t hz);
 265                 void (*power)(struct intel_connector *, bool enable);
 266         } backlight;
 267 };
 268
 269 struct intel_connector {
 270         struct drm_connector base;
 271         /*
 272          * The fixed encoder this connector is connected to.
 273          */
 274         struct intel_encoder *encoder;
 275
 276         /* Reads out the current hw, returning true if the connector is enabled
 277          * and active (i.e. dpms ON state). */
 278         bool (*get_hw_state)(struct intel_connector *);
 279
 280         /* Panel info for eDP and LVDS */
 281         struct intel_panel panel;
 282
 283         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 284         struct edid *edid;
 285         struct edid *detect_edid;
 286
 287         /* since POLL and HPD connectors may use the same HPD line keep the native
 288            state of connector->polled in case hotplug storm detection changes it */
 289         u8 polled;
 290
 291         void *port; /* store this opaque as its illegal to dereference it */
 292
 293         struct intel_dp *mst_port;
 294 };
 295
 296 struct dpll {
 297         /* given values */
 298         int n;
 299         int m1, m2;
 300         int p1, p2;
 301         /* derived values */
 302         int     dot;
 303         int     vco;
 304         int     m;
 305         int     p;
 306 };
 307
 308 struct intel_atomic_state {
 309         struct drm_atomic_state base;
 310
 311         unsigned int cdclk;
 312
 313         /*
 314          * Calculated device cdclk, can be different from cdclk
 315          * only when all crtc's are DPMS off.
 316          */
 317         unsigned int dev_cdclk;
 318
 319         bool dpll_set, modeset;
 320
 321         /*
 322          * Does this transaction change the pipes that are active?  This mask
 323          * tracks which CRTC's have changed their active state at the end of
 324          * the transaction (not counting the temporary disable during modesets).
 325          * This mask should only be non-zero when intel_state->modeset is true,
 326          * but the converse is not necessarily true; simply changing a mode may
 327          * not flip the final active status of any CRTC's
 328          */
 329         unsigned int active_pipe_changes;
 330
 331         unsigned int active_crtcs;
 332         unsigned int min_pixclk[I915_MAX_PIPES];
 333
 334         /* SKL/KBL Only */
 335         unsigned int cdclk_pll_vco;
 336
 337         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 338
 339         /*
 340          * Current watermarks can't be trusted during hardware readout, so
 341          * don't bother calculating intermediate watermarks.
 342          */
 343         bool skip_intermediate_wm;
 344
 345         /* Gen9+ only */
 346         struct skl_wm_values wm_results;
 347 };
 348
 349 struct intel_plane_state {
 350         struct drm_plane_state base;
 351         struct drm_rect src;
 352         struct drm_rect dst;
 353         struct drm_rect clip;
 354         bool visible;
 355
 356         struct {
 357                 u32 offset;
 358                 int x, y;
 359         } main;
 360         struct {
 361                 u32 offset;
 362                 int x, y;
 363         } aux;
 364
 365         /*
 366          * scaler_id
 367          *    = -1 : not using a scaler
 368          *    >=  0 : using a scalers
 369          *
 370          * plane requiring a scaler:
 371          *   - During check_plane, its bit is set in
 372          *     crtc_state->scaler_state.scaler_users by calling helper function
 373          *     update_scaler_plane.
 374          *   - scaler_id indicates the scaler it got assigned.
 375          *
 376          * plane doesn't require a scaler:
 377          *   - this can happen when scaling is no more required or plane simply
 378          *     got disabled.
 379          *   - During check_plane, corresponding bit is reset in
 380          *     crtc_state->scaler_state.scaler_users by calling helper function
 381          *     update_scaler_plane.
 382          */
 383         int scaler_id;
 384
 385         struct drm_intel_sprite_colorkey ckey;
 386
 387         /* async flip related structures */
 388         struct drm_i915_gem_request *wait_req;
 389 };
 390
 391 struct intel_initial_plane_config {
 392         struct intel_framebuffer *fb;
 393         unsigned int tiling;
 394         int size;
 395         u32 base;
 396 };
 397
 398 #define SKL_MIN_SRC_W 8
 399 #define SKL_MAX_SRC_W 4096
 400 #define SKL_MIN_SRC_H 8
 401 #define SKL_MAX_SRC_H 4096
 402 #define SKL_MIN_DST_W 8
 403 #define SKL_MAX_DST_W 4096
 404 #define SKL_MIN_DST_H 8
 405 #define SKL_MAX_DST_H 4096
 406
 407 struct intel_scaler {
 408         int in_use;
 409         uint32_t mode;
 410 };
 411
 412 struct intel_crtc_scaler_state {
 413 #define SKL_NUM_SCALERS 2
 414         struct intel_scaler scalers[SKL_NUM_SCALERS];
 415
 416         /*
 417          * scaler_users: keeps track of users requesting scalers on this crtc.
 418          *
 419          *     If a bit is set, a user is using a scaler.
 420          *     Here user can be a plane or crtc as defined below:
 421          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 422          *       bit 31    - crtc
 423          *
 424          * Instead of creating a new index to cover planes and crtc, using
 425          * existing drm_plane_index for planes which is well less than 31
 426          * planes and bit 31 for crtc. This should be fine to cover all
 427          * our platforms.
 428          *
 429          * intel_atomic_setup_scalers will setup available scalers to users
 430          * requesting scalers. It will gracefully fail if request exceeds
 431          * avilability.
 432          */
 433 #define SKL_CRTC_INDEX 31
 434         unsigned scaler_users;
 435
 436         /* scaler used by crtc for panel fitting purpose */
 437         int scaler_id;
 438 };
 439
 440 /* drm_mode->private_flags */
 441 #define I915_MODE_FLAG_INHERITED 1
 442
 443 struct intel_pipe_wm {
 444         struct intel_wm_level wm[5];
 445         struct intel_wm_level raw_wm[5];
 446         uint32_t linetime;
 447         bool fbc_wm_enabled;
 448         bool pipe_enabled;
 449         bool sprites_enabled;
 450         bool sprites_scaled;
 451 };
 452
 453 struct skl_pipe_wm {
 454         struct skl_wm_level wm[8];
 455         struct skl_wm_level trans_wm;
 456         uint32_t linetime;
 457 };
 458
 459 struct intel_crtc_wm_state {
 460         union {
 461                 struct {
 462                         /*
 463                          * Intermediate watermarks; these can be
 464                          * programmed immediately since they satisfy
 465                          * both the current configuration we're
 466                          * switching away from and the new
 467                          * configuration we're switching to.
 468                          */
 469                         struct intel_pipe_wm intermediate;
 470
 471                         /*
 472                          * Optimal watermarks, programmed post-vblank
 473                          * when this state is committed.
 474                          */
 475                         struct intel_pipe_wm optimal;
 476                 } ilk;
 477
 478                 struct {
 479                         /* gen9+ only needs 1-step wm programming */
 480                         struct skl_pipe_wm optimal;
 481
 482                         /* cached plane data rate */
 483                         unsigned plane_data_rate[I915_MAX_PLANES];
 484                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 485
 486                         /* minimum block allocation */
 487                         uint16_t minimum_blocks[I915_MAX_PLANES];
 488                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 489                 } skl;
 490         };
 491
 492         /*
 493          * Platforms with two-step watermark programming will need to
 494          * update watermark programming post-vblank to switch from the
 495          * safe intermediate watermarks to the optimal final
 496          * watermarks.
 497          */
 498         bool need_postvbl_update;
 499 };
 500
 501 struct intel_crtc_state {
 502         struct drm_crtc_state base;
 503
 504         /**
 505          * quirks - bitfield with hw state readout quirks
 506          *
 507          * For various reasons the hw state readout code might not be able to
 508          * completely faithfully read out the current state. These cases are
 509          * tracked with quirk flags so that fastboot and state checker can act
 510          * accordingly.
 511          */
 512 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 513         unsigned long quirks;
 514
 515         unsigned fb_bits; /* framebuffers to flip */
 516         bool update_pipe; /* can a fast modeset be performed? */
 517         bool disable_cxsr;
 518         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 519         bool fb_changed; /* fb on any of the planes is changed */
 520
 521         /* Pipe source size (ie. panel fitter input size)
 522          * All planes will be positioned inside this space,
 523          * and get clipped at the edges. */
 524         int pipe_src_w, pipe_src_h;
 525
 526         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 527          * between pch encoders and cpu encoders. */
 528         bool has_pch_encoder;
 529
 530         /* Are we sending infoframes on the attached port */
 531         bool has_infoframe;
 532
 533         /* CPU Transcoder for the pipe. Currently this can only differ from the
 534          * pipe on Haswell and later (where we have a special eDP transcoder)
 535          * and Broxton (where we have special DSI transcoders). */
 536         enum transcoder cpu_transcoder;
 537
 538         /*
 539          * Use reduced/limited/broadcast rbg range, compressing from the full
 540          * range fed into the crtcs.
 541          */
 542         bool limited_color_range;
 543
 544         /* Bitmask of encoder types (enum intel_output_type)
 545          * driven by the pipe.
 546          */
 547         unsigned int output_types;
 548
 549         /* Whether we should send NULL infoframes. Required for audio. */
 550         bool has_hdmi_sink;
 551
 552         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 553          * has_dp_encoder is set. */
 554         bool has_audio;
 555
 556         /*
 557          * Enable dithering, used when the selected pipe bpp doesn't match the
 558          * plane bpp.
 559          */
 560         bool dither;
 561
 562         /* Controls for the clock computation, to override various stages. */
 563         bool clock_set;
 564
 565         /* SDVO TV has a bunch of special case. To make multifunction encoders
 566          * work correctly, we need to track this at runtime.*/
 567         bool sdvo_tv_clock;
 568
 569         /*
 570          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 571          * required. This is set in the 2nd loop of calling encoder's
 572          * ->compute_config if the first pick doesn't work out.
 573          */
 574         bool bw_constrained;
 575
 576         /* Settings for the intel dpll used on pretty much everything but
 577          * haswell. */
 578         struct dpll dpll;
 579
 580         /* Selected dpll when shared or NULL. */
 581         struct intel_shared_dpll *shared_dpll;
 582
 583         /*
 584          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 585          * - enum skl_dpll on SKL
 586          */
 587         uint32_t ddi_pll_sel;
 588
 589         /* Actual register state of the dpll, for shared dpll cross-checking. */
 590         struct intel_dpll_hw_state dpll_hw_state;
 591
 592         /* DSI PLL registers */
 593         struct {
 594                 u32 ctrl, div;
 595         } dsi_pll;
 596
 597         int pipe_bpp;
 598         struct intel_link_m_n dp_m_n;
 599
 600         /* m2_n2 for eDP downclock */
 601         struct intel_link_m_n dp_m2_n2;
 602         bool has_drrs;
 603
 604         /*
 605          * Frequence the dpll for the port should run at. Differs from the
 606          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 607          * already multiplied by pixel_multiplier.
 608          */
 609         int port_clock;
 610
 611         /* Used by SDVO (and if we ever fix it, HDMI). */
 612         unsigned pixel_multiplier;
 613
 614         uint8_t lane_count;
 615
 616         /*
 617          * Used by platforms having DP/HDMI PHY with programmable lane
 618          * latency optimization.
 619          */
 620         uint8_t lane_lat_optim_mask;
 621
 622         /* Panel fitter controls for gen2-gen4 + VLV */
 623         struct {
 624                 u32 control;
 625                 u32 pgm_ratios;
 626                 u32 lvds_border_bits;
 627         } gmch_pfit;
 628
 629         /* Panel fitter placement and size for Ironlake+ */
 630         struct {
 631                 u32 pos;
 632                 u32 size;
 633                 bool enabled;
 634                 bool force_thru;
 635         } pch_pfit;
 636
 637         /* FDI configuration, only valid if has_pch_encoder is set. */
 638         int fdi_lanes;
 639         struct intel_link_m_n fdi_m_n;
 640
 641         bool ips_enabled;
 642
 643         bool enable_fbc;
 644
 645         bool double_wide;
 646
 647         bool dp_encoder_is_mst;
 648         int pbn;
 649
 650         struct intel_crtc_scaler_state scaler_state;
 651
 652         /* w/a for waiting 2 vblanks during crtc enable */
 653         enum pipe hsw_workaround_pipe;
 654
 655         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 656         bool disable_lp_wm;
 657
 658         struct intel_crtc_wm_state wm;
 659
 660         /* Gamma mode programmed on the pipe */
 661         uint32_t gamma_mode;
 662 };
 663
 664 struct vlv_wm_state {
 665         struct vlv_pipe_wm wm[3];
 666         struct vlv_sr_wm sr[3];
 667         uint8_t num_active_planes;
 668         uint8_t num_levels;
 669         uint8_t level;
 670         bool cxsr;
 671 };
 672
 673 struct intel_crtc {
 674         struct drm_crtc base;
 675         enum pipe pipe;
 676         enum plane plane;
 677         u8 lut_r[256], lut_g[256], lut_b[256];
 678         /*
 679          * Whether the crtc and the connected output pipeline is active. Implies
 680          * that crtc->enabled is set, i.e. the current mode configuration has
 681          * some outputs connected to this crtc.
 682          */
 683         bool active;
 684         unsigned long enabled_power_domains;
 685         bool lowfreq_avail;
 686         struct intel_overlay *overlay;
 687         struct intel_flip_work *flip_work;
 688
 689         atomic_t unpin_work_count;
 690
 691         /* Display surface base address adjustement for pageflips. Note that on
 692          * gen4+ this only adjusts up to a tile, offsets within a tile are
 693          * handled in the hw itself (with the TILEOFF register). */
 694         u32 dspaddr_offset;
 695         int adjusted_x;
 696         int adjusted_y;
 697
 698         uint32_t cursor_addr;
 699         uint32_t cursor_cntl;
 700         uint32_t cursor_size;
 701         uint32_t cursor_base;
 702
 703         struct intel_crtc_state *config;
 704
 705         /* reset counter value when the last flip was submitted */
 706         unsigned int reset_counter;
 707
 708         /* Access to these should be protected by dev_priv->irq_lock. */
 709         bool cpu_fifo_underrun_disabled;
 710         bool pch_fifo_underrun_disabled;
 711
 712         /* per-pipe watermark state */
 713         struct {
 714                 /* watermarks currently being used  */
 715                 union {
 716                         struct intel_pipe_wm ilk;
 717                         struct skl_pipe_wm skl;
 718                 } active;
 719
 720                 /* allow CxSR on this pipe */
 721                 bool cxsr_allowed;
 722         } wm;
 723
 724         int scanline_offset;
 725
 726         struct {
 727                 unsigned start_vbl_count;
 728                 ktime_t start_vbl_time;
 729                 int min_vbl, max_vbl;
 730                 int scanline_start;
 731         } debug;
 732
 733         /* scalers available on this crtc */
 734         int num_scalers;
 735
 736         struct vlv_wm_state wm_state;
 737 };
 738
 739 struct intel_plane_wm_parameters {
 740         uint32_t horiz_pixels;
 741         uint32_t vert_pixels;
 742         /*
 743          *   For packed pixel formats:
 744          *     bytes_per_pixel - holds bytes per pixel
 745          *   For planar pixel formats:
 746          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 747          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 748          */
 749         uint8_t bytes_per_pixel;
 750         uint8_t y_bytes_per_pixel;
 751         bool enabled;
 752         bool scaled;
 753         u64 tiling;
 754         unsigned int rotation;
 755         uint16_t fifo_size;
 756 };
 757
 758 struct intel_plane {
 759         struct drm_plane base;
 760         int plane;
 761         enum pipe pipe;
 762         bool can_scale;
 763         int max_downscale;
 764         uint32_t frontbuffer_bit;
 765
 766         /* Since we need to change the watermarks before/after
 767          * enabling/disabling the planes, we need to store the parameters here
 768          * as the other pieces of the struct may not reflect the values we want
 769          * for the watermark calculations. Currently only Haswell uses this.
 770          */
 771         struct intel_plane_wm_parameters wm;
 772
 773         /*
 774          * NOTE: Do not place new plane state fields here (e.g., when adding
 775          * new plane properties).  New runtime state should now be placed in
 776          * the intel_plane_state structure and accessed via plane_state.
 777          */
 778
 779         void (*update_plane)(struct drm_plane *plane,
 780                              const struct intel_crtc_state *crtc_state,
 781                              const struct intel_plane_state *plane_state);
 782         void (*disable_plane)(struct drm_plane *plane,
 783                               struct drm_crtc *crtc);
 784         int (*check_plane)(struct drm_plane *plane,
 785                            struct intel_crtc_state *crtc_state,
 786                            struct intel_plane_state *state);
 787 };
 788
 789 struct intel_watermark_params {
 790         unsigned long fifo_size;
 791         unsigned long max_wm;
 792         unsigned long default_wm;
 793         unsigned long guard_size;
 794         unsigned long cacheline_size;
 795 };
 796
 797 struct cxsr_latency {
 798         int is_desktop;
 799         int is_ddr3;
 800         unsigned long fsb_freq;
 801         unsigned long mem_freq;
 802         unsigned long display_sr;
 803         unsigned long display_hpll_disable;
 804         unsigned long cursor_sr;
 805         unsigned long cursor_hpll_disable;
 806 };
 807
 808 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 809 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 810 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 811 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 812 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 813 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 814 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 815 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 816 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 817
 818 struct intel_hdmi {
 819         i915_reg_t hdmi_reg;
 820         int ddc_bus;
 821         struct {
 822                 enum drm_dp_dual_mode_type type;
 823                 int max_tmds_clock;
 824         } dp_dual_mode;
 825         bool limited_color_range;
 826         bool color_range_auto;
 827         bool has_hdmi_sink;
 828         bool has_audio;
 829         enum hdmi_force_audio force_audio;
 830         bool rgb_quant_range_selectable;
 831         enum hdmi_picture_aspect aspect_ratio;
 832         struct intel_connector *attached_connector;
 833         void (*write_infoframe)(struct drm_encoder *encoder,
 834                                 enum hdmi_infoframe_type type,
 835                                 const void *frame, ssize_t len);
 836         void (*set_infoframes)(struct drm_encoder *encoder,
 837                                bool enable,
 838                                const struct drm_display_mode *adjusted_mode);
 839         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 840                                   const struct intel_crtc_state *pipe_config);
 841 };
 842
 843 struct intel_dp_mst_encoder;
 844 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 845
 846 /*
 847  * enum link_m_n_set:
 848  *      When platform provides two set of M_N registers for dp, we can
 849  *      program them and switch between them incase of DRRS.
 850  *      But When only one such register is provided, we have to program the
 851  *      required divider value on that registers itself based on the DRRS state.
 852  *
 853  * M1_N1        : Program dp_m_n on M1_N1 registers
 854  *                        dp_m2_n2 on M2_N2 registers (If supported)
 855  *
 856  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 857  *                        M2_N2 registers are not supported
 858  */
 859
 860 enum link_m_n_set {
 861         /* Sets the m1_n1 and m2_n2 */
 862         M1_N1 = 0,
 863         M2_N2
 864 };
 865
 866 struct intel_dp {
 867         i915_reg_t output_reg;
 868         i915_reg_t aux_ch_ctl_reg;
 869         i915_reg_t aux_ch_data_reg[5];
 870         uint32_t DP;
 871         int link_rate;
 872         uint8_t lane_count;
 873         uint8_t sink_count;
 874         bool link_mst;
 875         bool has_audio;
 876         bool detect_done;
 877         enum hdmi_force_audio force_audio;
 878         bool limited_color_range;
 879         bool color_range_auto;
 880         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 881         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 882         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 883         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 884         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 885         uint8_t num_sink_rates;
 886         int sink_rates[DP_MAX_SUPPORTED_RATES];
 887         struct drm_dp_aux aux;
 888         uint8_t train_set[4];
 889         int panel_power_up_delay;
 890         int panel_power_down_delay;
 891         int panel_power_cycle_delay;
 892         int backlight_on_delay;
 893         int backlight_off_delay;
 894         struct delayed_work panel_vdd_work;
 895         bool want_panel_vdd;
 896         unsigned long last_power_on;
 897         unsigned long last_backlight_off;
 898         ktime_t panel_power_off_time;
 899
 900         struct notifier_block edp_notifier;
 901
 902         /*
 903          * Pipe whose power sequencer is currently locked into
 904          * this port. Only relevant on VLV/CHV.
 905          */
 906         enum pipe pps_pipe;
 907         /*
 908          * Set if the sequencer may be reset due to a power transition,
 909          * requiring a reinitialization. Only relevant on BXT.
 910          */
 911         bool pps_reset;
 912         struct edp_power_seq pps_delays;
 913
 914         bool can_mst; /* this port supports mst */
 915         bool is_mst;
 916         int active_mst_links;
 917         /* connector directly attached - won't be use for modeset in mst world */
 918         struct intel_connector *attached_connector;
 919
 920         /* mst connector list */
 921         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 922         struct drm_dp_mst_topology_mgr mst_mgr;
 923
 924         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 925         /*
 926          * This function returns the value we have to program the AUX_CTL
 927          * register with to kick off an AUX transaction.
 928          */
 929         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 930                                      bool has_aux_irq,
 931                                      int send_bytes,
 932                                      uint32_t aux_clock_divider);
 933
 934         /* This is called before a link training is starterd */
 935         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 936
 937         /* Displayport compliance testing */
 938         unsigned long compliance_test_type;
 939         unsigned long compliance_test_data;
 940         bool compliance_test_active;
 941 };
 942
 943 struct intel_digital_port {
 944         struct intel_encoder base;
 945         enum port port;
 946         u32 saved_port_bits;
 947         struct intel_dp dp;
 948         struct intel_hdmi hdmi;
 949         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 950         bool release_cl2_override;
 951         uint8_t max_lanes;
 952         /* for communication with audio component; protected by av_mutex */
 953         const struct drm_connector *audio_connector;
 954 };
 955
 956 struct intel_dp_mst_encoder {
 957         struct intel_encoder base;
 958         enum pipe pipe;
 959         struct intel_digital_port *primary;
 960         struct intel_connector *connector;
 961 };
 962
 963 static inline enum dpio_channel
 964 vlv_dport_to_channel(struct intel_digital_port *dport)
 965 {
 966         switch (dport->port) {
 967         case PORT_B:
 968         case PORT_D:
 969                 return DPIO_CH0;
 970         case PORT_C:
 971                 return DPIO_CH1;
 972         default:
 973                 BUG();
 974         }
 975 }
 976
 977 static inline enum dpio_phy
 978 vlv_dport_to_phy(struct intel_digital_port *dport)
 979 {
 980         switch (dport->port) {
 981         case PORT_B:
 982         case PORT_C:
 983                 return DPIO_PHY0;
 984         case PORT_D:
 985                 return DPIO_PHY1;
 986         default:
 987                 BUG();
 988         }
 989 }
 990
 991 static inline enum dpio_channel
 992 vlv_pipe_to_channel(enum pipe pipe)
 993 {
 994         switch (pipe) {
 995         case PIPE_A:
 996         case PIPE_C:
 997                 return DPIO_CH0;
 998         case PIPE_B:
 999                 return DPIO_CH1;
1000         default:
1001                 BUG();
1002         }
1003 }
1004
1005 static inline struct drm_crtc *
1006 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1007 {
1008         struct drm_i915_private *dev_priv = to_i915(dev);
1009         return dev_priv->pipe_to_crtc_mapping[pipe];
1010 }
1011
1012 static inline struct drm_crtc *
1013 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1014 {
1015         struct drm_i915_private *dev_priv = to_i915(dev);
1016         return dev_priv->plane_to_crtc_mapping[plane];
1017 }
1018
1019 struct intel_flip_work {
1020         struct work_struct unpin_work;
1021         struct work_struct mmio_work;
1022
1023         struct drm_crtc *crtc;
1024         struct drm_framebuffer *old_fb;
1025         struct drm_i915_gem_object *pending_flip_obj;
1026         struct drm_pending_vblank_event *event;
1027         atomic_t pending;
1028         u32 flip_count;
1029         u32 gtt_offset;
1030         struct drm_i915_gem_request *flip_queued_req;
1031         u32 flip_queued_vblank;
1032         u32 flip_ready_vblank;
1033         unsigned int rotation;
1034 };
1035
1036 struct intel_load_detect_pipe {
1037         struct drm_atomic_state *restore_state;
1038 };
1039
1040 static inline struct intel_encoder *
1041 intel_attached_encoder(struct drm_connector *connector)
1042 {
1043         return to_intel_connector(connector)->encoder;
1044 }
1045
1046 static inline struct intel_digital_port *
1047 enc_to_dig_port(struct drm_encoder *encoder)
1048 {
1049         return container_of(encoder, struct intel_digital_port, base.base);
1050 }
1051
1052 static inline struct intel_dp_mst_encoder *
1053 enc_to_mst(struct drm_encoder *encoder)
1054 {
1055         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1056 }
1057
1058 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1059 {
1060         return &enc_to_dig_port(encoder)->dp;
1061 }
1062
1063 static inline struct intel_digital_port *
1064 dp_to_dig_port(struct intel_dp *intel_dp)
1065 {
1066         return container_of(intel_dp, struct intel_digital_port, dp);
1067 }
1068
1069 static inline struct intel_digital_port *
1070 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1071 {
1072         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1073 }
1074
1075 /*
1076  * Returns the number of planes for this pipe, ie the number of sprites + 1
1077  * (primary plane). This doesn't count the cursor plane then.
1078  */
1079 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1080 {
1081         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1082 }
1083
1084 /* intel_fifo_underrun.c */
1085 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1086                                            enum pipe pipe, bool enable);
1087 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1088                                            enum transcoder pch_transcoder,
1089                                            bool enable);
1090 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1091                                          enum pipe pipe);
1092 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1093                                          enum transcoder pch_transcoder);
1094 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1095 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1096
1097 /* i915_irq.c */
1098 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1099 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1100 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1101 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1102 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1103 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1104 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1105 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1106 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1107 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1108 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1109 {
1110         /*
1111          * We only use drm_irq_uninstall() at unload and VT switch, so
1112          * this is the only thing we need to check.
1113          */
1114         return dev_priv->pm.irqs_enabled;
1115 }
1116
1117 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1118 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1119                                      unsigned int pipe_mask);
1120 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1121                                      unsigned int pipe_mask);
1122
1123 /* intel_crt.c */
1124 void intel_crt_init(struct drm_device *dev);
1125 void intel_crt_reset(struct drm_encoder *encoder);
1126
1127 /* intel_ddi.c */
1128 void intel_ddi_clk_select(struct intel_encoder *encoder,
1129                           const struct intel_crtc_state *pipe_config);
1130 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1131 void hsw_fdi_link_train(struct drm_crtc *crtc);
1132 void intel_ddi_init(struct drm_device *dev, enum port port);
1133 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1134 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1135 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1136 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1137                                        enum transcoder cpu_transcoder);
1138 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1139 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1140 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1141                           struct intel_crtc_state *crtc_state);
1142 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1143 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1144 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1145 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1146 void intel_ddi_get_config(struct intel_encoder *encoder,
1147                           struct intel_crtc_state *pipe_config);
1148 struct intel_encoder *
1149 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1150
1151 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1152 void intel_ddi_clock_get(struct intel_encoder *encoder,
1153                          struct intel_crtc_state *pipe_config);
1154 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1155 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1156
1157 unsigned int intel_fb_align_height(struct drm_device *dev,
1158                                    unsigned int height,
1159                                    uint32_t pixel_format,
1160                                    uint64_t fb_format_modifier);
1161 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1162                               uint64_t fb_modifier, uint32_t pixel_format);
1163
1164 /* intel_audio.c */
1165 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1166 void intel_audio_codec_enable(struct intel_encoder *encoder);
1167 void intel_audio_codec_disable(struct intel_encoder *encoder);
1168 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1169 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1170
1171 /* intel_display.c */
1172 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1173 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1174 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1175                       const char *name, u32 reg, int ref_freq);
1176 extern const struct drm_plane_funcs intel_plane_funcs;
1177 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1178 unsigned int intel_fb_xy_to_linear(int x, int y,
1179                                    const struct intel_plane_state *state,
1180                                    int plane);
1181 void intel_add_fb_offsets(int *x, int *y,
1182                           const struct intel_plane_state *state, int plane);
1183 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1184 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1185 void intel_mark_busy(struct drm_i915_private *dev_priv);
1186 void intel_mark_idle(struct drm_i915_private *dev_priv);
1187 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1188 int intel_display_suspend(struct drm_device *dev);
1189 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1190 void intel_encoder_destroy(struct drm_encoder *encoder);
1191 int intel_connector_init(struct intel_connector *);
1192 struct intel_connector *intel_connector_alloc(void);
1193 bool intel_connector_get_hw_state(struct intel_connector *connector);
1194 void intel_connector_attach_encoder(struct intel_connector *connector,
1195                                     struct intel_encoder *encoder);
1196 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1197                                              struct drm_crtc *crtc);
1198 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1199 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1200                                 struct drm_file *file_priv);
1201 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1202                                              enum pipe pipe);
1203 static inline bool
1204 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1205                     enum intel_output_type type)
1206 {
1207         return crtc_state->output_types & (1 << type);
1208 }
1209 static inline bool
1210 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1211 {
1212         return crtc_state->output_types &
1213                 ((1 << INTEL_OUTPUT_DP) |
1214                  (1 << INTEL_OUTPUT_DP_MST) |
1215                  (1 << INTEL_OUTPUT_EDP));
1216 }
1217 static inline void
1218 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1219 {
1220         drm_wait_one_vblank(dev, pipe);
1221 }
1222 static inline void
1223 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1224 {
1225         const struct intel_crtc *crtc =
1226                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1227
1228         if (crtc->active)
1229                 intel_wait_for_vblank(dev, pipe);
1230 }
1231
1232 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1233
1234 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1235 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1236                          struct intel_digital_port *dport,
1237                          unsigned int expected_mask);
1238 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1239                                 struct drm_display_mode *mode,
1240                                 struct intel_load_detect_pipe *old,
1241                                 struct drm_modeset_acquire_ctx *ctx);
1242 void intel_release_load_detect_pipe(struct drm_connector *connector,
1243                                     struct intel_load_detect_pipe *old,
1244                                     struct drm_modeset_acquire_ctx *ctx);
1245 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1246                                unsigned int rotation);
1247 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1248 struct drm_framebuffer *
1249 __intel_framebuffer_create(struct drm_device *dev,
1250                            struct drm_mode_fb_cmd2 *mode_cmd,
1251                            struct drm_i915_gem_object *obj);
1252 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1253 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1254 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1255 int intel_prepare_plane_fb(struct drm_plane *plane,
1256                            const struct drm_plane_state *new_state);
1257 void intel_cleanup_plane_fb(struct drm_plane *plane,
1258                             const struct drm_plane_state *old_state);
1259 int intel_plane_atomic_get_property(struct drm_plane *plane,
1260                                     const struct drm_plane_state *state,
1261                                     struct drm_property *property,
1262                                     uint64_t *val);
1263 int intel_plane_atomic_set_property(struct drm_plane *plane,
1264                                     struct drm_plane_state *state,
1265                                     struct drm_property *property,
1266                                     uint64_t val);
1267 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1268                                     struct drm_plane_state *plane_state);
1269
1270 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1271                                uint64_t fb_modifier, unsigned int cpp);
1272
1273 static inline bool
1274 intel_rotation_90_or_270(unsigned int rotation)
1275 {
1276         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1277 }
1278
1279 void intel_create_rotation_property(struct drm_device *dev,
1280                                         struct intel_plane *plane);
1281
1282 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1283                                     enum pipe pipe);
1284
1285 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1286                      const struct dpll *dpll);
1287 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1288 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1289
1290 /* modesetting asserts */
1291 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1292                            enum pipe pipe);
1293 void assert_pll(struct drm_i915_private *dev_priv,
1294                 enum pipe pipe, bool state);
1295 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1296 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1297 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1298 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1299 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1300 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1301                        enum pipe pipe, bool state);
1302 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1303 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1304 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1305 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1306 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1307 u32 intel_compute_tile_offset(int *x, int *y,
1308                               const struct intel_plane_state *state, int plane);
1309 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1310 void intel_finish_reset(struct drm_i915_private *dev_priv);
1311 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1312 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1313 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1314 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1315 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1316 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1317 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1318                             enum dpio_phy phy);
1319 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1320                               enum dpio_phy phy);
1321 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1322 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1323 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1324 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1325 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1326 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1327 unsigned int skl_cdclk_get_vco(unsigned int freq);
1328 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1329 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1330 void intel_dp_get_m_n(struct intel_crtc *crtc,
1331                       struct intel_crtc_state *pipe_config);
1332 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1333 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1334 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1335                         struct dpll *best_clock);
1336 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1337
1338 bool intel_crtc_active(struct drm_crtc *crtc);
1339 void hsw_enable_ips(struct intel_crtc *crtc);
1340 void hsw_disable_ips(struct intel_crtc *crtc);
1341 enum intel_display_power_domain
1342 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1343 enum intel_display_power_domain
1344 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1345 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1346                                  struct intel_crtc_state *pipe_config);
1347
1348 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1349 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1350
1351 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1352
1353 u32 skl_plane_ctl_format(uint32_t pixel_format);
1354 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1355 u32 skl_plane_ctl_rotation(unsigned int rotation);
1356 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1357                      unsigned int rotation);
1358 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1359
1360 /* intel_csr.c */
1361 void intel_csr_ucode_init(struct drm_i915_private *);
1362 void intel_csr_load_program(struct drm_i915_private *);
1363 void intel_csr_ucode_fini(struct drm_i915_private *);
1364 void intel_csr_ucode_suspend(struct drm_i915_private *);
1365 void intel_csr_ucode_resume(struct drm_i915_private *);
1366
1367 /* intel_dp.c */
1368 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1369 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1370                              struct intel_connector *intel_connector);
1371 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1372                               const struct intel_crtc_state *pipe_config);
1373 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1374 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1375 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1376 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1377 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1378 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1379 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1380 bool intel_dp_compute_config(struct intel_encoder *encoder,
1381                              struct intel_crtc_state *pipe_config);
1382 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1383 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1384                                   bool long_hpd);
1385 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1386 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1387 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1388 void intel_edp_panel_on(struct intel_dp *intel_dp);
1389 void intel_edp_panel_off(struct intel_dp *intel_dp);
1390 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1391 void intel_dp_mst_suspend(struct drm_device *dev);
1392 void intel_dp_mst_resume(struct drm_device *dev);
1393 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1394 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1395 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1396 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1397 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1398 void intel_plane_destroy(struct drm_plane *plane);
1399 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1400 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1401 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1402                                unsigned int frontbuffer_bits);
1403 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1404                           unsigned int frontbuffer_bits);
1405 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1406                                   struct intel_digital_port *port);
1407
1408 void
1409 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1410                                        uint8_t dp_train_pat);
1411 void
1412 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1413 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1414 uint8_t
1415 intel_dp_voltage_max(struct intel_dp *intel_dp);
1416 uint8_t
1417 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1418 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1419                            uint8_t *link_bw, uint8_t *rate_select);
1420 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1421 bool
1422 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1423
1424 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1425 {
1426         return ~((1 << lane_count) - 1) & 0xf;
1427 }
1428
1429 /* intel_dp_aux_backlight.c */
1430 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1431
1432 /* intel_dp_mst.c */
1433 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1434 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1435 /* intel_dsi.c */
1436 void intel_dsi_init(struct drm_device *dev);
1437
1438 /* intel_dsi_dcs_backlight.c */
1439 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1440
1441 /* intel_dvo.c */
1442 void intel_dvo_init(struct drm_device *dev);
1443 /* intel_hotplug.c */
1444 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1445
1446
1447 /* legacy fbdev emulation in intel_fbdev.c */
1448 #ifdef CONFIG_DRM_FBDEV_EMULATION
1449 extern int intel_fbdev_init(struct drm_device *dev);
1450 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1451 extern void intel_fbdev_fini(struct drm_device *dev);
1452 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1453 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1454 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1455 #else
1456 static inline int intel_fbdev_init(struct drm_device *dev)
1457 {
1458         return 0;
1459 }
1460
1461 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1462 {
1463 }
1464
1465 static inline void intel_fbdev_fini(struct drm_device *dev)
1466 {
1467 }
1468
1469 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1470 {
1471 }
1472
1473 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1474 {
1475 }
1476 #endif
1477
1478 /* intel_fbc.c */
1479 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1480                            struct drm_atomic_state *state);
1481 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1482 void intel_fbc_pre_update(struct intel_crtc *crtc,
1483                           struct intel_crtc_state *crtc_state,
1484                           struct intel_plane_state *plane_state);
1485 void intel_fbc_post_update(struct intel_crtc *crtc);
1486 void intel_fbc_init(struct drm_i915_private *dev_priv);
1487 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1488 void intel_fbc_enable(struct intel_crtc *crtc,
1489                       struct intel_crtc_state *crtc_state,
1490                       struct intel_plane_state *plane_state);
1491 void intel_fbc_disable(struct intel_crtc *crtc);
1492 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1493 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1494                           unsigned int frontbuffer_bits,
1495                           enum fb_op_origin origin);
1496 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1497                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1498 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1499
1500 /* intel_hdmi.c */
1501 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1502 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1503                                struct intel_connector *intel_connector);
1504 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1505 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1506                                struct intel_crtc_state *pipe_config);
1507 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1508
1509
1510 /* intel_lvds.c */
1511 void intel_lvds_init(struct drm_device *dev);
1512 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1513 bool intel_is_dual_link_lvds(struct drm_device *dev);
1514
1515
1516 /* intel_modes.c */
1517 int intel_connector_update_modes(struct drm_connector *connector,
1518                                  struct edid *edid);
1519 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1520 void intel_attach_force_audio_property(struct drm_connector *connector);
1521 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1522 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1523
1524
1525 /* intel_overlay.c */
1526 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1527 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1528 int intel_overlay_switch_off(struct intel_overlay *overlay);
1529 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1530                                   struct drm_file *file_priv);
1531 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1532                               struct drm_file *file_priv);
1533 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1534
1535
1536 /* intel_panel.c */
1537 int intel_panel_init(struct intel_panel *panel,
1538                      struct drm_display_mode *fixed_mode,
1539                      struct drm_display_mode *downclock_mode);
1540 void intel_panel_fini(struct intel_panel *panel);
1541 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1542                             struct drm_display_mode *adjusted_mode);
1543 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1544                              struct intel_crtc_state *pipe_config,
1545                              int fitting_mode);
1546 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1547                               struct intel_crtc_state *pipe_config,
1548                               int fitting_mode);
1549 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1550                                     u32 level, u32 max);
1551 int intel_panel_setup_backlight(struct drm_connector *connector,
1552                                 enum pipe pipe);
1553 void intel_panel_enable_backlight(struct intel_connector *connector);
1554 void intel_panel_disable_backlight(struct intel_connector *connector);
1555 void intel_panel_destroy_backlight(struct drm_connector *connector);
1556 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1557 extern struct drm_display_mode *intel_find_panel_downclock(
1558                                 struct drm_device *dev,
1559                                 struct drm_display_mode *fixed_mode,
1560                                 struct drm_connector *connector);
1561
1562 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1563 int intel_backlight_device_register(struct intel_connector *connector);
1564 void intel_backlight_device_unregister(struct intel_connector *connector);
1565 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1566 static int intel_backlight_device_register(struct intel_connector *connector)
1567 {
1568         return 0;
1569 }
1570 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1571 {
1572 }
1573 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1574
1575
1576 /* intel_psr.c */
1577 void intel_psr_enable(struct intel_dp *intel_dp);
1578 void intel_psr_disable(struct intel_dp *intel_dp);
1579 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1580                           unsigned frontbuffer_bits);
1581 void intel_psr_flush(struct drm_i915_private *dev_priv,
1582                      unsigned frontbuffer_bits,
1583                      enum fb_op_origin origin);
1584 void intel_psr_init(struct drm_device *dev);
1585 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1586                                    unsigned frontbuffer_bits);
1587
1588 /* intel_runtime_pm.c */
1589 int intel_power_domains_init(struct drm_i915_private *);
1590 void intel_power_domains_fini(struct drm_i915_private *);
1591 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1592 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1593 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1594 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1595 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1596 const char *
1597 intel_display_power_domain_str(enum intel_display_power_domain domain);
1598
1599 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1600                                     enum intel_display_power_domain domain);
1601 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1602                                       enum intel_display_power_domain domain);
1603 void intel_display_power_get(struct drm_i915_private *dev_priv,
1604                              enum intel_display_power_domain domain);
1605 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1606                                         enum intel_display_power_domain domain);
1607 void intel_display_power_put(struct drm_i915_private *dev_priv,
1608                              enum intel_display_power_domain domain);
1609
1610 static inline void
1611 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1612 {
1613         WARN_ONCE(dev_priv->pm.suspended,
1614                   "Device suspended during HW access\n");
1615 }
1616
1617 static inline void
1618 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1619 {
1620         assert_rpm_device_not_suspended(dev_priv);
1621         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1622          * too much noise. */
1623         if (!atomic_read(&dev_priv->pm.wakeref_count))
1624                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1625 }
1626
1627 static inline int
1628 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1629 {
1630         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1631
1632         assert_rpm_wakelock_held(dev_priv);
1633
1634         return seq;
1635 }
1636
1637 static inline void
1638 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1639 {
1640         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1641                   "HW access outside of RPM atomic section\n");
1642 }
1643
1644 /**
1645  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1646  * @dev_priv: i915 device instance
1647  *
1648  * This function disable asserts that check if we hold an RPM wakelock
1649  * reference, while keeping the device-not-suspended checks still enabled.
1650  * It's meant to be used only in special circumstances where our rule about
1651  * the wakelock refcount wrt. the device power state doesn't hold. According
1652  * to this rule at any point where we access the HW or want to keep the HW in
1653  * an active state we must hold an RPM wakelock reference acquired via one of
1654  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1655  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1656  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1657  * users should avoid using this function.
1658  *
1659  * Any calls to this function must have a symmetric call to
1660  * enable_rpm_wakeref_asserts().
1661  */
1662 static inline void
1663 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1664 {
1665         atomic_inc(&dev_priv->pm.wakeref_count);
1666 }
1667
1668 /**
1669  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1670  * @dev_priv: i915 device instance
1671  *
1672  * This function re-enables the RPM assert checks after disabling them with
1673  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1674  * circumstances otherwise its use should be avoided.
1675  *
1676  * Any calls to this function must have a symmetric call to
1677  * disable_rpm_wakeref_asserts().
1678  */
1679 static inline void
1680 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1681 {
1682         atomic_dec(&dev_priv->pm.wakeref_count);
1683 }
1684
1685 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1686 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1687 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1688 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1689
1690 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1691
1692 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1693                              bool override, unsigned int mask);
1694 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1695                           enum dpio_channel ch, bool override);
1696
1697
1698 /* intel_pm.c */
1699 void intel_init_clock_gating(struct drm_device *dev);
1700 void intel_suspend_hw(struct drm_device *dev);
1701 int ilk_wm_max_level(const struct drm_device *dev);
1702 void intel_update_watermarks(struct drm_crtc *crtc);
1703 void intel_init_pm(struct drm_device *dev);
1704 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1705 void intel_pm_setup(struct drm_device *dev);
1706 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1707 void intel_gpu_ips_teardown(void);
1708 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1709 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1710 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1711 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1712 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1713 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1714 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1715 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1716 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1717 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1718 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1719                     struct intel_rps_client *rps,
1720                     unsigned long submitted);
1721 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1722 void vlv_wm_get_hw_state(struct drm_device *dev);
1723 void ilk_wm_get_hw_state(struct drm_device *dev);
1724 void skl_wm_get_hw_state(struct drm_device *dev);
1725 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1726                           struct skl_ddb_allocation *ddb /* out */);
1727 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1728 bool ilk_disable_lp_wm(struct drm_device *dev);
1729 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1730 static inline int intel_enable_rc6(void)
1731 {
1732         return i915.enable_rc6;
1733 }
1734
1735 /* intel_sdvo.c */
1736 bool intel_sdvo_init(struct drm_device *dev,
1737                      i915_reg_t reg, enum port port);
1738
1739
1740 /* intel_sprite.c */
1741 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1742 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1743                               struct drm_file *file_priv);
1744 void intel_pipe_update_start(struct intel_crtc *crtc);
1745 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1746
1747 /* intel_tv.c */
1748 void intel_tv_init(struct drm_device *dev);
1749
1750 /* intel_atomic.c */
1751 int intel_connector_atomic_get_property(struct drm_connector *connector,
1752                                         const struct drm_connector_state *state,
1753                                         struct drm_property *property,
1754                                         uint64_t *val);
1755 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1756 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1757                                struct drm_crtc_state *state);
1758 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1759 void intel_atomic_state_clear(struct drm_atomic_state *);
1760 struct intel_shared_dpll_config *
1761 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1762
1763 static inline struct intel_crtc_state *
1764 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1765                             struct intel_crtc *crtc)
1766 {
1767         struct drm_crtc_state *crtc_state;
1768         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1769         if (IS_ERR(crtc_state))
1770                 return ERR_CAST(crtc_state);
1771
1772         return to_intel_crtc_state(crtc_state);
1773 }
1774
1775 static inline struct intel_plane_state *
1776 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1777                                       struct intel_plane *plane)
1778 {
1779         struct drm_plane_state *plane_state;
1780
1781         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1782
1783         return to_intel_plane_state(plane_state);
1784 }
1785
1786 int intel_atomic_setup_scalers(struct drm_device *dev,
1787         struct intel_crtc *intel_crtc,
1788         struct intel_crtc_state *crtc_state);
1789
1790 /* intel_atomic_plane.c */
1791 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1792 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1793 void intel_plane_destroy_state(struct drm_plane *plane,
1794                                struct drm_plane_state *state);
1795 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1796
1797 /* intel_color.c */
1798 void intel_color_init(struct drm_crtc *crtc);
1799 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1800 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1801 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1802
1803 #endif /* __INTEL_DRV_H__ */