2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * Display PLLs used for driving outputs vary by platform. While some have
30 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
31 * from a pool. In the latter scenario, it is possible that multiple pipes
32 * share a PLL if their configurations match.
34 * This file provides an abstraction over display PLLs. The function
35 * intel_shared_dpll_init() initializes the PLLs for the given platform. The
36 * users of a PLL are tracked and that tracking is integrated with the atomic
37 * modest interface. During an atomic operation, a PLL can be requested for a
38 * given CRTC and encoder configuration by calling intel_get_shared_dpll() and
39 * a previously used PLL can be released with intel_release_shared_dpll().
40 * Changes to the users are first staged in the atomic state, and then made
41 * effective by calling intel_shared_dpll_swap_state() during the atomic
46 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
47 struct intel_shared_dpll_state *shared_dpll)
51 /* Copy shared dpll state */
52 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
53 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
55 shared_dpll[i] = pll->state;
59 static struct intel_shared_dpll_state *
60 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
62 struct intel_atomic_state *state = to_intel_atomic_state(s);
64 WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
66 if (!state->dpll_set) {
67 state->dpll_set = true;
69 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
73 return state->shared_dpll;
77 * intel_get_shared_dpll_by_id - get a DPLL given its id
78 * @dev_priv: i915 device instance
82 * A pointer to the DPLL with @id
84 struct intel_shared_dpll *
85 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
86 enum intel_dpll_id id)
88 return &dev_priv->shared_dplls[id];
92 * intel_get_shared_dpll_id - get the id of a DPLL
93 * @dev_priv: i915 device instance
100 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
101 struct intel_shared_dpll *pll)
103 if (WARN_ON(pll < dev_priv->shared_dplls||
104 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
107 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
111 void assert_shared_dpll(struct drm_i915_private *dev_priv,
112 struct intel_shared_dpll *pll,
116 struct intel_dpll_hw_state hw_state;
118 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
121 cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
122 I915_STATE_WARN(cur_state != state,
123 "%s assertion failure (expected %s, current %s)\n",
124 pll->info->name, onoff(state), onoff(cur_state));
128 * intel_prepare_shared_dpll - call a dpll's prepare hook
129 * @crtc: CRTC which has a shared dpll
131 * This calls the PLL's prepare hook if it has one and if the PLL is not
132 * already enabled. The prepare hook is platform specific.
134 void intel_prepare_shared_dpll(struct intel_crtc *crtc)
136 struct drm_device *dev = crtc->base.dev;
137 struct drm_i915_private *dev_priv = to_i915(dev);
138 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
140 if (WARN_ON(pll == NULL))
143 mutex_lock(&dev_priv->dpll_lock);
144 WARN_ON(!pll->state.crtc_mask);
145 if (!pll->active_mask) {
146 DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name);
148 assert_shared_dpll_disabled(dev_priv, pll);
150 pll->info->funcs->prepare(dev_priv, pll);
152 mutex_unlock(&dev_priv->dpll_lock);
156 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
157 * @crtc: CRTC which has a shared DPLL
159 * Enable the shared DPLL used by @crtc.
161 void intel_enable_shared_dpll(struct intel_crtc *crtc)
163 struct drm_device *dev = crtc->base.dev;
164 struct drm_i915_private *dev_priv = to_i915(dev);
165 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
166 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
167 unsigned int old_mask;
169 if (WARN_ON(pll == NULL))
172 mutex_lock(&dev_priv->dpll_lock);
173 old_mask = pll->active_mask;
175 if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) ||
176 WARN_ON(pll->active_mask & crtc_mask))
179 pll->active_mask |= crtc_mask;
181 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
182 pll->info->name, pll->active_mask, pll->on,
187 assert_shared_dpll_enabled(dev_priv, pll);
192 DRM_DEBUG_KMS("enabling %s\n", pll->info->name);
193 pll->info->funcs->enable(dev_priv, pll);
197 mutex_unlock(&dev_priv->dpll_lock);
201 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
202 * @crtc: CRTC which has a shared DPLL
204 * Disable the shared DPLL used by @crtc.
206 void intel_disable_shared_dpll(struct intel_crtc *crtc)
208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
209 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
210 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
212 /* PCH only available on ILK+ */
213 if (INTEL_GEN(dev_priv) < 5)
219 mutex_lock(&dev_priv->dpll_lock);
220 if (WARN_ON(!(pll->active_mask & crtc_mask)))
223 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
224 pll->info->name, pll->active_mask, pll->on,
227 assert_shared_dpll_enabled(dev_priv, pll);
230 pll->active_mask &= ~crtc_mask;
231 if (pll->active_mask)
234 DRM_DEBUG_KMS("disabling %s\n", pll->info->name);
235 pll->info->funcs->disable(dev_priv, pll);
239 mutex_unlock(&dev_priv->dpll_lock);
242 static struct intel_shared_dpll *
243 intel_find_shared_dpll(struct intel_crtc *crtc,
244 struct intel_crtc_state *crtc_state,
245 enum intel_dpll_id range_min,
246 enum intel_dpll_id range_max)
248 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
249 struct intel_shared_dpll *pll;
250 struct intel_shared_dpll_state *shared_dpll;
251 enum intel_dpll_id i;
253 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
255 for (i = range_min; i <= range_max; i++) {
256 pll = &dev_priv->shared_dplls[i];
258 /* Only want to check enabled timings first */
259 if (shared_dpll[i].crtc_mask == 0)
262 if (memcmp(&crtc_state->dpll_hw_state,
263 &shared_dpll[i].hw_state,
264 sizeof(crtc_state->dpll_hw_state)) == 0) {
265 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
266 crtc->base.base.id, crtc->base.name,
268 shared_dpll[i].crtc_mask,
274 /* Ok no matching timings, maybe there's a free one? */
275 for (i = range_min; i <= range_max; i++) {
276 pll = &dev_priv->shared_dplls[i];
277 if (shared_dpll[i].crtc_mask == 0) {
278 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
279 crtc->base.base.id, crtc->base.name,
289 intel_reference_shared_dpll(struct intel_shared_dpll *pll,
290 struct intel_crtc_state *crtc_state)
292 struct intel_shared_dpll_state *shared_dpll;
293 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
294 const enum intel_dpll_id id = pll->info->id;
296 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
298 if (shared_dpll[id].crtc_mask == 0)
299 shared_dpll[id].hw_state =
300 crtc_state->dpll_hw_state;
302 crtc_state->shared_dpll = pll;
303 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
304 pipe_name(crtc->pipe));
306 shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
310 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
311 * @state: atomic state
313 * This is the dpll version of drm_atomic_helper_swap_state() since the
314 * helper does not handle driver-specific global state.
316 * For consistency with atomic helpers this function does a complete swap,
317 * i.e. it also puts the current state into @state, even though there is no
318 * need for that at this moment.
320 void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
322 struct drm_i915_private *dev_priv = to_i915(state->dev);
323 struct intel_shared_dpll_state *shared_dpll;
324 struct intel_shared_dpll *pll;
325 enum intel_dpll_id i;
327 if (!to_intel_atomic_state(state)->dpll_set)
330 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
331 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
332 struct intel_shared_dpll_state tmp;
334 pll = &dev_priv->shared_dplls[i];
337 pll->state = shared_dpll[i];
338 shared_dpll[i] = tmp;
342 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
343 struct intel_shared_dpll *pll,
344 struct intel_dpll_hw_state *hw_state)
346 const enum intel_dpll_id id = pll->info->id;
349 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
352 val = I915_READ(PCH_DPLL(id));
353 hw_state->dpll = val;
354 hw_state->fp0 = I915_READ(PCH_FP0(id));
355 hw_state->fp1 = I915_READ(PCH_FP1(id));
357 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
359 return val & DPLL_VCO_ENABLE;
362 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
363 struct intel_shared_dpll *pll)
365 const enum intel_dpll_id id = pll->info->id;
367 I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
368 I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
371 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
376 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
378 val = I915_READ(PCH_DREF_CONTROL);
379 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
380 DREF_SUPERSPREAD_SOURCE_MASK));
381 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
384 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
385 struct intel_shared_dpll *pll)
387 const enum intel_dpll_id id = pll->info->id;
389 /* PCH refclock must be enabled first */
390 ibx_assert_pch_refclk_enabled(dev_priv);
392 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
394 /* Wait for the clocks to stabilize. */
395 POSTING_READ(PCH_DPLL(id));
398 /* The pixel multiplier can only be updated once the
399 * DPLL is enabled and the clocks are stable.
403 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
404 POSTING_READ(PCH_DPLL(id));
408 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
409 struct intel_shared_dpll *pll)
411 const enum intel_dpll_id id = pll->info->id;
412 struct drm_device *dev = &dev_priv->drm;
413 struct intel_crtc *crtc;
415 /* Make sure no transcoder isn't still depending on us. */
416 for_each_intel_crtc(dev, crtc) {
417 if (crtc->config->shared_dpll == pll)
418 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
421 I915_WRITE(PCH_DPLL(id), 0);
422 POSTING_READ(PCH_DPLL(id));
426 static struct intel_shared_dpll *
427 ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
428 struct intel_encoder *encoder)
430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
431 struct intel_shared_dpll *pll;
432 enum intel_dpll_id i;
434 if (HAS_PCH_IBX(dev_priv)) {
435 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
436 i = (enum intel_dpll_id) crtc->pipe;
437 pll = &dev_priv->shared_dplls[i];
439 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
440 crtc->base.base.id, crtc->base.name,
443 pll = intel_find_shared_dpll(crtc, crtc_state,
451 /* reference the pll */
452 intel_reference_shared_dpll(pll, crtc_state);
457 static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
458 struct intel_dpll_hw_state *hw_state)
460 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
461 "fp0: 0x%x, fp1: 0x%x\n",
468 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
469 .prepare = ibx_pch_dpll_prepare,
470 .enable = ibx_pch_dpll_enable,
471 .disable = ibx_pch_dpll_disable,
472 .get_hw_state = ibx_pch_dpll_get_hw_state,
475 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
476 struct intel_shared_dpll *pll)
478 const enum intel_dpll_id id = pll->info->id;
480 I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
481 POSTING_READ(WRPLL_CTL(id));
485 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
486 struct intel_shared_dpll *pll)
488 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);
489 POSTING_READ(SPLL_CTL);
493 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
494 struct intel_shared_dpll *pll)
496 const enum intel_dpll_id id = pll->info->id;
499 val = I915_READ(WRPLL_CTL(id));
500 I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
501 POSTING_READ(WRPLL_CTL(id));
504 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
505 struct intel_shared_dpll *pll)
509 val = I915_READ(SPLL_CTL);
510 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
511 POSTING_READ(SPLL_CTL);
514 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
515 struct intel_shared_dpll *pll,
516 struct intel_dpll_hw_state *hw_state)
518 const enum intel_dpll_id id = pll->info->id;
521 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
524 val = I915_READ(WRPLL_CTL(id));
525 hw_state->wrpll = val;
527 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
529 return val & WRPLL_PLL_ENABLE;
532 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
533 struct intel_shared_dpll *pll,
534 struct intel_dpll_hw_state *hw_state)
538 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
541 val = I915_READ(SPLL_CTL);
542 hw_state->spll = val;
544 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
546 return val & SPLL_PLL_ENABLE;
550 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
556 /* Constraints for PLL good behavior */
562 struct hsw_wrpll_rnp {
566 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
640 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
641 unsigned r2, unsigned n2, unsigned p,
642 struct hsw_wrpll_rnp *best)
644 uint64_t a, b, c, d, diff, diff_best;
646 /* No best (r,n,p) yet */
655 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
659 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
662 * and we would like delta <= budget.
664 * If the discrepancy is above the PPM-based budget, always prefer to
665 * improve upon the previous solution. However, if you're within the
666 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
668 a = freq2k * budget * p * r2;
669 b = freq2k * budget * best->p * best->r2;
670 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
671 diff_best = abs_diff(freq2k * best->p * best->r2,
672 LC_FREQ_2K * best->n2);
674 d = 1000000 * diff_best;
676 if (a < c && b < d) {
677 /* If both are above the budget, pick the closer */
678 if (best->p * best->r2 * diff < p * r2 * diff_best) {
683 } else if (a >= c && b < d) {
684 /* If A is below the threshold but B is above it? Update. */
688 } else if (a >= c && b >= d) {
689 /* Both are below the limit, so pick the higher n2/(r2*r2) */
690 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
696 /* Otherwise a < c && b >= d, do nothing */
700 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
701 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
705 struct hsw_wrpll_rnp best = { 0, 0, 0 };
708 freq2k = clock / 100;
710 budget = hsw_wrpll_get_budget_for_freq(clock);
712 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
713 * and directly pass the LC PLL to it. */
714 if (freq2k == 5400000) {
722 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
725 * We want R so that REF_MIN <= Ref <= REF_MAX.
726 * Injecting R2 = 2 * R gives:
727 * REF_MAX * r2 > LC_FREQ * 2 and
728 * REF_MIN * r2 < LC_FREQ * 2
730 * Which means the desired boundaries for r2 are:
731 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
734 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
735 r2 <= LC_FREQ * 2 / REF_MIN;
739 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
741 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
742 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
743 * VCO_MAX * r2 > n2 * LC_FREQ and
744 * VCO_MIN * r2 < n2 * LC_FREQ)
746 * Which means the desired boundaries for n2 are:
747 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
749 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
750 n2 <= VCO_MAX * r2 / LC_FREQ;
753 for (p = P_MIN; p <= P_MAX; p += P_INC)
754 hsw_wrpll_update_rnp(freq2k, budget,
764 static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,
765 struct intel_crtc *crtc,
766 struct intel_crtc_state *crtc_state)
768 struct intel_shared_dpll *pll;
770 unsigned int p, n2, r2;
772 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
774 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
775 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
776 WRPLL_DIVIDER_POST(p);
778 crtc_state->dpll_hw_state.wrpll = val;
780 pll = intel_find_shared_dpll(crtc, crtc_state,
781 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
789 static struct intel_shared_dpll *
790 hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock)
792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
793 struct intel_shared_dpll *pll;
794 enum intel_dpll_id pll_id;
798 pll_id = DPLL_ID_LCPLL_810;
801 pll_id = DPLL_ID_LCPLL_1350;
804 pll_id = DPLL_ID_LCPLL_2700;
807 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
811 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
819 static struct intel_shared_dpll *
820 hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
821 struct intel_encoder *encoder)
823 struct intel_shared_dpll *pll;
824 int clock = crtc_state->port_clock;
826 memset(&crtc_state->dpll_hw_state, 0,
827 sizeof(crtc_state->dpll_hw_state));
829 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
830 pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state);
831 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
832 pll = hsw_ddi_dp_get_dpll(encoder, clock);
833 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
834 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
837 crtc_state->dpll_hw_state.spll =
838 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
840 pll = intel_find_shared_dpll(crtc, crtc_state,
841 DPLL_ID_SPLL, DPLL_ID_SPLL);
849 intel_reference_shared_dpll(pll, crtc_state);
854 static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
855 struct intel_dpll_hw_state *hw_state)
857 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
858 hw_state->wrpll, hw_state->spll);
861 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
862 .enable = hsw_ddi_wrpll_enable,
863 .disable = hsw_ddi_wrpll_disable,
864 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
867 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
868 .enable = hsw_ddi_spll_enable,
869 .disable = hsw_ddi_spll_disable,
870 .get_hw_state = hsw_ddi_spll_get_hw_state,
873 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
874 struct intel_shared_dpll *pll)
878 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
879 struct intel_shared_dpll *pll)
883 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
884 struct intel_shared_dpll *pll,
885 struct intel_dpll_hw_state *hw_state)
890 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
891 .enable = hsw_ddi_lcpll_enable,
892 .disable = hsw_ddi_lcpll_disable,
893 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
896 struct skl_dpll_regs {
897 i915_reg_t ctl, cfgcr1, cfgcr2;
900 /* this array is indexed by the *shared* pll id */
901 static const struct skl_dpll_regs skl_dpll_regs[4] = {
905 /* DPLL 0 doesn't support HDMI mode */
910 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
911 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
916 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
917 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
922 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
923 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
927 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll)
930 const enum intel_dpll_id id = pll->info->id;
933 val = I915_READ(DPLL_CTRL1);
935 val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
937 DPLL_CTRL1_LINK_RATE_MASK(id));
938 val |= pll->state.hw_state.ctrl1 << (id * 6);
940 I915_WRITE(DPLL_CTRL1, val);
941 POSTING_READ(DPLL_CTRL1);
944 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll)
947 const struct skl_dpll_regs *regs = skl_dpll_regs;
948 const enum intel_dpll_id id = pll->info->id;
950 skl_ddi_pll_write_ctrl1(dev_priv, pll);
952 I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
953 I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
954 POSTING_READ(regs[id].cfgcr1);
955 POSTING_READ(regs[id].cfgcr2);
957 /* the enable bit is always bit 31 */
958 I915_WRITE(regs[id].ctl,
959 I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
961 if (intel_wait_for_register(dev_priv,
966 DRM_ERROR("DPLL %d not locked\n", id);
969 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
970 struct intel_shared_dpll *pll)
972 skl_ddi_pll_write_ctrl1(dev_priv, pll);
975 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
976 struct intel_shared_dpll *pll)
978 const struct skl_dpll_regs *regs = skl_dpll_regs;
979 const enum intel_dpll_id id = pll->info->id;
981 /* the enable bit is always bit 31 */
982 I915_WRITE(regs[id].ctl,
983 I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
984 POSTING_READ(regs[id].ctl);
987 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
988 struct intel_shared_dpll *pll)
992 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
993 struct intel_shared_dpll *pll,
994 struct intel_dpll_hw_state *hw_state)
997 const struct skl_dpll_regs *regs = skl_dpll_regs;
998 const enum intel_dpll_id id = pll->info->id;
1001 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1006 val = I915_READ(regs[id].ctl);
1007 if (!(val & LCPLL_PLL_ENABLE))
1010 val = I915_READ(DPLL_CTRL1);
1011 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1013 /* avoid reading back stale values if HDMI mode is not enabled */
1014 if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1015 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
1016 hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
1021 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1026 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
1027 struct intel_shared_dpll *pll,
1028 struct intel_dpll_hw_state *hw_state)
1031 const struct skl_dpll_regs *regs = skl_dpll_regs;
1032 const enum intel_dpll_id id = pll->info->id;
1035 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1040 /* DPLL0 is always enabled since it drives CDCLK */
1041 val = I915_READ(regs[id].ctl);
1042 if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
1045 val = I915_READ(DPLL_CTRL1);
1046 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1051 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1056 struct skl_wrpll_context {
1057 uint64_t min_deviation; /* current minimal deviation */
1058 uint64_t central_freq; /* chosen central freq */
1059 uint64_t dco_freq; /* chosen dco freq */
1060 unsigned int p; /* chosen divider */
1063 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1065 memset(ctx, 0, sizeof(*ctx));
1067 ctx->min_deviation = U64_MAX;
1070 /* DCO freq must be within +1%/-6% of the DCO central freq */
1071 #define SKL_DCO_MAX_PDEVIATION 100
1072 #define SKL_DCO_MAX_NDEVIATION 600
1074 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1075 uint64_t central_freq,
1077 unsigned int divider)
1081 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1084 /* positive deviation */
1085 if (dco_freq >= central_freq) {
1086 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1087 deviation < ctx->min_deviation) {
1088 ctx->min_deviation = deviation;
1089 ctx->central_freq = central_freq;
1090 ctx->dco_freq = dco_freq;
1093 /* negative deviation */
1094 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1095 deviation < ctx->min_deviation) {
1096 ctx->min_deviation = deviation;
1097 ctx->central_freq = central_freq;
1098 ctx->dco_freq = dco_freq;
1103 static void skl_wrpll_get_multipliers(unsigned int p,
1104 unsigned int *p0 /* out */,
1105 unsigned int *p1 /* out */,
1106 unsigned int *p2 /* out */)
1110 unsigned int half = p / 2;
1112 if (half == 1 || half == 2 || half == 3 || half == 5) {
1116 } else if (half % 2 == 0) {
1120 } else if (half % 3 == 0) {
1124 } else if (half % 7 == 0) {
1129 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1133 } else if (p == 5 || p == 7) {
1137 } else if (p == 15) {
1141 } else if (p == 21) {
1145 } else if (p == 35) {
1152 struct skl_wrpll_params {
1153 uint32_t dco_fraction;
1154 uint32_t dco_integer;
1155 uint32_t qdiv_ratio;
1159 uint32_t central_freq;
1162 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1164 uint64_t central_freq,
1165 uint32_t p0, uint32_t p1, uint32_t p2)
1169 switch (central_freq) {
1171 params->central_freq = 0;
1174 params->central_freq = 1;
1177 params->central_freq = 3;
1194 WARN(1, "Incorrect PDiv\n");
1211 WARN(1, "Incorrect KDiv\n");
1214 params->qdiv_ratio = p1;
1215 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1217 dco_freq = p0 * p1 * p2 * afe_clock;
1220 * Intermediate values are in Hz.
1221 * Divide by MHz to match bsepc
1223 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1224 params->dco_fraction =
1225 div_u64((div_u64(dco_freq, 24) -
1226 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1230 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1231 struct skl_wrpll_params *wrpll_params)
1233 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1234 uint64_t dco_central_freq[3] = {8400000000ULL,
1237 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1238 24, 28, 30, 32, 36, 40, 42, 44,
1239 48, 52, 54, 56, 60, 64, 66, 68,
1240 70, 72, 76, 78, 80, 84, 88, 90,
1242 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1243 static const struct {
1247 { even_dividers, ARRAY_SIZE(even_dividers) },
1248 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1250 struct skl_wrpll_context ctx;
1251 unsigned int dco, d, i;
1252 unsigned int p0, p1, p2;
1254 skl_wrpll_context_init(&ctx);
1256 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1257 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1258 for (i = 0; i < dividers[d].n_dividers; i++) {
1259 unsigned int p = dividers[d].list[i];
1260 uint64_t dco_freq = p * afe_clock;
1262 skl_wrpll_try_divider(&ctx,
1263 dco_central_freq[dco],
1267 * Skip the remaining dividers if we're sure to
1268 * have found the definitive divider, we can't
1269 * improve a 0 deviation.
1271 if (ctx.min_deviation == 0)
1272 goto skip_remaining_dividers;
1276 skip_remaining_dividers:
1278 * If a solution is found with an even divider, prefer
1281 if (d == 0 && ctx.p)
1286 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1291 * gcc incorrectly analyses that these can be used without being
1292 * initialized. To be fair, it's hard to guess.
1295 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1296 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1302 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
1303 struct intel_crtc_state *crtc_state,
1306 uint32_t ctrl1, cfgcr1, cfgcr2;
1307 struct skl_wrpll_params wrpll_params = { 0, };
1310 * See comment in intel_dpll_hw_state to understand why we always use 0
1311 * as the DPLL id in this function.
1313 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1315 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1317 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1320 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1321 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1322 wrpll_params.dco_integer;
1324 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1325 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1326 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1327 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1328 wrpll_params.central_freq;
1330 memset(&crtc_state->dpll_hw_state, 0,
1331 sizeof(crtc_state->dpll_hw_state));
1333 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1334 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1335 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1340 skl_ddi_dp_set_dpll_hw_state(int clock,
1341 struct intel_dpll_hw_state *dpll_hw_state)
1346 * See comment in intel_dpll_hw_state to understand why we always use 0
1347 * as the DPLL id in this function.
1349 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1350 switch (clock / 2) {
1352 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1355 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1358 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1362 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1365 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1368 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1372 dpll_hw_state->ctrl1 = ctrl1;
1376 static struct intel_shared_dpll *
1377 skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1378 struct intel_encoder *encoder)
1380 struct intel_shared_dpll *pll;
1381 int clock = crtc_state->port_clock;
1383 struct intel_dpll_hw_state dpll_hw_state;
1385 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
1387 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1388 bret = skl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
1390 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1393 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1394 bret = skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
1396 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1399 crtc_state->dpll_hw_state = dpll_hw_state;
1404 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1405 pll = intel_find_shared_dpll(crtc, crtc_state,
1409 pll = intel_find_shared_dpll(crtc, crtc_state,
1415 intel_reference_shared_dpll(pll, crtc_state);
1420 static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
1421 struct intel_dpll_hw_state *hw_state)
1423 DRM_DEBUG_KMS("dpll_hw_state: "
1424 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1430 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1431 .enable = skl_ddi_pll_enable,
1432 .disable = skl_ddi_pll_disable,
1433 .get_hw_state = skl_ddi_pll_get_hw_state,
1436 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1437 .enable = skl_ddi_dpll0_enable,
1438 .disable = skl_ddi_dpll0_disable,
1439 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1442 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1443 struct intel_shared_dpll *pll)
1446 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1448 enum dpio_channel ch;
1450 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1452 /* Non-SSC reference */
1453 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1454 temp |= PORT_PLL_REF_SEL;
1455 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1457 if (IS_GEMINILAKE(dev_priv)) {
1458 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1459 temp |= PORT_PLL_POWER_ENABLE;
1460 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1462 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1463 PORT_PLL_POWER_STATE), 200))
1464 DRM_ERROR("Power state not set for PLL:%d\n", port);
1467 /* Disable 10 bit clock */
1468 temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1469 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1470 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1473 temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1474 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1475 temp |= pll->state.hw_state.ebb0;
1476 I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
1478 /* Write M2 integer */
1479 temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1480 temp &= ~PORT_PLL_M2_MASK;
1481 temp |= pll->state.hw_state.pll0;
1482 I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
1485 temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1486 temp &= ~PORT_PLL_N_MASK;
1487 temp |= pll->state.hw_state.pll1;
1488 I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
1490 /* Write M2 fraction */
1491 temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1492 temp &= ~PORT_PLL_M2_FRAC_MASK;
1493 temp |= pll->state.hw_state.pll2;
1494 I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
1496 /* Write M2 fraction enable */
1497 temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1498 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1499 temp |= pll->state.hw_state.pll3;
1500 I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
1503 temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1504 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1505 temp &= ~PORT_PLL_INT_COEFF_MASK;
1506 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1507 temp |= pll->state.hw_state.pll6;
1508 I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
1510 /* Write calibration val */
1511 temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1512 temp &= ~PORT_PLL_TARGET_CNT_MASK;
1513 temp |= pll->state.hw_state.pll8;
1514 I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
1516 temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1517 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1518 temp |= pll->state.hw_state.pll9;
1519 I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
1521 temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1522 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1523 temp &= ~PORT_PLL_DCO_AMP_MASK;
1524 temp |= pll->state.hw_state.pll10;
1525 I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
1527 /* Recalibrate with new settings */
1528 temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1529 temp |= PORT_PLL_RECALIBRATE;
1530 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1531 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1532 temp |= pll->state.hw_state.ebb4;
1533 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1536 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1537 temp |= PORT_PLL_ENABLE;
1538 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1539 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1541 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1543 DRM_ERROR("PLL %d not locked\n", port);
1545 if (IS_GEMINILAKE(dev_priv)) {
1546 temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
1547 temp |= DCC_DELAY_RANGE_2;
1548 I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
1552 * While we write to the group register to program all lanes at once we
1553 * can read only lane registers and we pick lanes 0/1 for that.
1555 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1556 temp &= ~LANE_STAGGER_MASK;
1557 temp &= ~LANESTAGGER_STRAP_OVRD;
1558 temp |= pll->state.hw_state.pcsdw12;
1559 I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
1562 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1563 struct intel_shared_dpll *pll)
1565 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1568 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1569 temp &= ~PORT_PLL_ENABLE;
1570 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1571 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1573 if (IS_GEMINILAKE(dev_priv)) {
1574 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1575 temp &= ~PORT_PLL_POWER_ENABLE;
1576 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1578 if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1579 PORT_PLL_POWER_STATE), 200))
1580 DRM_ERROR("Power state not reset for PLL:%d\n", port);
1584 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1585 struct intel_shared_dpll *pll,
1586 struct intel_dpll_hw_state *hw_state)
1588 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1592 enum dpio_channel ch;
1594 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1596 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1601 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1602 if (!(val & PORT_PLL_ENABLE))
1605 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1606 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1608 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1609 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1611 hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1612 hw_state->pll0 &= PORT_PLL_M2_MASK;
1614 hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1615 hw_state->pll1 &= PORT_PLL_N_MASK;
1617 hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1618 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1620 hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1621 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1623 hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1624 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1625 PORT_PLL_INT_COEFF_MASK |
1626 PORT_PLL_GAIN_CTL_MASK;
1628 hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1629 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1631 hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1632 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1634 hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1635 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1636 PORT_PLL_DCO_AMP_MASK;
1639 * While we write to the group register to program all lanes at once we
1640 * can read only lane registers. We configure all lanes the same way, so
1641 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1643 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1644 if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
1645 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1647 I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
1648 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1653 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1658 /* bxt clock parameters */
1659 struct bxt_clk_div {
1671 /* pre-calculated values for DP linkrates */
1672 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1673 {162000, 4, 2, 32, 1677722, 1, 1},
1674 {270000, 4, 1, 27, 0, 0, 1},
1675 {540000, 2, 1, 27, 0, 0, 1},
1676 {216000, 3, 2, 32, 1677722, 1, 1},
1677 {243000, 4, 1, 24, 1258291, 1, 1},
1678 {324000, 4, 1, 32, 1677722, 1, 1},
1679 {432000, 3, 1, 32, 1677722, 1, 1}
1683 bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
1684 struct intel_crtc_state *crtc_state, int clock,
1685 struct bxt_clk_div *clk_div)
1687 struct dpll best_clock;
1689 /* Calculate HDMI div */
1691 * FIXME: tie the following calculation into
1692 * i9xx_crtc_compute_clock
1694 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1695 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1696 clock, pipe_name(intel_crtc->pipe));
1700 clk_div->p1 = best_clock.p1;
1701 clk_div->p2 = best_clock.p2;
1702 WARN_ON(best_clock.m1 != 2);
1703 clk_div->n = best_clock.n;
1704 clk_div->m2_int = best_clock.m2 >> 22;
1705 clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
1706 clk_div->m2_frac_en = clk_div->m2_frac != 0;
1708 clk_div->vco = best_clock.vco;
1713 static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
1717 *clk_div = bxt_dp_clk_val[0];
1718 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1719 if (bxt_dp_clk_val[i].clock == clock) {
1720 *clk_div = bxt_dp_clk_val[i];
1725 clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
1728 static bool bxt_ddi_set_dpll_hw_state(int clock,
1729 struct bxt_clk_div *clk_div,
1730 struct intel_dpll_hw_state *dpll_hw_state)
1732 int vco = clk_div->vco;
1733 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1734 uint32_t lanestagger;
1736 if (vco >= 6200000 && vco <= 6700000) {
1741 } else if ((vco > 5400000 && vco < 6200000) ||
1742 (vco >= 4800000 && vco < 5400000)) {
1747 } else if (vco == 5400000) {
1753 DRM_ERROR("Invalid VCO\n");
1759 else if (clock > 135000)
1761 else if (clock > 67000)
1763 else if (clock > 33000)
1768 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
1769 dpll_hw_state->pll0 = clk_div->m2_int;
1770 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
1771 dpll_hw_state->pll2 = clk_div->m2_frac;
1773 if (clk_div->m2_frac_en)
1774 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
1776 dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
1777 dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
1779 dpll_hw_state->pll8 = targ_cnt;
1781 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1783 dpll_hw_state->pll10 =
1784 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1785 | PORT_PLL_DCO_AMP_OVR_EN_H;
1787 dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1789 dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
1795 bxt_ddi_dp_set_dpll_hw_state(int clock,
1796 struct intel_dpll_hw_state *dpll_hw_state)
1798 struct bxt_clk_div clk_div = {0};
1800 bxt_ddi_dp_pll_dividers(clock, &clk_div);
1802 return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1806 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc *intel_crtc,
1807 struct intel_crtc_state *crtc_state, int clock,
1808 struct intel_dpll_hw_state *dpll_hw_state)
1810 struct bxt_clk_div clk_div = { };
1812 bxt_ddi_hdmi_pll_dividers(intel_crtc, crtc_state, clock, &clk_div);
1814 return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1817 static struct intel_shared_dpll *
1818 bxt_get_dpll(struct intel_crtc *crtc,
1819 struct intel_crtc_state *crtc_state,
1820 struct intel_encoder *encoder)
1822 struct intel_dpll_hw_state dpll_hw_state = { };
1823 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1824 struct intel_shared_dpll *pll;
1825 int i, clock = crtc_state->port_clock;
1827 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1828 !bxt_ddi_hdmi_set_dpll_hw_state(crtc, crtc_state, clock,
1832 if (intel_crtc_has_dp_encoder(crtc_state) &&
1833 !bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
1836 memset(&crtc_state->dpll_hw_state, 0,
1837 sizeof(crtc_state->dpll_hw_state));
1839 crtc_state->dpll_hw_state = dpll_hw_state;
1841 /* 1:1 mapping between ports and PLLs */
1842 i = (enum intel_dpll_id) encoder->port;
1843 pll = intel_get_shared_dpll_by_id(dev_priv, i);
1845 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1846 crtc->base.base.id, crtc->base.name, pll->info->name);
1848 intel_reference_shared_dpll(pll, crtc_state);
1853 static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
1854 struct intel_dpll_hw_state *hw_state)
1856 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
1857 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1858 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
1872 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1873 .enable = bxt_ddi_pll_enable,
1874 .disable = bxt_ddi_pll_disable,
1875 .get_hw_state = bxt_ddi_pll_get_hw_state,
1878 static void intel_ddi_pll_init(struct drm_device *dev)
1880 struct drm_i915_private *dev_priv = to_i915(dev);
1882 if (INTEL_GEN(dev_priv) < 9) {
1883 uint32_t val = I915_READ(LCPLL_CTL);
1886 * The LCPLL register should be turned on by the BIOS. For now
1887 * let's just check its state and print errors in case
1888 * something is wrong. Don't even try to turn it on.
1891 if (val & LCPLL_CD_SOURCE_FCLK)
1892 DRM_ERROR("CDCLK source is not LCPLL\n");
1894 if (val & LCPLL_PLL_DISABLE)
1895 DRM_ERROR("LCPLL is disabled\n");
1899 struct intel_dpll_mgr {
1900 const struct dpll_info *dpll_info;
1902 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
1903 struct intel_crtc_state *crtc_state,
1904 struct intel_encoder *encoder);
1906 void (*dump_hw_state)(struct drm_i915_private *dev_priv,
1907 struct intel_dpll_hw_state *hw_state);
1910 static const struct dpll_info pch_plls[] = {
1911 { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
1912 { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
1916 static const struct intel_dpll_mgr pch_pll_mgr = {
1917 .dpll_info = pch_plls,
1918 .get_dpll = ibx_get_dpll,
1919 .dump_hw_state = ibx_dump_hw_state,
1922 static const struct dpll_info hsw_plls[] = {
1923 { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
1924 { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
1925 { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
1926 { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON },
1927 { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
1928 { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
1932 static const struct intel_dpll_mgr hsw_pll_mgr = {
1933 .dpll_info = hsw_plls,
1934 .get_dpll = hsw_get_dpll,
1935 .dump_hw_state = hsw_dump_hw_state,
1938 static const struct dpll_info skl_plls[] = {
1939 { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1940 { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1941 { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1942 { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
1946 static const struct intel_dpll_mgr skl_pll_mgr = {
1947 .dpll_info = skl_plls,
1948 .get_dpll = skl_get_dpll,
1949 .dump_hw_state = skl_dump_hw_state,
1952 static const struct dpll_info bxt_plls[] = {
1953 { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
1954 { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1955 { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1959 static const struct intel_dpll_mgr bxt_pll_mgr = {
1960 .dpll_info = bxt_plls,
1961 .get_dpll = bxt_get_dpll,
1962 .dump_hw_state = bxt_dump_hw_state,
1965 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1966 struct intel_shared_dpll *pll)
1968 const enum intel_dpll_id id = pll->info->id;
1971 /* 1. Enable DPLL power in DPLL_ENABLE. */
1972 val = I915_READ(CNL_DPLL_ENABLE(id));
1973 val |= PLL_POWER_ENABLE;
1974 I915_WRITE(CNL_DPLL_ENABLE(id), val);
1976 /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
1977 if (intel_wait_for_register(dev_priv,
1978 CNL_DPLL_ENABLE(id),
1982 DRM_ERROR("PLL %d Power not enabled\n", id);
1985 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
1986 * select DP mode, and set DP link rate.
1988 val = pll->state.hw_state.cfgcr0;
1989 I915_WRITE(CNL_DPLL_CFGCR0(id), val);
1991 /* 4. Reab back to ensure writes completed */
1992 POSTING_READ(CNL_DPLL_CFGCR0(id));
1994 /* 3. Configure DPLL_CFGCR0 */
1995 /* Avoid touch CFGCR1 if HDMI mode is not enabled */
1996 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1997 val = pll->state.hw_state.cfgcr1;
1998 I915_WRITE(CNL_DPLL_CFGCR1(id), val);
1999 /* 4. Reab back to ensure writes completed */
2000 POSTING_READ(CNL_DPLL_CFGCR1(id));
2004 * 5. If the frequency will result in a change to the voltage
2005 * requirement, follow the Display Voltage Frequency Switching
2006 * Sequence Before Frequency Change
2008 * Note: DVFS is actually handled via the cdclk code paths,
2009 * hence we do nothing here.
2012 /* 6. Enable DPLL in DPLL_ENABLE. */
2013 val = I915_READ(CNL_DPLL_ENABLE(id));
2015 I915_WRITE(CNL_DPLL_ENABLE(id), val);
2017 /* 7. Wait for PLL lock status in DPLL_ENABLE. */
2018 if (intel_wait_for_register(dev_priv,
2019 CNL_DPLL_ENABLE(id),
2023 DRM_ERROR("PLL %d not locked\n", id);
2026 * 8. If the frequency will result in a change to the voltage
2027 * requirement, follow the Display Voltage Frequency Switching
2028 * Sequence After Frequency Change
2030 * Note: DVFS is actually handled via the cdclk code paths,
2031 * hence we do nothing here.
2035 * 9. turn on the clock for the DDI and map the DPLL to the DDI
2036 * Done at intel_ddi_clk_select
2040 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2041 struct intel_shared_dpll *pll)
2043 const enum intel_dpll_id id = pll->info->id;
2047 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
2048 * Done at intel_ddi_post_disable
2052 * 2. If the frequency will result in a change to the voltage
2053 * requirement, follow the Display Voltage Frequency Switching
2054 * Sequence Before Frequency Change
2056 * Note: DVFS is actually handled via the cdclk code paths,
2057 * hence we do nothing here.
2060 /* 3. Disable DPLL through DPLL_ENABLE. */
2061 val = I915_READ(CNL_DPLL_ENABLE(id));
2063 I915_WRITE(CNL_DPLL_ENABLE(id), val);
2065 /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
2066 if (intel_wait_for_register(dev_priv,
2067 CNL_DPLL_ENABLE(id),
2071 DRM_ERROR("PLL %d locked\n", id);
2074 * 5. If the frequency will result in a change to the voltage
2075 * requirement, follow the Display Voltage Frequency Switching
2076 * Sequence After Frequency Change
2078 * Note: DVFS is actually handled via the cdclk code paths,
2079 * hence we do nothing here.
2082 /* 6. Disable DPLL power in DPLL_ENABLE. */
2083 val = I915_READ(CNL_DPLL_ENABLE(id));
2084 val &= ~PLL_POWER_ENABLE;
2085 I915_WRITE(CNL_DPLL_ENABLE(id), val);
2087 /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
2088 if (intel_wait_for_register(dev_priv,
2089 CNL_DPLL_ENABLE(id),
2093 DRM_ERROR("PLL %d Power not disabled\n", id);
2096 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2097 struct intel_shared_dpll *pll,
2098 struct intel_dpll_hw_state *hw_state)
2100 const enum intel_dpll_id id = pll->info->id;
2104 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
2109 val = I915_READ(CNL_DPLL_ENABLE(id));
2110 if (!(val & PLL_ENABLE))
2113 val = I915_READ(CNL_DPLL_CFGCR0(id));
2114 hw_state->cfgcr0 = val;
2116 /* avoid reading back stale values if HDMI mode is not enabled */
2117 if (val & DPLL_CFGCR0_HDMI_MODE) {
2118 hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
2123 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2128 static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2129 int *qdiv, int *kdiv)
2132 if (bestdiv % 2 == 0) {
2137 } else if (bestdiv % 4 == 0) {
2139 *qdiv = bestdiv / 4;
2141 } else if (bestdiv % 6 == 0) {
2143 *qdiv = bestdiv / 6;
2145 } else if (bestdiv % 5 == 0) {
2147 *qdiv = bestdiv / 10;
2149 } else if (bestdiv % 14 == 0) {
2151 *qdiv = bestdiv / 14;
2155 if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2159 } else { /* 9, 15, 21 */
2160 *pdiv = bestdiv / 3;
2167 static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
2168 u32 dco_freq, u32 ref_freq,
2169 int pdiv, int qdiv, int kdiv)
2184 WARN(1, "Incorrect KDiv\n");
2201 WARN(1, "Incorrect PDiv\n");
2204 WARN_ON(kdiv != 2 && qdiv != 1);
2206 params->qdiv_ratio = qdiv;
2207 params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2209 dco = div_u64((u64)dco_freq << 15, ref_freq);
2211 params->dco_integer = dco >> 15;
2212 params->dco_fraction = dco & 0x7fff;
2215 int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
2217 int ref_clock = dev_priv->cdclk.hw.ref;
2220 * For ICL+, the spec states: if reference frequency is 38.4,
2221 * use 19.2 because the DPLL automatically divides that by 2.
2223 if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
2230 cnl_ddi_calculate_wrpll(int clock,
2231 struct drm_i915_private *dev_priv,
2232 struct skl_wrpll_params *wrpll_params)
2234 u32 afe_clock = clock * 5;
2236 u32 dco_min = 7998000;
2237 u32 dco_max = 10000000;
2238 u32 dco_mid = (dco_min + dco_max) / 2;
2239 static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
2240 18, 20, 24, 28, 30, 32, 36, 40,
2241 42, 44, 48, 50, 52, 54, 56, 60,
2242 64, 66, 68, 70, 72, 76, 78, 80,
2243 84, 88, 90, 92, 96, 98, 100, 102,
2244 3, 5, 7, 9, 15, 21 };
2245 u32 dco, best_dco = 0, dco_centrality = 0;
2246 u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2247 int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2249 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2250 dco = afe_clock * dividers[d];
2252 if ((dco <= dco_max) && (dco >= dco_min)) {
2253 dco_centrality = abs(dco - dco_mid);
2255 if (dco_centrality < best_dco_centrality) {
2256 best_dco_centrality = dco_centrality;
2257 best_div = dividers[d];
2266 cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2268 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
2270 cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
2276 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
2277 struct intel_crtc_state *crtc_state,
2280 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2281 uint32_t cfgcr0, cfgcr1;
2282 struct skl_wrpll_params wrpll_params = { 0, };
2284 cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
2286 if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))
2289 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
2290 wrpll_params.dco_integer;
2292 cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
2293 DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
2294 DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
2295 DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
2296 DPLL_CFGCR1_CENTRAL_FREQ;
2298 memset(&crtc_state->dpll_hw_state, 0,
2299 sizeof(crtc_state->dpll_hw_state));
2301 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2302 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
2307 cnl_ddi_dp_set_dpll_hw_state(int clock,
2308 struct intel_dpll_hw_state *dpll_hw_state)
2312 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
2314 switch (clock / 2) {
2316 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
2319 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
2322 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
2326 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
2329 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
2332 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
2335 /* Some SKUs may require elevated I/O voltage to support this */
2336 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
2339 /* Some SKUs may require elevated I/O voltage to support this */
2340 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
2344 dpll_hw_state->cfgcr0 = cfgcr0;
2348 static struct intel_shared_dpll *
2349 cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
2350 struct intel_encoder *encoder)
2352 struct intel_shared_dpll *pll;
2353 int clock = crtc_state->port_clock;
2355 struct intel_dpll_hw_state dpll_hw_state;
2357 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
2359 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2360 bret = cnl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
2362 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
2365 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
2366 bret = cnl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
2368 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
2371 crtc_state->dpll_hw_state = dpll_hw_state;
2373 DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",
2374 crtc_state->output_types);
2378 pll = intel_find_shared_dpll(crtc, crtc_state,
2382 DRM_DEBUG_KMS("No PLL selected\n");
2386 intel_reference_shared_dpll(pll, crtc_state);
2391 static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
2392 struct intel_dpll_hw_state *hw_state)
2394 DRM_DEBUG_KMS("dpll_hw_state: "
2395 "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
2400 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
2401 .enable = cnl_ddi_pll_enable,
2402 .disable = cnl_ddi_pll_disable,
2403 .get_hw_state = cnl_ddi_pll_get_hw_state,
2406 static const struct dpll_info cnl_plls[] = {
2407 { "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2408 { "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2409 { "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2413 static const struct intel_dpll_mgr cnl_pll_mgr = {
2414 .dpll_info = cnl_plls,
2415 .get_dpll = cnl_get_dpll,
2416 .dump_hw_state = cnl_dump_hw_state,
2420 * These values alrea already adjusted: they're the bits we write to the
2421 * registers, not the logical values.
2423 static const struct skl_wrpll_params icl_dp_combo_pll_24MHz_values[] = {
2424 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */
2425 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2426 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */
2427 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2428 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */
2429 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2430 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */
2431 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2432 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [4]: 2.16 */
2433 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
2434 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [5]: 4.32 */
2435 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2436 { .dco_integer = 0x195, .dco_fraction = 0x0000, /* [6]: 6.48 */
2437 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2438 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */
2439 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2442 /* Also used for 38.4 MHz values. */
2443 static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = {
2444 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */
2445 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2446 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */
2447 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2448 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */
2449 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2450 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */
2451 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2452 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [4]: 2.16 */
2453 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
2454 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [5]: 4.32 */
2455 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2456 { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */
2457 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2458 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */
2459 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2462 static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2463 .dco_integer = 0x151, .dco_fraction = 0x4000,
2464 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2467 static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2468 .dco_integer = 0x1A5, .dco_fraction = 0x7000,
2469 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2472 static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
2473 struct skl_wrpll_params *pll_params)
2475 const struct skl_wrpll_params *params;
2477 params = dev_priv->cdclk.hw.ref == 24000 ?
2478 icl_dp_combo_pll_24MHz_values :
2479 icl_dp_combo_pll_19_2MHz_values;
2483 *pll_params = params[0];
2486 *pll_params = params[1];
2489 *pll_params = params[2];
2492 *pll_params = params[3];
2495 *pll_params = params[4];
2498 *pll_params = params[5];
2501 *pll_params = params[6];
2504 *pll_params = params[7];
2507 MISSING_CASE(clock);
2514 static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
2515 struct skl_wrpll_params *pll_params)
2517 *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
2518 icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
2522 static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
2523 struct intel_encoder *encoder, int clock,
2524 struct intel_dpll_hw_state *pll_state)
2526 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2527 uint32_t cfgcr0, cfgcr1;
2528 struct skl_wrpll_params pll_params = { 0 };
2531 if (intel_port_is_tc(dev_priv, encoder->port))
2532 ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
2533 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2534 ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
2536 ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
2541 cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
2542 pll_params.dco_integer;
2544 cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
2545 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
2546 DPLL_CFGCR1_KDIV(pll_params.kdiv) |
2547 DPLL_CFGCR1_PDIV(pll_params.pdiv) |
2548 DPLL_CFGCR1_CENTRAL_FREQ_8400;
2550 pll_state->cfgcr0 = cfgcr0;
2551 pll_state->cfgcr1 = cfgcr1;
2555 int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
2558 uint32_t cfgcr0, cfgcr1;
2559 uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
2560 const struct skl_wrpll_params *params;
2561 int index, n_entries, link_clock;
2563 /* Read back values from DPLL CFGCR registers */
2564 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
2565 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
2567 dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
2568 dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2569 DPLL_CFGCR0_DCO_FRACTION_SHIFT;
2570 pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT;
2571 kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT;
2572 qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
2573 DPLL_CFGCR1_QDIV_MODE_SHIFT;
2574 qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
2575 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
2577 params = dev_priv->cdclk.hw.ref == 24000 ?
2578 icl_dp_combo_pll_24MHz_values :
2579 icl_dp_combo_pll_19_2MHz_values;
2580 n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
2582 for (index = 0; index < n_entries; index++) {
2583 if (dco_integer == params[index].dco_integer &&
2584 dco_fraction == params[index].dco_fraction &&
2585 pdiv == params[index].pdiv &&
2586 kdiv == params[index].kdiv &&
2587 qdiv_mode == params[index].qdiv_mode &&
2588 qdiv_ratio == params[index].qdiv_ratio)
2592 /* Map PLL Index to Link Clock */
2595 MISSING_CASE(index);
2598 link_clock = 540000;
2601 link_clock = 270000;
2604 link_clock = 162000;
2607 link_clock = 324000;
2610 link_clock = 216000;
2613 link_clock = 432000;
2616 link_clock = 648000;
2619 link_clock = 810000;
2626 static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
2628 return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
2631 static enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
2633 return port - PORT_C + DPLL_ID_ICL_MGPLL1;
2636 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
2637 uint32_t *target_dco_khz,
2638 struct intel_dpll_hw_state *state)
2640 uint32_t dco_min_freq, dco_max_freq;
2641 int div1_vals[] = {7, 5, 3, 2};
2645 dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
2646 dco_max_freq = is_dp ? 8100000 : 10000000;
2648 for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
2649 int div1 = div1_vals[i];
2651 for (div2 = 10; div2 > 0; div2--) {
2652 int dco = div1 * div2 * clock_khz * 5;
2653 int a_divratio, tlinedrv, inputsel;
2656 if (dco < dco_min_freq || dco > dco_max_freq)
2660 a_divratio = is_dp ? 10 : 5;
2666 inputsel = is_dp ? 0 : 1;
2673 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
2676 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
2679 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
2682 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
2686 *target_dco_khz = dco;
2688 state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
2690 state->mg_clktop2_coreclkctl1 =
2691 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
2693 state->mg_clktop2_hsclkctl =
2694 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
2695 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2697 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
2707 * The specification for this function uses real numbers, so the math had to be
2708 * adapted to integer-only calculation, that's why it looks so different.
2710 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
2711 struct intel_encoder *encoder, int clock,
2712 struct intel_dpll_hw_state *pll_state)
2714 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2715 int refclk_khz = dev_priv->cdclk.hw.ref;
2716 uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
2717 uint32_t iref_ndiv, iref_trim, iref_pulse_w;
2718 uint32_t prop_coeff, int_coeff;
2719 uint32_t tdc_targetcnt, feedfwgain;
2720 uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
2722 bool use_ssc = false;
2723 bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
2725 if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
2727 DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
2732 m2div_int = dco_khz / (refclk_khz * m1div);
2733 if (m2div_int > 255) {
2735 m2div_int = dco_khz / (refclk_khz * m1div);
2736 if (m2div_int > 255) {
2737 DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
2742 m2div_rem = dco_khz % (refclk_khz * m1div);
2744 tmp = (uint64_t)m2div_rem * (1 << 22);
2745 do_div(tmp, refclk_khz * m1div);
2748 switch (refclk_khz) {
2765 MISSING_CASE(refclk_khz);
2770 * tdc_res = 0.000003
2771 * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
2773 * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
2774 * was supposed to be a division, but we rearranged the operations of
2775 * the formula to avoid early divisions so we don't multiply the
2778 * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
2779 * we also rearrange to work with integers.
2781 * The 0.5 transformed to 5 results in a multiplication by 10 and the
2782 * last division by 10.
2784 tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
2787 * Here we divide dco_khz by 10 in order to allow the dividend to fit in
2788 * 32 bits. That's not a problem since we round the division down
2791 feedfwgain = (use_ssc || m2div_rem > 0) ?
2792 m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
2794 if (dco_khz >= 9000000) {
2803 tmp = (uint64_t)dco_khz * 47 * 32;
2804 do_div(tmp, refclk_khz * m1div * 10000);
2807 tmp = (uint64_t)dco_khz * 1000;
2808 ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
2815 pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
2816 MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
2817 MG_PLL_DIV0_FBDIV_INT(m2div_int);
2819 pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
2820 MG_PLL_DIV1_DITHER_DIV_2 |
2821 MG_PLL_DIV1_NDIVRATIO(1) |
2822 MG_PLL_DIV1_FBPREDIV(m1div);
2824 pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
2825 MG_PLL_LF_AFCCNTSEL_512 |
2826 MG_PLL_LF_GAINCTRL(1) |
2827 MG_PLL_LF_INT_COEFF(int_coeff) |
2828 MG_PLL_LF_PROP_COEFF(prop_coeff);
2830 pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
2831 MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
2832 MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
2833 MG_PLL_FRAC_LOCK_DCODITHEREN |
2834 MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
2835 if (use_ssc || m2div_rem > 0)
2836 pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
2838 pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
2839 MG_PLL_SSC_TYPE(2) |
2840 MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
2841 MG_PLL_SSC_STEPNUM(ssc_steplog) |
2843 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
2845 pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
2846 MG_PLL_TDC_COLDST_IREFINT_EN |
2847 MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
2848 MG_PLL_TDC_TDCOVCCORR_EN |
2849 MG_PLL_TDC_TDCSEL(3);
2851 pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
2852 MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
2853 MG_PLL_BIAS_BIAS_BONUS(10) |
2854 MG_PLL_BIAS_BIASCAL_EN |
2855 MG_PLL_BIAS_CTRIM(12) |
2856 MG_PLL_BIAS_VREF_RDAC(4) |
2857 MG_PLL_BIAS_IREFTRIM(iref_trim);
2859 if (refclk_khz == 38400) {
2860 pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
2861 pll_state->mg_pll_bias_mask = 0;
2863 pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
2864 pll_state->mg_pll_bias_mask = -1U;
2867 pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
2868 pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
2873 static struct intel_shared_dpll *
2874 icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
2875 struct intel_encoder *encoder)
2877 struct intel_digital_port *intel_dig_port =
2878 enc_to_dig_port(&encoder->base);
2879 struct intel_shared_dpll *pll;
2880 struct intel_dpll_hw_state pll_state = {};
2881 enum port port = encoder->port;
2882 enum intel_dpll_id min, max;
2883 int clock = crtc_state->port_clock;
2889 min = DPLL_ID_ICL_DPLL0;
2890 max = DPLL_ID_ICL_DPLL1;
2891 ret = icl_calc_dpll_state(crtc_state, encoder, clock,
2898 if (intel_dig_port->tc_type == TC_PORT_TBT) {
2899 min = DPLL_ID_ICL_TBTPLL;
2901 ret = icl_calc_dpll_state(crtc_state, encoder, clock,
2904 min = icl_port_to_mg_pll_id(port);
2906 ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
2916 DRM_DEBUG_KMS("Could not calculate PLL state.\n");
2920 crtc_state->dpll_hw_state = pll_state;
2922 pll = intel_find_shared_dpll(crtc, crtc_state, min, max);
2924 DRM_DEBUG_KMS("No PLL selected\n");
2928 intel_reference_shared_dpll(pll, crtc_state);
2933 static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
2939 case DPLL_ID_ICL_DPLL0:
2940 case DPLL_ID_ICL_DPLL1:
2941 return CNL_DPLL_ENABLE(id);
2942 case DPLL_ID_ICL_TBTPLL:
2943 return TBT_PLL_ENABLE;
2944 case DPLL_ID_ICL_MGPLL1:
2945 case DPLL_ID_ICL_MGPLL2:
2946 case DPLL_ID_ICL_MGPLL3:
2947 case DPLL_ID_ICL_MGPLL4:
2948 return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
2952 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
2953 struct intel_shared_dpll *pll,
2954 struct intel_dpll_hw_state *hw_state)
2956 const enum intel_dpll_id id = pll->info->id;
2961 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
2964 val = I915_READ(icl_pll_id_to_enable_reg(id));
2965 if (!(val & PLL_ENABLE))
2969 case DPLL_ID_ICL_DPLL0:
2970 case DPLL_ID_ICL_DPLL1:
2971 case DPLL_ID_ICL_TBTPLL:
2972 hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
2973 hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
2975 case DPLL_ID_ICL_MGPLL1:
2976 case DPLL_ID_ICL_MGPLL2:
2977 case DPLL_ID_ICL_MGPLL3:
2978 case DPLL_ID_ICL_MGPLL4:
2979 port = icl_mg_pll_id_to_port(id);
2980 hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
2981 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
2983 hw_state->mg_clktop2_coreclkctl1 =
2984 I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
2985 hw_state->mg_clktop2_coreclkctl1 &=
2986 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
2988 hw_state->mg_clktop2_hsclkctl =
2989 I915_READ(MG_CLKTOP2_HSCLKCTL(port));
2990 hw_state->mg_clktop2_hsclkctl &=
2991 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
2992 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
2993 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
2994 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
2996 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
2997 hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));
2998 hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));
2999 hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
3000 hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));
3002 hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));
3003 hw_state->mg_pll_tdc_coldst_bias =
3004 I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
3006 if (dev_priv->cdclk.hw.ref == 38400) {
3007 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
3008 hw_state->mg_pll_bias_mask = 0;
3010 hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3011 hw_state->mg_pll_bias_mask = -1U;
3014 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
3015 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3023 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
3027 static void icl_dpll_write(struct drm_i915_private *dev_priv,
3028 struct intel_shared_dpll *pll)
3030 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3031 const enum intel_dpll_id id = pll->info->id;
3033 I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
3034 I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
3035 POSTING_READ(ICL_DPLL_CFGCR1(id));
3038 static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
3039 struct intel_shared_dpll *pll)
3041 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3042 enum port port = icl_mg_pll_id_to_port(pll->info->id);
3046 * Some of the following registers have reserved fields, so program
3047 * these with RMW based on a mask. The mask can be fixed or generated
3048 * during the calc/readout phase if the mask depends on some other HW
3049 * state like refclk, see icl_calc_mg_pll_state().
3051 val = I915_READ(MG_REFCLKIN_CTL(port));
3052 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3053 val |= hw_state->mg_refclkin_ctl;
3054 I915_WRITE(MG_REFCLKIN_CTL(port), val);
3056 val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
3057 val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3058 val |= hw_state->mg_clktop2_coreclkctl1;
3059 I915_WRITE(MG_CLKTOP2_CORECLKCTL1(port), val);
3061 val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
3062 val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3063 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3064 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3065 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3066 val |= hw_state->mg_clktop2_hsclkctl;
3067 I915_WRITE(MG_CLKTOP2_HSCLKCTL(port), val);
3069 I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0);
3070 I915_WRITE(MG_PLL_DIV1(port), hw_state->mg_pll_div1);
3071 I915_WRITE(MG_PLL_LF(port), hw_state->mg_pll_lf);
3072 I915_WRITE(MG_PLL_FRAC_LOCK(port), hw_state->mg_pll_frac_lock);
3073 I915_WRITE(MG_PLL_SSC(port), hw_state->mg_pll_ssc);
3075 val = I915_READ(MG_PLL_BIAS(port));
3076 val &= ~hw_state->mg_pll_bias_mask;
3077 val |= hw_state->mg_pll_bias;
3078 I915_WRITE(MG_PLL_BIAS(port), val);
3080 val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
3081 val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
3082 val |= hw_state->mg_pll_tdc_coldst_bias;
3083 I915_WRITE(MG_PLL_TDC_COLDST_BIAS(port), val);
3085 POSTING_READ(MG_PLL_TDC_COLDST_BIAS(port));
3088 static void icl_pll_enable(struct drm_i915_private *dev_priv,
3089 struct intel_shared_dpll *pll)
3091 const enum intel_dpll_id id = pll->info->id;
3092 i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
3095 val = I915_READ(enable_reg);
3096 val |= PLL_POWER_ENABLE;
3097 I915_WRITE(enable_reg, val);
3100 * The spec says we need to "wait" but it also says it should be
3103 if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
3104 PLL_POWER_STATE, 1))
3105 DRM_ERROR("PLL %d Power not enabled\n", id);
3108 case DPLL_ID_ICL_DPLL0:
3109 case DPLL_ID_ICL_DPLL1:
3110 case DPLL_ID_ICL_TBTPLL:
3111 icl_dpll_write(dev_priv, pll);
3113 case DPLL_ID_ICL_MGPLL1:
3114 case DPLL_ID_ICL_MGPLL2:
3115 case DPLL_ID_ICL_MGPLL3:
3116 case DPLL_ID_ICL_MGPLL4:
3117 icl_mg_pll_write(dev_priv, pll);
3124 * DVFS pre sequence would be here, but in our driver the cdclk code
3125 * paths should already be setting the appropriate voltage, hence we do
3129 val = I915_READ(enable_reg);
3131 I915_WRITE(enable_reg, val);
3133 if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
3134 1)) /* 600us actually. */
3135 DRM_ERROR("PLL %d not locked\n", id);
3137 /* DVFS post sequence would be here. See the comment above. */
3140 static void icl_pll_disable(struct drm_i915_private *dev_priv,
3141 struct intel_shared_dpll *pll)
3143 const enum intel_dpll_id id = pll->info->id;
3144 i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
3147 /* The first steps are done by intel_ddi_post_disable(). */
3150 * DVFS pre sequence would be here, but in our driver the cdclk code
3151 * paths should already be setting the appropriate voltage, hence we do
3155 val = I915_READ(enable_reg);
3157 I915_WRITE(enable_reg, val);
3159 /* Timeout is actually 1us. */
3160 if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, 0, 1))
3161 DRM_ERROR("PLL %d locked\n", id);
3163 /* DVFS post sequence would be here. See the comment above. */
3165 val = I915_READ(enable_reg);
3166 val &= ~PLL_POWER_ENABLE;
3167 I915_WRITE(enable_reg, val);
3170 * The spec says we need to "wait" but it also says it should be
3173 if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, 0,
3175 DRM_ERROR("PLL %d Power not disabled\n", id);
3178 static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
3179 struct intel_dpll_hw_state *hw_state)
3181 DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
3182 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
3183 "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
3184 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
3185 "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
3186 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
3187 hw_state->cfgcr0, hw_state->cfgcr1,
3188 hw_state->mg_refclkin_ctl,
3189 hw_state->mg_clktop2_coreclkctl1,
3190 hw_state->mg_clktop2_hsclkctl,
3191 hw_state->mg_pll_div0,
3192 hw_state->mg_pll_div1,
3193 hw_state->mg_pll_lf,
3194 hw_state->mg_pll_frac_lock,
3195 hw_state->mg_pll_ssc,
3196 hw_state->mg_pll_bias,
3197 hw_state->mg_pll_tdc_coldst_bias);
3200 static const struct intel_shared_dpll_funcs icl_pll_funcs = {
3201 .enable = icl_pll_enable,
3202 .disable = icl_pll_disable,
3203 .get_hw_state = icl_pll_get_hw_state,
3206 static const struct dpll_info icl_plls[] = {
3207 { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3208 { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
3209 { "TBT PLL", &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
3210 { "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
3211 { "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
3212 { "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
3213 { "MG PLL 4", &icl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
3217 static const struct intel_dpll_mgr icl_pll_mgr = {
3218 .dpll_info = icl_plls,
3219 .get_dpll = icl_get_dpll,
3220 .dump_hw_state = icl_dump_hw_state,
3224 * intel_shared_dpll_init - Initialize shared DPLLs
3227 * Initialize shared DPLLs for @dev.
3229 void intel_shared_dpll_init(struct drm_device *dev)
3231 struct drm_i915_private *dev_priv = to_i915(dev);
3232 const struct intel_dpll_mgr *dpll_mgr = NULL;
3233 const struct dpll_info *dpll_info;
3236 if (IS_ICELAKE(dev_priv))
3237 dpll_mgr = &icl_pll_mgr;
3238 else if (IS_CANNONLAKE(dev_priv))
3239 dpll_mgr = &cnl_pll_mgr;
3240 else if (IS_GEN9_BC(dev_priv))
3241 dpll_mgr = &skl_pll_mgr;
3242 else if (IS_GEN9_LP(dev_priv))
3243 dpll_mgr = &bxt_pll_mgr;
3244 else if (HAS_DDI(dev_priv))
3245 dpll_mgr = &hsw_pll_mgr;
3246 else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
3247 dpll_mgr = &pch_pll_mgr;
3250 dev_priv->num_shared_dpll = 0;
3254 dpll_info = dpll_mgr->dpll_info;
3256 for (i = 0; dpll_info[i].name; i++) {
3257 WARN_ON(i != dpll_info[i].id);
3258 dev_priv->shared_dplls[i].info = &dpll_info[i];
3261 dev_priv->dpll_mgr = dpll_mgr;
3262 dev_priv->num_shared_dpll = i;
3263 mutex_init(&dev_priv->dpll_lock);
3265 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
3267 /* FIXME: Move this to a more suitable place */
3268 if (HAS_DDI(dev_priv))
3269 intel_ddi_pll_init(dev);
3273 * intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination
3275 * @crtc_state: atomic state for @crtc
3278 * Find an appropriate DPLL for the given CRTC and encoder combination. A
3279 * reference from the @crtc to the returned pll is registered in the atomic
3280 * state. That configuration is made effective by calling
3281 * intel_shared_dpll_swap_state(). The reference should be released by calling
3282 * intel_release_shared_dpll().
3285 * A shared DPLL to be used by @crtc and @encoder with the given @crtc_state.
3287 struct intel_shared_dpll *
3288 intel_get_shared_dpll(struct intel_crtc *crtc,
3289 struct intel_crtc_state *crtc_state,
3290 struct intel_encoder *encoder)
3292 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3293 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
3295 if (WARN_ON(!dpll_mgr))
3298 return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
3302 * intel_release_shared_dpll - end use of DPLL by CRTC in atomic state
3303 * @dpll: dpll in use by @crtc
3305 * @state: atomic state
3307 * This function releases the reference from @crtc to @dpll from the
3308 * atomic @state. The new configuration is made effective by calling
3309 * intel_shared_dpll_swap_state().
3311 void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
3312 struct intel_crtc *crtc,
3313 struct drm_atomic_state *state)
3315 struct intel_shared_dpll_state *shared_dpll_state;
3317 shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
3318 shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
3322 * intel_shared_dpll_dump_hw_state - write hw_state to dmesg
3323 * @dev_priv: i915 drm device
3324 * @hw_state: hw state to be written to the log
3326 * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS.
3328 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
3329 struct intel_dpll_hw_state *hw_state)
3331 if (dev_priv->dpll_mgr) {
3332 dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state);
3334 /* fallback for platforms that don't use the shared dpll
3337 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
3338 "fp0: 0x%x, fp1: 0x%x\n",